Low dropout regulator with current-limiting protection, chip and electronic equipment

Abstract

The invention discloses a low dropout regulator with current-limiting protection, a chip and electronic equipment. The low dropout regulator comprises an LDO main circuit unit, a voltage buffer unit and a current-limiting protection unit, the LDO main circuit unit comprises a first error amplifier, a power tube, a first resistor and a second resistor. When the output current of the LDO exceeds the threshold current, the current-limiting protection unit starts the current-limiting protection function, LDO main loop control is cut off after the gain of the voltage buffer unit is controlled to be reduced to zero, the output current of the LDO is controlled to be stabilized at the threshold current through a current-limiting loop, LDO current-limiting protection is achieved, meanwhile, the problem of competition of two loop control is effectively avoided, and the service life of the LDO is prolonged. Therefore, the circuit does not oscillate.

Description

Technical Field

[0001] The invention relates to a low voltage dropout linear regulator with current limiting protection, and also relates to an integrated circuit chip including the low voltage dropout linear regulator and corresponding electronic equipment, belonging to the technical field of integrated circuits. Background Art

[0002] Low Dropout Regulator (LDO) is a voltage-stabilized power supply with excellent performance such as micro-power consumption, low noise, and high power supply rejection ratio. It is widely used in various integrated circuits and electronic devices. The power supply reliability of the LDO circuit is a very important performance indicator. In practical applications, the output drive capability of the LDO is usually limited. When the load current exceeds the set range, the power tube will generate a large amount of heat loss, causing the LDO temperature to rise, resulting in a reduction in the life of the LDO or even burning. A good setting of the current limiting protection function in the LDO circuit will greatly improve the power supply reliability of the LDO.

[0003] In the prior art, a typical LDO current limiting protection circuit is as follows Figure 1 As shown. Among them, the PMOS tube PM2 proportionally replicates the output current of the power tube PM1 through the current mirror structure. The mirror current is converted into a voltage V3 through the resistor R3 and compared with the reference voltage V_ocp representing the current threshold. When the voltage V3 is greater than the reference voltage V_ocp, the comparator CMP1 is reversed, and the PMOS tube PM3 is controlled to turn on, so that the gate voltage of the power tube PM1 is clamped to the power supply voltage VDD and the power tube PM1 is turned off, or the output current is clamped to the current threshold in a steady state, thereby achieving overcurrent protection. The problem with the above technical solution is that when the output current reaches the current threshold, the current limiting loop starts to work and controls the gate voltage of the power tube PM1. If the PMOS tube PM3 works in the switching state, the circuit will continue to oscillate in the state of "PM1 overcurrent->turn off PM1->PM1 no overcurrent->turn on PM1->PM1 overcurrent". If the PMOS tube PM3 works in the saturation region, the output of the comparator CMP1 will no longer be a logic level but a stable voltage. The output current of the power tube PM1 is stabilized at the current threshold through the loop, and the input voltage V3 of the comparator CMP1 is equal to the reference voltage V_ocp. In this state, the current limiting loop will conflict with the error amplifier EA1 of the LDO main loop, causing the circuit to oscillate.

[0004] In addition, in the Chinese invention patent with patent number ZL 202310627415.0, a current limiting protection circuit and a linear regulator for a low voltage drop linear regulator are disclosed. The current limiting protection circuit includes: a current sampling unit, a voltage comparison unit and a current limiting loop control unit; the current limiting loop control unit is used to turn on or off the current limiting according to the output of the voltage comparison unit, and when the current limiting is turned on, the sampling current of the current sampling unit is fed back to the gate of the power tube to limit the current flowing through the power tube. Summary of the invention

[0005] The primary technical problem to be solved by the present invention is to provide a low voltage dropout linear regulator with current limiting protection.

[0006] Another technical problem to be solved by the present invention is to provide an integrated circuit chip including the low voltage drop linear regulator.

[0007] Another technical problem to be solved by the present invention is to provide an electronic device including the low voltage dropout linear regulator.

[0008] In order to achieve the above object, the present invention adopts the following technical solutions:

[0009] According to a first aspect of an embodiment of the present invention, a low voltage dropout linear regulator with current limiting protection is provided, comprising an LDO main circuit unit, a voltage buffer unit and a current limiting protection unit; the LDO main circuit unit comprises a first error amplifier, a power tube, a first resistor and a second resistor; wherein,

[0010] The negative input terminal of the first error amplifier is connected to the reference voltage terminal, and the output terminal is connected to the input terminal of the voltage buffer unit; the output terminal of the voltage buffer unit is connected to the gate terminal of the power tube and the input terminal and the output terminal of the current limiting protection unit; the source terminal of the power tube is connected to the power supply voltage terminal, and the drain terminal is connected to the first resistor and the LDO output terminal; the other end of the first resistor is connected to the second resistor on one hand, and is connected to the positive input terminal of the first error amplifier on the other hand; the other end of the second resistor is connected to the ground potential terminal;

[0011] The LDO main circuit unit is used to generate an output voltage according to an input reference voltage and provide the output voltage to a load circuit;

[0012] The voltage buffer unit is used for buffering the output voltage of the first error amplifier and then providing it to the power tube;

[0013] The current limiting protection unit is used to turn on or off the current limiting protection function according to the comparison result between the LDO output current and the threshold current;

[0014] When the LDO output current exceeds the threshold current, the current limiting protection unit turns on the current limiting protection function, controls the gain of the voltage buffer unit to be reduced to zero, and then disconnects the LDO main loop control, and controls the LDO output current to be stabilized at the threshold current by the current limiting loop, thereby realizing LDO current limiting protection.

[0015] Preferably, the voltage buffer unit comprises a first PMOS tube, a second PMOS tube and a first NMOS tube; wherein the first PMOS tube, the second PMOS tube and the first NMOS tube constitute a source follower amplifier with a gain of 1;

[0016] The source-drain current value of the first NMOS tube is greater than the source-drain current value of the first PMOS tube.

[0017] Preferably, in the voltage buffer unit, the gate end of the second PMOS tube is connected to the output end of the first error amplifier as an input end, and the source end of the second PMOS tube is connected to the drain end of the first PMOS tube, the gate end of the power tube, and the input end and output end of the current limiting protection unit as an output end; the source end of the first PMOS tube is connected to the power supply voltage end, and the gate end of the first PMOS tube is connected to the first bias voltage end; the drain end of the second PMOS tube is connected to the drain end of the first NMOS tube NM1, and the source end of the first NMOS tube NM1 is connected to the ground potential end; the gate end of the first NMOS tube NM1 is connected to the second bias voltage end.

[0018] Preferably, the current limiting protection unit includes a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube and a sixth PMOS tube, and a second NMOS tube and a third NMOS tube; wherein,

[0019] The third PMOS tube and the power tube form a current mirror structure with a ratio of M:1, which is used to detect the LDO output current; wherein M is a positive integer;

[0020] The second NMOS tube and the third NMOS tube form a current mirror structure, which is used to copy the mirror output current to the threshold current branch for comparison;

[0021] The fourth PMOS tube is the threshold current branch;

[0022] The fifth PMOS tube and the sixth PMOS tube form a current mirror structure with a ratio of 1:K, which is used to mirror the overcurrent formed by the difference between the mirror output current and the threshold current to the output end of the current limiting protection unit to control the on or off state of the current limiting protection function; wherein K is a positive integer.

[0023] Preferably, in the current limiting protection unit, the gate end of the third PMOS tube is connected to the gate end of the power tube and the output end of the voltage buffer unit as an input end, the source end of the third PMOS tube is connected to the power supply voltage end, and the drain end of the third PMOS tube is connected to the drain end of the second NMOS tube; the drain end of the second NMOS tube is connected to the gate end of the third NMOS tube after being short-circuited with the gate end, and the source ends of the second NMOS tube and the third NMOS tube are both connected to the ground potential end; the drain end of the third NMOS tube is connected to the drain ends of the fourth PMOS tube and the fifth PMOS tube, and the drain end of the fifth PMOS tube is connected to the gate end of the sixth PMOS tube after being short-circuited with the gate end; the source ends of the fourth PMOS tube, the fifth PMOS tube and the sixth PMOS tube are all connected to the power supply voltage end; the gate end of the fourth PMOS tube is connected to the first bias voltage end; the drain end of the sixth PMOS tube is connected to the gate end of the power tube and the output end of the voltage buffer unit as an output end.

[0024] Preferably, under normal load working conditions, the first PMOS tube and the second PMOS tube in the voltage buffer unit work in the saturation region, and the first NMOS tube works in the linear region; when the load gradually increases to an overload, the current limiting protection function is turned on, and the second PMOS tube in the voltage buffer unit gradually changes from working in the saturation region to the linear region, so that the gain of the voltage buffer unit gradually decreases from 1 to 0, thereby disconnecting the control of the LDO main loop.

[0025] Preferably, the first PMOS tube in the voltage buffer unit is replaced by a native NMOS tube to achieve accurate tracking of input and output voltages.

[0026] Preferably, the current limiting protection unit further includes a second error amplifier for accurately mirroring the LDO output current; wherein,

[0027] The negative input terminal of the second error amplifier is connected to the LDO output terminal, the positive input terminal is connected to the drain terminals of the third PMOS tube and the second NMOS tube, and the output terminal is connected to the gate terminals of the second NMOS tube and the third NMOS tube.

[0028] According to a second aspect of an embodiment of the present invention, an integrated circuit chip is provided. The integrated circuit chip includes the above-mentioned low voltage dropout linear regulator with current limiting protection.

[0029] According to a third aspect of an embodiment of the present invention, an electronic device is provided, wherein the electronic device includes the above-mentioned low voltage dropout linear regulator with current limiting protection.

[0030] Compared with the prior art, the low-voltage difference linear regulator with current limiting protection provided by the present invention adopts a technical solution of amplifying the current of the LDO output current exceeding the threshold value and using it as a control signal to control the working state of the voltage buffer unit. In the overcurrent state, the negative feedback control of the main loop is changed to the current limiting loop to limit the output current. While realizing the LDO current limiting protection function, the competition problem of the two control loops is effectively avoided, and the circuit will not oscillate. Therefore, the low-voltage difference linear regulator with current limiting protection provided by the present invention has the beneficial effects of ingenious and reasonable structural design, high power supply reliability, and excellent current limiting effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 The following is a schematic diagram of a typical LDO current limiting protection circuit in the prior art;

[0032] Figure 2 A structural block diagram of a low-dropout linear regulator with current limiting protection provided by an embodiment of the present invention;

[0033] Figure 3 The circuit schematic diagram of a low voltage drop linear regulator with current limiting protection in an embodiment of the present invention;

[0034] Figure 4 A circuit schematic diagram of a second solution of a voltage buffer unit in an embodiment of the present invention;

[0035] Figure 5 This is a circuit schematic diagram of the second solution of the current limiting protection unit in an embodiment of the present invention;

[0036] Figure 6 This is a simulation test result diagram of LDO current limiting protection in an embodiment of the present invention;

[0037] Figure 7 The diagram is a schematic diagram of an electronic device using the low voltage dropout linear regulator provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0038] The technical content of the present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0039] like Figure 2As shown, a low voltage difference linear regulator with current limiting protection provided by an embodiment of the present invention includes an LDO main circuit unit, a voltage buffer unit and a current limiting protection unit; the LDO main circuit unit includes a first error amplifier EA1, a power tube PM1, a first resistor R1 and a second resistor R2; wherein, the negative input terminal of the first error amplifier EA1 is connected to the reference voltage (VREF) terminal, and the output terminal is connected to the input terminal of the voltage buffer unit; the output terminal of the voltage buffer unit is connected to the gate terminal of the power tube PM1 and the input terminal and the output terminal of the current limiting protection unit; the source terminal of the power tube PM1 is connected to the power supply voltage (VDD) terminal, and the drain terminal is connected to the first resistor R1 and the LDO output terminal (VOUT); the other end of the first resistor R1 is connected to the second resistor R2 on the one hand, and is connected to the positive input terminal of the first error amplifier EA1 on the other hand; the other end of the second resistor R2 is connected to the ground potential terminal.

[0040] The LDO main circuit unit is used to generate an output voltage VOUT according to the input reference voltage VREF and provide it to the load circuit. The voltage buffer unit is used to buffer the output voltage of the first error amplifier EA1 and provide it to the power tube PM1. The current limiting protection unit is used to turn on or off the current limiting protection function according to the comparison result between the LDO output current and the threshold current.

[0041] When the LDO output current exceeds the threshold current, the current limiting protection unit turns on the current limiting protection function, controls the gain of the voltage buffer unit to be reduced to zero, and then disconnects the LDO main loop control. The current limiting loop controls the LDO output current to be stable at the threshold current, thereby realizing LDO current limiting protection.

[0042] In one embodiment of the present invention, Figure 3 As shown, a low voltage difference linear regulator with current limiting protection provided by an embodiment of the present invention includes an LDO main circuit unit, a voltage buffer unit and a current limiting protection unit; the LDO main circuit unit includes a first error amplifier EA1, a power tube PM1, a first resistor R1 and a second resistor R2; wherein, the circuit structure and working principle of the voltage buffer unit and the current limiting protection unit are as follows.

[0043] The voltage buffer unit includes a first PMOS transistor PM4, a second PMOS transistor PM5 and a first NMOS transistor NM1; wherein the gate end of the second PMOS transistor PM5 is connected to the output end of the first error amplifier EA1 as an input end, and the source end of the second PMOS transistor PM5 is connected to the drain end of the first PMOS transistor PM4, the gate end of the power transistor PM1 and the input end and the output end of the current limiting protection unit as an output end; the source end of the first PMOS transistor PM4 is connected to the power supply voltage (VDD) end, and the gate end of the first PMOS transistor PM4 is connected to the first bias voltage (VBP) end; the drain end of the second PMOS transistor PM5 is connected to the drain end of the first NMOS transistor NM1, and the source end of the first NMOS transistor NM1 is connected to the ground potential end; the gate end of the first NMOS transistor NM1 is connected to the second bias voltage (VBN) end.

[0044] In the voltage buffer unit, the first PMOS tube PM4, the second PMOS tube PM5 and the first NMOS tube NM1 form a source follower amplifier structure (referred to as a source follower), whose output terminal voltage changes with the change of the input terminal voltage. The gain of the amplifier of this structure is approximately 1, and the original function of the LDO main loop is not affected under normal load working conditions. At the same time, in theory, the source-drain current value of the first NMOS tube NM 1 can be equal to the drain-source current of the first PMOS tube PM4. Considering the actual process deviation of the MOS tube and the consistency of mass production, in this embodiment, in order to facilitate circuit and layout design, the source-drain current value (2*I0) of the first NMOS tube NM 1 is twice the source-drain current (I0) of the first PMOS tube PM4, so as to ensure that under normal load working conditions, the drain terminal voltage V2 of the first NMOS tube NM 1 is low level and does not affect the loop operation. In other embodiments, the source-drain current value of the first NMOS tube NM 1 can be greater than the drain-source current of the first PMOS tube PM4.

[0045] The current limiting protection unit includes a third PMOS tube PM2, a fourth PMOS tube PM6, a fifth PMOS tube PM7 and a sixth PMOS tube PM8, as well as a second NMOS tube NM2 and a third NMOS tube NM3. Among them, the gate end of the third PMOS tube PM2 is connected to the gate end of the power tube PM1 and the output end of the voltage buffer unit as an input end, the source end of the third PMOS tube PM2 is connected to the power supply voltage (VDD) end, and the drain end of the third PMOS tube PM2 is connected to the drain end of the second NMOS tube NM2; the drain end of the second NMOS tube NM2 is short-circuited with the gate end and then connected to the gate end of the third NMOS tube NM3; the source ends of the second NMOS tube NM2 and the third NMOS tube NM3 are both connected to the ground potential end; the drain end of the third NMOS tube NM3 is connected to the ground potential end; The drain terminal of the fourth PMOS tube PM6 and the fifth PMOS tube PM7 are connected, and the drain terminal of the fifth PMOS tube PM7 is short-circuited with the gate terminal and then connected to the gate terminal of the sixth PMOS tube PM8; the source terminals of the fourth PMOS tube PM6, the fifth PMOS tube PM7 and the sixth PMOS tube PM8 are all connected to the power supply voltage (VDD) terminal; the gate terminal of the fourth PMOS tube PM6 is connected to the first bias voltage (VBP) terminal; the drain terminal of the sixth PMOS tube PM8 is connected to the gate terminal of the power tube PM1 and the output terminal of the voltage buffer unit as an output terminal.

[0046] In the current limiting protection unit, the third PMOS tube PM2 and the power tube PM1 of the LDO main unit form a current mirror structure, the ratio is M:1 (M is a positive integer), which is used to detect the LDO output current; assuming M = 1000, the relationship between the mirror output current Isense and the LDO output current Iout is: Isense = Iout / 1000. The second NMOS tube NM2 and the third NMOS tube NM3 form a current mirror structure, the ratio is 1:1, which is used to copy the mirror output current Isense to the threshold current branch for comparison. The fourth PMOS tube PM6 is a threshold current branch. By controlling the fourth PMOS tube PM6 with the first bias voltage VBP, the threshold of the LDO output current can be set. According to the ratio M:1, the threshold current Iocp of the threshold current branch is 1 / M of the actual current threshold; when M = 1000, the threshold current Iocp = Iocp_a / 1000, and Iocp_a represents the threshold of the LDO output current. The fifth PMOS tube PM7 and the sixth PMOS tube PM8 form a current mirror structure with a ratio of 1:K (K is a positive integer), which is used to mirror the overcurrent Idelta formed by the difference between the mirror output current Isense and the threshold current Iocp to the output end of the current limiting protection unit. The current is K*Idelta to control the on or off state of the current limiting protection function.

[0047] In a low-dropout linear regulator with current limiting protection provided by an embodiment of the present invention, an LDO main circuit unit and a voltage buffer unit constitute an LDO main loop, which is used to perform negative feedback control on the output of the LDO under normal load working conditions; the current limiting protection unit, the voltage buffer unit and the power tube PM1 in the LDO main circuit unit constitute a current limiting loop, which is used to perform current limiting control on the output of the LDO when overloaded and overcurrent occurs; the specific working principles are described in detail below.

[0048] Under normal load working conditions, the LDO output current Iout is less than the set threshold current Iocp_a. In the current limiting protection unit, the mirror output current Isense is less than the threshold current Iocp. The overcurrent Idelta formed by the difference between the mirror output current Isense and the threshold current Iocp is approximately 0, so the sixth PMOS tube PM8 is in the cut-off state, that is, the current limiting function is in the off state. At this time, the first PMOS tube PM4 and the second PMOS tube PM5 in the voltage buffer unit work in the saturation region, and the current of the first NMOS tube NM1 is 2*I0. Since the current provided by the first PMOS tube PM4 is 1*I0, the drain voltage V2 of the first NMOS tube NM1 will become low and close to 0 volts. Therefore, the first NMOS tube NM1 works in the linear region. After the output voltage V1 of the first error amplifier EA1 is input to the gate terminal of the second PMOS transistor PM5, a driving voltage Vdrv is generated at the output terminal, i.e., the source terminal of the second PMOS transistor PM5, and Vdrv≈V1+Vth; wherein Vth is the conduction threshold voltage of the second PMOS transistor PM5. The driving voltage Vdrv drives the power transistor PM1 to generate a stable output voltage VOUT at the output terminal of the LDO, which is provided to the load circuit. At the same time, the voltage divider network composed of the first resistor R1 and the second resistor R2 in the LDO main circuit unit feeds back the generated feedback voltage Vfb to the positive input terminal of the first error amplifier EA1; in the LDO main loop, when the output voltage VOUT increases, the feedback voltage Vfb increases accordingly, so that the feedback voltage Vfb is greater than the reference voltage VREF at the negative input terminal, the output voltage V1 of the first error amplifier EA1 increases, and the drive voltage Vdrv output by the voltage buffer unit increases accordingly. The drive voltage Vdrv drives the power tube PM1, so that the output voltage VOUT of the LDO decreases, forming a negative feedback control of the LDO main loop. When a stable state is reached, VOUT=G1*(Vfb-VREF), wherein G1 is the open-loop gain of the first error amplifier EA1.

[0049] When the load gradually increases to an overload, the LDO output current Iout is greater than the set threshold current Iocp_a. In the current limiting protection unit, the mirror output current Isense is greater than the threshold current Iocp. The overcurrent Idelta formed by the difference between the mirror output current Isense and the threshold current Iocp begins to increase, and the sixth PMOS tube PM8 becomes conductive, that is, the current limiting function becomes turned on. The output current Ipm8 of the sixth PMOS tube PM8 (i.e., equal to K*Idelta) gradually increases from 0. When Ipm8<I0, the sum of the current I0 and Ipm8 of the first PMOS tube PM4 in the voltage buffer unit is less than 2*I0, so the first NMOS tube NM1 still works in the linear region, the drain voltage V2 of the first NMOS tube NM1 remains close to 0, the second PMOS tube PM5 works in the saturation region, and the voltage buffer unit works normally. When the output current Ipm8 of the sixth PMOS tube PM8>I0, the drain voltage V2 of the first NMOS tube NM1 gradually increases. Since the driving voltage Vdrv at the output end of the voltage buffer unit, i.e., the source end of the second PMOS tube PM5, is equal to V2+Vds, where Vds is the source-drain voltage of the second PMOS tube PM5, the driving voltage Vdrv gradually increases with the voltage V2, so that the second PMOS tube PM5 works in the linear region, the source follower voltage following function fails, and the first error amplifier EA1 loses control of the driving voltage Vdrv. At this time, the influence of the drain voltage V2 of the first NMOS tube NM1 on the driving voltage Vdrv becomes dominant, that is, the current limiting loop formed by the current limiting protection unit begins to control the change of the driving voltage Vdrv. In the overcurrent state, the driving voltage Vdrv gradually increases with the voltage V2, and the driving voltage Vdrv drives the power tube PM1, so that the LDO output current Iout decreases, and finally reaches a stable state, so that the output current Iout is stable near the threshold current Iocp_a. At the same time, in the overcurrent state, the increase of the driving voltage Vdrv causes the output voltage VOUT of the LDO to decrease. In order to increase VOUT, the output voltage V1 of the first error amplifier EA1 of the LDO main loop will decrease. Since the source follower cannot be controlled, the output voltage V1 will continue to be lowered until it is close to 0V, causing the second PMOS tube PM5 to enter the linear region faster.

[0050] It can be seen from the above description that in the current limiting protection unit, the fifth PMOS tube PM7 and the sixth PMOS tube PM8 form a current mirror to amplify the current Idelta of the LDO output current exceeding the threshold by K times, and use it (K*Idelta) as a control signal to control the working state of the voltage buffer unit, i.e., the source follower. In the overcurrent state, the output current K*Idelta of the current limiting protection unit gradually increases, so that the working state of the second PMOS tube PM5 gradually enters the linear region from the saturation region, and the gain of the voltage buffer unit, i.e., the source follower, gradually decreases from 1 to 0. The LDO main loop control is gradually disconnected due to the decrease in the gain of the source follower. When the gain of the source follower is reduced to 0, the current limiting loop dominated by the current limiting protection unit completely controls the driving voltage Vdrv and the output current Iout, so that the output current Iout is stable near the threshold current Iocp_a, and the current limiting protection function of the LDO is realized. When the LDO recovers from overload to normal load operation, the current limiting protection function is turned off, and the LDO main loop resumes to dominate the negative feedback control of the LDO output. Therefore, there will be no competition problem between the two control loops, and the circuit will not oscillate.

[0051] It can be seen that by adjusting the proportional coefficient K of the current mirror formed by the fifth PMOS tube PM7 and the sixth PMOS tube PM8 in the current limiting protection unit, the output current K*Idelta of the current limiting protection unit can be changed, thereby optimizing the stability of system regulation. In addition, by adjusting the values ​​of the proportional coefficients K and M, the threshold of the LDO output current can be adjusted and set.

[0052] It should be noted that the circuit structures of the current limiting protection unit and the voltage buffer unit are not limited in the embodiments of the present invention, and the circuit structures that can realize the functions of the units can be used in other embodiments. For example, in another embodiment of the present invention, the circuit structure of the voltage buffer unit is as follows: Figure 4 As shown, the voltage buffer unit includes a first PMOS tube PM4, a fourth NMOS tube NM5 and a first NMOS tube NM1. The difference from the above embodiment is that the core amplifier tube of the voltage buffer unit in the above embodiment is the second PMOS tube PM5, and the present embodiment uses a native NMOS tube instead, that is, the fourth NMOS tube NM5, and the native NMOS tube has a characteristic of close to zero threshold voltage, so that the driving voltage Vdrv generated by the source end, that is, the output end of the fourth NMOS tube NM5 satisfies Vdrv≈V1+Vth≈V1; wherein V1 is the gate voltage of the fourth NMOS tube NM5, Vth is the threshold voltage of the fourth NMOS tube NM5, and Vth≈0; therefore, the source follower formed by the voltage buffer unit in the present embodiment can realize a more accurate input and output voltage following function.

[0053] For another example, in another embodiment of the present invention, the circuit structure of the current limiting protection unit is as follows: Figure 5 As shown. The difference from the above embodiment is that, in addition to the current mirror structure, the current limiting protection unit also includes a second error amplifier EA2 for accurately mirroring the LDO output current. Among them, the negative input terminal of the second error amplifier EA2 is connected to the LDO output terminal, the positive input terminal is connected to the drain terminal of the third PMOS tube PM2 and the second NMOS tube NM2, and the output terminal is connected to the gate terminal of the second NMOS tube NM2 and the third NMOS tube NM3. The source-drain voltage Vds of the third PMOS tube PM2 and the power tube PM1 in the current limiting protection unit are completely equal. Through the adjustment of the second error amplifier EA2, the drain voltage Vsense of the third PMOS tube PM2 is completely equal to the drain voltage of the power tube PM 1, that is, the output voltage VOUT. Therefore, the mirror output current Isense is more accurate, and the accuracy of the current limiting protection is improved.

[0054] In order to verify the current limiting protection effect of the low voltage drop linear regulator provided by the embodiment of the present invention, the inventors conducted a simulation test of the current limiting protection of the technical solution. The threshold current of the low voltage drop linear regulator was set to 150mA. The test results are as follows: Figure 6 From the simulation test results, it can be seen that when the load current iload increases from low to high to 600mA, when the load current exceeds 150mA, the LDO output current I is limited to around 160mA, and the effect of current limiting protection is very significant.

[0055] Based on the above-mentioned low-voltage dropout linear regulator with current limiting protection, an embodiment of the present invention further provides an integrated circuit chip, which includes the above-mentioned low-voltage dropout linear regulator with current limiting protection, and is used as an important component of a power module in an integrated circuit system to provide a reliable power supply voltage for the system. The specific structure of the low-voltage dropout linear regulator with current limiting protection in the integrated circuit chip will not be described in detail here.

[0056] The low voltage drop linear regulator provided by the embodiment of the present invention can also be used in electronic devices as an important component of a power supply component. Figure 7As shown, the electronic device at least includes a processor, a memory and a power supply component, and may further include a communication component, a sensor component, a multimedia component and an input / output interface according to actual needs. Among them, the memory, the communication component, the sensor component, the power supply component, the multimedia component and the input / output interface are all connected to the processor. The memory may be a static random access memory (SRAM), an electrically erasable programmable read-only memory (EEPROM), an erasable programmable read-only memory (EPROM), a programmable read-only memory (PROM), a read-only memory (ROM), a magnetic memory, a flash memory, etc., and the processor may be a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processing (DSP) chip, etc. Other communication components, sensor components, multimedia components, etc. may all be implemented using general components, which will not be specifically described here.

[0057] In summary, compared with the prior art, the low-voltage difference linear regulator with current limiting protection provided by the present invention adopts a technical solution of amplifying the current of the LDO output current exceeding the threshold and using it as a control signal to control the working state of the voltage buffer unit. In the overcurrent state, the negative feedback control of the main loop is changed to the current limiting loop to limit the output current. While realizing the LDO current limiting protection function, the competition problem of the two loop controls is effectively avoided, and the circuit will not oscillate. Therefore, the low-voltage difference linear regulator with current limiting protection provided by the present invention has the beneficial effects of ingenious and reasonable structural design, high power supply reliability, and excellent current limiting effect.

[0058] It should be noted that the above embodiments are only examples, and the technical solutions of the various embodiments can be combined, all within the protection scope of the present invention.

[0059] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0060] The above is a detailed description of the low-dropout linear regulator, chip and electronic device with current limiting protection provided by the present invention. For those skilled in the art, any obvious changes made to it without departing from the essence of the present invention will constitute an infringement of the patent right of the present invention and will bear corresponding legal responsibilities.

Claims

1. A low voltage dropout linear regulator with current limiting protection, characterized in that It includes an LDO main circuit unit, a voltage buffer unit and a current limiting protection unit; the LDO main circuit unit includes a first error amplifier, a power tube, a first resistor and a second resistor; wherein, The negative input terminal of the first error amplifier is connected to the reference voltage terminal, and the output terminal is connected to the input terminal of the voltage buffer unit; the output terminal of the voltage buffer unit is connected to the gate terminal of the power tube and the input terminal and the output terminal of the current limiting protection unit; the source terminal of the power tube is connected to the power supply voltage terminal, and the drain terminal is connected to the first resistor and the LDO output terminal; the other end of the first resistor is connected to the second resistor on one hand, and is connected to the positive input terminal of the first error amplifier on the other hand; the other end of the second resistor is connected to the ground potential terminal; The LDO main circuit unit is used to generate an output voltage according to an input reference voltage and provide the output voltage to a load circuit; The voltage buffer unit is used for buffering the output voltage of the first error amplifier and then providing it to the power tube; The current limiting protection unit is used to turn on or off the current limiting protection function according to the comparison result between the LDO output current and the threshold current; When the LDO output current exceeds the threshold current, the current limiting protection unit turns on the current limiting protection function, controls the gain of the voltage buffer unit to be reduced to zero, and then disconnects the LDO main loop control, and controls the LDO output current to be stable at the threshold current by the current limiting loop, thereby realizing LDO current limiting protection.

2. The low-dropout linear regulator with current limiting protection according to claim 1, characterized in that: The voltage buffer unit includes a first PMOS tube, a second PMOS tube and a first NMOS tube; wherein the first PMOS tube, the second PMOS tube and the first NMOS tube constitute a source follower amplifier with a gain of 1; The source-drain current value of the first NMOS tube is greater than the source-drain current value of the first PMOS tube.

3. The low voltage dropout linear regulator with current limiting protection as claimed in claim 2, characterized in that: In the voltage buffer unit, the gate end of the second PMOS tube is connected to the output end of the first error amplifier as an input end, and the source end of the second PMOS tube is connected to the drain end of the first PMOS tube, the gate end of the power tube, and the input end and output end of the current limiting protection unit as an output end; the source end of the first PMOS tube is connected to the power supply voltage end, and the gate end of the first PMOS tube is connected to the first bias voltage end; the drain end of the second PMOS tube is connected to the drain end of the first NMOS tube NM1, and the source end of the first NMOS tube NM1 is connected to the ground potential end; the gate end of the first NMOS tube NM1 is connected to the second bias voltage end.

4. The low-dropout linear regulator with current limiting protection according to claim 1, characterized in that: The current limiting protection unit includes a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube and a sixth PMOS tube, and a second NMOS tube and a third NMOS tube; wherein, The third PMOS tube and the power tube form a current mirror structure with a ratio of M:1, which is used to detect the LDO output current; wherein M is a positive integer; The second NMOS tube and the third NMOS tube form a current mirror structure, which is used to copy the mirror output current to the threshold current branch for comparison; The fourth PMOS tube is the threshold current branch; The fifth PMOS tube and the sixth PMOS tube form a current mirror structure with a ratio of 1:K, which is used to mirror the overcurrent formed by the difference between the mirror output current and the threshold current to the output end of the current limiting protection unit to control the on or off state of the current limiting protection function; wherein K is a positive integer.

5. The low-dropout linear regulator with current limiting protection according to claim 4, characterized in that: In the current limiting protection unit, the gate end of the third PMOS tube is connected to the gate end of the power tube and the output end of the voltage buffer unit as an input end, the source end of the third PMOS tube is connected to the power supply voltage end, and the drain end of the third PMOS tube is connected to the drain end of the second NMOS tube; the drain end of the second NMOS tube is connected to the gate end of the third NMOS tube after being short-circuited with the gate end, and the source ends of the second NMOS tube and the third NMOS tube are both connected to the ground potential end; the drain end of the third NMOS tube is connected to the drain ends of the fourth PMOS tube and the fifth PMOS tube, and the drain end of the fifth PMOS tube is connected to the gate end of the sixth PMOS tube after being short-circuited with the gate end; the source ends of the fourth PMOS tube, the fifth PMOS tube and the sixth PMOS tube are all connected to the power supply voltage end; the gate end of the fourth PMOS tube is connected to the first bias voltage end; the drain end of the sixth PMOS tube is connected to the gate end of the power tube and the output end of the voltage buffer unit as an output end.

6. The low-dropout linear regulator with current limiting protection according to claim 2, characterized in that: Under normal load working conditions, the first PMOS tube and the second PMOS tube in the voltage buffer unit work in the saturation region, and the first NMOS tube works in the linear region; when the load gradually increases to an overload, the current limiting protection function is turned on, and the second PMOS tube in the voltage buffer unit gradually changes from working in the saturation region to the linear region, so that the gain of the voltage buffer unit gradually decreases from 1 to 0, thereby disconnecting the control of the LDO main loop.

7. The low-dropout linear regulator with current limiting protection according to claim 2, characterized in that: The first PMOS tube in the voltage buffer unit is replaced by a native NMOS tube to achieve accurate tracking of input and output voltages.

8. The low-dropout linear regulator with current limiting protection according to claim 4, characterized in that: The current limiting protection unit also includes a second error amplifier for accurately mirroring the LDO output current; wherein, The negative input terminal of the second error amplifier is connected to the LDO output terminal, the positive input terminal is connected to the drain terminals of the third PMOS tube and the second NMOS tube, and the output terminal is connected to the gate terminals of the second NMOS tube and the third NMOS tube.

9. An integrated circuit chip, characterized in that A low voltage drop linear regulator with current limiting protection as claimed in any one of claims 1 to 8.

10. An electronic device, characterized in that A low voltage drop linear regulator with current limiting protection as claimed in any one of claims 1 to 8.

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