Operating method of memory device and memory system

Abstract

The invention provides an operating method of a memory device and a memory system. An operating method of a memory device includes applying a read voltage to a selected memory page of a plurality of written memory pages. A first pass voltage is applied to unselected memory pages of the plurality of written memory pages. A second pass voltage is applied to at least one unwritten memory page, wherein the first pass voltage is greater than the second pass voltage. The memory system comprises a 3D NAND flash memory with high capacity and high performance.

Description

Technical Field

[0001] The present disclosure relates to an operating method of a memory device and a memory system, and more particularly to a reading method of a memory device and a memory system. Background Art

[0002] The write operation is an operation of writing data to a memory device. However, when performing a write operation on a memory device, the write operation may be interrupted due to a user's operation or external factors, and only the write operation of a portion of the memory pages in the selected memory block is completed. The memory block including the written memory pages and the unwritten memory pages is called an open block.

[0003] When performing a read operation on the open block, the operating window of the memory device will gradually decrease as the read operation is continuously performed. That is, applying the above pass voltage to the word line corresponding to the unwritten memory page will invisibly increase its read stress and shorten the threshold voltage window of the corresponding memory cell, which will reduce the reliability of the memory device. Summary of the invention

[0004] The present disclosure provides an operating method of a memory device, which can reduce the read pressure of at least one unwritten memory page and improve the reliability of the memory device.

[0005] In the operating method of the memory device disclosed in the present invention, the memory device includes a memory block, and the memory block includes a first memory cell string and a second memory cell string. Each of the first memory cell string and the second memory cell string includes a plurality of memory cells connected in series, wherein each memory cell in the first memory cell string and the second memory cell string connected to the same word line belongs to a written memory page or an unwritten memory page. The operating method of the memory device of the present invention includes performing the following operations. Applying a read voltage to a selected memory page among a plurality of written memory pages. Applying a first pass voltage to an unselected memory page among a plurality of written memory pages. Applying a second pass voltage to at least one unwritten memory page, wherein the first pass voltage is greater than the second pass voltage.

[0006] The present disclosure provides a memory device whose reliability can be improved.

[0007] The memory system disclosed in the present invention includes a memory device and a controller. The memory device includes a memory array, an address decoder, a voltage generator, a page buffer and a control logic. The memory array includes a plurality of memory blocks, and one of the plurality of memory blocks includes a first memory cell string and a second memory cell string. Each of the first memory cell string and the second memory cell string includes a plurality of memory cells connected in series, wherein each memory cell in the first memory cell string and the second memory cell string connected to the same word line belongs to a written memory page or an unwritten memory page. The address decoder is coupled to the memory array. The voltage generator is coupled to the address decoder to generate a voltage provided to the written memory page and the unwritten memory page. The page buffer is coupled to the memory array. The control logic is coupled to the address decoder, the voltage generator and the page buffer. The controller is coupled to the memory device. The controller issues a read command to the memory device to control a read operation performed in the memory device. According to the write state of the memory device, the control logic determines the voltage value of the pass voltage to be provided to the written memory page and the unwritten memory page in the read operation. The pass voltages include a first pass voltage applied to a written memory page and a second pass voltage applied to at least one unwritten memory page, wherein the first pass voltage is greater than the second pass voltage.

[0008] Based on the above, the present disclosure can reduce the read pressure of at least one unwritten memory page by making the first pass voltage applied to the written memory page greater than the second pass voltage applied to at least one unwritten memory page. Based on this, the possibility of shortening the threshold voltage interval of the storage cell in at least one unwritten memory page can be reduced, so as to improve the reliability of the memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 FIG. 4 is a block diagram of a memory system according to an embodiment of the present invention.

[0010] Figure 2A Based on Figure 1 A partial schematic diagram of an embodiment of a memory block in a memory array of FIG.

[0011] Figure 2B Based on Figure 1 A partial schematic diagram of another embodiment of a memory block in a memory array of FIG.

[0012] Figure 3 The flowchart is a method for operating a memory device according to an embodiment of the present invention.

[0013] Figure 4FIG. 1 is a schematic diagram of a writing sequence of memory blocks in a memory array when performing a writing operation according to an embodiment of the present invention.

[0014] Figure 5A FIG. 4 is a schematic diagram of an open block in a memory array according to an embodiment of the present invention.

[0015] Figure 5B FIG. 4 is a schematic diagram of a closed block in a memory array according to an embodiment of the present invention.

[0016] Fig. 6A It is a schematic diagram of performing a read operation on an open block in a memory array according to an embodiment of the present invention.

[0017] Figure 6B It is a schematic diagram of performing a read operation on an open block in a memory array according to another embodiment of the present invention.

[0018] Figure 6C It is a schematic diagram of performing a read operation on an open block in a memory array according to yet another embodiment of the present invention.

[0019] Description of Reference Numerals

[0020] 10: Memory system

[0021] 100: Memory device

[0022] 110: Memory cell array

[0023] 120: Address decoder

[0024] 130: Voltage generator

[0025] 140: Page Buffer

[0026] 150: Control Logic

[0027] 200: Controller

[0028] 210: Storage unit

[0029] BL, BL0, BL1, BLm-1, BLm: bit lines

[0030] BLK1, BLK2, BLKn-1, BLKn: memory blocks

[0031] BLKa1: 2D memory block

[0032] BLKb1: 3D memory block

[0033] CS0, CS1, CSm-1, CSm: storage cell string

[0034] CSL: Shared Source Line

[0035] GSL: Ground Select Line

[0036] GST: Ground Select Transistor

[0037] MCn: Storage unit

[0038] OP: How to operate

[0039] PG0, PG1, PG2, PGn, PGn+1, PGn+2, PGn+3, PG127, PG128, PG159, PG160, PG189, PG190, PG191: Memory pages

[0040] PGA, PGD: The first group of memory pages

[0041] PGB, PGE: The second group of memory pages

[0042] PGC, PGF: The third group of memory pages

[0043] S10, S20, S100, S200, S300: Steps

[0044] SSL: string select line

[0045] SST: String Select Transistor

[0046] VPASSR: First pass voltage

[0047] VPASSR′, VPASSR1′, VPASSR2′, VPASSR3′: Second pass voltage

[0048] Vread: read voltage

[0049] WL0, WL1, WLn-1, WLn: word lines

[0050] X: Second direction

[0051] Y: Third direction

[0052] Z: First direction DETAILED DESCRIPTION

[0053] The following examples are listed and described in detail with the accompanying drawings, but the examples provided are not intended to limit the scope of the present invention. In addition, the drawings are for illustration purposes only and are not drawn to their original size. For ease of understanding, the same elements will be described with the same symbols in the following description.

[0054] Figure 1 is a block diagram of a memory system according to an embodiment of the present invention, Figure 2A Based on Figure 1 A partial schematic diagram of an embodiment of a memory block in a memory array of Figure 2B Based on Figure 1 A partial schematic diagram of another embodiment of a memory block in a memory array of FIG.

[0055] Please refer to Figure 1 , which shows the memory system 10 of the present embodiment. The memory system 10 may include, for example, a three-dimensional memory, which may be, for example, a three-dimensional NAND flash memory with high capacity and high performance, but the present disclosure is not limited thereto. The memory system 10 may also include, for example, a two-dimensional memory, which may include, for example, a two-dimensional NAND flash memory. In the present embodiment, the memory system 10 includes a memory device 100 and a controller 200.

[0056] Memory device 100 may be used, for example, to store data to be accessed by an external host device (not shown). For example, memory device 100 may provide stored data to the external host device during a read operation, and may store data provided from the external host device during a write operation.

[0057] In the present embodiment, the memory device 100 includes a memory array 110 , an address decoder 120 , a voltage generator 130 , a page buffer 140 , and a control logic 150 , but the disclosure is not limited thereto.

[0058] The memory array 110 may include, for example, a plurality of memory blocks BLK1-BLK n , wherein a plurality of memory blocks BLK1 to BLK n Each of the memory blocks BLK1 may be, for example, a two-dimensional memory block or a three-dimensional memory block. Specifically, taking the memory block BLK1 as an example, the memory block BLK1 may be, for example, Figure 2A The two-dimensional memory block BLKa1 or Figure 2B The three-dimensional memory block BLKb1 is shown, but the disclosure is not limited thereto.

[0059] Please refer to Figure 2A The two-dimensional memory block BLKa1 of the present embodiment includes a plurality of memory cell strings CS0-CS m , a plurality of bit lines BL0 to BL m , a plurality of word lines WL0 to WL n , a string selection line SSL, a ground selection line GSL and a shared source line CSL.

[0060] Multiple storage cell strings CS0~CS m Each of them is connected to bit lines BL0~BL mIn some embodiments, a plurality of memory cell strings CS0-CS m Each of the bit lines BL0 to BL1 may include a string select transistor SST, a plurality of memory cells connected in series, and a ground select transistor GST. The string select transistor SST is connected to a string select line SSL, and the ground select transistor GST is connected to a ground select line GSL. In addition, the string select transistor SST may be connected to corresponding bit lines BL0 to BL2. m , and the ground selection transistor GST can be connected to the shared source line CSL. A plurality of memory cell strings CS0-CS m The memory cells in the memory are connected to the corresponding word lines WL0~WL n To form multiple memory pages. For example, connected to the same word line (eg, word line WL n ) of the memory cell string CS0 to the memory cell string CS m Each memory cell in the memory cell string may form a memory page. In some embodiments, the shared source line CSL is commonly connected to a plurality of memory cell strings CS0-CS1. m .

[0061] It is worth noting that the two-dimensional memory block BLKa1 of the present disclosure is not limited to the above embodiments.

[0062] Please refer to Figure 2B The three-dimensional memory block BLKb1 includes a plurality of memory cell strings CS0-CS m , bit line BL (including a plurality of bit lines BL0~BL m ), word lines WL (including multi-layer word lines WL o ~WL n ), string selection line SSL, ground selection line GSL and shared source line CSL. It is worth noting that in order to make the drawings simple, Figure 2B Not every memory cell string in the three-dimensional memory block BLKb1 is labeled.

[0063] Multiple storage cell strings CS0~CS m For example, the plurality of memory cell strings CS0-CS1 extend in a first direction Z. m Each of them is connected to a corresponding bit line BL0-BL extending in the second direction X. m In some embodiments, a plurality of memory cell strings CS0-CS mEach of the bit lines BL0 to BL1 may include a string selection transistor SST, a plurality of memory cells connected in series to each other, and a ground selection transistor GST. The string selection transistor SST is connected to a string selection line SSL, and the ground selection transistors GST are each connected to a ground selection line GSL. In addition, the string selection transistors SST may be connected to corresponding bit lines BL0 to BL2. m , and the ground selection transistor GST can be connected to the shared source line CSL. A plurality of memory cells are each connected to a corresponding word line WL0~WL n (which are layers extending in the second direction X and the third direction Y) to form a multi-layer memory page (which is stacked in the first direction Z). In some embodiments, the shared source line CSL is commonly connected to a plurality of memory cell strings CS0-CS m .

[0064] Please also refer to Figure 1 as well as Figure 2B The coupling relationship between the components in the memory device 100 will be described below by taking the three-dimensional memory block BLKb1 as an example.

[0065] In some embodiments, the string selection line SSL, the word line WL, and the ground selection line GSL may be controlled by the address decoder 120 , the bit line BL may be controlled by the page buffer 140 , and the shared source line CSL may be controlled by the control logic 150 .

[0066] The address decoder 120 is coupled to the memory array 110. In detail, the address decoder 120 may be coupled to the memory array 110 via word lines WL. In some embodiments, the address decoder 120 is configured to operate under the control of the control logic 150. For example, the address decoder 120 may receive address data from the outside via the control logic 150, wherein the address data may include a word line address. In some embodiments, the address decoder 120 may include a word line decoder (not shown), but the present disclosure is not limited thereto.

[0067] The word line decoder may be used to decode the word line address to apply the voltage provided by the voltage generator 130 to the corresponding word line WL according to the decoded word line address. For example, during a read operation, the word line decoder may apply a read voltage to the selected word line WL. n , and a pass voltage may be applied to unselected word lines (word lines WL n to the word line WL n The selected memory cell (e.g., memory cell string CS m The storage unit MC n ) to perform a read operation.

[0068] The voltage generator 130 is coupled to the address decoder 120 and is used to generate a voltage for a plurality of memory cell strings CS0-CS m In some embodiments, the voltage generator 130 includes a plurality of internal power supplies (not shown), and the plurality of internal power supplies are activated under the control of the control logic 150 to generate a plurality of voltages, wherein the generated plurality of voltages are applied to the corresponding word lines WL0-WL1 through the address decoder 120. n .

[0069] The page buffer 140 is coupled to the memory array 110. In some embodiments, the page buffer 140 may include a plurality of bit lines BL0-BL1. m The plurality of page buffer units (not shown) are connected to each other and operate under the control of the control logic 150. For example, during a read operation, the page buffer 140 reads data through the corresponding bit lines BL0-BL m Data of memory cells connected to the selected word line are read and output to an external host device through a data input / output unit (not shown) coupled to the page buffer 140 .

[0070] The control logic 150 is coupled to the address decoder 120, the voltage generator 130, and the page buffer 140. In some embodiments, the control logic 150 may receive a read command and address data from the controller 200, and control the address decoder 120, the voltage generator 130, and the page buffer 140 in response to the read command. In addition, the control logic 150 sends the above-mentioned address data to the address decoder 120.

[0071] The controller 200 may, for example, respond to a request from an external host device to control the memory device 100. Specifically, the controller 200 may, for example, control a read operation, a write operation, an erase operation, and / or other suitable operations of the memory device 100. For example, the controller 200 may provide data read from the memory device 100 to the external host device, and may store the data provided from the external host device in the memory device 100. In the present embodiment, the controller 200 may issue a read command to the memory array 110 in the memory device 100 to control the read operation performed in the memory device 100.

[0072] In this embodiment, the controller 200 includes a storage unit 210. When the controller 200 controls the operation of the memory device 100, the storage unit 210 can be used to record information when the memory device 100 performs a read operation, a write operation, an erase operation, and / or other operations. For example, the write status information recorded by the controller 200 includes the memory blocks BLK1-BLK n The last memory page written in a write operation.

[0073] In this embodiment, the storage unit 210 can record each memory block BLK1-BLK n Specifically, in some embodiments, the controller 200 may also control at least one memory block BLK1-BLK in the memory array 110. n The write command is issued to control a write operation performed in the memory device 100 .

[0074] Memory blocks BLK1 to BLK n The memory blocks BLK1 to BLK2 can be divided into open blocks or closed blocks according to their write status. n In the memory array 110, a memory block including only a portion of the memory pages written in the write operation and the remaining memory pages not written is called an open block, and a memory block that completes the write operation on all memory pages is called a closed block. The reason for the formation of an open block may be, for example, that the write operation is interrupted due to user operation or external factors, so that the open block may include at least one written memory page and at least one unwritten memory page. In some embodiments, the controller 200 may store each memory block BLK1-BLK2 of the memory array 110 recorded by the storage unit 210. n The write status of the memory page is used to distinguish at least one written memory page and at least one unwritten memory page.

[0075] In this embodiment, the controller 200 can store each memory block BLK1 ˜BLK of the memory array 110 recorded by the storage unit 210 n Specifically, the controller 200 may, for example, use the memory blocks BLK1-BLK recorded in the storage unit 210 to distinguish the closed blocks from the open blocks. n The last memory page written in a write operation is used to distinguish an open block. n Taking the case of a closed block as an example, the controller 200 may check the address of the last memory page written to the memory block BLK1 and the address of the last memory page written to the memory block BLK2. n The address of the last memory page of the memory block BLK1 is the same as that of the last memory page of the memory block BLK1 to determine whether all memory pages in the checked memory block BLK1 have been written, thereby judging whether the memory block BLK1 is an open block or a closed block.

[0076] In this embodiment, when performing a read operation on the memory device 100 , the controller 200 may use the information of the closed blocks and the open blocks stored in the storage unit 210 to generate a corresponding read command.

[0077] In detail, when a read operation is performed on an open block in the memory device 100, the control logic 150 may respond to a read command from the controller 200 to control the voltage generator 130 so that the voltage generator 130 may provide a corresponding operating voltage to the address decoder 120. The address decoder 120 may apply a read voltage to a selected memory page among a plurality of written memory pages, and apply a first pass voltage to an unselected memory page among a plurality of written memory pages, and apply a second pass voltage to at least one unwritten memory page. In this embodiment, the first pass voltage is greater than the second pass voltage. In some embodiments, the difference between the first pass voltage and the second pass voltage is greater than 300 mV.

[0078] By making the first pass voltage applied to the unselected memory pages among the written memory pages greater than the second pass voltage applied to at least one unwritten memory page, the read stress on the at least one unwritten memory page can be reduced. Based on this, the possibility of a reduction in the threshold voltage interval of the memory cell corresponding to the at least one unwritten memory page can be reduced, thereby improving the reliability of the memory device.

[0079] Figure 3 FIG. 1 is a flow chart of an operation method of a memory device according to an embodiment of the present invention. Figure 3 The memory device described is based on the memory device 100 mentioned above as an example, but it should be noted that the present disclosure is not limited thereto.

[0080] Please refer to Figure 3 The operation method OP of the memory device of the present embodiment includes the following steps. First, in step S10, a read command is received. Then, in step S20, a read operation is performed on a selected memory block in the memory device, wherein a read voltage is applied to a selected memory page among a plurality of written memory pages, a first pass voltage is applied to an unselected memory page among a plurality of written memory pages, and a second pass voltage is applied to at least one unwritten memory page, wherein the first pass voltage is greater than the second pass voltage.

[0081] In some embodiments, before performing step S10 , step S100 , step S200 , and step S300 may be performed in sequence; however, the present disclosure is not limited thereto.

[0082] First, in step S100, a write command is received. Then, in step S200, a write operation is performed on at least one memory block in the memory device. Next, in step S300, the write status of the memory block is recorded.

[0083] In step S100 , a write command from an external host device may be received by the controller 200 , and a write operation corresponding to the write command may be performed on the memory device 100 .

[0084] In step S200, a write operation is performed on the memory device 100. Specifically, at least one memory block BLK1-BLK in the memory array 110 of the memory device 100 may be written. n It is worth noting that Figure 4 The writing operation to the memory block BLK1 is taken as an example. Although the present embodiment takes the writing operation from the top of the memory block BLK1 to the bottom of the memory block BLK1 (from the memory page PG0 to the memory page PG1) as an example, the writing operation from the top of the memory block BLK1 to the bottom of the memory block BLK1 is taken as an example. 191 In other embodiments, the writing operation may be performed from the bottom of the memory block BLK1 to the top of the memory block BLK1 (from the memory page PG 191 To memory page PG0) for write operation.

[0085] In step S300, the write status of the memory device 100 is recorded. Specifically, in this embodiment, each memory block BLK1-BLK n As described in the above embodiment, the memory blocks BLK1-BLK n It can be divided into open blocks or closed blocks according to its writing status. For example, the following takes the writing operation of the memory blocks BLK1 and BLK2 as an example. Figure 5A As shown, the memory block BLK1 is an open block, which includes the written memory pages PG0-PG n and unwritten memory pages PG n+1 ~PG 191 In some embodiments, the memory block BLK1 includes at least one unwritten memory page PG n+1 ~PG 191 .like Figure 5B As shown, the memory block BLK2 is a closed block, which includes all written memory pages PG0-PG 191 .

[0086] After performing the above steps S100 to S300, step S10 may be performed, but the present disclosure is not limited thereto. In step S10, a read command from an external host device may be received by the controller 200, and a read operation corresponding to the read command may be performed on the memory device 100, which includes selecting a plurality of memory blocks BLK1 to BLK2 to be read in the memory array 110. n one of the.

[0087] When executing step S20, the controller 200 may store information about the plurality of memory blocks BLK1-BLK in the storage unit 210. n After the write operation is performed, the control logic 150 can respond to the read command from the controller 200 to control the voltage generator 130, so that the voltage generator 130 can generate the corresponding read voltage and pass voltage to provide to the selected multiple memory blocks BLK1~BLK n one of the.

[0088] For example, Fig. 6A As shown, when the selected memory block is the memory block BLK1 (open block), a read voltage Vread is applied to a plurality of written memory pages PG0-PG n The selected memory page (memory page PG1) in the memory is applied with a first pass voltage VPASSR to a plurality of written memory pages PG0 to PG n The unselected memory pages (memory pages PG0, PG2 to PG n ), and applying a second pass voltage VPASSR′ to at least one unwritten memory page PG n+1 ~PG 191 The at least one unwritten memory page PG n+1 ~PG 191 Also called unselected memory page PG n+1 ~PG 191 It is worth noting that the same word line (eg, word line WL n ) of a first memory cell string (eg, memory cell string CS0) and a second memory cell string (eg, memory cell string CS m ) may belong to a written memory page or an unwritten memory page, which will not be described in detail below.

[0089] In this embodiment, the written memory pages PG0-PG n The unselected memory pages (memory pages PG0, PG2 to PG n ) The first pass voltage VPASSR applied is greater than the first pass voltage VPASSR applied to at least one unwritten memory page PG n+1 ~PG 191 The applied second pass voltage VPASSR′. In some embodiments, the difference between the first pass voltage VPASSR and the second pass voltage VPASSR′ is greater than 300 mV.

[0090] Since the first pass voltage VPASSR is greater than the second pass voltage VPASSR′, it can reduce the PG of at least one unwritten memory page. n+1 ~PG 191 Based on this, the PG corresponding to at least one unwritten memory page can be reduced. n+1 ~PG 191 The possibility of reducing the threshold voltage range of the memory cell can be improved, thereby improving the reliability of the memory device 100.

[0091] In this embodiment, at least one unwritten memory page PG n+1 ~PG 191 The applied second pass voltages VPASSR′ are identical to each other; however, the present disclosure is not limited thereto.

[0092] Specifically, the at least one unwritten memory page PG n+1 ~PG 191 Contains multiple unwritten memory pages PG n+1 ~PG 191 The above-mentioned multiple unwritten memory pages PG n+1 ~PG 191 The grouping includes two groups of unwritten memory pages, which may each be a first group of unwritten memory pages and a second group of unwritten memory pages, wherein a second pass voltage applied to a first group of word lines corresponding to the first group of unwritten memory pages is different from a second pass voltage applied to a second group of word lines corresponding to the second group of unwritten memory pages.

[0093] For example, Figure 6B As shown, at least one unwritten memory page PG n+1 ~PG 191 Contains multiple unwritten memory pages PG n+1 ~PG 191 . Multiple unwritten memory pages PG n+1 ~PG 191 It can be divided into three groups, including a first group of unwritten memory pages PGA, a second group of unwritten memory pages PGB and a third group of unwritten memory pages PGC, which can each include a first group of word lines, a second group of word lines and a third group of word lines. In this embodiment, the second pass voltages VPASSR′ applied to the first group of word lines, the second group of word lines and the third group of word lines are different from each other. For the above three groups of unwritten memory pages, the reason why the applied second pass voltages VPASSR′ are different from each other may be, for example, due to the fact that in the memory blocks BLK1 to BLK n The corresponding memory cell strings (eg, memory cell strings CS0 to CS m) does not have the same size in each memory page, so a corresponding second pass voltage VPASSR′ may be applied according to the situation of each memory page.

[0094] In detail, Figure 6B As shown, when the selected memory block is the memory block BLK1 (open block), a read voltage Vread is applied to a plurality of written memory pages PG0-PG n The selected memory page (memory page PG1) in the memory is applied with a first pass voltage VPASSR to a plurality of written memory pages PG0 to PG n The unselected memory pages (memory pages PG0, PG2 to PG n ), applying a second pass voltage VPASSR1′ to a plurality of unwritten memory pages PG n+1 ~PG 191 The first group of unwritten memory pages PGA (memory page PG n+1 ~PG 127 ), applying a second pass voltage VPASSR2′ to a plurality of unwritten memory pages PG n+1 ~PG 191 The second group of unwritten memory pages PGB (memory pages PG 128 ~PG 159 ), and applying a second pass voltage VPASSR3′ to a plurality of unwritten memory pages PG n+1 ~PG 191 The third group of unwritten memory pages PGC (memory page PG 160 ~PG 191 In some embodiments, the second pass voltage VPASSR1′ is greater than the second pass voltage VPASSR2′, and the second pass voltage VPASSR2′ is greater than the second pass voltage VPASSR3′, but the present disclosure is not limited thereto.

[0095] In this embodiment, at least one unwritten memory page PG n+1 ~PG 191 Contains multiple unwritten memory pages PG n+1 ~PG 191 . For multiple unwritten memory pages PG n+1 ~PG 191The grouping includes a first group of unwritten memory pages (e.g., a first group of unwritten memory pages PGA) and a second group of unwritten memory pages (e.g., a second group of unwritten memory pages PGB), each of which includes a first group of word lines and a second group of word lines, wherein the first group of word lines and the second group of word lines each include at least two word lines adjacent to each other; however, the present disclosure is not limited to this.

[0096] In detail, the first group of word lines and the second group of word lines may each include at least two word lines that are not adjacent to each other.

[0097] For example, Figure 6C As shown, at least one unwritten memory page PG n+1 ~PG 191 Contains multiple unwritten memory pages PG n+1 ~PG 191 . Multiple unwritten memory pages PG n+1 ~PG 191 It can be divided into three groups, including a first group of unwritten memory pages PGD, a second group of unwritten memory pages PGE and a third group of unwritten memory pages PGF, which can each include a first group of word lines, a second group of word lines and a third group of word lines. In this embodiment, the first group of word lines, the second group of word lines and the third group of word lines all include at least two word lines that are not adjacent to each other.

[0098] In detail, Figure 6C As shown, when the selected memory block is the memory block BLK1 (open block), a read voltage Vread is applied to a plurality of written memory pages PG0-PG n The selected memory page (memory page PG1) in the memory is applied with a first pass voltage VPASSR to a plurality of written memory pages PG0 to PG n The unselected memory pages (memory pages PG0, PG2 to PG n ), applying a second pass voltage VPASSR1′ to a plurality of unwritten memory pages PG n+1 ~PG 191 The first group of unwritten memory pages PGD (including memory pages PG n+1 PG 189 ), applying a second pass voltage VPASSR2′ to a plurality of unwritten memory pages PG n+1 ~PG 191 The second group of unwritten memory pages PGE (including memory pages PG n+2 PG 190 ), and applying a second pass voltage VPASSR3′ to a plurality of unwritten memory pages PGn+1 ~PG 191 The third group of unwritten memory pages PGF (including memory pages PG n+3 PG 191 ).

[0099] It is worth noting that although Figure 6C It is shown that the first group of word lines, the second group of word lines, and the third group of word lines of the first group of unwritten memory pages PGD, the second group of unwritten memory pages PGE, and the third group of unwritten memory pages PGF each include at least two word lines that are not adjacent to each other, but the present disclosure is not limited thereto. For example, in other embodiments, the first group of word lines and the second group of word lines include at least two word lines that are not adjacent to each other, and the third group of word lines may include at least two word lines that are adjacent to each other.

[0100] It is worth noting that, although the operation method of the memory device 100 of the present embodiment takes the operation method of a three-dimensional memory device as an example, the operation method of the memory device 100 of the present disclosure can be applied to a two-dimensional memory device (e.g., a two-dimensional NAND flash memory). In addition, the operation method of the memory device 100 of the present disclosure can be applied to a memory cell including a single-level cell (SLC), a multi-level cell (MLC), a triple-level cell (TLC), or a quad-level cell (QLC).

[0101] In summary, the present disclosure can reduce the read pressure of at least one unwritten memory page by making the first pass voltage applied to the unselected memory page in the written memory page greater than the second pass voltage applied to at least one unwritten memory page. Based on this, the possibility of reducing the threshold voltage interval of the storage cell corresponding to at least one unwritten memory page can be reduced, thereby improving the reliability of the memory device. In other words, the present disclosure can provide a three-dimensional NAND flash memory with high capacity and high performance.

Claims

1. A method for operating a memory device, wherein the memory device comprises a memory block, the memory block comprises a first memory cell string and a second memory cell string, each of the first memory cell string and the second memory cell string comprises a plurality of memory cells connected in series, wherein each memory cell in the first memory cell string and the second memory cell string connected to the same word line belongs to a written memory page or an unwritten memory page, wherein the method comprises: Performing a read operation on the memory block in the memory device, the memory block comprising a plurality of the written memory pages and at least one unwritten memory page, wherein the read operation comprises: applying a read voltage to a selected memory page among the plurality of written memory pages; applying a first pass voltage to unselected memory pages among the plurality of written memory pages; and applying a second pass voltage to the at least one unwritten memory page, The first pass voltage is greater than the second pass voltage. 2 . The operating method of the memory device according to claim 1 , wherein a difference between the first pass voltage and the second pass voltage is greater than 300 mV.

3. The operating method of a memory device according to claim 1, wherein the at least one unwritten memory page includes a plurality of unwritten memory pages, the plurality of unwritten memory pages correspond to a first group of word lines and a second group of word lines, and the second pass voltage applied to the first group of word lines is different from the second pass voltage applied to the second group of word lines. 4 . The operating method of the memory device according to claim 3 , wherein the second pass voltage applied to the first group of word lines is greater than the second pass voltage applied to the second group of word lines. 5 . The operating method of the memory device according to claim 3 , wherein the first group of word lines and the second group of word lines each include at least two word lines adjacent to each other. 6 . The operating method of the memory device according to claim 3 , wherein the first group of word lines and the second group of word lines each include at least two word lines that are not adjacent to each other.

7. The method for operating a memory device according to claim 3, further comprising: performing a write operation on the memory device; as well as The write status of the memory block in the memory device is recorded. 8 . The operating method of the memory device according to claim 7 , wherein recording the write status of the memory block comprises distinguishing the plurality of written memory pages and the at least one unwritten memory page. 9 . The operating method of the memory device according to claim 7 , wherein a controller is used to record the write status of the memory block, and the controller is coupled to the memory device. 10 . The operating method of the memory device according to claim 8 , wherein distinguishing the plurality of written memory pages and the at least one unwritten memory page comprises recording a last memory page of the memory block written in the write operation.

11. A memory system comprising: A memory device comprising: A memory array comprising a plurality of memory blocks, wherein one of the plurality of memory blocks comprises a first memory cell string and a second memory cell string, each of the first memory cell string and the second memory cell string comprises a plurality of memory cells connected in series, wherein each memory cell in the first memory cell string and the second memory cell string connected to the same word line belongs to a written memory page or an unwritten memory page; an address decoder coupled to the memory array; A voltage generator, coupled to the address decoder, for generating a voltage provided to the written memory page and the unwritten memory page; A page buffer coupled to the memory array; and a control logic coupled to the address decoder, the voltage generator, and the page buffer; and a controller coupled to the memory device, wherein the controller issues a read command to the memory device to control a read operation performed in the memory device, wherein the control logic determines the voltage value of the pass voltage to be provided to the written memory page and the unwritten memory page in the read operation according to the write state of the memory device, The pass voltages include a first pass voltage applied to the written memory page and a second pass voltage applied to at least one of the unwritten memory pages, and the first pass voltage is greater than the second pass voltage. 12 . The memory system of claim 11 , wherein a difference between the first pass voltage and the second pass voltage is greater than 300 mV.

13. The memory system of claim 11 , wherein the at least one unwritten memory page comprises a plurality of unwritten memory pages, the plurality of unwritten memory pages corresponding to a first group of word lines and a second group of word lines, and the second pass voltage applied to the first group of word lines is different from the second pass voltage applied to the second group of word lines. 14 . The memory system of claim 13 , wherein the second pass voltage applied to the first group of word lines is greater than the second pass voltage applied to the second group of word lines. 15 . The memory system of claim 13 , wherein the first group of word lines and the second group of word lines each include at least two word lines adjacent to each other. 16 . The memory system of claim 13 , wherein the first group of word lines and the second group of word lines each include at least two word lines that are not adjacent to each other.

17. The memory system of claim 11, wherein the controller further issues a write command to the memory device and records the write status of the plurality of memory blocks in the memory device.

18. The memory system of claim 17, wherein the write status comprises a state in which at least one of the plurality of memory blocks is an open block.

19. The memory system according to claim 17, wherein the controller comprises a storage unit, and the storage unit records the write status of the plurality of memory blocks. 20 . The memory system of claim 18 , wherein the write status information recorded by the controller includes a last memory page of the memory block written in the write operation.

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