Storage device and control method thereof

Abstract

A memory device includes a memory device including a plurality of memory blocks, a temperature sensor that measures an internal temperature of the memory device, and a controller in which the temperature sensor measures a program temperature at a point in time at which data is programmed in the plurality of memory blocks, and the controller stores the program temperature at which the memory blocks are programmed, wherein the controller determines, as an error block, at least one memory block in which data programmed in the plurality of memory blocks is failed to be read, and when a program temperature and a read attempt temperature of the error block fall within a drive guarantee temperature range, the controller is configured to calculate a temperature difference between the program temperature and the read attempt temperature of the error block, the temperature difference is compared to a guaranteed size to register an error block as a bad block or a refresh candidate block.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0128832 filed in the Korean Intellectual Property Office on September 26, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Various example embodiments of the inventive concepts relate to a storage device and a control method thereof. Background Art

[0004] The storage device may include a memory device, and the memory device may include a plurality of memory blocks. A plurality of memory blocks may be divided into normal operation blocks, bad blocks, reserved blocks, etc. As a result of repeatedly performing data programming and reading into the normal operation blocks, the normal operation blocks may become read failure blocks that fail to read data. The data programmed in the read failure blocks may be sent as reserved blocks to prevent data loss, and the read failure blocks may be registered as bad blocks to prevent any more data from being programmed. However, according to the internal temperature of the storage device, data read failure may occur temporarily. When the memory blocks that failed to read can be uniformly registered as bad blocks, even the memory blocks that temporarily failed to read can also be registered as bad blocks, and therefore, data may not be programmed to waste storage space in the memory device. Summary of the invention

[0005] Various example embodiments of the inventive concept are to provide a memory device and a control method thereof, measuring a programming temperature as an internal temperature of a memory device at a time point when data is programmed in a memory block, and measuring a read attempt temperature as an internal temperature at a time point when data programmed in the memory block is attempted to be read, and using the programming temperature and the read attempt temperature to determine whether it corresponds to a temporary read failure, so as to reduce unnecessary block replacement and prevent (or reduce) consumption of reserved blocks.

[0006] Some example embodiments of the inventive concept provide a memory device, comprising: a memory device including a plurality of memory blocks; a temperature sensor configured to measure an internal temperature of the memory device; and a controller configured to control the memory device and the temperature sensor, wherein the temperature sensor is configured to measure a programming temperature at a point in time when data is programmed in each of the plurality of memory blocks by the controller, and the controller is configured to store a programming temperature of a programmed memory block whose programming temperature is outside a stable range in the memory device, wherein the controller is further configured to store a time point at which data programmed in each of the plurality of memory blocks is failed to be read. At least one memory block is determined as an error block, and when a programming temperature of the error block and a read attempt temperature at a time point when attempting to read data programmed in the error block fall within a drive guarantee temperature range, and the error block is not included in the programmed memory blocks, the controller is configured to register the error block as a bad block, and when the programming temperature and the read attempt temperature of the error block fall within the drive guarantee temperature range, and the error block is included in the programmed memory blocks, the controller is configured to calculate a temperature difference between the programming temperature and the read attempt temperature of the error block, and compare the temperature difference with a guarantee magnitude to register the error block as a bad block or a refresh candidate block.

[0007] Some example embodiments provide a memory device, the memory device comprising: a memory device including a plurality of memory blocks; a temperature sensor configured to measure an internal temperature of the memory device; a controller configured to control the memory device and the temperature sensor, program data in each of the plurality of memory blocks, and read the data programmed to each of the plurality of memory blocks, wherein the temperature sensor is configured to measure a programming temperature at a time point when programming data to each of the plurality of memory blocks, and a read attempt temperature at a time point when attempting to read the data programmed to each of the plurality of memory blocks, and wherein the controller is further configured to: program the programming temperature in the memory device, determine at least one memory block among the plurality of memory blocks that fails to be read as an error block, calculate a temperature difference corresponding to a difference between a programming temperature and a read attempt temperature of the error block, register the error block as a bad block or a refresh candidate block based on the temperature difference and a guaranteed size and whether the programming temperature and the read attempt temperature of the error block fall within a driving guaranteed temperature range, and when the internal temperature of the memory device falls within a stable range, start with a refresh operation on the refresh candidate block to re-read the data programmed in the refresh candidate block.

[0008] Some example embodiments of the inventive concept provide a method of controlling a memory device, the method comprising: measuring a programming temperature, which is an internal temperature of the memory device at a time point when data is programmed in a programming target block among a plurality of memory blocks included in the memory device; when the programming temperature is outside a stable range, programming the programming temperature to a temperature of the programming target block in the memory device; measuring a read attempt temperature, which is an internal temperature of the memory device at a time point when an attempt is made to read data programmed in a read target block among a plurality of memory blocks; when the data programmed in the read target block fails to be read, determining that the read target block is an error block, and determining a programming error of the error block; whether the programming temperature and the read attempt temperature fall within the driver guaranteed temperature range; calculating a temperature difference corresponding to the difference between the programming temperature and the read attempt temperature of the error block to compare the temperature difference with a guaranteed size; when the temperature difference is less than the guaranteed size, registering the error block as a bad block, and when the temperature difference is greater than the guaranteed size or the programming temperature and the read attempt temperature of the error block are outside the driver guaranteed temperature range, registering the error block as a refresh candidate block; and when the internal temperature of the storage device falls within a stable range, starting with a refresh operation on the refresh candidate block according to a result of re-reading the data programmed in the refresh candidate block to register the refresh candidate block as a bad block or program new data in the refresh candidate block. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features and advantages of the present invention will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a block diagram illustrating a host-storage system according to an example embodiment.

[0011] Figure 2 is a block diagram simply illustrating a memory block according to example embodiments.

[0012] Figure 3 is a view illustrating a 3D V-NAND structure applicable to a memory device according to example embodiments.

[0013] Figure 4 is a view showing threshold voltage distributions of memory cells according to example embodiments.

[0014] Figure 5 is a view illustrating a driving temperature range of a memory device according to example embodiments.

[0015] Figure 6 is a flowchart illustrating a process of programming data in a memory block according to example embodiments.

[0016] Figure 7is a view illustrating storage of programming temperatures according to data programming according to example embodiments.

[0017] Figure 8 is a flowchart illustrating a process of reading data from a memory block according to example embodiments.

[0018] Fig. 9 is a view illustrating an output of a programming temperature according to a data read failure according to example embodiments.

[0019] Fig.10 is a flowchart illustrating a process of performing a refresh operation on a memory block according to example embodiments.

[0020] Fig.11 is a view illustrating a memory device according to example embodiments.

[0021] Fig.12 is a view illustrating a system to which a storage device according to an example embodiment is applied. DETAILED DESCRIPTION

[0022] Hereinafter, various example embodiments will be described with reference to the accompanying drawings.

[0023] As described herein, an element "on" another element may be above or below another element or adjacent to another element (e.g., horizontally adjacent). An element on another element may be directly on another element, such that the element is in direct contact with the other element. An element on another element may be indirectly on another element, such that the element is isolated from the other element by one or more intervening spaces and / or structures and is not in direct contact with the other element.

[0024] It should be understood that elements and / or their properties (e.g., structures, surfaces, directions, etc.) that may be referred to as "perpendicular", "parallel", etc., relative to other elements and / or their properties (e.g., structures, surfaces, directions, etc.) may be "perpendicular", "parallel", etc., respectively relative to other elements and / or their properties, or may be "substantially perpendicular", "substantially parallel".

[0025] It should be understood that elements and / or properties thereof may be described herein as being "the same" or "equal" to other elements, and it should also be understood that elements and / or properties described herein as being "identical", "same" or "equal" to other elements may be "identical", "same" or "equal" or "substantially identical", "substantially identical" or "substantially equal" to other elements and / or properties. Elements and / or properties thereof that are "substantially identical", "substantially identical" or "substantially equal" to other elements and / or properties will be understood to include elements and / or properties that are identical, identical or equal to other elements and / or properties within manufacturing tolerances and / or material tolerances. Elements and / or properties that are identical or substantially identical and / or identical or substantially identical to other elements and / or properties may be identical or substantially identical in structure, identical or substantially identical in function, and / or identical or substantially identical in composition.

[0026] It should be understood that elements and / or properties thereof described herein as being "substantially" the same and / or identical include elements and / or properties thereof having a relative size difference of equal to or less than 10%. In addition, regardless of whether an element and / or property thereof is modified to be "substantially", it should be understood that these elements and / or properties thereof should be interpreted as including manufacturing or operating tolerances (e.g., ±10%) around the element and / or property thereof.

[0027] Figure 1 is a block diagram illustrating a host-storage system according to an example embodiment.

[0028] The host-storage system 10 may include a host 100 and a storage device 200. In addition, the storage device 200 may include a controller 210, a memory device 220, and a temperature sensor 230.

[0029] The host 100 may include an electronic device, for example, a portable electronic device such as a mobile phone, an MP3 player, a laptop computer, etc., or an electronic device such as a desktop computer, a game console, a TV, a projector, etc. The host 100 may include at least one operating system (OS). The operating system may generally manage and control the functions and operations of the host 100.

[0030] The storage device 200 may include a storage medium for storing data according to a request from the host 100. As an example, the storage device 200 may include at least one of a solid state drive (SSD), an embedded memory, or a removable external memory. In some example embodiments, when the storage device 200 is an SSD, the storage device 200 may be a device that complies with the non-volatile memory express (NVMe) standard. In some example embodiments, when the storage device 200 is an embedded memory or an external memory, the storage device 200 may be a device that complies with the universal flash storage (UFS) standard or the embedded multimedia card (eMMC) standard. The host 100 and the storage device 200 may generate and send packets according to the adopted standard protocol, respectively.

[0031] The memory device 220 may maintain stored data even when power is not supplied. The memory device 220 may store data provided from the host 100 through a program operation, and may output data stored in the memory device 220 through a read operation. The memory device 220 may include a plurality of memory blocks, and each memory block may include a plurality of pages, and each page may include a plurality of memory cells connected to a word line. In an example embodiment, the memory device 220 may be a flash memory.

[0032] In some example embodiments, when the memory device 220 of the memory device 200 includes a flash memory, the flash memory may include a 2D NAND memory array or a 3D (or vertical) NAND (VNAND) memory array. As another example, the memory device 200 may include other various types of non-volatile memories. For example, in the memory device 200, magnetic RAM (MRAM), spin-transfer torque MRAM, conductive bridge RAM (CBRAM), ferroelectric RAM (FeRAM), phase RAM (PRAM), resistive memory (resistive RAM), and various other types of memory may be applied.

[0033] The controller 210 may control the memory device 220 in response to a request from the host 100. For example, the controller 210 may provide data read from the memory device 220 to the host 100, and may program data provided from the host 100 in the memory device 220.

[0034] The controller 210 may include a host interface 211, a memory interface 212, and a central processing unit (CPU) 213. In addition, the controller 210 may further include a flash translation layer (FTL) 214, a packet manager 215, a buffer memory 216, an error correction code (ECC) 217 ​​engine, and an advanced encryption standard (AES) engine 218. The controller 210 may also include a working memory (not shown) into which the flash translation layer (FTL) 214 is loaded, and may control programming and reading operations of data of the memory device 220 by executing the flash translation layer 214 by the CPU 213.

[0035] The host interface 211 may transmit and receive packets to and from the host 100. Packets transmitted from the host 100 to the host interface 211 may include commands, data to be programmed to the memory device 220, etc., and packets transmitted from the host interface 211 to the host 100 may include responses to commands, data to be read from the memory device 220, etc.

[0036] Memory interface 212 may send data to be programmed into memory device 220 to memory device 220 or may receive data to be read from memory device 220. Memory interface 212 may be implemented to conform to a standard protocol, such as switching or Open NAND Flash Interface (ONFI).

[0037] The CPU 213 may control the overall operation of the controller 210 , and may execute the flash translation layer 214 .

[0038] The flash translation layer 214 may perform various functions, such as address mapping, wear leveling, and garbage collection. The address mapping operation may be an operation of changing a logical address received from the host 100 into a physical address for actually storing data in the memory device 220. Wear leveling may be a technique for preventing (or reducing) excessive degradation / deterioration of a particular block by ensuring that the blocks in the memory device 220 are used evenly, and may be implemented, for example, by a firmware technique for balancing the erase counts of physical blocks. Garbage collection may be a technique for protecting available capacity in the memory device 220 by copying valid data of an existing block to a new block and then erasing the existing block.

[0039] The packet manager 215 may generate a packet according to an interface protocol negotiated with the host 100, or may parse various types of information from a packet received from the host 100. In addition, the buffer memory 216 may temporarily store data to be programmed to or read from the memory device 220. The buffer memory 216 may be provided in the controller 210, but may be disposed outside the controller 210.

[0040] The ECC engine 217 may perform an error detection and correction function on the read data read from the memory device 220. More specifically, the ECC engine 217 may generate a parity bit for the write data to be written into the memory device 220, and the generated parity bit may be stored in the memory device 220 together with the write data. In some example embodiments, when reading data from the memory device 220, the ECC engine 217 may correct errors in the read data using the parity bit read from the memory device 220 and the read data, and may output the error-corrected read data.

[0041] The AES engine 218 may perform at least one of an encryption operation or a decryption operation on data input to the controller 210 using a symmetric key algorithm.

[0042] The temperature sensor 230 may measure the internal temperature of the memory device 200. For example, the temperature sensor 230 may measure a programming temperature at a time point when data is programmed in each of a plurality of memory blocks of the memory device 220 and a read attempt temperature at a time point when the programmed data is attempted to be read. The temperature sensor 230 may transmit the programming temperature and the read attempt temperature to the controller 210. For example, the controller 210 may store the programming temperature in the memory device 220, but is not limited thereto, and the programming temperature may be stored in a page, etc.

[0043] For example, the time point of attempting to read may mean the time point when the read voltage is applied to the memory block. For example, the memory device 220 may determine the memory block to be read based on the read request from the host 100. Thereafter, the memory device 220 may repeatedly apply a set of read voltages with different values ​​to read the memory block until it is determined whether the read is successful or failed, and the time point of applying the last set of read voltages may correspond to the time point of attempting to read.

[0044] In some example embodiments, when reading data programmed in each of the plurality of memory blocks fails, the controller 210 may determine whether the memory block that failed to read is processed as a bad block. The cause of the read failure may include a defective memory block of the storage device 200, an internal temperature condition, and the like. For example, when a memory block becomes defective, the memory block may be processed as a bad block because data is repeatedly programmed to and deleted from the memory block and the reading of the data fails. For example, the data stored in the corresponding memory block may be sent to a reserved block, and the corresponding memory block may be registered as a bad block so that the data may no longer be programmed.

[0045] In some example embodiments, when the difference between the programming temperature and the read attempt temperature of the memory device 200 satisfies a specific condition, the data read failure may be a temporary phenomenon. For example, when the memory device 200 satisfies the appropriately designed temperature condition, the data may be read again. Even in this case, when the memory block is consistently treated as a bad block in the same manner as when the memory block becomes defective, the reserved block may be consumed unnecessarily.

[0046] In an example embodiment, in a data read failure temporarily caused by the internal temperature of the storage device 200, a refresh operation may be performed on a memory block without treating the memory block as a bad block. For example, the memory block may be reused to reduce unnecessary block replacement and prevent (or reduce) consumption of a reserved block.

[0047] Hereinafter, before describing the memory device 200 according to example embodiments, a memory block included in the memory device 220 will be described in more detail. Figures 2 to 4 is a view illustrating in more detail a memory block included in a memory device according to example embodiments.

[0048] Figure 2 is a block diagram simply illustrating a memory block according to example embodiments.

[0049] refer to Figure 2 , the memory device 300 may include a control logic circuit 320, a memory cell array 330, a page buffer 340, a voltage generator 350, and a row decoder 360. Figure 2 Although not illustrated, the memory device 300 may further include a memory interface circuit that receives a command CMD and an address ADDR externally and exchanges data DATA externally, and may further include a column logic, a pre-decoder, a temperature sensor, a command decoder, an address decoder, and the like.

[0050] The control logic circuit 320 may generally control various operations in the memory device 300. The control logic circuit 320 may output various control signals in response to a command CMD and / or an address ADDR from the memory interface circuit. For example, the control logic circuit 320 may output a voltage control signal CTRL_vol, a row address X-ADDR, and a column address Y-ADDR.

[0051] The memory cell array 330 may include a plurality of memory blocks BLK1 to BLKz (where z is a positive integer), and each of the plurality of memory blocks BLK1 to BLKz may include a plurality of memory cells. The memory cell array 330 may be connected to the page buffer 340 through the bit lines BL, and may be connected to the row decoder 360 through the word lines WL, the string selection lines SSL, and the ground selection lines GSL.

[0052] In example embodiments, the memory cell array 330 may include a 3D memory cell array, and the 3D memory cell array may include a plurality of NAND strings. Each of the NAND strings may include memory cells respectively connected to word lines vertically stacked on a substrate. In example embodiments, the memory cell array 330 may include a two-dimensional memory cell array, and the two-dimensional memory cell array may include a plurality of NAND strings arranged in row and column directions.

[0053] The page buffer 340 may include a plurality of page buffers PB1 to PBn (where n is an integer greater than or equal to 3), and the plurality of page buffers PB1 to PBn may be connected to the memory cells respectively through a plurality of bit lines BL. The page buffer 340 may select at least one bit line among the bit lines BL in response to the column address Y-ADDR. The page buffer 340 may operate as a write driver or a sense amplifier according to the operation mode. For example, during a programming operation, the page buffer 340 may apply a bit line voltage corresponding to the data to be programmed to the selected bit line. During a read operation, the page buffer 340 may sense the data stored in the memory cell by sensing the current or voltage of the selected bit line.

[0054] The voltage generator 350 may generate various types of voltages for performing programming, reading, and erasing operations based on the voltage control signal CTRL_vol. For example, the voltage generator 350 may generate a programming voltage, a reading voltage, a programming verification voltage, an erasing voltage, etc. as the word line voltage VWL.

[0055] The row decoder 360 may select one of the plurality of word lines WL in response to the row address X-ADDR, and may select one of the plurality of string selection lines SSL. For example, the row decoder 360 may apply a program voltage and a program verification voltage to the selected word line during a program operation, and may apply a read voltage to the selected word line during a read operation.

[0056] Figure 3 1 is a diagram showing a 3D V-NAND structure applicable to a storage device according to an example embodiment. In some example embodiments, when the memory device of the storage device is implemented as a 3D V-NAND type flash memory, a plurality of memory blocks constituting the memory device may be respectively composed of Figure 3 The equivalent circuit representation is shown.

[0057] Figure 3 is a view illustrating a 3D V-NAND structure applicable to a memory device according to example embodiments.

[0058] For example, a plurality of memory NAND strings included in the memory block BLKi may be formed in a direction perpendicular to the substrate.

[0059] refer to Figure 3 , the memory block BLKi may include a plurality of memory NAND strings NS11 to NS33 connected between bit lines BL1, BL2, and BL3 and a common source line CSL. Each of the plurality of memory NAND strings NS11 to NS33 may include a string selection transistor SST, a plurality of memory cells MC1, MC2, ..., MC8, and a ground selection transistor GST. Although Figure 3 It is shown in FIG. 4 that each of the plurality of memory NAND strings NS11 to NS33 includes eight memory cells MC1 , MC2 , . . . , MC8 , but the inventive concept is not limited thereto.

[0060] The string selection transistor SST may be connected to the string selection lines SSL1, SSL2, and SSL3 corresponding thereto. A plurality of memory cells MC1, MC2, ..., MC8 may be connected to the gate lines GTL1, GTL2, ..., GTL8 corresponding thereto, respectively. The gate lines GTL1, GTL2, ..., GTL8 may correspond to word lines, and a portion of the gate lines GTL1, GTL2, ..., GTL8 may correspond to dummy word lines. The ground selection transistor GST may be connected to the ground selection lines GSL1, GSL2, and GSL3 corresponding thereto. The string selection transistor SST may be connected to the bit lines BL1, BL2, and BL3 corresponding thereto, and the ground selection transistor GST may be connected to the common source line CSL.

[0061] Word lines (eg, WL1) having the same height may be connected in common, and ground selection lines GSL1, GSL2, and GSL3 and string selection lines SSL1, SSL2, and SSL3 may be separated from each other. Figure 3 , the memory block BLKi is illustrated as being connected to eight gate lines GTL1 , GTL2 , . . . , GTL8 and three bit lines BL1 , BL2 , BL3 , but the inventive concept is not necessarily limited thereto.

[0062] Figure 4 is a view showing threshold voltage distributions of memory cells according to example embodiments.

[0063] refer to Figure 4 , in the graph, the horizontal axis indicates the magnitude of the threshold voltage, and the vertical axis indicates the number of memory cells.

[0064] exist Figure 4In the example embodiment shown in , the memory cell may correspond to a multi-level cell (MLC) storing 2-bit data, but the number of data bits stored by the memory cell is not limited thereto. In some example embodiments, when the memory cell is an MLC, the memory cell may have a threshold voltage corresponding to any one of the first programming state P1 to the fourth programming state P4. The read voltage set for distinguishing each of the first programming state P1 to the fourth programming state P4 may include a first read voltage Vb1 to a third read voltage Vb3. The first read voltage Vb1 may be a read voltage for distinguishing the first programming state P1 from the second programming state P2. The second read voltage Vb2 may be a read voltage for distinguishing the second programming state P2 from the third programming state P3. The third read voltage Vb3 may be a read voltage for distinguishing the third programming state P3 from the fourth programming state P4.

[0065] The distribution of the first programming state P1 to the fourth programming state P4 may vary depending on (or based on) the internal temperature of the storage device. For example, the distribution may vary depending on (or based on) the difference between the programming temperature of the storage device at the time point when the data is programmed in the memory block and the read attempt temperature of the storage device at the time point when the programming data is read. For example, when the programming temperature is higher than the read attempt temperature, the center of the distribution of the first programming state P1 to the fourth programming state P4 may move to the left or right, and / or the degree of the distribution of the first programming state P1 to the fourth programming state P4 may increase or decrease. As another example, when the programming temperature is lower than the read attempt temperature, the center of the distribution of the first programming state P1 to the fourth programming state P4 may move to the right or left, and / or the degree of the distribution of the first programming state P1 to the fourth programming state P4 may decrease or increase. As another example, as the difference between the programming temperature and the read attempt temperature increases, the center of the distribution of the first programming state P1 to the fourth programming state P4 may move with a higher magnitude, and / or the degree of the distribution of the first programming state P1 to the fourth programming state P4 may change with a higher magnitude.

[0066] The distribution of the first to fourth programming states P1 to P4 may include an overlapping area, and an error bit may occur in the overlapping area to cause a data read failure. According to example embodiments, when a difference occurs between a programming temperature of a memory device and a read attempt temperature, an overlapping area of ​​the distribution of the first to fourth programming states P1 to P4 may increase. For example, the number of data read failure cases may increase.

[0067] A storage device according to an example embodiment may include a temperature sensor that measures an internal temperature of the storage device. For example, the temperature sensor may measure a programming temperature at a time point when data is programmed in each of a plurality of memory blocks, and a read attempt temperature at a time point when the programmed data is read. When determining whether to perform a refresh operation on a memory block that failed to read data, a controller included in the storage device may use the programming temperature and the read attempt temperature. For example, it may be determined whether a read failure is a temporary read failure of a memory block caused by a temperature difference between the programming temperature and the read attempt temperature to reduce the number of situations to be processed as bad blocks.

[0068] Figure 5 is a view illustrating a driving temperature range of a memory device according to example embodiments.

[0069] The storage device according to the example embodiment may have a driving temperature range 400, and the driving temperature range 400 may include a driving guarantee temperature range 420 and a driving non-guaranteed temperature range 440. The driving guarantee temperature range 420 may correspond to a range of internal temperatures at which the storage device can be normally driven. For example, when the internal temperature of the storage device falls within the driving guarantee temperature range 420, normal driving of the storage device can be guaranteed.

[0070] In some example embodiments, when the internal temperature of the memory device is outside the driving guarantee temperature range 420 and falls within the driving non-guaranteed temperature range 440, normal driving of the memory device may not be guaranteed. In example embodiments, a programming temperature, which is the internal temperature of the memory device at a time point when programming data in each of a plurality of memory blocks, and a read attempt temperature, which is the internal temperature of the memory device at a time point when attempting to read the programmed data, fall within the driving non-guaranteed temperature range 440, registration of the corresponding memory block as a bad block may be postponed, and a refresh operation may be performed.

[0071] A storage device according to an example embodiment may have a guaranteed size. The guaranteed size may be compared with a temperature difference, which may be a difference between a programming temperature and a read attempt temperature. In some example embodiments, when the temperature difference is greater than the guaranteed size, bad block processing may be postponed. According to an example embodiment, when a read fails, depending on (or based on) a comparison result between the temperature difference and the guaranteed size, a corresponding memory block may be registered as a bad block, or a refresh operation may be performed on the corresponding memory block.

[0072] The operation guarantee temperature range 420 may correspond to a temperature range between a maximum driving temperature TMAX and a minimum driving temperature TMIN, and the maximum driving temperature TMAX may correspond to a temperature higher than the minimum driving temperature TMIN. According to an example embodiment, the driving guarantee temperature range 420 may include a first temperature section TZ1 and a second temperature section TZ2. The size of the first temperature section TZ1 and the size of the second temperature section TZ2 may be the same, and these sizes may be guaranteed sizes. In an example, the guaranteed size may be greater than half the size of the driving guarantee temperature range 420.

[0073] According to example embodiments, the first temperature zone TZ1 may correspond to a zone from a maximum driving temperature TMAX to a first temperature T1, and the first temperature T1 may correspond to a temperature lower than the maximum driving temperature TMAX by a guaranteed amount. The second temperature zone TZ2 may correspond to a zone from a minimum driving temperature TMIN to a second temperature T2, and the second temperature T2 may correspond to a temperature higher than the minimum driving temperature TMIN by a guaranteed amount.

[0074] The storage device according to the example embodiment may have a stable range SZ. The stable range SZ may correspond to a range of the internal temperature of the storage device in which the data programmed to the memory block will not fail to read. For example, when the programming temperature is outside the stable range SZ and the read attempt temperature falls within the stable range SZ, the temperature difference may always be less than the guaranteed size. For another example, when the read attempt temperature is outside the stable range SZ and the programming temperature falls within the stable range SZ, the temperature difference may always be less than the guaranteed size. Therefore, when at least one of the programming temperature or the read attempt temperature falls within the stable range SZ, a read failure due to the internal temperature of the storage device may not occur.

[0075] The stable range SZ may correspond to a portion of the drive guarantee temperature range 420, and specifically, may correspond to an area where the first temperature zone TZ1 and the second temperature zone TZ2 overlap. For example, when the internal temperature of the storage device at the time point of programming data falls within the stable range SZ, the temperature may not be stored in the memory device. For example, when the internal temperature of the storage device at the time point of programming data falls within the stable range SZ and data reading fails, the corresponding data block may be registered as a bad block. In addition, according to example embodiments, when the internal temperature of the storage device falls within the stable range SZ, the failed data reading may be attempted again.

[0076] Figure 6 is a flowchart illustrating a process of programming data in a memory block according to example embodiments. Figure 7 is a view illustrating storage of programming temperatures according to data programming according to example embodiments.

[0077] The storage device may include a memory device, a controller, a temperature sensor, etc. The memory device may include a plurality of memory blocks. The temperature sensor may measure the internal temperature of the storage device and may send the measured temperature to the controller. The controller may control the memory device and the temperature sensor.

[0078] according to Figure 6 In the example embodiment shown in FIG. 1 , a host may request data to be programmed into a memory device (S100). Thereafter, a controller may program data into a memory block (S110), and the programmed data may correspond to data provided by the host. A temperature sensor may measure a programming temperature at a point in time when data is programmed into a memory block (S120).

[0079] according to Figure 6 In the example embodiment shown, the controller may determine whether the programming temperature is outside the stable range (S130). For example, the stable range may correspond to a portion of the drive guarantee temperature range of the storage device, and some example embodiments of the stable range may be similar to Figure 5 For example, when the programming temperature is not outside the stable range (No in S130), the process of programming data may be terminated without storing the programming temperature of the program memory block.

[0080] In some example embodiments, when the programming temperature is outside the stable range (Yes in S130), the controller may store a memory block whose programming temperature is outside the stable range as a programmed memory block in the memory device (S140), and store the programming temperature of the programmed memory block in the memory device (S150).

[0081] In an example embodiment, the programming temperature may be higher than Figure 5 The maximum driving temperature TMAX is shown. For example, the programming temperature may fall within the driving non-guaranteed temperature range. In some example embodiments, the controller may store the corresponding memory block as a programming memory block in the memory device, and the programming temperature of the programming memory block may be stored in the memory device.

[0082] refer to Figure 7, showing the 101st to 103rd memory blocks. The controller may store data in a memory device (NVM), and specifically, may program the data in a plurality of memory blocks, respectively. In some example embodiments, the temperature sensor may measure a programming temperature, which is an internal temperature of the memory device. For example, the controller may program data in each of the 101st to 103rd memory blocks. The programming temperature of the 101st memory block may be T101, the programming temperature of the 102nd memory block may be T102, and the programming temperature of the 103rd memory block may be T103.

[0083] According to example embodiments, when data is programmed multiple times in each of a plurality of memory blocks, the temperature sensor may measure the internal temperature of the storage device multiple times while the data is programmed. In some example embodiments, the controller may determine the highest value among the measured internal temperatures as the programming temperature. For example, when data is programmed multiple times in the 101st memory block, the temperature sensor may measure the internal temperature of the storage device multiple times while the data is programmed, and the controller may determine T101, which is the highest value among the measured internal temperatures, as the programming temperature.

[0084] According to an example embodiment, the temperature sensor can send the programmed temperature to the controller. The controller can determine whether the programmed temperature is outside the stable range. Figure 6 In the example embodiment described in , the programming temperature may be stored only when the programming temperature is outside the stable range. For example, a memory block whose programming temperature is outside the stable range may be stored as a programming memory block, and the programming temperature of the programming memory block may be stored.

[0085] refer to Figure 7 , the programming temperature data may be stored to form a table. For example, the programming temperature of each programming memory block may be stored to form a table. However, the inventive concept is not limited thereto, and the programming temperature data may be stored to form a queue or a list. For example, Figure 7 As shown, if the controller determines that T101 and T103 are outside the stable range and T102 is not outside the stable range, the 102nd memory block and T102 may not be stored.

[0086] and Figure 6 Unlike the example shown in FIG. 1 , in an example embodiment, the controller may store the programmed temperature regardless of whether the programmed temperature is outside the stable range. For example, the Figure 6 Operations S130 and S140 of the present invention may be performed, and even when the programming temperature is not outside the stable range, the programming temperature of the memory block may be stored. For example, the programming temperature measured by the temperature sensor may be stored. Figure 7Unlike shown in , the 102 th memory block and T102 may be stored as programming temperature data.

[0087] Figure 8 is a flowchart illustrating a process of reading data from a memory block according to example embodiments. Fig. 9 is a view illustrating an output of a programming temperature according to a data read failure according to example embodiments.

[0088] The storage device may include a memory device, a controller, a temperature sensor, etc. The memory device may include a plurality of memory blocks. The temperature sensor may measure the internal temperature of the storage device and may send the measured temperature to the controller. The controller may control the memory device and the temperature sensor.

[0089] according to Figure 8 In the example embodiment shown in FIG. 1 , the host may request to read data programmed in the memory device ( S200 ). The controller may attempt to read the data programmed in the memory block, and the temperature sensor may measure the read attempt temperature at the time point of attempting to read the data programmed in the memory block ( S210 ).

[0090] In some example embodiments, when the read data does not fail (No in S220), the controller may output the read data to the host (S270). For example, when the read data fails (Yes in S220), the controller may determine the memory block that failed to read as an error block (S230).

[0091] Thereafter, the controller may determine whether the programming temperature and the read attempt temperature of the error block fall within the driving guarantee temperature range (S235). For example, the storage device may have a driving guarantee temperature range, and some example embodiments may be similar to Figure 5 In some example embodiments, when the programming temperature and the read attempt temperature of the error block do not fall within the driving guarantee temperature range (No in S235), the controller may register the error block as a refresh candidate block (S280).

[0092] In some example embodiments, when the programming temperature and the read attempt temperature of the error block fall within the driving guarantee temperature range (Yes in S235), the controller may determine whether the programming temperature of the error block is outside the stable range (S240). Figure 6 In the illustrated example embodiment, when only the programming temperature of the program memory block and the memory block determined as the program memory block are stored, it can be determined whether the programming temperature of the error block is outside the stable range by whether the error block is included in the program memory block. Figure 6In an example embodiment not shown in FIG. 1 , when all memory blocks and programming temperatures are stored, whether the programming temperature of the error block is outside the stable range may be determined by whether the stored programming temperature is outside the stable range.

[0093] In some example embodiments, when the programming temperature of the error block is not outside the stable range (No in S240), the controller may process the error block as a bad block (S290). Even when the memory block read fails, in the memory block whose programming temperature is within the stable range, the temperature difference between the programming temperature and the read attempt temperature may not have a value greater than the guaranteed size. For example, in this case, the read failure may not be due to the internal temperature of the storage device. Therefore, the time period required (or used) for processing can be shortened by immediately registering (or by registering) the memory block as a bad block instead of registering it as a refresh candidate block.

[0094] In some example embodiments, when the programming temperature of the error block is outside the stable range (Yes in S240), the controller may calculate a temperature difference of the error block (S250), and the temperature difference may correspond to a difference between the programming temperature and the read attempt temperature. The controller may compare the temperature difference with the guaranteed size, and may register the error block as a bad block or a refresh candidate block. For example, the storage device may have a guaranteed size, and some example embodiments of the guaranteed size may be similar to Figure 5 Those described in .

[0095] In some example embodiments, when the temperature difference is less than the guaranteed size (No in S260), the controller may process the error block as a bad block (S290). In some example embodiments, when the temperature difference is greater than the guaranteed size (Yes in S260), the controller may register the error block as a refresh candidate block (S280).

[0096] refer to Fig. 9 , showing the 101st to 103rd memory blocks. The controller may attempt to read data programmed in a memory device (NVM), and specifically, may attempt to read data programmed in a plurality of memory blocks, respectively. In some example embodiments, a temperature sensor may measure a read attempt temperature, which is an internal temperature of the memory device. According to an example embodiment, the temperature sensor may send the read attempt temperature to the controller. For example, the controller may attempt to read data programmed in each of the 101st to 103rd memory blocks.

[0097] According to example embodiments, when the controller fails to read data, the memory block corresponding thereto may be determined as an error block. The controller may calculate the temperature difference only for the error block whose programming temperature and read attempt temperature fall within the driving guarantee temperature range and whose programming temperature is outside the stable range.

[0098] For example, in an error block included in a program memory block, the controller may calculate a temperature difference using stored program temperature data and a read attempt temperature. Fig. 9 As shown, only the programming memory block and the programming temperature of the programming memory block may be stored as programming temperature data. Therefore, the temperature difference may be calculated only for the error block whose programming temperature is outside the stable range.

[0099] As another example, in an error block where the programming temperature is outside of a stable range, the controller can calculate the temperature difference using the stored programming temperature data and the read attempt temperature. Fig. 9 Unlike the example shown, the programming temperature data may include all memory blocks and the programming temperatures of all memory blocks. For example, the 102nd memory block and T102 may be stored in the programming temperature data. Therefore, the temperature difference may be calculated after determining whether the programming temperature of the error block is outside the stable range.

[0100] The controller may determine whether the temperature difference is greater than a guaranteed size, and depending on (or based on) the result therefrom, the erroneous block may be registered as a refresh candidate block or a bad block.

[0101] Fig.10 is a flowchart illustrating a process of performing a refresh operation on a memory block according to example embodiments.

[0102] The storage device may include a memory device, a controller, a temperature sensor, etc. The memory device may include a plurality of memory blocks. The temperature sensor may measure the internal temperature of the storage device and may send the measured temperature to the controller. The controller may control the memory device and the temperature sensor.

[0103] Can be executed on refresh candidate blocks Fig.10 The operation of determining whether a block corresponds to a refresh candidate block can be similar to the operation previously described in Figure 8 . According to the example embodiment, when the internal temperature of the storage device can be within the stable range, a refresh operation can be started on the refresh candidate block. Thereafter, the controller can determine whether the data programmed in the refresh candidate block is re-read and whether the programming temperature of the refresh candidate block falls within the drive guarantee temperature range. Depending on (or based on) the determination result, new data can be programmed in the refresh candidate block, or the refresh candidate block can be registered as a bad block.

[0104] First, the temperature sensor may measure the internal temperature of the storage device (S300). The controller may determine whether the internal temperature of the storage device falls within a stable range (S310). For example, the stable range may correspond to a portion of the drive guaranteed temperature range of the storage device, and some example embodiments of the stable range may be similar to Figure 5Those described in .

[0105] In some example embodiments, when the internal temperature of the memory device does not fall within the stable range (No in S310), the temperature sensor may repeat the operation of measuring the internal temperature of the memory device (S300). For example, when the internal temperature of the memory device falls within the stable range (Yes in S310), the controller may start with a refresh operation on the refresh candidate block (S320). The refresh operation may be performed by Fig.10 For example, the refresh operation may include an operation of re-reading data programmed in the refresh candidate block to reprogram the data to the reserved block, and an operation of programming new data in the refresh candidate block.

[0106] In some example embodiments, when the data programmed in the refresh candidate block has not failed to be reread (No in S330), the controller may program new data in the refresh candidate block (S340). For example, the refresh candidate block may be reused without registering it as a bad block, and unnecessary use of the reserved block may be prevented (or reduced). In some example embodiments, when the data programmed in the refresh candidate block has failed to be reread (Yes in S330), the controller may determine whether the programming temperature of the refresh candidate block falls within the driving guarantee temperature range (S350). In some example embodiments, when the programming temperature of the refresh candidate block does not fall within the driving guarantee temperature range (No in S350), the new data may be programmed in the refresh candidate block.

[0107] In some example embodiments, when the programming temperature of the refresh candidate block falls within the driving guarantee temperature range (Yes in S350), the controller may register the refresh candidate block as a bad block (S360). In an example embodiment, the controller may send the data programmed in the refresh candidate block to the new block. For example, the new block may correspond to a reserved block, and data loss may be prevented (or reduced) by the sending process of programming data. After that, no data is programmed in the refresh candidate block.

[0108] Next, we will refer to Fig.11 and Fig.12 Examples of a structure of a memory device to which the inventive concept is applied and a system to which the inventive concept is applied are described.

[0109] Fig.11 is a view illustrating a memory device according to example embodiments.

[0110] refer to Fig.11, the memory device 600 may have a chip-to-chip (C2C) structure. The C2C structure may refer to a structure formed by manufacturing an upper chip including a cell area CELL on a first wafer, manufacturing a lower chip including a peripheral circuit area PERI on a second wafer different from the first wafer, and then bonding the upper chip and the lower chip to each other through a bonding process. For example, the bonding process may refer to a method of electrically connecting a bonding metal formed on the uppermost metal layer of the upper chip and a bonding metal formed on the uppermost metal layer of the lower chip. For example, when the bonding metal is formed of copper (Cu), the bonding method may be a Cu-Cu bonding method, and the bonding metal may also be formed of aluminum or tungsten.

[0111] Each of the peripheral circuit region PERI and the cell region CELL of the memory device 600 may include an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA. The peripheral circuit region PERI may include a first substrate 710, an interlayer insulating layer 715, a plurality of circuit elements 720a, 720b, and 720c formed on the first substrate 710, a first metal layer (730a, 730b, and 730c) connected to the plurality of circuit elements 720a, 720b, and 720c, respectively, and a second metal layer (740a, 740b, and 740c) formed on the first metal layer (730a, 730b, and 730c). In example embodiments, the first metal layer (730a, 730b, and 730c) may be formed of tungsten having a relatively high resistivity, and the second metal layer (740a, 740b, and 740c) may be formed of copper having a relatively low resistivity.

[0112] In some example embodiments, only the first metal layer (730a, 730b, and 730c) and the second metal layer (740a, 740b, and 740c) are shown and described, but example embodiments are not limited thereto, and at least one or more metal layers may be further formed on the second metal layer (740a, 740b, and 740c). At least a portion of the one or more metal layers formed on the second metal layer (740a, 740b, and 740c) may be formed of aluminum or the like having a lower resistance than copper forming the second metal layer (740a, 740b, and 740c).

[0113] The interlayer insulating layer 715 may be disposed on the first substrate 710 to cover the plurality of circuit elements 720a, 720b, and 720c, the first metal layer (730a, 730b, and 730c), and the second metal layer (740a, 740b, and 740c), and may include an insulating material such as silicon oxide, silicon nitride, or the like.

[0114] A lower bonding metal (771b and 772b) may be formed on the second metal layer 740b in the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metal (771b and 772b) in the peripheral circuit area PERI may be electrically bonded to the upper bonding metal (871b and 872b) of the cell area CELL. The lower bonding metal (771b, 772b) and the upper bonding metal (871b, 872b) may be formed of aluminum, copper, tungsten, or the like. The upper bonding metal (871b and 872b) of the cell area CELL may be referred to as a first metal pad, and the lower bonding metal (771b and 772b) of the peripheral circuit area PERI may be referred to as a second metal pad.

[0115] The cell region CELL may include at least one memory block. The cell region CELL may include a second substrate 810 and a common source line 820. On the second substrate 810, a plurality of word lines 831 to 838 (e.g., 830) may be stacked in a direction (Z-axis direction) perpendicular to the upper surface of the second substrate 810. A string selection line and a ground selection line may be arranged above and below the plurality of word lines 830, respectively, and the plurality of word lines 830 may be arranged between at least one string selection line and at least one ground selection line.

[0116] In the bit line bonding area BLBA, the channel structure CH may extend in a direction perpendicular to the upper surface of the second substrate 810, and may pass through a plurality of word lines 830, string selection lines, and ground selection lines. The channel structure CH may include a data storage layer, a channel layer, a buried insulating layer, and the like, and the channel layer may be electrically connected to the first metal layer 850c and the second metal layer 860c. For example, the first metal layer 850c may be a bit line contact, and the second metal layer 860c may be a bit line. In example embodiments, the bit line may extend in a first direction (Y-axis direction) parallel to the upper surface of the second substrate 810.

[0117] exist Fig.11 In the illustrated example embodiment, a region in which a channel structure CH, a bit line, and the like are disposed may be defined as a bit line bonding region BLBA. In the bit line bonding region BLBA, the bit line may be electrically connected to a circuit element 720c providing a page buffer 893 in the peripheral circuit region PERI. The bit line may be connected to upper bonding metals 871c and 872c in the peripheral circuit region PERI, and the upper bonding metals 871c and 872c may be connected to lower bonding metals (771c and 772c) connected to the circuit element 720c of the page buffer 893.

[0118] In the word line bonding area WLBA, the word line 830 may extend in a second direction (X-axis direction) parallel to the upper surface of the second substrate 810 and perpendicular to the first direction, and may be connected to a plurality of cell contact plugs 841 to 847 (e.g., 840). The plurality of word lines 830 and the plurality of cell contact plugs 840 may be connected to each other in a pad provided by at least a portion of the plurality of word lines 830 extending in different lengths in the second direction. The first metal layer 850b and the second metal layer 860b may be sequentially connected to the upper portions of the plurality of cell contact plugs 840, and the plurality of cell contact plugs 840 are connected to the plurality of word lines 830. The plurality of cell contact plugs 840 may be connected to the peripheral circuit region PERI through the upper bonding metal (871b and 872b) of the cell region CELL in the word line bonding area WLBA and the lower bonding metal (771b and 772b) of the peripheral circuit region PERI.

[0119] The cell contact plug 840 may be electrically connected to the circuit element 720b forming the row decoder 894 in the peripheral circuit region PERI. In example embodiments, the operation voltage of the circuit element 720b of the row decoder 894 may be different from the operation voltage of the circuit element 720c forming the page buffer 893. For example, the operation voltage of the circuit element 720c forming the page buffer 893 may be greater than the operation voltage of the circuit element 720b forming the row decoder 894.

[0120] The common source line contact plug 880 may be disposed in the external pad bonding area PA. The common source line contact plug 880 may be formed of a conductive material such as a metal, a metal compound, polysilicon, etc., and may be electrically connected to the common source line 820. The first metal layer 850a and the second metal layer 860a may be sequentially stacked on the upper portion of the common source line contact plug 880. For example, a region in which the common source line contact plug 880, the first metal layer 850a, and the second metal layer 860a are disposed may be defined as the external pad bonding area PA.

[0121] The input / output pads 705 and 805 may be disposed in the external pad bonding area PA. Fig.11, a lower insulating film 701 covering the lower surface of the first substrate 710 may be formed under the first substrate 710, and a first input / output pad 705 may be formed on the lower insulating film 701. The first input / output pad 705 may be connected to at least one of a plurality of circuit elements 720a, 720b, and 720c disposed in the peripheral circuit region PERI through the first input / output contact plug 703, and may be separated from the first substrate 710 by the lower insulating film 701. In some example embodiments, a side insulating film may be disposed between the first input / output contact plug 703 and the first substrate 710 to electrically separate the first input / output contact plug 703 and the first substrate 710.

[0122] refer to Fig.11 , an upper insulating film 801 covering the upper surface of the second substrate 810 may be formed on the second substrate 810, and a second input / output pad 805 may be disposed on the upper insulating film 801. The second input / output pad 805 may be connected to at least one of the plurality of circuit elements 720a, 720b, and 720c disposed in the peripheral circuit region PERI through a second input / output contact plug 803.

[0123] In some example embodiments, the second substrate 810 and the common source line 820 may not be disposed in a region where the second input / output contact plug 803 is disposed. In addition, the second input / output pad 805 may not overlap the word line 830 in the third direction (Z-axis direction). Fig.11 The second input / output contact plug 803 may be separated from the second substrate 810 in a direction parallel to the upper surface of the second substrate 810 , and may pass through the interlayer insulating layer 815 of the cell region CELL to be connected to the second input / output pad 805 .

[0124] In some example embodiments, the first input / output pad 705 and the second input / output pad 805 may be selectively formed. For example, the memory device 600 may include only the first input / output pad 705 disposed on the first substrate 710, or may include only the second input / output pad 805 disposed on the second substrate 810. Alternatively, the memory device 600 may include both the first input / output pad 705 and the second input / output pad 805.

[0125] In each of the external pad bonding area PA and the bit line bonding area BLBA respectively included in the cell area CELL and the peripheral circuit area PERI, a metal pattern to be disposed on the uppermost metal layer may be set as a dummy pattern, or the uppermost metal layer may not exist.

[0126] In the external pad bonding area PA, the memory device 600 may include a lower metal pattern 773a corresponding to an upper metal pattern 872a formed in the uppermost metal layer of the cell area CELL, and having the same cross-sectional shape in the uppermost metal layer of the peripheral circuit area PERI as the upper metal pattern 872a of the cell area CELL to be connected to each other. In the peripheral circuit area PERI, the lower metal pattern 773a formed in the uppermost metal layer of the peripheral circuit area PERI may also not be connected to the contact. Similarly, in the external pad bonding area PA, an upper metal pattern corresponding to the lower metal pattern formed in the uppermost metal layer of the peripheral circuit area PERI may be formed in the uppermost metal layer of the cell area CELL, and the upper metal pattern has the same shape as the lower metal pattern of the peripheral circuit area PERI.

[0127] The lower bonding metal (771b and 772b) may be formed on the second metal layer 740b in the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metal (771b and 772b) of the peripheral circuit area PERI may be electrically connected to the upper bonding metal (871b and 872b) of the cell area CELL by bonding.

[0128] In addition, in the bit line bonding area BLBA, an upper metal pattern 892 may be formed in the uppermost metal layer of the cell area CELL, the upper metal pattern 892 corresponding to the lower metal pattern 752 formed in the uppermost metal layer of the peripheral circuit area PERI and having the same cross-sectional shape as the lower metal pattern 752 of the peripheral circuit area PERI. A contact may not be formed on the upper metal pattern 892 formed in the uppermost metal layer of the cell area CELL.

[0129] In some example embodiments, a reinforcement metal pattern may be formed corresponding to a metal pattern formed on an uppermost metal layer of one of the cell region CELL or the peripheral circuit region PERI and having the same cross-sectional shape as a metal pattern formed on an uppermost metal layer of the other of the cell region CELL or the peripheral circuit region PERI. No contact may be formed in the reinforcement metal pattern.

[0130] According to an example embodiment, a storage device may include a memory device 600 and a temperature sensor. The memory device 600 may include a plurality of memory blocks storing data, and the temperature sensor may measure the internal temperature of the memory device. For example, when data programmed in each of the plurality of memory blocks fails to be read, a refresh operation may be performed by determining whether the read failure is temporary. Specifically, by determining whether the read failure is temporary using the condition of the internal temperature of the storage device, it may be determined whether to perform a refresh operation on the memory block corresponding thereto. For example, when the read failure is temporary, determination as a bad block may be postponed, and a refresh operation may be performed to reuse the memory device 600, thereby improving its lifespan.

[0131] Fig.12 is a view illustrating a system to which a storage device according to an example embodiment is applied.

[0132] Fig.12 The system 1000 may basically be a mobile system such as a mobile phone, a smart phone, a tablet personal computer (PC), a wearable device, a healthcare device, or an Internet of Things (IOT) device, but example embodiments are not limited thereto. Fig.12 The system 1000 is not necessarily limited to mobile systems and may be used in vehicles, such as personal computers, laptop computers, servers, media players, automotive equipment (such as navigation systems), and the like.

[0133] refer to Fig.12 , system 1000 may include a main processor 1100, memories 1200a and 1200b, and storage devices 1300a and 1300b, and may also include at least one of an image capture device 1410, a user input device 1420, a sensor 1430, a communication device 1440, a display 1450, a speaker 1460, a power supply device 1470, or a connection interface 1480.

[0134] The main processor 1100 may control the overall operation of the system 1000, and more specifically, control operations of other components constituting the system 1000. The main processor 1100 may be implemented as a general-purpose processor, a dedicated processor, an application processor, or the like.

[0135] The main processor 1100 may include at least one CPU core 1110, and may further include a controller 1120 for controlling memories 1200a and 1200b and / or storage devices 1300a and 1300b. According to an example embodiment, the main processor 1100 may further include an accelerator 1130, which may be a dedicated circuit for high-speed data operations such as artificial intelligence (AI) data operations, etc. The accelerator 1130 may include a graphics processing unit (GPU), a neural processing unit (NPU), and / or a data processing unit (DPU), etc., and may be implemented as a separate chip physically independent of other components of the main processor 1100.

[0136] The memories 1200a and 1200b may be used as main memory devices of the system 1000 and may include volatile memories such as SRAM and / or DRAM, but may also include non-volatile memories such as flash memory, PRAM and / or RRAM, etc. The memories 1200a and 1200b may be implemented in the same package with the main processor 1100.

[0137] The storage devices 1300a and 1300b may be used as non-volatile storage devices that store data regardless of whether power is supplied or not, and may have a relatively larger storage capacity than the memories 1200a and 1200b. The storage devices 1300a and 1300b may include storage controllers 1310a and 1310b, and non-volatile memories (NVM) 1320a and 1320b for storing data under the control of the storage controllers 1310a and 1310b. The non-volatile memories 1320a and 1320b may include flash memories having a 2D (2-dimensional) structure or a 3D (3-dimensional) vertical NAND (V-NAND) structure, but may include other types of non-volatile memories such as PRAM and / or RRAM, etc.

[0138] The storage devices 1300a and 1300b may be included in the system 1000 in a state of being physically separated from the main processor 1100, or may be implemented in the same package together with the main processor 1100. In addition, the storage devices 1300a and 1300b may have a shape such as a solid state device (SSD) or a memory card to be detachably coupled to other components of the system 1000 through an interface such as a connection interface 1480 described later. Such storage devices 1300a and 1300b may be devices to which a standard protocol such as universal flash storage (UFS), embedded multimedia card (eMMC), or non-volatile memory express (NVMe) is applied, but the inventive concept is not necessarily limited thereto.

[0139] The storage devices 1300a and 1300b according to example embodiments may include a temperature sensor. The temperature sensor may measure the internal temperature of the storage devices 1300a and 1300b. For example, when a read failure occurs in a memory block of the storage devices 1300a and 1300b, information on the internal temperature may be used to determine whether the read failure is a temporary read failure. For example, when the read failure is a temporary read failure, the storage devices 1300a and 1300b may perform a refresh operation on the memory block and reuse the memory block, rather than treating the memory block as a bad block, to improve its lifespan.

[0140] The image capturing device 1410 may capture still images or moving images and may be a camera, a camcorder, and / or a webcam, etc.

[0141] The user input device 1420 may receive various types of data of the system 1000 input by a user, and may be a touch pad, a keypad, a keyboard, a mouse, and / or a microphone, among others.

[0142] The sensor 1430 may detect various types of physical quantities that may be acquired from the outside of the system 1000, and may convert the sensed physical quantities into electrical signals. Such a sensor 1430 may be a temperature sensor, a pressure sensor, an illumination sensor, a position sensor, an acceleration sensor, a biosensor, and / or a gyro sensor, etc.

[0143] The communication device 1440 may transmit and receive signals between other devices outside the system 1000 according to various communication protocols. Such a communication device 1440 may be implemented to include an antenna, a transceiver, and / or a modem, etc.

[0144] Display 1450 and speaker 1460 may be used as output devices for outputting visual information and auditory information, respectively, to a user of system 1000 .

[0145] The power supply device 1470 may appropriately convert power supplied from a battery (not shown) installed in the system 1000 and / or an external power source, and may supply the converted power to each component of the system 1000 .

[0146] The connection interface 1480 may provide a connection between the system 1000 and an external device that may be connected to the system 1000, and may exchange data with the system 1000. The connection interface 1480 may be implemented in various interface methods, such as Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), PCI express (PCIe), NVMe, IEEE 1394, Universal Serial Bus (USB), Secure Digital (SD) card, MultiMediaCard (MMC), eMMC, UFS, Embedded Universal Flash Storage (eUFS), Compact Flash (CF) card interface, etc.

[0147] According to example embodiments, when reading data stored in a memory block fails, it can be determined whether the temporary read failure is due to the internal temperature of the memory device. The life of the memory device can be improved by reusing the memory block determined to be a temporary read failure instead of treating it as a bad block to reduce the consumption of the reserved block.

[0148] Various advantages and effects of the present inventive concept are not limited to the above and can be more easily understood through the description of some exemplary embodiments.

[0149] One or more of the elements disclosed above may include or be implemented in a processing circuit, such as hardware including logic circuits; a hardware / software combination, such as a processor that executes software; or a combination thereof. For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc.

[0150] While certain example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A storage device, comprising: a memory device comprising a plurality of memory blocks; a temperature sensor configured to measure an internal temperature of the storage device; as well as a controller configured to control the memory device and the temperature sensor, wherein the temperature sensor is configured to measure a programming temperature at a point in time when data is programmed in each of the plurality of memory blocks by the controller, and the controller is configured to store the programming temperature of a programmed memory block whose programming temperature is outside a stable range in the memory device, Wherein, the controller is further configured as: determining at least one memory block in which the data programmed in each of the plurality of memory blocks fails to be read as an error block, When the programming temperature of the error block and a read attempt temperature at a time point of attempting to read the data programmed in the error block fall within a driving guarantee temperature range and the error block is not included in the program memory blocks, the controller is configured to register the error block as a bad block, and When the programming temperature and the read attempt temperature of the error block fall within the driving guaranteed temperature range and the error block is included in the programming memory block, the controller is configured to calculate a temperature difference between the programming temperature and the read attempt temperature of the error block, and compare the temperature difference with a guaranteed size to register the error block as a bad block or a refresh candidate block.

2. The storage device according to claim 1, wherein: The drive guarantee temperature range corresponds to a temperature range in which the storage device is normally driven, and The stable range corresponds to a part of the driving guaranteed temperature range.

3. The storage device according to claim 2, wherein: The driving guaranteed temperature range includes a first temperature section and a second temperature section, and the driving guaranteed temperature range also includes a maximum driving temperature and a minimum driving temperature, The first temperature section corresponds to a section between the maximum driving temperature and a temperature lower than the maximum driving temperature by a certain amount, and The second temperature section corresponds to a section between the lowest driving temperature and a temperature higher than the lowest driving temperature by the guaranteed value.

4. The storage device according to claim 3, wherein: The guaranteed size is larger than half the size of the driving guaranteed temperature range.

5. The storage device according to claim 4, wherein: The stable range corresponds to a region where the first temperature section and the second temperature section overlap.

6. The storage device according to claim 1, wherein: When data is programmed multiple times to each memory block of the plurality of memory blocks, The temperature sensor is configured to measure an internal temperature of the memory device at a plurality of time points when the data is programmed, and The controller is configured to determine a highest value among the measured internal temperatures as the programmed temperature.

7. The storage device according to claim 1, wherein: The controller is configured to process the error block as a bad block when the temperature difference is less than the guaranteed size.

8. The storage device according to claim 1, wherein: The controller is configured to register the error block as a refresh candidate block when the temperature difference is greater than the guaranteed size or when the programming temperature and the read attempt temperature of the error block are outside a driving guaranteed temperature range.

9. The storage device according to claim 8, wherein: The controller is configured to re-read data programmed in the refresh candidate block starting with a refresh operation on the refresh candidate block when an internal temperature of the memory device falls within the stable range.

10. The storage device according to claim 9, wherein: The controller is configured to: When data programmed in the refresh candidate block fails to be re-read and the programming temperature of the refresh candidate block falls within the driving guarantee temperature range, registering the refresh candidate block as a bad block, and When data programmed in the refresh candidate block fails to be re-read and the programming temperature of the refresh candidate block is outside the driving guarantee temperature range, new data is programmed in the refresh candidate block.

11. The storage device according to claim 9, wherein: The controller is configured to program new data in the refresh candidate block when data programmed in the refresh candidate block is successfully re-read.

12. A storage device comprising: a memory device comprising a plurality of memory blocks; a temperature sensor configured to measure an internal temperature of the storage device; as well as a controller configured to control the memory device and the temperature sensor, program data in each of the plurality of memory blocks, and read the data programmed into each of the plurality of memory blocks, wherein the temperature sensor is configured to measure a programming temperature at a time point when the data is programmed into each of the plurality of memory blocks, and a read attempt temperature at a time point when an attempt is made to read the data programmed into each of the plurality of memory blocks, and Wherein, the controller is further configured as: programming the programming temperature in the memory device, determining at least one memory block among the plurality of memory blocks that fails to be read as an error block, calculating a temperature difference corresponding to a difference between the programming temperature and the read attempt temperature of the error block, registering the error block as a bad block or a refresh candidate block based on the temperature difference and the guaranteed size and whether the programming temperature and the read attempt temperature of the error block fall within a drive guaranteed temperature range, and When the internal temperature of the memory device falls within a stable range, a refresh operation on the refresh candidate block is started to re-read data programmed in the refresh candidate block.

13. The storage device according to claim 12, wherein: The driving guarantee temperature range corresponds to a temperature range in which the storage device is normally driven, and the driving guarantee temperature range includes a first temperature section and a second temperature section, and also includes a maximum driving temperature and a minimum driving temperature, The first temperature section corresponds to a section between the maximum driving temperature and a temperature lower than the maximum driving temperature by a certain amount, and The second temperature section corresponds to a section between the lowest driving temperature and a temperature higher than the lowest driving temperature by the guaranteed value.

14. The storage device according to claim 13, wherein: The guaranteed size is greater than half the size of the driving guaranteed temperature range, and The stable range corresponds to a region where the first temperature section and the second temperature section overlap.

15. The storage device according to claim 14, wherein: When data is programmed multiple times to each memory block of the plurality of memory blocks, The temperature sensor is configured to measure an internal temperature of the memory device at a plurality of time points when the data is programmed, and The controller is configured to determine a highest value among the measured internal temperatures as the programmed temperature.

16. The storage device according to claim 12, wherein: The controller is configured to: When the temperature difference is less than the guaranteed size, registering the error block as a bad block, and When the temperature difference is greater than the guaranteed size, or when the programming temperature and the read attempt temperature of the error block are outside the driving guaranteed temperature range, the error block is registered as a refresh candidate block.

17. The storage device according to claim 16, wherein: The controller is configured to register the refresh candidate block as a bad block when data programmed in the refresh candidate block fails to be re-read and the programming temperature of the refresh candidate block falls within the driving guarantee temperature range.

18. The storage device according to claim 16, wherein: The controller is configured to program new data in the refresh candidate block when data programmed in the refresh candidate block fails to be re-read and the programming temperature of the refresh candidate block is outside the driving guarantee temperature range.

19. A method for controlling a storage device, comprising: measuring a programming temperature, the programming temperature being an internal temperature of the memory device at a point in time when data is programmed in a programming target block among a plurality of memory blocks included in the memory device; When the programming temperature is outside a stable range, programming the programming temperature to a temperature of the programming target block in the memory device; measuring a read attempt temperature, the read attempt temperature being an internal temperature of the memory device at a time point of attempting to read data programmed in a read target block among the plurality of memory blocks; When the data programmed in the read target block fails to be read, determining the read target block to be an error block, and determining whether the programming temperature and the read attempt temperature of the error block fall within a driving guarantee temperature range; calculating a temperature difference corresponding to a difference between the programming temperature and the read attempt temperature of the error block to compare the temperature difference with a guaranteed size; When the temperature difference is less than the guaranteed size, registering the error block as a bad block, and when the temperature difference is greater than the guaranteed size or the programming temperature and the read attempt temperature of the error block are outside the driving guaranteed temperature range, registering the error block as a refresh candidate block; as well as When the internal temperature of the storage device falls within the stable range, the refresh candidate block is registered as a bad block or new data is programmed in the refresh candidate block by starting a refresh operation on the refresh candidate block according to a result of rereading data programmed in the refresh candidate block.

20. The method according to claim 19, wherein: The registering the refresh candidate block as a bad block or programming new data in the refresh candidate block comprises: When data programmed in the refresh candidate block fails to be re-read and the programming temperature of the refresh candidate block falls within the driving guarantee temperature range, treating the refresh candidate block as a bad block; and When data programmed in the refresh candidate block fails to be reread and the programming temperature of the refresh candidate block is outside the driving guarantee temperature range, or when data programmed in the refresh candidate block succeeds in being reread, new data is programmed in the refresh candidate block.

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