Multi-threaded Dynamic Binary Translation Method, Device, Equipment and Product

Abstract

The present invention discloses a multi-threaded dynamic binary translation method, apparatus, device and product, including: respectively establishing a cache table and a prediction table; the execution thread searches whether the address of the code block to be translated is recorded in the cache table, if it is recorded, the corresponding translated code block is executed, if it is not recorded, after the translation thread translates the code block to be translated, the execution thread executes it; further, according to preset conditions, the target code block recorded in the prediction table is selected for translation. The present invention can realize multi-threaded binary translation through the mutual cooperation of the execution thread and the translation thread; by means of the instantaneously updated cache table, it avoids repeated translation of the same code block and reduces the waste of computing resources; by means of the instantaneously updated prediction table, it can pre-translate the target code block with a high jump frequency, thereby improving the overall efficiency of binary translation, reducing the program startup time, and better meeting the requirements of different hardware platforms.

Description

Technical Field

[0001] The present invention belongs to the field of dynamic binary translation, and in particular, relates to a multi-threaded dynamic binary translation method, device, equipment, and product. Background Art

[0002] In the current computer field, the x86 architecture has established a mature and large software ecosystem with its wide application in the desktop and server markets. This ecosystem contains a large number of efficient and stable software developed and optimized for the x86 architecture. However, with the rapid development of embedded devices, the Internet of Things, and mobile computing, other architectures such as ARM and RISC-V have gradually gained attention. These emerging architectures, with the characteristics of low power consumption and high performance, have promoted their applications in low-power and high-performance scenarios. However, due to the immaturity of the software ecosystems of these emerging architectures, it severely restricts the wide use of emerging architectures and the improvement of user experience.

[0003] The emergence of dynamic binary translation technology provides an important means to solve the above problems. By dynamically translating the binary code of the x86 architecture into the machine code of the target architecture during program execution, software can run compatibly on different hardware platforms. This technology not only protects existing software investments but also significantly reduces the migration cost of new hardware architectures and greatly improves cross-platform compatibility. However, in practical applications, existing dynamic binary translation technologies have problems such as repeated translation of the same code blocks, wasting a large amount of computing resources and significantly extending the program startup time. At the same time, they fail to effectively allocate translation tasks, resulting in uneven load or resource contention among threads and failing to fully utilize the hardware parallel processing capabilities. Summary of the Invention

[0004] In view of this, the present invention aims to overcome the defects in the prior art and proposes a multi-threaded dynamic binary translation method, device, equipment, and product.

[0005] To achieve the above object, the technical solution of the present invention is realized as follows:

[0006] In a first aspect, the present invention discloses a multi-threaded dynamic binary translation method, including:

[0007] Establish a cache table and a prediction table respectively, where the cache table is used to record the address of the translated code block and the address of the translated code block, and the prediction table is used to record the address and the number of times the translated code block jumps to the target code block;

[0008] The execution thread searches whether the address of the code block to be translated is recorded in the cache table. If it is recorded, the corresponding translated code block is executed. If it is not recorded, after the translation thread translates the code block to be translated, it is executed by the execution thread, and the address of the code block to be translated that is not recorded and the address of the corresponding translated code block are recorded in the cache table;

[0009] According to preset conditions, the target code block recorded in the prediction table is selected for translation, and the address of the target code block for translation and the address of the corresponding translated code block are recorded in the cache table.

[0010] In another embodiment of the present invention, the method further includes: establishing a sorting table, which is used to immediately record the execution time sorting of the translated code blocks. When the cache table record is full, according to the execution time sorting, the record of the translated code block that has not been executed for the longest time is deleted, and the corresponding storage space is synchronously released.

[0011] In another embodiment of the present invention, selecting the target code block recorded in the prediction table for translation according to preset conditions includes: determining the target code block for translation according to the number of jumps of the target code block recorded in the prediction table.

[0012] In another embodiment of the present invention, determining the target code block for translation according to the number of jumps of the target code block recorded in the prediction table includes: translating the target code blocks in the first several positions after sorting the number of jumps in descending order.

[0013] In another embodiment of the present invention, the method further includes: translating the adjacent code blocks of the code block to be translated currently being translated, and recording the address of the adjacent code blocks and the address of the corresponding translated code blocks in the cache table.

[0014] In another embodiment of the present invention, the execution thread updates the records in the prediction table.

[0015] In another embodiment of the present invention, before selecting the target code block recorded in the prediction table for translation according to preset conditions, it further includes: if the address of the target code block is recorded in the cache table, the corresponding target code block is not translated.

[0016] In a second aspect, the present invention discloses a multi-thread dynamic binary translation device, and the device includes:

[0017] A table establishment module, which is used to establish a cache table and a prediction table respectively. Among them, the cache table is used to record the address of the translated code block and the address of the translated code block, and the prediction table is used to record the address and the number of times of the target code block jumped by the translated code block;

[0018] An execution module, configured to execute a thread to search whether the address of the code block to be translated has been recorded in the cache table. If it has been recorded, the corresponding translated code block is executed. If it has not been recorded, after the translation thread translates the code block to be translated, the execution thread executes it, and the address of the code block to be translated that has not been recorded and the address of the corresponding translated code block are recorded in the cache table;

[0019] A pre-translation module, configured to select a target code block recorded in the prediction table for translation according to preset conditions, and record the address of the translated target code block and the address of the corresponding translated code block in the cache table.

[0020] In a third aspect, the present invention discloses an electronic device, including: one or more processors; a storage device, configured to store one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors are caused to execute the above method.

[0021] In a fourth aspect, the present invention discloses a computer program product, including a computer program, which implements the above method when executed by a processor.

[0022] Compared with the prior art, the present invention has the following advantages:

[0023] The present invention discloses a multi-threaded dynamic binary translation method, apparatus, device, and product, including: respectively establishing a cache table and a prediction table; an execution thread searches whether the address of the code block to be translated has been recorded in the cache table. If it has been recorded, the corresponding translated code block is executed. If it has not been recorded, after the translation thread translates the code block to be translated, the execution thread executes it; further, according to preset conditions, a target code block recorded in the prediction table is selected for translation, and the address of the translated target code block and the address of the corresponding translated code block are recorded in the cache table. The multi-threaded dynamic binary translation method, apparatus, device, and product disclosed by the present invention can realize multi-threaded binary translation through the mutual cooperation of the execution thread and the translation thread; by means of the instantaneously updated cache table, it is possible to avoid repeated translation of the same code block and reduce the waste of computing resources; by means of the instantaneously updated prediction table, it is possible to pre-translate the target code block with a high jump frequency, thereby improving the overall efficiency of binary translation, reducing the program startup time, and better adapting to the requirements of different hardware platforms. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The drawings constituting a part of the present invention are used to provide a further understanding of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation to the present invention.

[0025] In the drawings:

[0026] Figure 1 Schematic diagram of an application scenario of a multi-threaded dynamic binary translation method according to an embodiment of the present invention;

[0027] Figure 2 Schematic diagram of a multi-threaded dynamic binary translation method according to an embodiment of the present invention;

[0028] Figure 3 Schematic diagram of releasing space in a cache table by a multi-threaded dynamic binary translation method according to an embodiment of the present invention;

[0029] Figure 4 Schematic diagram of adjacent code blocks for translation by a multi-threaded dynamic binary translation method according to an embodiment of the present invention;

[0030] Figure 5 Schematic diagram of a multi-threaded dynamic binary translation device according to an embodiment of the present invention;

[0031] Figure 6 Schematic diagram of an electronic device for multi-threaded dynamic binary translation according to an embodiment of the present invention. Detailed implementation manners

[0032] It should be noted that, without conflict, the embodiments in the present invention and the features in the embodiments may be combined with each other.

[0033] In the description of the present invention, it should be noted that, unless otherwise clearly defined and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention may be understood according to specific situations.

[0034] In the description of the present invention, it should be further noted that the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first", "second", etc. may explicitly or implicitly include one or more of such features. In the description of the present invention, unless otherwise stated, the meaning of "a plurality" is two or more.

[0035] The application scenarios of a multi-threaded dynamic binary translation method, device, equipment and product disclosed by the present invention are as Figure 1As shown, under the existing technical conditions, the existing dynamic binary translation technology has problems such as repeating the translation of the same code block, wasting a large amount of computing resources, significantly extending the program startup time, and failing to fully utilize the hardware parallel processing ability. The present invention discloses a multi-threaded dynamic binary translation method, device, equipment, and product, including respectively establishing a cache table and a prediction table; and being able to select, according to preset conditions, the target code block recorded in the prediction table for translation, and record the address of the translated target code block and the address of the corresponding translated code block into the cache table. The multi-threaded dynamic binary translation method, device, equipment, and product disclosed by the present invention can achieve multi-threaded binary translation through the mutual cooperation of the execution thread and the translation thread; by means of the instantaneously updated cache table, avoid repeating the translation of the same code block, and reduce the waste of computing resources; by means of the instantaneously updated prediction table, the target code block with a high jump frequency can be translated in advance, thereby improving the overall efficiency of binary translation, reducing the program startup time, and improving the fluency of program operation.

[0036] The present invention will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

[0037] In an embodiment of the present invention, as Figure 2 shown, a multi-threaded dynamic binary translation method includes:

[0038] Step S201, respectively establish a cache table and a prediction table, where the cache table is used to record the address of the translated code block and the address of the translated code block, and the prediction table is used to record the address and the number of times of the jump from the translated code block to the target code block;

[0039] In this embodiment, both the cache table and the prediction table are hash tables. The key of the prediction table is the address of the currently translated code block, and the value is the list of target code blocks that this translated code block is to jump to.

[0040] Step S202, the execution thread searches whether the address of the code block to be translated has been recorded in the cache table. If it has been recorded, the corresponding translated code block is executed. If it has not been recorded, after the translation thread translates the code block to be translated, it is executed by the execution thread, and the address of the code block to be translated that has not been recorded and the address of the corresponding translated code block are recorded into the cache table;

[0041] In this embodiment, during the dynamic binary translation process, the execution thread searches, for the program to be translated, according to the program flow, block by block, whether the address of the code block to be translated has been recorded in the cache table.

[0042] In this embodiment, if the address of the code block to be translated has been recorded in the cache table, the corresponding translated code block is directly executed to achieve non-repetitive translation of the code block.

[0043] The execution thread updates the records in the prediction table.

[0044] Step S203: According to preset conditions, select the target code blocks recorded in the prediction table for translation, and record the addresses of the target code blocks to be translated and the corresponding addresses of the translated code blocks into the cache table.

[0045] In this embodiment, multiple translation threads are provided, which can translate several target code blocks in parallel at the same time. Cooperating with the code blocks to be translated that are being translated simultaneously, multi-threaded simultaneous translation is achieved, significantly improving the program startup speed and operation.

[0046] In this embodiment, before step S203, it further includes: if the address of the target code block has been recorded in the cache table, the corresponding target code block is not translated.

[0047] This embodiment can achieve multi-threaded binary translation through the mutual cooperation of the execution thread and the translation thread; by means of the cache table updated in real time, it avoids repeated translation of the same code blocks and reduces the waste of computing resources; by means of the prediction table updated in real time, it can translate in advance the target code blocks with a high jump frequency, thereby improving the overall efficiency of binary translation and reducing the program startup time.

[0048] Based on the previous embodiment, in another embodiment of the present invention, as Figure 3 shown, the multi-threaded dynamic binary translation method further includes: establishing a sorting table, which is used to immediately record the execution time sorting of the translated code blocks. When the cache table record is full, according to the execution time sorting, delete the record of the translated code block that has not been executed for the longest time, and synchronously release the corresponding storage space.

[0049] In this embodiment, the sorting table is a doubly linked list. Each translated code block to be executed is inserted into the head of the list, indicating the most recently executed translated code block, while the tail indicates the translated code block that has not been executed for the longest time.

[0050] This embodiment can immediately release the storage space corresponding to the cache table, realize the dynamic management of the cache, and reduce redundancy and storage space occupation.

[0051] Based on the previous embodiment, in another embodiment of the present invention, as Figure 2 shown, in step S203, according to preset conditions, selecting the target code blocks recorded in the prediction table for translation includes: determining the target code blocks to be translated according to the number of jumps of the target code blocks recorded in the prediction table.

[0052] Furthermore, in this embodiment, translate the target code blocks in the first several positions in descending order of the number of jumps.

[0053] Exemplarily, the number of the first several bits can be set as needed, for example, the first three bits.

[0054] In this embodiment, according to the setting situation, the target code blocks with high jump frequencies can be translated in advance, and the selection range of the target code blocks to be translated in advance can be freely adjusted, so as to improve the overall binary translation efficiency and reduce the program startup time.

[0055] Based on the previous embodiment, in another embodiment of the present invention, as Figure 4 shown, the method further includes: translating adjacent code blocks of the code block to be translated currently, and recording the addresses of the adjacent code blocks and the addresses of the corresponding translated code blocks into a cache table.

[0056] In this example, the adjacent code blocks can be translated using independent translation threads.

[0057] In this embodiment, there are multiple translation threads. Exemplarily, one of the translation threads is used to translate the adjacent code blocks, and the other multiple translation threads respectively perform one-to-one parallel translations on multiple target code blocks.

[0058] The translation of the adjacent code blocks reflects the principle of spatial locality, and the target code blocks reflect the activity degree of future code blocks. The two forms of adjacent code blocks and target code blocks are respectively independently translated using translation threads in advance, and the two cooperate with each other, effectively improving the overall efficiency of binary translation and reducing the program startup time.

[0059] Exemplarily, for example, an ELF file of an x86 application needs to run on a RISC-V platform and needs to be translated. According to the program entry in the ELF file, the execution thread starts from the code block to be translated 0x1000, and searches whether the address of the code block to be translated 0x1000 has been recorded in the cache table. If it has been recorded, the translated code block corresponding to the code block to be translated 0x1000 is directly executed;

[0060] If it has not been recorded, the execution thread notifies the translation thread to translate the code block to be translated 0x1000;

[0061] After the translation thread finishes the translation, it sends the address of the translated code block to the execution thread for execution. At the same time, the address of the code block to be translated 0x1000 and the address of the corresponding translated code block are recorded into the cache table, and the address of the code block to be translated 0x1000 is inserted into the head of the sorting table, indicating that it has been recently used for execution;

[0062] The cache table is updated to include the address of the code block 0x1000 to be translated and the address of the corresponding translated code block, and the head of the sorting table is updated to the address of the code block 0x1000 to be translated.

[0063] Another translation thread translates the adjacent blocks of the current code block 0x1000 to be translated, such as 0x1010 and 0x1020, and at the same time records the addresses of the corresponding translated code blocks in the cache table, and further inserts the addresses of the code blocks 0x1010 and 0x1020 to be translated into the head of the sorting table;

[0064] The cache table is updated to include the code blocks 0x1000, 0x1010, and 0x1020 to be translated and the addresses of the corresponding translated code blocks, and the sorting table is updated to have the code block 0x1020 to be translated at the head, followed by the code block 0x1010 to be translated, and the code block 0x1000 to be translated at the tail.

[0065] The prediction table records show that the historical jump targets of the code block 0x1000 to be translated are the code blocks 0x2000 (jumped 5 times), 0x3000 (jumped 3 times), and 0x4000 (jumped 2 times). In addition, multiple translation threads parallelly translate the code blocks 0x2000, 0x3000, and 0x4000 to be translated, record them in the cache table, and update the head of the sorting table.

[0066] The cache table is updated to include the code blocks 0x1000, 0x1010, 0x1020, 0x2000, 0x3000, 0x4000 to be translated and the addresses of the corresponding translated code blocks, and the sorting table is updated to have the code block 0x4000 to be translated at the head, followed by the code blocks 0x3000, 0x2000, 0x1020, 0x1010, and 0x1000 in sequence.

[0067] When the cache table is full and a new record of the code block 0x5000 to be translated is needed, the record of the code block 0x1000 to be translated at the tail of the sorting table is deleted, the record of 0x1000 is removed from the cache table, and the corresponding storage space is synchronously released.

[0068] The cache table is updated to include the code blocks 0x5000, 0x4000, 0x3000, 0x2000, 0x1020, 0x1010 to be translated; the sorting table is updated to have 0x5000 at the head and 0x1010 at the tail;

[0069] As Figure 5 shown, the present invention also discloses a multi-threaded dynamic binary translation device, including:

[0070] The table creation module 501 is used to create a cache table and a prediction table respectively. The cache table is used to record the address of the code block to be translated and the address of the translated code block. The prediction table is used to record the address and the number of times that the code block to be translated jumps to the target code block.

[0071] The execution module 502 is used to execute a thread to search whether the address of the code block to be translated is recorded in the cache table. If it is recorded, the corresponding translated code block is executed. If it is not recorded, after the translation thread translates the code block to be translated, the execution thread executes it, and the address of the code block to be translated that is not recorded and the address of the corresponding translated code block are recorded into the cache table.

[0072] The pre-translation module 503 is used to select the target code block recorded in the prediction table for translation according to a preset condition, and record the address of the translated target code block and the address of the corresponding translated code block into the cache table.

[0073] The present invention also discloses an electronic device, such as Figure 6 shown, which discloses an embodiment, and is a block diagram of an electronic device applicable to the above multi-threaded dynamic binary translation.

[0074] The electronic device 60 of this embodiment includes a processor 601, which can perform various appropriate actions and processes according to the program stored in the ROM 602 or the program loaded from the storage section 608 into the RAM 603. The processor 601 can include, for example, a general microprocessor, an instruction set processor, and / or a related chipset and / or a dedicated microprocessor, etc. The processor 601 can also include on-board memory for caching purposes. The processor 601 can include a single processing unit or multiple processing units for performing different actions of the method flow according to the embodiment of the present invention.

[0075] In the RAM 603, various programs and data required for the operation of the electronic device 60 are stored. The processor 601, the ROM 602, and the RAM 603 are connected to each other through a bus 604. The processor 601 performs various operations of the method flow according to the embodiment of the present invention by executing the programs in the ROM 602 and / or the RAM 603. It should be noted that the program can also be stored in one or more memories other than the ROM 602 and the RAM 603, and the processor 601 can also perform various operations of the method flow according to the embodiment of the present invention by executing the programs stored in one or more memories.

[0076] According to an embodiment of the present invention, the electronic device 60 may further include an I / O interface 605, and the I / O interface 605 is also connected to the bus 604. The electronic device 60 may further include one or more of the following components connected to the I / O interface 605: an input portion 606 including a keyboard, a mouse, etc.; an output portion 607 including a cathode ray tube, a liquid crystal display, a speaker, etc.; a storage portion 608 including a hard disk, etc.; and a communication portion 609 including a network interface card such as a LAN card, a modem, etc. The communication portion 609 performs communication processing via a network such as the Internet. The drive 6010 is also connected to the I / O interface 605 as needed. A removable medium 6011, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 6010 as needed, so that a computer program read from it is installed into the storage portion 608 as needed.

[0077] The present invention also provides a computer-readable storage medium.

[0078] The computer-readable storage medium may be included in the electronic device / device system described in the above embodiment; or it may exist separately without being assembled into the electronic device / device. The above computer-readable storage medium carries one or more programs, and when the above one or more programs are executed, the method according to the embodiment of the present invention is implemented.

[0079] According to an embodiment of the present invention, the computer-readable storage medium may be a non-volatile computer-readable storage medium. For example, it may include but is not limited to: a portable computer disk, a hard disk, a random access memory RAM, a read-only memory ROM, an erasable programmable read-only memory EPROM or a flash memory, a portable compact disk read-only memory CD-ROM, an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present invention, the computer-readable storage medium may be any tangible medium that contains or stores a program, and the program can be used by or combined with an instruction execution system, device, or device.

[0080] An embodiment of the present invention further includes a computer program product.

[0081] The computer program product includes a computer program, and the computer program contains program codes for executing the method provided by the embodiment of the present invention. When the computer program product runs on an electronic device, the program codes are used to cause the electronic device to implement the method provided by the embodiment of the present invention.

[0082] In one embodiment, the computer program may rely on tangible storage media such as optical storage devices and magnetic storage devices. In another embodiment, the computer program may also be transmitted and distributed in the form of signals on a network medium. The program code included in the computer program may be transmitted using any suitable network medium, including but not limited to: wireless, wired, etc., or any suitable combination of the above.

[0083] According to an embodiment of the present invention, the program code for executing the computer program provided by the embodiments of the present invention may be written in any combination of one or more programming languages. Specifically, these computing programs may be implemented using high-level procedures and / or object-oriented programming languages. Programming languages include but are not limited to, for example, Java, C++, Python, C language, or similar programming languages. The program code may be executed entirely on the user's computing device, partially on the user's device, partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device may be connected to the user's computing device through any type of network, including a local area network or a wide area network, or may be connected to an external computing device.

[0084] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, a program segment, or a part of code that contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than that marked in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram or flowchart, and the combination of blocks in the block diagram or flowchart, may be implemented using a dedicated hardware-based system for performing the specified functions or operations, or may be implemented using a combination of dedicated hardware and computer instructions. Those skilled in the art will understand that the features recited in the various embodiments and / or claims of the present invention may be combined and / or combined in various ways, even if such combinations or combinations are not explicitly recited in the present invention. In particular, without departing from the spirit and teachings of the present invention, the features recited in the various embodiments and / or claims of the present invention may be combined and / or combined in various ways. All such combinations and / or combinations fall within the scope of the present invention.

[0085] The embodiments of the present invention have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present invention. Although the embodiments have been described separately above, this does not mean that the measures in each embodiment cannot be used advantageously in combination. The scope of the present invention is defined by the appended claims and their equivalents, and without departing from the scope of the present invention, those skilled in the art can make various substitutions and modifications, and all such substitutions and modifications should fall within the scope of the present invention.

Claims

1. A multi-threaded dynamic binary translation method, characterized in that: include: Establishing a cache table and a prediction table respectively, wherein the cache table is used to record the address of the translated code block and the address of the translated code block, and the prediction table is used to record the address and number of times the translated code block jumps to the target code block; The execution thread searches whether the address of the code block to be translated has been recorded in the cache table. If it has been recorded, the corresponding translated code block is executed. If it has not been recorded, the translation thread translates the code block to be translated, which is then executed by the execution thread, and the address of the code block to be translated that has not been recorded and the corresponding address of the translated code block are recorded in the cache table. According to preset conditions, the target code block recorded in the prediction table is selected for translation, the target code block with high jump frequency is translated in advance, and the address of the translated target code block and the corresponding address of the translated code block are recorded in the cache table; The step of selecting the target code block recorded in the prediction table for translation according to a preset condition comprises: determining the target code block for translation according to the number of jumps of the target code block recorded in the prediction table; determining the target code block for translation according to the number of jumps of the target code block recorded in the prediction table comprises: translating the target code blocks with the first several digits in descending order of the number of jumps; translating the adjacent code blocks of the code block to be translated currently being translated, and recording the addresses of the adjacent code blocks and the corresponding addresses of the translated code blocks in the cache table.

2. A multi-threaded dynamic binary translation method according to claim 1, characterized in that: The method further includes: establishing a sorting table, the sorting table being used to instantly record the execution time sorting of the translated code blocks, and when the cache table records are full, deleting the records of the translated code blocks that have not been executed for the longest time according to the execution time sorting, and synchronously releasing the corresponding storage space.

3. A multi-threaded dynamic binary translation method according to claim 1, characterized in that: The execution thread updates the records in the prediction table.

4. A multi-threaded dynamic binary translation method according to claim 1, characterized in that: Before selecting the target code block recorded in the prediction table for translation according to the preset condition, the method further includes: if the address of the target code block has been recorded in the cache table, the corresponding target code block is not translated.

5. A multi-threaded dynamic binary translation device, characterized in that: The device comprises: A table establishment module, used to establish a cache table and a prediction table respectively, wherein the cache table is used to record the address of the translated code block and the address of the translated code block, and the prediction table is used to record the address and number of times the translated code block jumps to the target code block; An execution module, configured to execute a thread to search whether the address of the code block to be translated has been recorded in the cache table, and if so, to execute the corresponding translated code block; if not, the translation thread translates the code block to be translated, which is then executed by the execution thread, and the address of the code block to be translated that has not been recorded and the address of the corresponding translated code block are recorded in the cache table; The pre-translation module is used to select the target code block recorded in the prediction table for translation according to preset conditions, translate the target code block with high jump frequency in advance, and record the address of the translated target code block and the corresponding address of the translated code block in the cache table; the selecting the target code block recorded in the prediction table for translation according to the preset conditions includes: determining the target code block to be translated according to the number of jumps of the target code block recorded in the prediction table; determining the target code block to be translated according to the number of jumps of the target code block recorded in the prediction table includes: translating the target code blocks with the first several digits in descending order of the number of jumps; translating the adjacent code blocks of the code block to be translated currently being translated, and recording the addresses of the adjacent code blocks and the corresponding address of the translated code block in the cache table.

6. An electronic device, characterized in that: include: one or more processors; A storage device for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors are caused to perform the method according to any one of claims 1 to 4.

7. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the method according to any one of claims 1 to 4 is implemented.

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