Interrupt information query method and device, electronic equipment and storage medium

Abstract

The invention discloses an interrupt information query method and device, electronic equipment and a storage medium, and relates to the technical field of computers, and the method comprises the steps: carrying out the classification according to types based on obtained interrupt signals, and storing the interrupt signals in interrupt convergence register equipment of a corresponding type, the method comprises the following steps: detecting at least one interrupt convergence register device based on a preset polling mechanism, if an interrupt event is detected, positioning a target interrupt convergence register device corresponding to the interrupt event and a target interrupt event, and acquiring an interrupt information source of the target interrupt event by using an interrupt detailed information register device. The problems of resource waste, poor interrupt query real-time performance, low accuracy and the like caused by querying all interrupt signals based on a fixed polling mechanism are solved, each interrupt convergence register device is detected based on the polling mechanism of the interrupt frequency adjustment polling period, resource occupation can be reduced, the detection accuracy is improved, and the detection efficiency is improved. Therefore, an optimal balance point between resource occupation and real-time requirements is found.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a method, device, electronic equipment and storage medium for querying interrupt information. Background Art

[0002] In modern computers and embedded systems, the interrupt mechanism is one of the core technologies for achieving efficient task scheduling and event response, especially in switches, network cards and other devices. CPLD (Complicated Programmable Logic Device) or FPGA (Field Programmable Gate Array) as the underlying device is an important part of the switch, responsible for managing the interrupt signals of various peripherals and passing them to the upper system. The interrupt processing method affects the reliability and performance of the upper system.

[0003] In the related art, the interrupt processing method usually adopts a polling mechanism, that is, the bottom layer device directly transmits the interrupt signal to the upper layer system, and the upper layer system determines whether an interrupt occurs by periodically querying the status of the bottom layer device.

[0004] However, the above-mentioned polling interrupt processing method has the following problems: (1) High upper-level system resource usage: The underlying device directly transmits the interrupt signal to the upper-level system, and the upper-level system queries the interrupt status through the polling mechanism, which will occupy a large amount of CPU (Central Processor Unit) resources; (2) Poor real-time performance: If the polling cycle is too long, the rapidly changing interrupt signal may be missed, resulting in the degradation of the upper-level system performance, which needs to be solved urgently. Summary of the invention

[0005] The present invention provides a method, device, electronic device and storage medium for querying interrupt information, so as to at least solve the technical problems in the related art of querying the interrupt status of all interrupt signals based on a fixed polling mechanism, thereby causing waste of CPU resources, poor real-time performance of interrupt query and low accuracy.

[0006] The present invention provides a method for querying interrupt information, comprising: Obtain at least one interrupt signal, and classify each interrupt signal based on its category, and store them in interrupt aggregation register devices of corresponding categories respectively; Based on a preset polling mechanism, at least one interrupt aggregation storage device is detected to determine whether there is an interrupt event in at least one interrupt aggregation storage device; If an interrupt event exists in at least one interrupt aggregation register, the target interrupt aggregation register corresponding to the interrupt event is located, the target interrupt event in the target interrupt aggregation register is located, and the interrupt detailed information register is used to obtain the interrupt information source of the target interrupt event.

[0007] The present invention also provides a device for querying interrupt information, comprising: A first acquisition module, used for acquiring at least one interrupt signal, and classifying each interrupt signal based on its category, and storing them in interrupt aggregation register devices of corresponding categories respectively; A judgment module, used to detect at least one interrupt aggregation storage device based on a preset polling mechanism, and judge whether there is an interrupt event in at least one interrupt aggregation storage device; The second acquisition module is used to locate the target interrupt aggregation storage device corresponding to the interrupt event if there is an interrupt event in at least one interrupt aggregation storage device, locate the target interrupt event in the target interrupt aggregation storage device, and use the interrupt detailed information storage device to obtain the interrupt information source of the target interrupt event.

[0008] The present invention also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any one of the above-mentioned interruption information query methods when executing the computer program.

[0009] The present invention also provides a computer-readable storage medium, in which a computer program is stored, wherein when the computer program is executed by a processor, the steps of any one of the above-mentioned methods for querying interrupt information are implemented.

[0010] The present invention also provides a computer program product, including a computer program, which implements the steps of any one of the above-mentioned interruption information query methods when executed by a processor.

[0011] According to the present invention, since the interrupt signals obtained are classified according to categories and stored in the interrupt aggregation storage devices of the corresponding categories respectively, at least one interrupt aggregation storage device is detected based on a preset polling mechanism. If an interrupt event is detected in at least one interrupt aggregation storage device, the target interrupt aggregation storage device and the target interrupt event corresponding to the interrupt event are located, and the interrupt detailed information storage device is used to obtain the interrupt information source of the target interrupt event. The technical problems such as CPU resource waste, poor real-time performance of interrupt query and low accuracy caused by querying the interrupt status of all interrupt signals based on a fixed polling mechanism are solved. By introducing a polling mechanism that adjusts the polling cycle based on the interrupt frequency to detect each category of interrupt aggregation storage devices, resource occupation is reduced and detection accuracy is improved, so as to find the best balance between resource occupation and real-time requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0013] Figure 1 A flowchart of a method for querying interrupt information provided by an embodiment of the present invention; Figure 2 A schematic diagram of signal transmission for interrupt aggregation classification and status record query according to an embodiment of the present invention; Figure 3 is a block diagram of an example of a device for querying interrupt information according to an embodiment of the present invention; Figure 4 FIG. 4 is a schematic diagram of the structure of an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0014] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0015] It should be noted that, in the description of the present invention, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present invention are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0016] In order to enable those skilled in the art to better understand the scheme of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0017] An embodiment of the present invention provides a method for querying interrupt information. The method is described in detail in conjunction with the execution flow of the method for querying interrupt information.

[0018] Before introducing the embodiments of the present invention, the technical background related to the present invention is first introduced. CPLD / FPGA is a semi-customized application-specific integrated circuit with a series of advantages such as flexible programming, fast response, and high integration. It is increasingly widely used in the early development verification and control application fields in the fields of national defense, computers, switches, vehicles, and AI (Artificial Intelligence). In the switch system, the management of the data layer of the entire switch system is mainly achieved through CPLD / FPGA, including I2C (Inter-Integrated Circuit) devices, MDC (Modular Digital Converter) / MDIO (Management Data Input / Output) devices, SPI (Serial Peripheral Interface) devices, etc. Among them, CPLD / FPGA is an important part of the switch and is also an important part of the collection and reporting of bottom-level device information. The interrupt processing method is an important part that affects the reliability and performance of the system. The interrupt aggregation and reporting method is an important content of CPLD / FPGA design, which affects the interrupt processing speed and processing efficiency of the entire switch system. Therefore, the embodiment of the present invention detects each category of interrupt aggregation storage devices by introducing a polling mechanism based on the interrupt frequency to adjust the polling cycle, thereby reducing resource occupation and improving detection accuracy, so as to find the best balance between resource occupation and real-time requirements.

[0019] Specifically, Figure 1 The present invention is a flowchart of a method for querying interrupt information provided by an embodiment of the present invention.

[0020] like Figure 1 As shown, the query method of the interruption information includes the following steps: In step S101 , at least one interrupt signal is acquired, and each interrupt signal is classified based on its category and stored in an interrupt aggregation register device of a corresponding category.

[0021] Specifically, in an embodiment of the present invention, it mainly includes two parts: interrupt aggregation classification and status record query, wherein interrupt aggregation classification refers to classifying and aggregating the obtained interrupt signals, and storing the same type of interrupt signals in the corresponding category of interrupt aggregation storage devices, which are registers specially used to aggregate interrupt status, and are used to implement the "or" operation of all similar interrupts, that is, in the same category, any interrupt signal will be recorded in the corresponding interrupt aggregation storage device; status record query refers to accessing the interrupt signal status information in various storage devices, log files, databases or other data storage media to obtain the target interrupt aggregation storage device where the interrupt event exists and the target interrupt event in the target interrupt aggregation storage device, and record and query the interrupt information source of the target interrupt event, so as to realize effective monitoring, fault diagnosis and performance optimization of the preset upper-level system.

[0022] Specifically, if Figure 2 As shown, the embodiment of the present invention is based on the logic design of CPLD / FPGA, and the related logic devices involved mainly include an interrupt aggregation register (interrupt aggregation register), an interrupt status register (interrupt status register) and an interrupt change register (interrupt change register). In order to solve the technical problems of CPU resource waste, poor real-time performance of interrupt query and low accuracy caused by querying the interrupt status of all interrupt signals based on a fixed polling mechanism, the embodiment of the present invention classifies at least one interrupt signal obtained, and stores each type of interrupt signal in the corresponding category of interrupt aggregation register respectively. At this time, only a few interrupt aggregation registers need to be polled and detected, avoiding the preset upper system from polling to obtain all interrupt signals, thereby reducing the resource occupation of the preset upper system and improving the query efficiency. At the same time, the interrupt aggregation classification and status record query mechanism involved in the embodiment of the present invention can make the interrupt signal classification clearer, and at the same time, repeated polling is avoided through a few interrupt aggregation registers, I / O or in-band transmission interrupt mechanism.

[0023] In step S102, based on a preset polling mechanism, at least one interrupt aggregation register device is detected to determine whether there is an interrupt event in the at least one interrupt aggregation register device.

[0024] The preset polling mechanism may be set by those skilled in the art based on actual test requirements, or may be obtained through a limited number of computer simulations, and is not specifically limited here.

[0025] Specifically, Figure 2As shown, in an embodiment of the present invention, the preset upper system can integrate all the obtained interrupt signals into one signal and transmit it through I / O (Input / Output) or in-band interrupt, or communicate through protocols such as I2C, LPC (Low Pin Count), SPI, PCIe (Peripheral Component Interconnect Express), etc., which are not specifically limited here. Therefore, the preset upper system can communicate with CPLD / FPGA based on the above information communication method, detect at least one interrupt aggregation register device through a preset polling mechanism, and determine whether there is an interrupt event in at least one interrupt aggregation register device, so that when the interrupt event is detected in at least one interrupt aggregation register device, the target interrupt aggregation register device with the interrupt event is further located, wherein the target interrupt aggregation register device with the interrupt event can be one or more, and the detailed information of the target interrupt event in the target interrupt aggregation register device is scanned to obtain the interrupt information source of the target interrupt event. The relevant implementation methods will be specifically introduced below.

[0026] According to one embodiment of the present invention, at least one interrupt aggregation storage device is detected based on a preset polling mechanism, including: setting a preset initial polling mechanism for each interrupt aggregation storage device based on preset design requirements and functional characteristics of an upper-layer system and the type of the interrupt aggregation storage device; monitoring the interrupt frequency of interrupt events in each interrupt aggregation storage device, and dynamically adjusting the preset initial polling mechanism according to the interrupt frequency; and obtaining a preset polling mechanism based on the dynamically adjusted preset initial polling mechanism.

[0027] According to one embodiment of the present invention, dynamically adjusting the preset initial polling mechanism according to the interruption frequency includes: determining whether the interruption frequency is greater than a preset frequency threshold; if the interruption frequency is greater than the preset frequency threshold, shortening the preset initial polling mechanism, otherwise, extending the preset initial polling mechanism.

[0028] Among them, the preset upper system, the preset initial polling mechanism and the preset frequency threshold can all be set by those skilled in the art based on actual test requirements and are not specifically limited here.

[0029] Specifically, since different preset upper-layer systems may have different design requirements, such as real-time requirements, resource limitations, etc. of the upper-layer systems, the embodiments of the present invention can set the preset initial polling mechanism of each interrupt aggregation register device based on the design requirements and functional characteristics of the preset upper-layer system and the type of the interrupt aggregation register device, so as to meet the design requirements and functional characteristics of different preset upper-layer systems and improve the performance and reliability of the preset upper-layer system; at the same time, in order to quickly respond to high-frequency interrupts, avoid missed reports or delays, and reduce resource consumption, the embodiments of the present invention can use an interrupt frequency monitoring algorithm (such as a time interval statistics method, an adaptive threshold algorithm, etc.) to monitor the interrupt frequency in each interrupt aggregation register device. The interrupt frequency of interrupt events is monitored, and the preset initial polling mechanism is dynamically adjusted based on the interrupt frequency of interrupt events in each interrupt aggregation storage device, so as to avoid that in high-frequency interrupt scenarios, the fixed polling cycle may cause system overload, thereby affecting stability, and at the same time avoid that in low-frequency interrupt scenarios, the fixed polling cycle may cause waste of CPU resources. Therefore, the dynamic adjustment of the preset initial polling mechanism can optimize the polling cycle in real time, reduce unnecessary resource consumption while ensuring real-time performance, and more accurately reflect actual needs. It reduces the risk of misjudgment caused by fixed polling cycles. Finally, the optimal preset polling mechanism is obtained based on the dynamically adjusted preset initial polling mechanism.

[0030] Among them, if the interrupt frequency is greater than the preset frequency threshold, that is, the scenario that requires a quick response (such as high-speed data acquisition or real-time control), the polling cycle can be shortened to ensure timely capture of interrupt events. If the interrupt frequency is less than or equal to the preset frequency threshold, that is, for low-frequency or infrequent interrupt events, the polling cycle can be appropriately extended to reduce the number of CPU queries and reduce resource consumption, so as to flexibly balance resource usage and real-time requirements in different scenarios and optimize system performance.

[0031] For example, taking the status change of a switch port as an example, when the network traffic is large, the status change of the switch port may be more frequent. Therefore, its preset initial polling mechanism can be set to 10ms / time. If the switch port status change frequency is detected to be high (such as more than 10 times per second), the preset initial polling mechanism can be shortened to 5ms / time. If the switch port status change frequency is low (such as less than 1 time per second), the preset initial polling mechanism can be extended to 20ms / time. By real-time monitoring of the interruption frequency and flexibly adjusting the query frequency, the preset upper-layer system can better adapt to different application scenarios and load changes, thereby improving overall performance and user experience.

[0032] According to one embodiment of the present invention, after detecting at least one interrupt aggregation storage device based on a preset polling mechanism, it also includes: determining whether a preset interrupt signal is detected; if a preset interrupt signal is detected, recording and storing the preset interrupt signal based on the interrupt edge recording storage device.

[0033] Among them, the preset interrupt signal can be a rapidly changing interrupt signal, which often has a higher frequency or a shorter pulse width. Such signals may come from external sensors, clock sources or other high-speed devices, and specific rapidly changing interrupt signals can be identified based on the detection experience of historical data.

[0034] Specifically, in order to avoid missing the rapidly changing interrupt signal due to the low detection frequency of the preset polling mechanism, the present invention realizes the rapid change record of some interrupt signals based on CPLD / FPGA. The interrupt edge record storage device can be set through CPLD / FPGA, and the interrupt edge record storage device records the rapidly changing interrupt signal, and stores the detailed information of the rapidly changing interrupt signal to the corresponding interrupt detailed information storage device. The interrupt edge record storage device is a hardware register specially used to capture the edge change (rising edge or falling edge) of the signal. When the edge of the input signal changes, the edge record register will automatically record the event and save the detailed information of each edge event (such as timestamp and status), providing complete data for subsequent analysis, and then notifying the target upper-level system through interrupt or other mechanisms for further processing, thereby realizing the capture of the edge event of the rapidly changing interrupt signal, ensuring that no important state changes are missed. At the same time, the interrupt edge record storage device can work automatically in the background without the need for the CPU to frequently query the signal status, thereby reducing system resource consumption.

[0035] According to one embodiment of the present invention, determining whether an interrupt event exists in at least one interrupt aggregation register device includes: determining whether a value of at least one interrupt aggregation register device is a preset value; if the value of at least one interrupt aggregation register device is the preset value, determining that an interrupt event exists in at least one interrupt aggregation register device.

[0036] The preset value may be set by a person skilled in the art based on actual test requirements, or may be obtained through a limited number of computer simulations, and is not specifically limited here.

[0037] Specifically, after the embodiment of the present invention detects at least one interrupt aggregation register device through a preset polling mechanism, it is necessary to further determine whether there is an interrupt event in the at least one interrupt aggregation register device. The interrupt status register device can be used to identify the interrupt aggregation register device where the interrupt event occurs. Therefore, first, the value of at least one interrupt aggregation register device is read through the interrupt status register device; secondly, it is determined whether the value of at least one interrupt aggregation register device is a preset value (for example, 1). If the value of at least one interrupt aggregation register device is the preset value, it can be determined that there is an interrupt event in the at least one interrupt aggregation register device. That is to say, when the value of at least one interrupt aggregation register device is 1, it can be determined that there is an interrupt event in the at least one interrupt aggregation register device. At this time, if an interrupt event is detected, the preset upper-layer system obtains the interrupt event through the interrupt aggregation register device, I / O or in-band transmission interrupt, and immediately enters the interrupt processing process. If no interrupt event is detected, other tasks continue to be executed or low power consumption mode is entered.

[0038] For example, as an implementable manner, based on non-zero detection, if the value of at least one interrupt aggregation register is 1, it means that at least one interrupt aggregation register triggers an interrupt, and at this time, it can be indicated that an interrupt event exists in at least one interrupt aggregation register.

[0039] As another possible implementation, bitwise operations, you can use bitwise logic operations (such as OR or AND) to quickly detect the status of a specific interrupt aggregation register device.

[0040] Thus, by quickly detecting the status of at least one interrupt aggregation register, the preset upper system can determine whether there is an interrupt event in at least one interrupt aggregation register in the shortest time, thereby responding in time, reducing the number of queries, and reducing the CPU load.

[0041] It should be noted that in a multi-tasking environment, the preset upper-layer system can also quickly determine whether an interrupt event occurs through the interrupt aggregation register device, and give priority to processing high-priority tasks.

[0042] In step S103, if there is an interrupt event in at least one interrupt aggregation register, the target interrupt aggregation register corresponding to the interrupt event is located, the target interrupt event in the target interrupt aggregation register is located, and the interrupt detailed information register is used to obtain the interrupt information source of the target interrupt event.

[0043] The target interrupt aggregation register device is an interrupt aggregation register device having an interrupt event, and the target interrupt event is a specific interrupt event existing in the target interrupt aggregation register device.

[0044] Specifically, when an interrupt event is detected in at least one interrupt aggregation storage device, it means that in the process of detecting at least one interrupt aggregation storage device based on the preset polling mechanism, at least one interrupt aggregation storage device value is detected to be 1, that is, there is an interrupt event in at least one interrupt aggregation storage device. At this time, it is necessary to further locate the corresponding interrupt aggregation storage device where the interrupt event exists, that is, locate the target interrupt aggregation storage device, and after locating the target interrupt aggregation storage device, further use the interrupt detailed information storage device to obtain the interrupt information source of the target interrupt event in the target interrupt aggregation storage device, that is, obtain the detailed information of the target interrupt information.

[0045] According to one embodiment of the present invention, locating a target interrupt aggregation register device corresponding to an interrupt event includes: obtaining an interrupt type of the interrupt event, an interrupt timestamp of the interrupt event, and data information of the interrupt event; determining a target address of the interrupt aggregation register device according to the interrupt type of the interrupt event, the timestamp of the interrupt event, and the data information of the interrupt event, so as to locate the target interrupt aggregation register device according to the target address.

[0046] Specifically, in the process of locating the target interrupt aggregation storage device corresponding to the interrupt event, first, the interrupt type of the interrupt event can be obtained based on the interrupt type information carried by the interrupt signal itself; secondly, when the interrupt event occurs, the value of the hardware timer will be written into the interrupt timestamp storage device, and the relevant hardware device will also write the relevant data information of the interrupt event into a specific data storage device. At this time, the preset upper-level system reads the interrupt timestamp storage device to obtain the interrupt timestamp of the interrupt event. At the same time, the corresponding data storage device is queried according to the interrupt type of the interrupt event to obtain the data information of the interrupt event, such as the sensor value or link status of the interrupt event, so as to determine the target address of the interrupt aggregation storage device according to the interrupt type, timestamp and data information of the interrupt event, so as to locate the target interrupt aggregation storage device where the interrupt event exists according to the target address, and the target address is the target address of the target interrupt aggregation storage device.

[0047] Furthermore, to ensure the accuracy of identifying the target interrupt aggregation register device with an interrupt event, after locating the target interrupt aggregation register device with an interrupt event, the embodiment of the present invention can further perform verification. For example, a hardware simulation tool (such as an FPGA development board or an embedded simulator) can be used to simulate the interrupt event to verify whether the behavior of the target interrupt aggregation register device meets expectations. Alternatively, verification can be performed at the software level by verifying the read and write and state consistency of the target interrupt aggregation register device. When performing the read and write verification, read and write operations can be performed on the target interrupt aggregation register device to verify whether its behavior meets expectations. When verifying the state consistency, after the interrupt is triggered, check whether the state of the target interrupt aggregation register device is consistent with the actual interrupt source. If a GPIO (General Purpose Input / Output) pin triggers an interrupt, it is confirmed that the relevant bit in the corresponding interrupt aggregation register device is set to 1. At this time, based on the above verification method, the accuracy of the target interrupt aggregation register device with an interrupt event can be determined.

[0048] Optionally, if an error occurs in identifying the target interrupt aggregation register device with an interrupt event, redetection can be performed through error handling or fault tolerance mechanisms. For example, if two target interrupt aggregation register devices report the same interrupt source at the same time, it may be necessary to recheck the hardware connection or software configuration, or in the event of identification failure, implement an automatic retry mechanism to ensure correctness, and record the process and results of each interrupt identification to facilitate subsequent analysis and debugging.

[0049] It should be noted that the above verification mechanism is only exemplary, and the specific verification mechanism can be selected based on actual test requirements and is not specifically limited here.

[0050] Therefore, by accurately locating the target interrupt aggregation register device where the interrupt event occurs, the corresponding interrupt service program can be quickly entered, the interrupt response time can be shortened, the real-time performance of the system can be improved, and misjudgment or omission of interrupt events can be avoided, ensuring that the preset upper-level system correctly responds to all interrupts.

[0051] According to one embodiment of the present invention, locating a target interrupt event in a target interrupt aggregation register device includes: detecting the interrupt signal state of each bit in the target interrupt aggregation register device; determining whether the interrupt signal state is a preset state; and if the interrupt signal state is a preset state, obtaining the target interrupt event in the target interrupt aggregation register device based on the interrupt signal state.

[0052] The preset state may be set by technicians in this field based on actual test requirements, or may be obtained through a limited number of computer simulations, which is not specifically limited here.

[0053] Specifically, after locating the target interrupt aggregation storage device where the interrupt event exists, in order to achieve refined identification of the interrupt event, the embodiment of the present invention needs to further locate the target interrupt event in the target interrupt aggregation storage device so as to accurately identify the state of each interrupt signal to avoid omissions or misjudgments. At the same time, only processing the target interrupt events that meet the preset state can also reduce unnecessary query operations and reduce the CPU load.

[0054] Specifically, the target interrupt aggregation register is a register that aggregates multiple interrupt signal states, and each bit usually corresponds to an interrupt signal. First, by reading the value of the target interrupt aggregation register, the interrupt signal state of each bit of the target interrupt aggregation register is checked bit by bit, and then which interrupt signals trigger the interrupt event are determined; secondly, it is determined whether the interrupt signal state is a preset state, that is, whether the interrupt signal state is 1. If the interrupt signal state is 1, it indicates that there is an interrupt at this bit, that is, there is a target interrupt event; finally, since each target interrupt event corresponds to an interrupt detailed information register device to store the detailed information of the target interrupt event, the present invention can The mapping of the interrupt detailed information storage device written into the read-only memory is realized so that the preset upper-layer system can obtain the detailed information of the written target interrupt event. Therefore, according to the position or identification of the bit, the interrupt detailed information storage device can be further used to obtain the interrupt information source of the target interrupt event, that is, the detailed information of the target interrupt event (such as interrupt type, timestamp, data information, etc.), so as to accurately locate and process the specific target interrupt event. The interrupt detailed information storage device includes an interrupt status storage device and an interrupt record storage device, so as to record the detailed information of the interrupt information source of the target interrupt event, the interrupt status, the interrupt record and other information.

[0055] It should be noted that if there are multiple interrupt signals that meet the preset status at the same time in the target interrupt aggregation register device, they can be processed in the order of priority of each interrupt signal, for example, by adopting a hardware priority mechanism or a software scheduling algorithm. At the same time, in a multi-tasking environment, data consistency between the interrupt handler and the main program must be ensured. Mutex locks or disabling interrupts can be used to protect shared resources.

[0056] Therefore, by checking the interrupt signal status in the target interrupt aggregation register device bit by bit, the status of each interrupt signal can be accurately identified, so that it is possible to accurately identify which bit in the target interrupt aggregation register device has been interrupted, and correspond to a specific target interrupt event, and then obtain the detailed information of the target interrupt event according to the interrupt detailed information register device corresponding to the target interrupt event, thereby improving the stability and robustness of the preset upper-layer system.

[0057] According to one embodiment of the present invention, after obtaining the interrupt information source of the interrupt event using the interrupt detailed information storage device, it also includes: judging whether the interrupt information source is recorded successfully; if the interrupt information source is recorded successfully, writing a clear instruction to the interrupt clearing storage device according to the target interrupt aggregation storage device; based on the clear instruction, clearing the interrupt information source in the target interrupt aggregation storage device using the interrupt clearing storage device.

[0058] Specifically, in the embodiment of the present invention, after the interruption detailed information storage device obtains the interruption information source of the interruption event, it is necessary to actively clear the content of the target interruption aggregation storage device to ensure that the target interruption aggregation storage device can be recycled to provide space for the next interruption record.

[0059] Specifically, first, after obtaining the interrupt information source of the interrupt event, the CPLD / FPGA records and saves it to the interrupt detailed information storage device, that is, the interrupt record storage device in the interrupt detailed information storage device records it, and after the interrupt information source is successfully recorded, space is provided for the next interrupt record to ensure that the interrupt record storage device can record the next interrupt. The preset upper system needs to determine the address of the interrupt record storage device that has been successfully recorded, and after determining the address of the interrupt record storage device that has been successfully recorded, write a clear instruction to the interrupt clearing storage device according to the target interrupt aggregation storage device. Based on the clear instruction, the interrupt clearing storage device is used to clear the interrupt information source in the target interrupt aggregation storage device, that is, the CPLD / FPGA determines that the preset upper system automatically clears after reading the interrupt information source, or the preset upper system writes to this interrupt record storage device, so that after the clearing operation is completed, a confirmation signal is transmitted upward to ensure that the preset upper system knows that the clearing is completed, and at the same time allows the preset upper system to clear the contents of multiple interrupt record registers at one time, simplifying the operation process. At this time, the interrupt record register is restored to an idle state and can record the next interrupt behavior.

[0060] Therefore, in order to avoid the situation where a new interrupt event may overwrite old data, resulting in the loss of important information, or when the interrupt information source is not cleared, it may be mistakenly believed that the same interrupt event has occurred again, resulting in repeated processing, it is necessary to use an active clearing mechanism after obtaining the interrupt information source based on the interrupt detailed information storage device to ensure that the interrupt record storage device can be used continuously, and each interrupt event can be correctly recorded and processed without errors caused by data overwriting or repeated processing, supporting the recording of more interrupt events.

[0061] It should be noted that, in the embodiment of the present invention, the control can be made more flexible by using an interrupt shielding register device. When the preset upper layer system does not pay attention to the interrupt, the interrupt shielding register device is directly used for shielding to prevent interrupts from occurring during critical operations.

[0062] According to one embodiment of the present invention, before clearing the interrupt information source in the target interrupt aggregation storage device using the interrupt clearing storage device based on the clearing instruction, it also includes: obtaining the clearing identity of the interrupt information source; judging whether the clearing identity is verified; if the clearing identity is verified, obtaining the clearing key of the interrupt information source, and judging whether the clearing key satisfies the preset clearing condition; if the clearing key satisfies the preset clearing condition, recording the verification information and the clearing key information, and generating the clearing instruction execution information.

[0063] The preset clearing condition may be set by a person skilled in the art based on actual test requirements, or may be obtained through a limited number of computer simulations, and is not specifically limited here.

[0064] Specifically, in order to avoid data loss that may be caused by the clearing operation being triggered by mistake or the execution of unauthorized operations, for example, unprocessed interrupt information may be cleared by mistake, resulting in the system being unable to respond correctly to certain events, or causing instability in the preset upper-level system. For example, unauthorized clearing operations may destroy the normal operating state of the system and affect real-time performance or functional integrity. Therefore, in order to improve the security and reliability of the preset upper-level system, the embodiment of the present invention needs to further add a verification mechanism before using the interrupt clearing storage device to clear the interrupt information source in the target interrupt aggregation storage device to ensure that only authorized operations can trigger the clearing.

[0065] Specifically, first, it is necessary to clarify which operations or users have the authority to trigger the clearing operation, that is, to obtain the clearing identity of the interruption information source, and to verify the clearing identity of the interruption information source, for example, to verify the user ID (Identification) and device ID, and whether the verification operation occurs within the allowed time window. If both the user ID and the device ID are verified, and the operation occurs within the allowed time window, it can be said that the clearing identity verification is passed. Then, the clearing key of the interruption information source is further obtained, and it is determined whether the clearing key meets the preset clearing conditions, that is, whether the clearing key is correct. If the clearing key meets the preset clearing conditions, the verification pass information and the clearing key information are recorded. At this time, the clearing instruction execution information can be generated to clear the interruption information source.

[0066] The clearing key may be static (fixed value) or dynamic (generated based on time or other factors), which is not specifically limited here.

[0067] Therefore, based on the above-mentioned clearing identity verification mechanism, illegal or accidental clearing operations can be prevented, important data in the interruption record storage device can be protected, and it can be ensured that the clearing operation is only initiated by legal operations, avoiding data loss or system abnormalities caused by misoperation or malicious attacks. In a multi-user or multi-task system, the verification mechanism can distinguish the permissions of different users to ensure that each user can only clear the interruption records related to him or her.

[0068] According to one embodiment of the present invention, after determining whether the verification of clearing the identity identification has passed, it also includes: if the verification of clearing the identity identification has not passed, generating an instruction to prohibit clearing the interruption information source and recording the reason for the failure of the identity identification verification; obtaining the number of clearing identity identification verifications, and determining whether the number of clearing identity identification verifications is greater than a first preset verification threshold; if the number of clearing identity identification verifications is greater than the first preset verification threshold, generating a first alarm prompt.

[0069] Among them, the first preset verification threshold can be set by technical personnel in this field based on actual test requirements, or can be obtained through a limited number of computer simulations, and is not specifically limited here.

[0070] Specifically, if the clearing identity verification fails, it means that the user's operation is risky. At this time, it is necessary to generate an instruction to prohibit clearing the interruption information source and record the reason why the identity verification failed for subsequent verification analysis. For example, record the operation source, operation timestamp, specific operation content and failure reason, etc. If the user verifies multiple times, the number of clearing identity verifications is obtained at this time. If the number of clearing identity verifications is greater than the first preset verification threshold, it means that there is an illegal or malicious clearing operation. At this time, a first alarm prompt can be generated, such as triggering a high priority alarm, notifying the administrator to check the system security, and the user's clearing authority can be temporarily disabled for 10 minutes.

[0071] Therefore, by verifying and clearing the identity, it can be ensured that all operation attempts are strictly recorded and monitored, so that an alarm can be issued when the verification fails, preventing unauthorized operations from affecting system stability.

[0072] According to one embodiment of the present invention, after determining whether the clearing key satisfies the preset clearing conditions, it also includes: if the clearing key does not satisfy the preset clearing conditions, recording the timestamp of the clearing key, the clearing key request address and the reason why the clearing key does not satisfy the preset clearing conditions; obtaining the number of clearing key verification times, and determining whether the number of clearing key verification times is greater than a second preset verification threshold; if the number of clearing identity verification times is greater than the second preset verification threshold, generating a second alarm prompt.

[0073] The second preset verification threshold may be set by a person skilled in the art based on actual test requirements, or may be obtained through a limited number of computer simulations, and is not specifically limited here.

[0074] Specifically, if the clearing key does not meet the preset clearing conditions, it means that the provided key is invalid or wrong, the operation source lacks the necessary authority, or the operation does not meet the specific time window or other restrictions. At this time, in order to protect the preset upper-level system from the impact of illegal operations, it is necessary to immediately terminate the clearing operation process and return a clear rejection message (for example, "Clearing failed: key invalid") and other prompt messages to the requesting party, and record the timestamp of the clearing key, the clearing key request address, and the reason why the clearing key does not meet the preset clearing conditions. At the same time, the number of clearing key verifications is obtained. If the number of clearing key verifications is greater than the second preset verification threshold, it means that there is an illegal or malicious clearing operation. At this time, a second alarm prompt is generated, for example, through a low-level alarm or a high-level alarm. Among them, the high-level alarm can be to send an email, text message, or start a sound alarm, etc., and the low-level alarm can be recorded in the log without further notification.

[0075] Therefore, through the key verification mechanism, it can be ensured that all operation attempts are strictly recorded and monitored, so that an alarm can be issued when the verification fails, preventing unauthorized operations from affecting system stability.

[0076] According to one embodiment of the present invention, after clearing the interrupt information source in the target interrupt aggregation storage device using the interrupt clearing storage device based on the clearing instruction, it also includes: judging whether the interrupt information source has been cleared; if the interrupt information source has been cleared, a clearing confirmation signal is generated, otherwise, a clearing incomplete log or a clearing error log is recorded, and cleared again.

[0077] Specifically, after using the interrupt clearing register device to clear the interrupt information source in the target interrupt aggregation register device, it is necessary to read the related register devices of the interrupt information source and check whether the values ​​of these register devices meet the clearing completion criteria, for example, all related bits are 0, to ensure that the interrupt information source is cleared. If the interrupt information source is cleared, a clear confirmation signal is generated and sent to the relevant module or recorded in the log to notify other parts of the system that the interrupt processing has been completed, thereby facilitating subsequent coordinated task scheduling and resource allocation.

[0078] Therefore, through multiple checks and re-clearing mechanisms, it is ensured that the status of the interrupt information source is completely cleared. Based on the clearing status of the interrupt information source, a corresponding clearing confirmation signal is generated to provide clear feedback to other parts of the system, thereby facilitating problem troubleshooting and system maintenance.

[0079] In summary, based on the above-mentioned query method for interrupt information, the entire interrupt design is made clearer through the design of a perfect interrupt aggregation storage device, an interrupt detailed information storage device, and an interrupt edge recording storage device for recording rapidly changing signals, thereby improving the upper system access efficiency and the overall machine performance.

[0080] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method.

[0081] The embodiment of the present invention also provides a device for querying interruption information.

[0082] Figure 3 It is a block diagram of an example of a device for querying interrupt information according to an embodiment of the present invention.

[0083] like Figure 3 As shown, the query device 10 for interruption information includes: a first acquisition module 100 , a judgment module 200 and a second acquisition module 300 .

[0084] The first acquisition module 100 is used to acquire at least one interrupt signal, and classify each interrupt signal based on its category, and store them in interrupt aggregation register devices of corresponding categories respectively; The judging module 200 is used to detect at least one interrupt aggregation register device based on a preset polling mechanism to judge whether there is an interrupt event in at least one interrupt aggregation register device; The second acquisition module 300 is used to locate the target interrupt aggregation storage device corresponding to the interrupt event if there is an interrupt event in at least one interrupt aggregation storage device, locate the target interrupt event in the target interrupt aggregation storage device, and use the interrupt detailed information storage device to obtain the interrupt information source of the target interrupt event.

[0085] According to an embodiment of the present invention, after detecting at least one interrupt aggregation register device based on a preset polling mechanism, the judgment module 200 further includes: A first judging unit, used to judge whether a preset interrupt signal is detected; The storage unit is used to record and store the preset interrupt signal based on the interrupt edge recording and storage device if the preset interrupt signal is detected.

[0086] According to one embodiment of the present invention, the second acquisition module 300 includes: A first acquisition unit, used to acquire an interrupt type of an interrupt event, an interrupt timestamp of the interrupt event, and data information of the interrupt event; The positioning unit is used to determine the target address of the interrupt aggregation register device according to the interrupt type of the interrupt event, the timestamp of the interrupt event and the data information of the interrupt event, so as to locate the target interrupt aggregation register device according to the target address.

[0087] According to one embodiment of the present invention, the determination module 200 includes: A second judgment unit, used to judge whether the value of at least one interrupt aggregation register device is a preset value; The determination unit is configured to determine that an interrupt event exists in at least one interrupt aggregation register device if the value of at least one interrupt aggregation register device is a preset value.

[0088] According to one embodiment of the present invention, the second acquisition module 300 includes: A detection unit, used to detect the interrupt signal state of each bit in the target interrupt aggregation register device; A third judging unit, used to judge whether the interrupt signal state is a preset state; The second acquisition unit is configured to obtain a target interrupt event in the target interrupt aggregation register device based on the interrupt signal state if the interrupt signal state is a preset state.

[0089] According to an embodiment of the present invention, after obtaining the interruption information source of the interruption event based on the interruption detailed information storage device, the second obtaining module 300 includes: A fourth judgment unit, used to judge whether the interruption information source is recorded successfully; An instruction writing unit, used for writing a clear instruction to an interrupt clearing register device according to a target interrupt aggregation register device if the interrupt information source is recorded successfully; The clearing unit is used to clear the interrupt information source in the target interrupt aggregation register device by using the interrupt clearing register device based on the clearing instruction.

[0090] According to one embodiment of the present invention, before clearing the interrupt information source in the target interrupt aggregation register device using the interrupt clearing register device based on the clearing instruction, the clearing unit further includes: Get sub-component, used to get the clearing identity of the interruption information source; The first judgment element is used to judge whether the verification of clearing the identity mark is passed; The second judgment element is used to obtain the clearing key of the interruption information source if the clearing identity verification is passed, and to judge whether the clearing key meets the preset clearing condition; The first generating component is used to record the verification pass information and the clear key information if the clear key meets the preset clear condition, and generate the clear instruction execution information.

[0091] According to an embodiment of the present invention, after determining whether the clearing identity mark is verified, the first determination element further includes: The first generating sub-component is used to generate an instruction to prohibit clearing the interrupt information source and record the reason why the identity verification fails if the clearing identity verification fails; The first judgment sub-component is used to obtain the number of times of clearing identity verification and to judge whether the number of times of clearing identity verification is greater than a first preset verification threshold; The second generating component is used to generate a first alarm prompt if the number of times of clearing identity verification is greater than a first preset verification threshold.

[0092] According to an embodiment of the present invention, after determining whether the clearing key satisfies the preset clearing condition, the second determination element further includes: A record sub-component, used to record the timestamp of clearing the key, the address of clearing the key request, and the reason why the clearing key does not meet the preset clearing condition if the clearing key does not meet the preset clearing condition; The second judgment sub-component is used to obtain the number of clear key verification times and determine whether the number of clear key verification times is greater than a second preset verification threshold; The third generating component is used to generate a second alarm prompt if the number of times of clearing identity verification is greater than a second preset verification threshold.

[0093] According to one embodiment of the present invention, after clearing the interrupt information source in the target interrupt aggregation register device using the interrupt clear register device based on the clear instruction, the clearing unit further includes: The third judgment element is used to judge whether the interrupt information source has been cleared; The second generating component is used to generate a clearing confirmation signal if the clearing of the interruption information source is completed, otherwise, record a clearing incomplete log or a clearing error log, and clear again.

[0094] According to one embodiment of the present invention, the determination module 200 includes: A setting unit, used to set a preset initial polling mechanism for each interrupt aggregation register device based on the preset design requirements and functional characteristics of the upper layer system and the type of the interrupt aggregation register device; A dynamic adjustment unit, used to monitor the interrupt frequency of interrupt events in each interrupt aggregation register device, and dynamically adjust the preset initial polling mechanism according to the interrupt frequency; The third acquisition unit is used to obtain the preset polling mechanism based on the dynamically adjusted preset initial polling mechanism.

[0095] According to one embodiment of the present invention, the dynamic adjustment unit includes: A fifth judgment unit, used to judge whether the interruption frequency is greater than a preset frequency threshold; The dynamic adjustment unit is used to shorten the preset initial polling mechanism if the interruption frequency is greater than the preset frequency threshold, otherwise, extend the preset initial polling mechanism.

[0096] In summary, the description of the features in the embodiment corresponding to the device for querying interruption information can refer to the relevant description of the embodiment corresponding to the method for querying interruption information, which will not be described in detail here.

[0097] Figure 4 A schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. The electronic device may include: Memory 401 , processor 402 , and a computer program stored in the memory 401 and executable on the processor 402 .

[0098] When the processor 402 executes the program, the multi-device communication method provided in the above embodiment is implemented.

[0099] Furthermore, the electronic device further comprises: The communication interface 403 is used for communication between the memory 401 and the processor 402 .

[0100] The memory 401 is used to store computer programs that can be executed on the processor 402 .

[0101] The memory 401 may include a high-speed RAM memory, and may also include a non-volatile memory (non-volatile memory), such as at least one disk memory.

[0102] If the memory 401, the processor 402 and the communication interface 403 are implemented independently, the communication interface 403, the memory 401 and the processor 402 can be connected to each other through a bus and communicate with each other. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 4 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0103] Optionally, in a specific implementation, if the memory 401, the processor 402 and the communication interface 403 are integrated on a chip, the memory 401, the processor 402 and the communication interface 403 can communicate with each other through an internal interface.

[0104] The processor 402 may be a central processing unit (CPU), or an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present invention.

[0105] An embodiment of the present invention further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any one of the above-mentioned interruption information query method embodiments when running.

[0106] An embodiment of the present invention further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above-mentioned interrupt information query method embodiments are implemented.

[0107] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0108] The above is a detailed introduction to a method for querying interrupt information provided by the present invention. This article uses specific examples to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method and core ideas of the present invention. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present invention, the present invention can also be improved and modified, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A method for querying interruption information, characterized in that: The following steps are involved: Obtain at least one interrupt signal, and classify each interrupt signal based on its category, and store them in interrupt aggregation register devices of corresponding categories respectively; Based on a preset polling mechanism, at least one interrupt aggregation storage device is detected to determine whether there is an interrupt event in the at least one interrupt aggregation storage device; If the interrupt event exists in the at least one interrupt aggregation register, locate the target interrupt aggregation register corresponding to the interrupt event, locate the target interrupt event in the target interrupt aggregation register, and use the interrupt detailed information register to obtain the interrupt information source of the target interrupt event.

2. The method for querying interruption information according to claim 1, characterized in that: After detecting at least one interrupt aggregation register device based on the preset polling mechanism, the method further includes: Determine whether a preset interrupt signal is detected; If the preset interrupt signal is detected, the preset interrupt signal is recorded and stored based on the interrupt edge recording and storage device.

3. The method for querying interruption information according to claim 1, characterized in that: The locating the target interrupt aggregation register device corresponding to the interrupt event includes: Obtaining an interrupt type of the interrupt event, an interrupt timestamp of the interrupt event, and data information of the interrupt event; The target address of the interrupt aggregation register device is determined according to the interrupt type of the interrupt event, the timestamp of the interrupt event and the data information of the interrupt event, so as to locate the target interrupt aggregation register device according to the target address.

4. The method for querying interruption information according to claim 1, characterized in that: The determining whether there is an interrupt event in at least one interrupt aggregation register device includes: Determining whether the at least one interrupt aggregation register value is a preset value; If the value of the at least one interrupt aggregation register device is the preset value, it is determined that the interrupt event exists in the at least one interrupt aggregation register device.

5. The method for querying interruption information according to claim 1, characterized in that: The locating the target interrupt event in the target interrupt aggregation register device includes: Detecting the interrupt signal status of each bit in the target interrupt aggregation register; Determining whether the interrupt signal state is a preset state; If the interrupt signal state is the preset state, a target interrupt event in the target interrupt aggregation register device is obtained based on the interrupt signal state.

6. The method for querying interruption information according to claim 1, characterized in that: After obtaining the interruption information source of the target interruption event by using the interruption detailed information storage device, the method further includes: Determining whether the interruption information source is recorded successfully; If the interrupt information source is recorded successfully, a clear instruction is written to the interrupt clear register device according to the target interrupt aggregation register device; Based on the clear instruction, the interrupt clear register device is used to clear the interrupt information source in the target interrupt aggregation register device.

7. The method for querying interruption information according to claim 6, characterized in that: Before clearing the interrupt information source in the target interrupt aggregation register device using the interrupt clearing register device based on the clearing instruction, the method further includes: Obtaining a clearing identity of the interruption information source; Determine whether the clearing identity is verified; If the clearing identity verification is passed, obtaining the clearing key of the interruption information source, and determining whether the clearing key satisfies a preset clearing condition; If the clear key satisfies the preset clear condition, the verification pass information and the clear key information are recorded, and clear instruction execution information is generated.

8. The method for querying interruption information according to claim 7, characterized in that: After determining whether the clearing identity is verified, the method further includes: If the clearing identity verification fails, generating an instruction to prohibit clearing the interrupt information source and recording the reason why the identity verification fails; Obtaining the number of times of clearing identity verification, and determining whether the number of times of clearing identity verification is greater than a first preset verification threshold; If the number of times of clearing identity verification is greater than the first preset verification threshold, a first alarm prompt is generated.

9. The method for querying interruption information according to claim 7, characterized in that: After determining whether the clearing key satisfies a preset clearing condition, the method further includes: If the clear key does not meet the preset clear condition, then record the timestamp of the clear key, the clear key request address and the reason why the clear key does not meet the preset clear condition; Obtaining the number of clear key verification times, and determining whether the number of clear key verification times is greater than a second preset verification threshold; If the number of times of clearing identity verification is greater than the second preset verification threshold, a second alarm prompt is generated.

10. The method for querying interruption information according to claim 6, characterized in that: After clearing the interrupt information source in the target interrupt aggregation register device by using the interrupt clearing register device based on the clearing instruction, the method further includes: Determine whether the interrupt information source has been cleared; If the interrupt information source is cleared, a clearing confirmation signal is generated; otherwise, a clearing incomplete log or a clearing error log is recorded and cleared again.

11. The method for querying interruption information according to claim 1, characterized in that: The detecting of at least one interrupt aggregation register device based on a preset polling mechanism includes: Based on the preset design requirements and functional characteristics of the upper layer system and the type of the interrupt aggregation register device, respectively set a preset initial polling mechanism for each interrupt aggregation register device; Monitoring the interrupt frequency of the interrupt event in each interrupt aggregation register device, and dynamically adjusting the preset initial polling mechanism according to the interrupt frequency; The preset polling mechanism is obtained based on the dynamically adjusted preset initial polling mechanism.

12. The method for querying interruption information according to claim 11, characterized in that: The dynamically adjusting the preset initial polling mechanism according to the interruption frequency includes: Determining whether the interruption frequency is greater than a preset frequency threshold; If the interruption frequency is greater than the preset frequency threshold, the preset initial polling mechanism is shortened; otherwise, the preset initial polling mechanism is prolonged.

13. A device for querying interruption information, characterized in that: include: A first acquisition module, used for acquiring at least one interrupt signal, and classifying each interrupt signal based on its category, and storing them in interrupt aggregation register devices of corresponding categories respectively; A judgment module, configured to detect at least one interrupt aggregation storage device based on a preset polling mechanism, and judge whether there is an interrupt event in the at least one interrupt aggregation storage device; The second acquisition module is used to locate the target interrupt aggregation storage device corresponding to the interrupt event if the interrupt event exists in the at least one interrupt aggregation storage device, locate the target interrupt event in the target interrupt aggregation storage device, and use the interrupt detailed information storage device to obtain the interrupt information source of the target interrupt event.

14. An electronic device, characterized in that: include: The invention comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of the method for querying interrupt information according to any one of claims 1 to 12.

15. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the method for querying interrupt information according to any one of claims 1 to 12.

16. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method for querying interrupt information according to any one of claims 1 to 12 are implemented.

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