Reliability design method for intelligent computing system of multi-dimensional COTS device

By setting up a fault detection and recovery module in the intelligent computing module and the external interface module, and combining a long-delay system-level watchdog for two-layer reliability design, the problem of insufficient reliability when low-cost commercial devices are applied in the space environment is solved, and a high reliability and resource-saving design is achieved.

CN119718746AActive Publication Date: 2025-03-28BEIJING INST OF CONTROL ENG
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Patent Information

Application Number
CN202411802174.X
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2024-12-09
Publication Date
2025-03-28
Estimated Expiration
2044-12-09

AI Technical Summary

Technical Problem

When low-cost commercial devices are used in space environments, they are prone to failure. Existing reliability design methods such as backup design lead to design redundancy and occupy more space and computing resources.

Method used

The reliability design method of intelligent computing system of multi-dimensional COTS devices is adopted, and a fault detection and recovery module is set up in the intelligent computing module and the external interface module, and a two-layer reliability design is carried out in combination with a long-delay system-level watchdog.

Benefits of technology

It improves the reliability of the system, realizes the system recovery mechanism in the event of failure, reduces the use of space and computing resources, and is more cost-effective than backup design.

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Abstract

The invention relates to the technical field of spatial fault tolerance, in particular to a reliability design method for an intelligent computing system of a multi-dimensional COTS device. The method comprises the following steps of: respectively arranging a corresponding fault detection and recovery module in the intelligent computing module and each external interface module, and arranging a long-delay system-level watchdog respectively connected with the intelligent computing module and the external interface module; the long-time-delay system-level watchdog comprises a latch arbitration circuit and multiple paths of long-time-delay pulse generators, and the latch arbitration circuit is used for receiving clear signals sent by the intelligent calculation module and the N external interface modules and clearing timing of each path of long-time-delay pulse generator after latching and arbitration; and if the timing exceeds the first set time delay, outputting a first reset signal, and resetting and restarting the corresponding intelligent computing module or the external interface module. According to the scheme, two-stage reliability design is adopted, and compared with backup design, occupation of space and computing resources can be reduced.
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Citation Information

Patent Citations

  • Heterogeneous satellite-borne fault-tolerant computer based on COTS (Commercial Off The Shelf) device

    CN102053882A

  • Intelligent watchdog system based on complex programmable logic device

    CN109753373A