Memory system, memory management method, equipment and medium

Abstract

The invention discloses a memory system, a memory management method, equipment and a medium in the technical field of computers. According to the method, the processor is additionally arranged in the switching equipment in the memory system, the processor can realize transmission of the memory error information of the downstream memory equipment to the corresponding host, and the controller in the memory equipment only needs to report equipment state information such as memory temperature to the host BMC and does not need to report the memory error condition to the host BMC; the problem of communication resource scrambling of memory error information and equipment state information is solved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a memory system, a memory management method, a device and a medium. Background Art

[0002] Currently, in a memory system with multiple memory devices, the controller in the memory device needs to frequently interact with the host BMC to let the host know whether each CXL memory device is faulty. Since the controller in the memory device also needs to report device status information such as memory temperature to the host BMC, it can be seen that there is a phenomenon of communication resource competition between memory error information and device status information.

[0003] Therefore, how to solve the problem of contention for communication resources between memory error information and device status information is a problem that needs to be solved by those skilled in the art. Summary of the invention

[0004] In view of this, the purpose of this application is to provide a memory system, a memory management method, a device and a medium to solve the problem of contention for communication resources of memory error information and device status information. The specific solution is as follows:

[0005] In a first aspect, the present application provides a memory system, comprising: a plurality of hosts, a switching device, and a plurality of memory devices;

[0006] Wherein, the multiple hosts are connected to multiple upstream physical ports of the switching device, and the multiple memory devices are connected to multiple downstream physical ports of the switching device;

[0007] The switching device includes: a processor; the processor is used to: after receiving a first error interrupt signal sent by any target memory device, obtain error information from the target memory device, write the error information into a target upstream physical port corresponding to the target memory device according to the upstream and downstream port routing relationship of the target memory device, and send a second error interrupt signal to a target host connected to the target upstream physical port, so that the target host processes the error information based on the second error interrupt signal.

[0008] Optionally, the processor is used to: obtain an error type, an error location, and a function number of the target memory device from the target memory device, and generate the error information based on the error type, the error location, and the function number.

[0009] Optionally, the processor is used to: query a preset routing mapping table to obtain the upstream and downstream port routing relationship.

[0010] Optionally, the switching device includes: a switching management controller;

[0011] Accordingly, the processor is used to: send the error type of the error information and the downstream physical port number corresponding to the target memory device to the switch management controller;

[0012] Accordingly, the switch management controller is used to synchronize the error type and the downstream physical port number to the device management controller in the target memory device.

[0013] Optionally, the switch management controller is used to: send a reset command to the device management controller;

[0014] Correspondingly, the device management controller is used to reset and restart the target memory device according to the reset command.

[0015] Optionally, the processor is used to: if it is confirmed that the first error interrupt signal belongs to an MSI interrupt, then use the operating system of the processor to obtain error information from the target memory device; if it is confirmed that the first error interrupt signal belongs to an SMI interrupt, then use the basic input and output system of the processor to obtain error information from the target memory device.

[0016] Optionally, the processor includes: an interrupt processing module, a switching management module and an out-of-band interaction module;

[0017] The interrupt processing module is used to: receive the first error interrupt signal, obtain the error information from the target memory device, write the error information into the target upstream physical port corresponding to the target memory device according to the upstream and downstream port routing relationship of the target memory device, and send a second error interrupt signal to the target host connected to the target upstream physical port;

[0018] The switch management module is used to: configure and manage the switch device; maintain a preset routing mapping table to manage the routing relationship between the upstream and downstream ports of each memory device;

[0019] The out-of-band interaction module is used to interact with a switch management controller in the switch device, so that the switch management controller sends a reset command to a device management controller in the target memory device.

[0020] In a second aspect, the present application provides a memory management method, which is applied to a processor in a switching device, wherein the switching device is arranged in a memory system, and a plurality of upstream physical ports of the switching device are connected to a plurality of hosts in the memory system; a plurality of downstream physical ports of the switching device are connected to a plurality of memory devices in the memory system;

[0021] The method includes:

[0022] receiving a first error interrupt signal sent by any target memory device;

[0023] Obtaining error information from the target memory device;

[0024] Writing the error information into a target upstream physical port corresponding to the target memory device according to the upstream and downstream port routing relationship of the target memory device;

[0025] A second error interrupt signal is sent to a target host connected to the target upstream physical port, so that the target host processes the error information based on the second error interrupt signal.

[0026] Optionally, obtaining error information from the target memory device includes: obtaining an error type, an error location, and a function number of the target memory device from the target memory device, and generating the error information based on the error type, the error location, and the function number.

[0027] Optionally, it also includes:

[0028] The preset routing mapping table is queried to obtain the upstream and downstream port routing relationship.

[0029] Optionally, the switching device includes: a switching management controller;

[0030] The method also includes: sending the error type of the error information and the downstream physical port number corresponding to the target memory device to the switch management controller, so that the switch management controller synchronizes the error type and the downstream physical port number to the device management controller in the target memory device.

[0031] Optionally, the switch management controller further sends a reset command to the device management controller, so that the device management controller resets and restarts the target memory device according to the reset command.

[0032] Optionally, obtaining error information from the target memory device includes: if it is confirmed that the first error interrupt signal belongs to an MSI interrupt, obtaining error information from the target memory device using the operating system of the processor; if it is confirmed that the first error interrupt signal belongs to an SMI interrupt, obtaining error information from the target memory device using the basic input and output system of the processor.

[0033] In a third aspect, the present application provides an electronic device, including:

[0034] Memory for storing computer programs;

[0035] The processor is used to execute the computer program to implement the aforementioned disclosed memory management method.

[0036] In a fourth aspect, the present application provides a non-volatile storage medium for storing a computer program, wherein the computer program implements the aforementioned disclosed memory management method when executed by a processor.

[0037] In a fifth aspect, the present application provides a computer program product, including a computer program / instruction, which implements the steps of the aforementioned disclosed memory management method when executed by a processor.

[0038] It can be seen from the above scheme that the present application provides a memory system, including: multiple hosts, a switching device and multiple memory devices; wherein, the multiple hosts are connected to multiple upstream physical ports of the switching device, and the multiple memory devices are connected to multiple downstream physical ports of the switching device; the switching device includes: a processor; the processor is used to: after receiving a first error interrupt signal sent by any target memory device, obtain error information from the target memory device, write the error information into the target upstream physical port corresponding to the target memory device according to the upstream and downstream port routing relationship of the target memory device, and send a second error interrupt signal to the target host connected to the target upstream physical port, so that the target host processes the error information based on the second error interrupt signal.

[0039] It can be seen that the present application adds a processor in the switching device in the memory system, and the processor can realize the transmission of memory error information of the downstream memory device to the corresponding host. Specifically, after receiving the first error interrupt signal sent by any target memory device, the processor obtains the error information from the target memory device, writes the error information to the target upstream physical port corresponding to the target memory device according to the upstream and downstream port routing relationship of the target memory device, and sends a second error interrupt signal to the target host connected to the target upstream physical port, so that the target host processes the error information based on the second error interrupt signal. In this scheme, the processor in the switching device realizes the transmission of memory error information of the downstream memory device to the corresponding host, and the controller in the memory device only needs to report device status information such as memory temperature to the host BMC, and there is no need to report memory error conditions to the host BMC, which solves the problem of communication resource competition between memory error information and device status information.

[0040] Correspondingly, a memory management method, device and medium provided by the present application also have the above-mentioned technical effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0042] Figure 1 A schematic diagram of a memory system disclosed in this application;

[0043] Figure 2 A schematic diagram of a second memory system disclosed in this application;

[0044] Figure 3 A flow chart of a memory management method disclosed in this application;

[0045] Figure 4 A flow chart of a memory management method disclosed in this application;

[0046] Figure 5 A schematic diagram of an electronic device disclosed in this application;

[0047] Figure 6 A server structure diagram provided for this application;

[0048] Figure 7 A terminal structure diagram provided for this application. DETAILED DESCRIPTION

[0049] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other examples obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0050] At present, in a memory system with multiple memory devices, the controller in the memory device needs to interact frequently with the host BMC (Baseboard Management Controller) to let the host know whether each CXL (Compute Express Link, a high-speed interconnect technology) memory device is wrong. Since the controller in the memory device also needs to report device status information such as memory temperature to the host BMC, it can be seen that there is a phenomenon of communication resource competition between memory error information and device status information. To this end, the present application provides a memory management solution that can realize the transmission of memory error information of downstream memory devices to the corresponding host by the processor in the switching device. The controller in the memory device only needs to report device status information such as memory temperature to the host BMC, and there is no need to report memory errors to the host BMC, which solves the problem of communication resource competition between memory error information and device status information.

[0051] See also Figure 1 As shown, an embodiment of the present application discloses a memory system, including: multiple hosts, a switching device and multiple memory devices; wherein the multiple hosts are connected to multiple upstream physical ports of the switching device, and the multiple memory devices are connected to multiple downstream physical ports of the switching device.

[0052] In this embodiment, the switching device includes a processor; the processor is used to: after receiving a first error interrupt signal sent by any target memory device, obtain error information from the target memory device, write the error information to the target upstream physical port corresponding to the target memory device according to the upstream and downstream port routing relationship of the target memory device, and send a second error interrupt signal to the target host connected to the target upstream physical port, so that the target host processes the error information based on the second error interrupt signal.

[0053] It should be noted that each memory device in the memory system provided in this embodiment is a CXL memory device. The processor may be a low-profile processor, which may not support the CXL protocol itself, but needs to support PCIe, so that the processor can see all downstream CXL memory devices and can send PCIe data packets to them. That is, the processor can communicate with all downstream CXL memory devices through PCIe, and the CXL protocol supports the device to receive data packets in the MCTP over PCIe format, so this format can be used to handle error information. The MCTP (Management Component Transport Protocol) protocol is a transmission protocol for device management and control, which can provide an efficient and reliable solution for communication between devices. PCIe (Peripheral Component Interconnect express) is a high-speed serial computer expansion bus standard.

[0054] In one embodiment, the processor may include: an interrupt processing module, a switching management module and an out-of-band interaction module; the interrupt processing module is used to: receive a first error interrupt signal, obtain error information from a target memory device, write the error information into a target upstream physical port corresponding to the target memory device according to the upstream and downstream port routing relationship of the target memory device, and send a second error interrupt signal to a target host connected to the target upstream physical port; the switching management module (SW management module) is used to: configure and manage the switching device; maintain a preset routing mapping table to manage the upstream and downstream port routing relationship of each memory device; the out-of-band interaction module is used to: interact with a switching management controller in the switching device so that the switching management controller sends a reset command to the device management controller in the target memory device.

[0055] It should also be noted that the processor can obtain the error type, error location and function number of the target memory device from the target memory device, and generate error information based on the error type, error location and function number. The processor can also query the preset routing mapping table to obtain the upstream and downstream port routing relationship. If the processor confirms that the first error interrupt signal belongs to the MSI interrupt, the processor's operating system is used to obtain error information from the target memory device; if the processor confirms that the first error interrupt signal belongs to the SMI interrupt, the processor's basic input and output system is used to obtain error information from the target memory device.

[0056] In one embodiment, the switching device includes: a switching management controller; accordingly, the processor is used to: send the error type of the error information and the downstream physical port number corresponding to the target memory device to the switching management controller; accordingly, the switching management controller is used to: synchronize the error type and the downstream physical port number to the device management controller in the target memory device. The switching management controller is also used to: send a reset command to the device management controller; accordingly, the device management controller is used to: reset and restart the target memory device according to the reset command.

[0057] It can be seen that in this embodiment, a processor is added to the switching device in the memory system, and the processor can realize the transmission of memory error information of the downstream memory device to the corresponding host. Specifically, after receiving the first error interrupt signal sent by any target memory device, the processor obtains error information from the target memory device, writes the error information to the target upstream physical port corresponding to the target memory device according to the upstream and downstream port routing relationship of the target memory device, and sends a second error interrupt signal to the target host connected to the target upstream physical port, so that the target host processes the error information based on the second error interrupt signal. In this solution, the processor in the switching device realizes the transmission of memory error information of the downstream memory device to the corresponding host, and the controller in the memory device only needs to report device status information such as memory temperature to the host BMC, and does not need to report memory error conditions to the host BMC, which solves the problem of communication resource competition between memory error information and device status information.

[0058] See also Figure 2 , the memory system can include three parts: host pool, switch device (CXL Switch) and memory pool. Among them, the host pool is obtained by pooling multiple host terminals, and the memory pool is obtained by pooling multiple CXL memory devices. Each host terminal is equipped with BIOS (Basic Input Output System) and OS (Operating System). Each CXL memory device includes MXC (CXL memory controller) and BMC. MXC (Memory Expander Controller) is a memory expansion controller.

[0059] CXL Switch is a memory switch with mCPU (Management CPU, i.e. the processor mentioned above). The memory switch contains multiple physical ports, which can be divided into upstream and downstream. Figure 2 EP port) is connected to the host side, and the downstream port (i.e. Figure 2 The DSP port in the memory pool is connected to the port of the memory pool. The upstream port can be routed to the downstream port. The mCPU is the management center for managing the memory switch configuration. It can configure the switch registers to control the switch port mapping. Among them, a physical port can be logically mapped to multiple logical ports. Therefore, the mapping of an upstream port to a downstream port actually realizes a one-to-one non-repetitive mapping of multiple upstream logical ports to multiple downstream logical ports.

[0060] See also Figure 3During the normal operation of the memory system, MXC monitors the memory health in real time. When an error occurs, MXC triggers an interrupt to mCPU. mCPU obtains specific error information from MXC through PCIe, including error types, such as correctable error, uncorrectable error, and fatal error; specific error locations, such as dimmrank, channel, bank group, bank, row, and column; PCI Error Message contains the BDF of the device where the error occurs, namely, bus, device, and function. Then mCPU queries the routing mapping table of SW through the I2C (Inter-Integrated Circuit) bus to obtain which EP ports the error device is mapped to; triggers IPMI command to send error information to the BMC of mCPU through the LPC bus (Low Pin Count Bus), which includes the error type and SW Port number; configures SW (i.e. CXL Switch) through the I2C bus to trigger an interrupt to the EP port of the device involved in the error; then, after receiving the error type and SW Port number, the BMC of mCPU synchronizes the information to the BMC in the memory pool. It should be noted that if the same device repeatedly has fatal errors (uncorrectable error or fatal error), the mCPU can send IPMI commands to the BMC control single port to reset the memory device. If it cannot be restored, the corresponding memory device will be powered off. If the host receives an interrupt, the host can use the general PCIe error handling process to handle the interrupt.

[0061] It should be noted that the interrupt triggered by MXC can be in MSI mode or SMI mode. If it is in MSI mode, then MXC receives the memory error and triggers MSI to the OS of mCPU; the OS of mCPU sends a request to MXC through MCTP Over PCIe protocol to obtain the specific error location, and records the obtained MXC error information and MXC location information to the event counter of Switch to retain the error information, finds out which EP ports the error memory is mapped to according to the specific mapping table of Switch, and triggers MSI to these EP ports by operating the SW register, so that the host OS receives MSI and records it, and then the upper-layer software of the host processes it according to the general error handling process. If it is SMI mode, then MXC receives a memory error and triggers SMI to the BIOS of the mCPU, causing the mCPU to enter SMM mode. The BIOS of the mCPU sends an MCTP over PCIe data packet to MXC to obtain specific error information. The BIOS enters the PCIe error handling process to record the error information and triggers IPMI communication to the mCPU BMC to record it. The mCPU BIOS triggers NMI / MSI to the mCPU OS and includes a PCIe Error Message. The mCPU OS receives NMI / MSI and obtains the specific device location of the error according to the BDF message in the PCIe Error Message. The mCPU OS finds out which EP ports the error memory is mapped to according to the specific mapping table of the Switch, and triggers SMI to these EP ports by operating the SW register. After that, the host-side BIOS receives the SMI and enters the general error handling process for processing.

[0062] In this embodiment, the functional modules implemented in the mCPU include: Interrupt processing module: responsible for automatically triggering MCTP Over PCIe to access MXC to obtain specific error information after receiving the interrupt sent by MXC, and responsible for configuring SW to trigger interrupt to the host side through I2C after obtaining the EP port involved in the error. SW management module: responsible for accessing SW based on I2C and PCIe protocols, used to configure and manage SW. The main function in this solution is to query the EP port affected by the error according to the location of the error device. Out-of-band interaction module: responsible for interacting with the Switch BMC. Mainly through IPMI, it can send error information and control the reset and power on and off of downstream devices.

[0063] It can be seen that this embodiment implements a memory fault reporting solution based on in-band, so that the host side can receive CXL memory errors in the memory pool, and is applicable to any version of the CXL protocol, and the host side does not need special adaptation and development.

[0064] A memory management method provided in an embodiment of the present application is introduced below. The memory management method described below can be cross-referenced with other embodiments described in this document.

[0065] The embodiment of the present application discloses a memory management method, which is applied to a processor in a switching device, wherein the switching device is arranged in a memory system, and multiple upstream physical ports of the switching device are connected to multiple hosts in the memory system; multiple downstream physical ports of the switching device are connected to multiple memory devices in the memory system;

[0066] See also Figure 4 As shown, the memory management method disclosed in the embodiment of the present application includes:

[0067] S401. Receive a first error interrupt signal sent by any target memory device.

[0068] S402: Obtain error information from the target memory device.

[0069] S403: Write the error information into the target upstream physical port corresponding to the target memory device according to the upstream and downstream port routing relationship of the target memory device.

[0070] S404: Send a second error interrupt signal to a target host connected to the target upstream physical port, so that the target host processes error information based on the second error interrupt signal.

[0071] In one embodiment, obtaining error information from the target memory device includes: obtaining an error type, an error location, and a function number of the target memory device from the target memory device, and generating error information based on the error type, the error location, and the function number.

[0072] In one implementation, a processor in the switching device queries a preset routing mapping table to obtain the upstream and downstream port routing relationship.

[0073] In one embodiment, the switching device includes: a switching management controller; the method also includes: a processor in the switching device sends the error type of the error information and the downstream physical port number corresponding to the target memory device to the switching management controller, so that the switching management controller synchronizes the error type and the downstream physical port number to the device management controller in the target memory device.

[0074] In one implementation, the switch management controller further sends a reset command to the device management controller, so that the device management controller resets and restarts the target memory device according to the reset command.

[0075] In one embodiment, obtaining error information from a target memory device includes: if it is confirmed that the first error interrupt signal belongs to an MSI interrupt, obtaining error information from the target memory device using the operating system of the processor; if it is confirmed that the first error interrupt signal belongs to an SMI interrupt, obtaining error information from the target memory device using the basic input and output system of the processor.

[0076] Among them, for more specific working processes of each module and unit in this embodiment, reference can be made to the corresponding contents disclosed in the aforementioned embodiments, which will not be repeated here.

[0077] It can be seen that this embodiment provides a memory management method, which can realize the transmission of memory error information of downstream memory devices to the corresponding host by the processor in the switching device. The controller in the memory device only needs to report device status information such as memory temperature to the host BMC, and there is no need to report memory errors to the host BMC, thereby solving the problem of competition for communication resources between memory error information and device status information.

[0078] An electronic device provided in an embodiment of the present application is introduced below, and the electronic device described below can be cross-referenced with other embodiments described herein. The electronic device in this embodiment can be each device, module or component in the aforementioned memory system.

[0079] See also Figure 5 As shown, the embodiment of the present application discloses an electronic device, including:

[0080] Memory 501, used for storing computer programs;

[0081] The processor 502 is used to execute the computer program to implement the method disclosed in any of the above embodiments.

[0082] In this embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: receiving a first error interrupt signal sent by any target memory device; obtaining error information from the target memory device; writing the error information to the target upstream physical port corresponding to the target memory device according to the upstream and downstream port routing relationship of the target memory device; and sending a second error interrupt signal to the target host connected to the target upstream physical port, so that the target host processes the error information based on the second error interrupt signal.

[0083] In this embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: obtaining the error type, error location and function number of the target memory device from the target memory device, and generating error information based on the error type, error location and function number.

[0084] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: querying a preset routing mapping table to obtain an upstream and downstream port routing relationship.

[0085] In this embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: the error type of the error information and the downstream physical port number corresponding to the target memory device are sent to the switching management controller, so that the switching management controller synchronizes the error type and the downstream physical port number to the device management controller in the target memory device.

[0086] In this embodiment, when the processor executes the computer program stored in the memory, the following steps may be specifically implemented: sending a reset command to the device management controller, so that the device management controller resets and restarts the target memory device according to the reset command.

[0087] In this embodiment, when the processor executes the computer program stored in the memory, the following steps can be specifically implemented: if it is confirmed that the first error interrupt signal belongs to an MSI interrupt, the error information is obtained from the target memory device using the operating system of the processor; if it is confirmed that the first error interrupt signal belongs to an SMI interrupt, the error information is obtained from the target memory device using the basic input and output system of the processor.

[0088] Furthermore, the present application also provides an electronic device. The electronic device can be Figure 6 The server shown can also be Figure 7 Terminal shown. Figure 6 and Figure 7 All of them are structural diagrams of electronic devices according to an exemplary embodiment, and the contents in the diagrams cannot be regarded as any limitation on the scope of use of the present application.

[0089] Figure 6 A schematic diagram of the structure of a server provided in an embodiment of the present application. The server may specifically include: at least one processor, at least one memory, a power supply, a communication interface, an input / output interface, and a communication bus. The memory is used to store a computer program, and the computer program is loaded and executed by the processor to implement the relevant steps in the memory management disclosed in any of the aforementioned embodiments.

[0090] In this embodiment, the power supply is used to provide working voltage for each hardware device on the server; the communication interface can create a data transmission channel between the server and external devices, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of the present application, and is not specifically limited here; the input and output interface is used to obtain external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0091] In addition, the memory as a carrier for resource storage can be a read-only memory, random access memory, disk or CD, etc. The resources stored thereon include operating system, computer programs and data, etc. The storage method can be temporary storage or permanent storage.

[0092] The operating system is used to manage and control the hardware devices and computer programs on the server to realize the operation and processing of the data in the memory by the processor, and it can be Windows Server, Netware, Unix, Linux, etc. In addition to the computer program that can be used to complete the memory management method disclosed in any of the aforementioned embodiments, the computer program can further include computer programs that can be used to complete other specific tasks. In addition to data such as application update information, the data can also include data such as application developer information.

[0093] Figure 7 A schematic diagram of the structure of a terminal provided in an embodiment of the present application, the terminal may specifically include but is not limited to a smart phone, a tablet computer, a laptop computer or a desktop computer, etc.

[0094] Generally, the terminal in this embodiment includes: a processor and a memory.

[0095] Among them, the processor may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor may also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.

[0096] The memory may include one or more computer non-volatile storage media, which may be non-transitory. The memory may also include high-speed random access memory, and non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In this embodiment, the memory is at least used to store the following computer program, wherein, after the computer program is loaded and executed by the processor, it can implement the relevant steps in the memory management method performed by the terminal side disclosed in any of the aforementioned embodiments. In addition, the resources stored in the memory may also include an operating system and data, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system may include Windows, Unix, Linux, etc. The data may include, but is not limited to, update information of the application.

[0097] In some embodiments, the terminal may also include a display screen, an input and output interface, a communication interface, a sensor, a power supply, and a communication bus.

[0098] Those skilled in the art will understand that Figure 7 The structure shown in the figure does not constitute a limitation on the terminal, and may include more or fewer components than those shown in the figure.

[0099] A non-volatile storage medium provided in an embodiment of the present application is introduced below. The non-volatile storage medium described below can be cross-referenced with other embodiments described herein.

[0100] A non-volatile storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the memory management method disclosed in the above embodiment. The non-volatile storage medium is a computer-readable non-volatile storage medium, which, as a carrier for storing resources, may be a read-only memory, a random access memory, a disk or an optical disk, etc. The resources stored thereon include an operating system, a computer program, and data, etc., and the storage method may be temporary storage or permanent storage.

[0101] A computer program product provided in an embodiment of the present application is introduced below. The computer program product described below can be cross-referenced with other embodiments described in this document.

[0102] A computer program product includes a computer program / instruction, which implements the steps of the aforementioned disclosed memory management method when executed by a processor.

[0103] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0104] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of non-volatile storage medium known in the art.

[0105] Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A memory system, characterized in that: include: Multiple hosts, switching devices, and multiple memory devices; Wherein, the multiple hosts are connected to multiple upstream physical ports of the switching device, and the multiple memory devices are connected to multiple downstream physical ports of the switching device; The switching device includes: a processor; the processor is used to: after receiving a first error interrupt signal sent by any target memory device, obtain error information from the target memory device, write the error information into a target upstream physical port corresponding to the target memory device according to the upstream and downstream port routing relationship of the target memory device, and send a second error interrupt signal to a target host connected to the target upstream physical port, so that the target host processes the error information based on the second error interrupt signal.

2. The memory system according to claim 1, wherein: The processor is used for obtaining an error type, an error location and a function number of the target memory device from the target memory device, and generating the error information based on the error type, the error location and the function number.

3. The memory system according to claim 1, wherein: The processor is used to query a preset routing mapping table to obtain the upstream and downstream port routing relationship.

4. The memory system according to claim 1, wherein: The switching device comprises: a switching management controller; Accordingly, the processor is used to: send the error type of the error information and the downstream physical port number corresponding to the target memory device to the switch management controller; Accordingly, the switch management controller is used to synchronize the error type and the downstream physical port number to the device management controller in the target memory device.

5. The memory system according to claim 4, characterized in that: The switch management controller is used to: send a reset command to the device management controller; Correspondingly, the device management controller is used to reset and restart the target memory device according to the reset command.

6. The memory system according to claim 1, wherein: The processor is used to: if it is confirmed that the first error interrupt signal belongs to an MSI interrupt, then use the operating system of the processor to obtain error information from the target memory device; if it is confirmed that the first error interrupt signal belongs to an SMI interrupt, then use the basic input and output system of the processor to obtain error information from the target memory device.

7. The memory system according to any one of claims 1 to 6, characterized in that: The processor includes: an interrupt processing module, a switching management module and an out-of-band interaction module; The interrupt processing module is used to: receive the first error interrupt signal, obtain the error information from the target memory device, write the error information into the target upstream physical port corresponding to the target memory device according to the upstream and downstream port routing relationship of the target memory device, and send a second error interrupt signal to the target host connected to the target upstream physical port; The switch management module is used to: configure and manage the switch device; maintain a preset routing mapping table to manage the routing relationship between the upstream and downstream ports of each memory device; The out-of-band interaction module is used to interact with a switch management controller in the switch device, so that the switch management controller sends a reset command to a device management controller in the target memory device.

8. A memory management method, characterized in that: A processor applied to a switching device, wherein the switching device is arranged in a memory system, and a plurality of upstream physical ports of the switching device are connected to a plurality of hosts in the memory system; The plurality of downstream physical ports of the switching device are connected to a plurality of memory devices in the memory system; The method includes: receiving a first error interrupt signal sent by any target memory device; Obtaining error information from the target memory device; Writing the error information into a target upstream physical port corresponding to the target memory device according to the upstream and downstream port routing relationship of the target memory device; A second error interrupt signal is sent to a target host connected to the target upstream physical port, so that the target host processes the error information based on the second error interrupt signal.

9. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to execute the computer program to implement the method according to claim 8.

10. A non-volatile storage medium, characterized in that: Used to store a computer program, wherein the computer program implements the method according to claim 8 when executed by a processor.

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