Cyclic redundancy check comparison for error detection

Abstract

The invention relates to cyclic redundancy check (CRC) comparison for error detection. The host system may determine an error cause associated with writing data to or reading data from the memory system. To write data, the host system may transmit data and CRC values to the memory system. The memory system may compute another CRC value and indicate an error and the computed CRC value based on the receiving being different from the computed CRC value. The host system may compare the calculated CRC value to the initially transmitted CRC value to determine an error cause. To read data, the host system may receive data and an associated CRC value from the memory system, calculate a CRC value using the received data, and determine an error cause based on a comparison of the received CRC value, the calculated CRC, and an expected CRC value.

Description

[0001] Cross Reference

[0002] This patent application claims priority to U.S. Patent Application No. 18 / 774,412, filed by Schneider et al. on July 16, 2024, entitled “CYCLIC REDUNDANCY CHECK COMPARISON FOR ERROR DETECTION,” and U.S. Provisional Patent Application No. 63 / 585,768, filed by Schneider et al. on September 27, 2023, entitled “CYCLIC REDUNDANCY CHECK COMPARISON FOR ERROR DETECTION,” each of which is assigned to its assignee and each of which is expressly incorporated herein by reference in its entirety.

[0003] The technical field relates to cyclic redundancy check (CRC) comparison for error detection. Background Art

[0004] Memory devices are used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and others. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell is programmable to one of two supported states, typically represented by a logical 1 or a logical 0. In some examples, a single memory cell may support more than two states, either of which may be stored by the memory cell. To store information, a memory device may write (e.g., program, set, assign) a state to a memory cell. To access stored information, a memory device may read (e.g., sense, detect, retrieve, determine) a state from a memory cell. Summary of the invention

[0005] A method is described. The method may include transmitting data via a set of data channels and transmitting via an error detection channel a first indication of a first cyclic redundancy check (CRC) value corresponding to the data, receiving a second indication of an error associated with the first CRC value, and receiving a third indication of a second CRC value corresponding to the data based at least in part on receiving the second indication of the error.

[0006] A method is described. The method may include receiving data via a set of data channels and receiving a first indication of a first cyclic redundancy check (CRC) value corresponding to the data via an error detection channel; calculating a second CRC value based at least in part on the data; transmitting a second indication of an error based at least in part on the first CRC value being different from the second CRC value; and transmitting a third indication of the second CRC value based at least in part on transmitting the second indication of the error.

[0007] A method is described. The method may include transmitting a command to a memory system to read data from the memory system, receiving the data via a set of data channels and receiving a first indication of a first cyclic redundancy check (CRC) value associated with the data via an error detection channel, calculating a second CRC value based at least in part on the data, and determining an error type associated with the data based at least in part on a comparison of the first CRC value associated with the data, the second CRC value, and an expected CRC value. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 An example of a system supporting cyclic redundancy check (CRC) comparison for error detection according to examples disclosed herein is presented.

[0009] Figure 2 An example of an architecture supporting CRC comparison for error detection according to examples disclosed herein is shown.

[0010] Figure 3 and 4 An example of a system supporting CRC comparison for error detection according to examples disclosed herein is presented.

[0011] Figure 5 A block diagram of a host system supporting CRC comparison for error detection according to examples disclosed herein is shown.

[0012] Figure 6 A block diagram of a memory system supporting CRC comparison for error detection according to examples disclosed herein is shown.

[0013] Figures 7 to 9 A flow chart illustrating one or several methods supporting CRC comparison for error detection according to examples disclosed herein is shown. DETAILED DESCRIPTION

[0014] Some systems may utilize a cyclic redundancy check (CRC) to detect errors in data. For example, a CRC value may be calculated based on the data, and the CRC values ​​calculated using the same data may be the same. Therefore, the difference in the CRC value may indicate an error in the data and it may be caused by an error in the transmission, storage, or retrieval of the data and / or the transmission of the CRC value. For example, a host system may calculate a CRC value associated with the data and may transmit the data and the associated CRC value to a memory system. After receiving the data and the CRC value, the memory system may calculate another CRC value using the received data (e.g., before storing the data, after storing and retrieving the data). The memory system may compare the CRC value calculated by the memory system with the CRC value received from the host system. If the received CRC value does not match the CRC value calculated by the memory system, the memory system may transmit an error flag indicating an error to the host system, which may be referred to as a CRC error. However, while indicating a detected error to the host system may be beneficial to the memory system, neither the memory system nor the host system can determine which link in the data transmission, storage, or retrieval or in the CRC transmission may have an error, which may result in more errors and / or ineffective or inefficient error correction techniques.

[0015] According to the examples described herein, the memory system and the host system may support determining one or more causes of a CRC error based on a comparison of a CRC value associated with the data, which may support the implementation of efficient and effective correction actions. For example, the host system and the memory system may support determining the cause of an error associated with writing data to the memory system. To support this determination, in addition to the indication of a CRC error, the memory system may also transmit a CRC value calculated by the memory system to the host system. The host system may utilize the CRC value initially transmitted to the memory system and the CRC value calculated by the memory system received from the memory system to determine the cause of the error at a finer granularity. For example, the CRC value initially transmitted is different from the CRC value calculated by the memory system, which may indicate that the error is associated with at least the transmission, storage, or retrieval of the data. The CRC value initially transmitted is different from the CRC value calculated by the memory system, which may indicate that the error is associated with the transmission of the original CRC value from the host system to the memory system.

[0016] Additionally or alternatively, the host system may support determining the cause of an error associated with reading data from the memory system. For example, the host system may transmit a command to read data from the memory system. According to the command, the memory system may calculate a CRC value associated with the requested data and transmit the data and the CRC value to the host system. The host system may receive the data and the CRC value and may calculate another CRC value using the received data. The host system may compare the CRC value calculated from the received data with the CRC value received from the memory system and the expected CRC value (e.g., the CRC value associated with the data received from the memory system expected by the host system) to determine one or more causes of a CRC error. For example, as described herein, the comparison of the CRC value may indicate whether the CRC error is associated with the memory system transmitting the CRC value or with data before or after the CRC value is calculated. By implementing the error cause determination techniques described herein, the error cause may be determined at a finer granularity, which may support relatively more efficient and effective error correction techniques to support improved performance and other benefits of the memory system.

[0017] Features of the present disclosure are illustrated and described in the context of systems and architectures. Features of the present disclosure are further illustrated and described in the context of block diagrams and flow charts.

[0018] Figure 1 An example of a system 100 supporting CRC comparison for error detection according to examples disclosed herein is illustrated. The system 100 may include a portion of an electronic device, such as a computing device, a mobile computing device, a wireless communication device, a graphics processing device, a vehicle, a smartphone, a wearable device, an Internet-connected device, a vehicle controller, a single-chip system (SoC), or other fixed or portable electronic system, among other examples. The system 100 includes a host system 105, a memory device 110, and one or more channels 115 coupling the host system 105 with the memory device 110 (e.g., for supporting a communication coupling). The system 100 may include any number of one or more memory systems 110 coupled to the host system 105.

[0019] The host system 105 may include one or more components (e.g., circuitry, processing circuitry, one or more processing components) that use memory to perform processes, any one or more of which may be referred to as or included in a processor 125. The processor 125 may include at least one of one or more processing elements that may be co-located or distributed, including a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a controller, discrete gate or transistor logic, one or more discrete hardware components, or a combination thereof. The processor 125 may be an example of a central processing unit (CPU), a graphics processing unit (GPU), a general purpose GPU (GPGPU), or a SoC, or components thereof, as well as other examples.

[0020] The host system 105 may also include at least one of one or more components (e.g., circuitry, logic, instructions) that implement the functionality of an external memory controller (e.g., a host system memory controller), which may be referred to as or included in a host system controller 120. For example, the host system controller 120 may issue commands or other signaling for operating the memory system 110, such as write commands, read commands, configuration signaling, or other operational signaling. In some examples, the host system controller 120 or associated functions described herein may be implemented by or be part of the processor 125. For example, the host system controller 120 may be hardware, instructions (e.g., software, firmware), or some combination thereof implemented by the processor 125 or other components of the host system 105. In various examples, the host system 105 or the host system controller 120 may be referred to as a host.

[0021] The memory system 110 provides physical memory locations (e.g., addresses) that can be used or referenced by the system 100. The memory system 110 can include a memory system controller 140 and one or more memory devices 145 (e.g., memory packages, memory dies, memory chips) operable to store data. The memory system 110 can be configured to operate with different types of host systems 105, and can respond to commands from the host system 105 (e.g., from the host system controller 120). For example, the memory system 110 (e.g., the memory system controller 140) can receive a write command instructing the memory system 110 to store data received from the host system 105, or receive a read command instructing the memory system 110 to provide data stored in the memory device 145 to the host system 105, or receive a refresh command instructing the memory system 110 to refresh data stored in the memory device 145, as well as other types of commands and operations.

[0022] The memory system controller 140 may include at least one of one or more components (e.g., circuitry, logic, instructions) operable to control the operation of the memory system 110. The memory system controller 140 may include hardware or instructions that support the memory system 110 to perform various operations, and may be operable to receive, transmit, or respond to commands, data, or control information related to the operation of the memory system 110. The memory system controller 140 may be operable to communicate with one or more of the host system controller 120, one or more memory devices 145, or the processor 125. In some examples, the memory system controller 140 may cooperate with the host system controller 120, the local controller 150 of the memory device 145, or any combination thereof to control the operation of the memory system 110. Although examples of the memory system controller 140 are illustrated as separate components of the memory system 110, in some examples, aspects of the functionality of the memory system 110 may be implemented by at least one of the processor 125, the host system controller 120, the one or more local controllers 150, or any combination thereof.

[0023] Each memory device 145 may include a local controller 150 and one or more memory arrays 155. The memory array 155 may be a collection of memory cells (e.g., a two-dimensional array, a three-dimensional array), each of which is operable to store data (e.g., as one or more memory bits). Each memory array 155 may include memory cells of various architectures, such as random access memory (RAM) cells, dynamic RAM (DRAM) cells, synchronous dynamic RAM (SDRAM) cells, static RAM (SRAM) cells, ferroelectric RAM (FeRAM) cells, magnetic RAM (MRAM) cells, resistive RAM (RRAM) cells, phase change memory (PCM) cells, chalcogenide memory cells, or NOR memory cells and NAND memory cells or any combination thereof.

[0024] The local controller 150 may include at least one of one or more components (e.g., circuitry, logic, instructions) operable to control the operation of the memory device 145. In some examples, the local controller 150 may be operable to communicate with the memory system controller 140 (e.g., receive or transmit data or commands or both). In some examples, the memory system 110 may not include the memory system controller 140, and the local controller 150 or the host system controller 120 may perform the functions of the memory system controller 140 described herein. In some examples, the local controller 150 or the memory system controller 140 or both may include a decoding component operable to access addresses of the memory array 155, a sensing component for sensing the state of the memory cells of the memory array 155, a writing component for writing the state to the memory cells of the memory array 155, or various other components operable to support the described operations of the memory system 110.

[0025] The host system 105 (e.g., host system controller 120) and the memory system 110 (e.g., memory system controller 140) may communicate information (e.g., data, commands, control information, configuration information) using one or more channels 115. Each channel 115 may be an example of a transmission medium that carries information, and each channel 115 may include one or more signal paths (e.g., transmission media, electrical conductors, conductive paths) between terminals (e.g., nodes, pins, contacts) associated with components of the system 100. Terminals may be examples of conductive input or output points of devices of the system 100, and terminals may operate as part of a channel 115. To support communication via channel 115, host system 105 (e.g., host system controller 120) and memory system 110 (e.g., memory system controller 140) may include a receiver (e.g., a latch) for receiving signals, a transmitter (e.g., a driver) for transmitting signals, a decoder for decoding or demodulating received signals or an encoder for encoding or modulating signals to be transmitted, and other components that support signaling via channel 115, which may be included in corresponding interface portions of the corresponding systems.

[0026] The channels 115 are dedicated to conveying one or more types of information, and the channels 115 may include unidirectional channels, bidirectional channels, or both. For example, the channels 115 may include one or more command / address channels, one or more clock signal channels, one or more data channels, and other channels or combinations thereof. In some examples, the channels 115 may be configured to provide power from one system to another (e.g., from the host system 105 to the memory system 110, according to the regulated voltage). In some examples, at least a subset of the channels 115 may be configured according to a protocol (e.g., a logic protocol, a communication protocol, an operating protocol, an industry standard), which may support configuration operations and interactions between the host system 105 and the memory system 110.

[0027] The command / address channel (e.g., CA channel) is operable to communicate commands between the host system 105 and the memory system 110, including control information associated with the commands (e.g., address information, configuration information). The commands carried by the command / address channel may include a write command having an address of data to be written to the memory system 110 or a read command having an address of data to be read from the memory system 110.

[0028] The clock signal channel may be operable to communicate one or more clock signals between the host system 105 and the memory system 110. The clock signal may oscillate between a high state and a low state and may support coordination (e.g., in time) between the operations of the host system 105 and the memory system 110. In some examples, the clock signal may provide a timing reference for the operations of the memory system 110. The clock signal may be referred to as a control clock signal, a command clock signal, or a system clock signal. The system clock signal may be generated by a system clock, which may include one or more hardware components (e.g., oscillators, crystals, logic gates, transistors).

[0029] The data channel 160 (e.g., DQ channel) is operable to communicate information (e.g., data 170, control information) between the host system 105 and the memory system 110 (e.g., bidirectionally). For example, the data communication may communicate information written from the host system 105 to the memory system 110 or information read from the memory system 110 to the host system 105. In some examples, the channel 115 may include one or more error detection code (EDC) channels 165. The EDC channel 165 is operable to communicate error detection signals (e.g., one or more CRC values ​​175, checksum or parity bits), which may accompany the information passed through the data channel. In some examples, the EDC channel 165 may be an example of a DQE channel, which is operable to communicate error detection signals and may additionally or alternatively be operable to communicate one or more data symbols, severity (SEV) information, poison (PSN) information, or a combination thereof.

[0030] According to examples described herein, the memory system 110 and the host system 105 may be configured to determine one or more causes of a CRC error based on a comparison of a CRC value 175 associated with the data 170, which may support implementation of efficient and effective corrective actions. The host system 105 may be configured to determine a cause of a CRC error associated with writing the data 170 to the memory system 110. For example, the host system 105 may transmit the data 170 and the associated CRC value 175 to the memory system 110 (e.g., via the data channel 160 and the EDC channel 165, respectively). The memory system 110 may store the data 170 and may calculate another CRC value 175 using the data 170 received from the host system 105 (e.g., the stored data 170). The memory system 110 may compare the CRC value 175 received from the host system 105 (e.g., which may be different from the CRC value 175 originally transmitted by the host system 105, such as based on errors associated with transmitting the CRC value 175 via the EDC channel 165) with the calculated CRC value 175. If the two CRC values ​​are not identical, the memory system 110 may transmit an indication of a CRC error to the host system 105. Based on the CRC error, the memory system 110 may transmit a calculated CRC value 175 to the host system 105. The host system 105 may compare the CRC value 175 originally transmitted to the memory system 110 with the calculated CRC value 175 received from the memory system 110 to determine the cause of the error at a finer granularity. For example, the originally transmitted CRC value 175 and the calculated CRC value 175 being different may indicate that an error is associated with at least the transmission, storage, or retrieval of the data 170. The originally transmitted CRC value 175 and the calculated CRC value 175 being different may indicate that an error is associated with transmitting the original CRC value 175 via the EDC channel 165.

[0031] Additionally or alternatively, the host system 105 may be configured to determine a cause of an error associated with reading data from the memory system 110. For example, the host system 105 may transmit a command to read data 170 from the memory system 110. In accordance with the command, the memory system 110 may calculate a CRC value 175 associated with the requested data 170 and transmit the data 170 and the CRC value 175 to the host system 105 (e.g., via the data channel 160 and the EDC channel 165, respectively). The host system 105 may receive the data 170 and the calculated CRC value 175 and may calculate another CRC value 175 using the received data 170. The host system 105 may compare the CRC value 175 calculated from the received data 170, the CRC value 175 received from the memory system 110, and an expected CRC value 175 (e.g., a CRC value 175 associated with the data 170 that the host system 105 expects to receive from the memory system 110) to determine one or more causes of a CRC error. For example, a comparison of CRC values ​​may indicate whether a CRC error is associated with the memory system transmitting the CRC value or with data before or after the CRC value is calculated. By implementing the error cause determination techniques described herein, error causes may be determined at a finer granularity, which may support relatively more efficient and effective error correction techniques to support improved performance of the memory system, among other benefits.

[0032] In addition to being applied in the systems described herein, error detection techniques utilizing CRC comparisons may generally be implemented to improve the performance of various electronic devices and systems (including games). Some electronic device applications, including games and other high-performance applications, may be associated with relatively high processing requirements, while also benefiting from relatively fast response times to improve the user experience. Thus, it may be desirable to increase processing speed, reduce response time, or otherwise improve electronic device performance. Implementation of the techniques described herein may improve electronic device performance by improving error detection and correction techniques, which may reduce the occurrence of errors, may improve memory access speeds, reduce processing or latency times, improve response times, or otherwise improve the user experience, among other benefits.

[0033] Figure 2 An example of an architecture 200 (e.g., a memory architecture) that supports CRC comparisons for error detection according to examples disclosed herein is illustrated. The architecture 200 can be implemented in the memory system 110 or one or more components thereof (e.g., the memory device 145). Aspects of the architecture 200 can be referred to or implemented in a semiconductor component (e.g., a memory die).

[0034] The architecture 200 includes memory cells 205 that are programmable to store information. In some examples, the memory cells 205 are operable to store one bit of information at a time (e.g., a logical 0 or a logical 1). In some examples, the memory cells 205 (e.g., multi-level memory cells) are operable to store more than one bit of information at a time (e.g., a logical 00, a logical 01, a logical 10, a logical 11). The memory cells 205 can be arranged in an array, such as the memory array 155.

[0035] In the example of architecture 200, memory cell 205 may include a storage component (e.g., capacitor 230) and a selection component 235 (e.g., a cell selection component, a transistor). Capacitor 230 may be a dielectric capacitor or a ferroelectric capacitor. A node of capacitor 230 may be coupled to a voltage source 240, which may be a cell plate reference voltage (e.g., Vpl) or may be a ground voltage (e.g., Vss). The charge stored by memory cell 205 (e.g., by capacitor 230) may represent a programming state. Other memory architectures supporting the techniques described herein may implement different types or arrangements of storage components and associated circuitry (e.g., with or without selection components).

[0036] The architecture 200 may include various arrangements of access lines, such as word lines 210 and digit lines 215. The access lines may be conductive lines coupled to the memory cells 205 and may be used to perform access operations on the memory cells 205. The word lines 210 may be referred to as row lines, and the digit lines 215 may be referred to as column lines or bit lines, among other nomenclatures. The memory cells 205 may be located at the intersections of the access lines, and the intersections may be referred to as the addresses of the memory cells 205.

[0037] In some architectures, the word line 210 can be coupled to the gate of the selection element 235 of the memory cell 205 and can be operated to control the selection element 235 (e.g., switch, modulate the conductivity of the selection element 235). The digit line 215 can be operated to couple the memory cell 205 with the sensing element 245. In some architectures, the memory cell 205 (e.g., the capacitor 230) can be coupled to the digit line 215 during a portion of the access operation. For example, the word line 210 and the selection element 235 of the memory cell 205 can be operated to couple or isolate the capacitor 230 of the memory cell 205 from the digit line 215.

[0038] Operations such as reading and writing can be performed on the memory cell 205 by activating (e.g., applying a voltage to) an access line such as a word line 210 or a digit line 215. Access to the memory cell 205 can be controlled by a row decoder 220 or a column decoder 225, or a combination thereof. For example, the row decoder 220 can receive a row address (e.g., from a local memory controller 260) and activate the word line 210 based on the received row address, and the column decoder 225 can receive a column address and activate the digit line 215 based on the received column address. Selecting or deselecting the memory cell 205 can include activating or deactivating the selection component 235 using the word line 210. For example, the capacitor 230 can be isolated from the digit line 215 when the selection component 235 is deactivated, and the capacitor 230 can be coupled to the digit line 215 when the selection component 235 is activated.

[0039] The sensing component 245 is operable to detect a state (e.g., charge) stored by the capacitor 230 of the memory cell 205 and determine a logic state of the memory cell 205 based on the stored state. The sensing component 245 may include one or more sense amplifiers for amplifying or otherwise converting a signal caused by accessing the memory cell 205. The sensing component 245 may compare the signal detected from the memory cell 205 with a reference 250 (e.g., a reference voltage). The detected logic state of the memory cell 205 may be provided as an output of the sensing component 245 (e.g., via an input / output 255), and the detected logic state may be indicated to another component of the memory system 110 implementing the architecture 200.

[0040] The local memory controller 260 can control access to the memory cells 205 through various components (e.g., row decoder 220, column decoder 225, sense component 245), and can be an instance of or otherwise included in the local controller 150 or the memory system controller 140 or both. In some examples, one or more of the row decoder 220, column decoder 225, and sense component 245 can be co-located with or included in the local memory controller 260. The local memory controller 260 can be operable to receive commands or data from one or more different controllers (e.g., host system controller 120, memory system controller 140), translate the commands or data into information that can be used by the architecture 200, initiate or control one or more operations of the architecture 200, and communicate data from the architecture 200 to the host (e.g., host system 105) based on performing one or more operations.

[0041] The local memory controller 260 is operable to perform one or more access operations on one or more memory cells 205 of the architecture 200. Examples of access operations may include write operations, read operations, refresh operations, precharge operations, or activate operations, among others. In some examples, the access operations may be performed or otherwise coordinated by the local memory controller 260 in response to one or more access commands (e.g., from the host system 105). The local memory controller 260 is operable to perform other access operations not listed here or other operations related to the operation of the architecture 200 that are not directly related to accessing the memory cells 205.

[0042] According to the examples described herein, a memory system (e.g., an implementation architecture 200 thereof) and a host system may be configured to determine one or more causes of a CRC error based on a comparison of a CRC value 270 associated with data 265, which may support the implementation of efficient and effective corrective actions. The host system may be configured to determine the cause of an error associated with writing data 265 to the memory system. For example, the host system may transmit data 265 and an associated CRC value 270 to the memory system. The memory system may store the data 265 and may calculate another CRC value 270 using the stored data 265. The memory system may compare the received CRC value 270 with the calculated CRC value 270 and if the two CRC values ​​are not the same, an indication of a CRC error and the calculated CRC value 270 may be transmitted to the host system. The host system may utilize the CRC value 270 initially transmitted to the memory system and the calculated CRC value 270 received from the memory system to determine the cause of the error at a finer granularity, such as occurring on an EDC channel or caused by the transmission, storage, or retrieval of data 265.

[0043] Additionally or alternatively, the host system may be configured to determine a cause of an error associated with reading data 265 from the memory system. For example, the memory system may calculate a CRC value 270 associated with the data 265 requested by the host system and transmit the data 265 and the CRC value 270 to the host system. The host system may receive the data 265 and the CRC value 270 and may calculate another CRC value 270 using the received data 265. The host system may compare the CRC value 270 calculated from the received data 265 with a CRC value received from the memory system and an expected CRC value (e.g., a CRC value that may be associated with data that the host system may expect from the memory system) to determine one or more causes of a CRC error.

[0044] Figure 3 An example of a system 300 supporting CRC comparison for error detection according to examples disclosed herein is shown. The system 300 may be provided by reference to Figure 1 and 2The described system 100, architecture 200, or one or more components thereof (eg, host system 105, memory system 110, local memory controller 260) implements aspects of the system 300. The system 300 may support relatively finer-grained determination of causes of CRC errors associated with writing data to a memory system.

[0045] System 300 may include a host system 305 and a memory system 310, which may be any of the foregoing (including references to Figure 1 and 2 ) is an example of a corresponding system described in the accompanying drawings. The host system 305 can communicate with the memory system 310 via one or more channels, such as a CA channel 312, one or more data channels 315 (such as one or more DQ channels), and an EDC channel 320 (such as a DQE channel), which can be referenced Figure 1 In addition, although the non-limiting examples of system 300 herein are generally described in terms of application to a memory system, a memory subsystem, a memory device, or a combination thereof, examples of system 300 are not limited thereto. For example, aspects of the present disclosure may be equally applicable to any computing system, computing subsystem, processing system, processing subsystem, component, device, structure, or other type of system or subsystem used for applications such as data collection, data processing, data storage, networking, communication, power, artificial intelligence, single chip system, control, telemetry, sensing and monitoring, digital entertainment, or any combination thereof.

[0046] The host system 305 and the memory system 310 may include components for supporting improved error cause determination techniques. For example, the host system 305 may include an error detector 365 that can compare one or more CRC values ​​to determine the cause of a CRC error. The memory system 310 may include a CRC calculator 335. The memory system 310 may input data 330 received from the host system 305 via the data channel 315 into the CRC calculator 335, and the CRC calculator 335 may generate (e.g., calculate) a calculated CRC value 340 associated with (e.g., based on) the data 330. In some examples, the calculated CRC value 340 (e.g., and one or more other CRC values) may be used to support error detection associated with the data 330 (e.g., caused by transmission of the data 330, storage of the data 330, retrieval of the stored data 330) or associated with the communication of the CRC value associated with the data 330. For example, the memory system 310 may include an error detector 355 that may receive as input the calculated CRC value 340 and the CRC value 350 received from the host system 305 via the EDC channel 320 and may compare the calculated CRC value 340 with the received CRC value 350 to detect errors. If the error detector 355 determines that the calculated CRC value 340 and the CRC value 350 may not match, the error detector 355 may indicate a CRC error to the host system 305 (e.g., output an indication of a CRC error).

[0047] According to examples described herein, the host system 305 may compare CRC values ​​associated with the data 330 to determine where detected errors may have occurred as part of a write operation. For example, the host system 305 may transmit data (e.g., data 330) and an associated CRC value (e.g., CRC value 370 calculated using the data) to the memory system 310. The host system 305 may transmit the data via a data channel 315 (e.g., a DQ pin, a DQ channel) and may transmit the CRC value 370 via an EDC channel 320. The memory system 310 may receive the data and the CRC value. The data 330 may be the same as the data transmitted by the host system 305, e.g., if there are no errors associated with the transmission of data to the memory system 310 (e.g., and / or the storage of data or the retrieval of data from a memory array of the memory system). The data 330 may be different from the data transmitted by the host system 305, e.g., if there are errors associated with the transmission of data (e.g., storage and / or retrieval). Similarly, CRC value 350 received from host system 305 may be the same as CRC value 370 transmitted by the host system, e.g., if there are no errors associated with transmitting CRC value 370 via EDC channel 320. Alternatively, CRC value 350 may be different from CRC value 370, e.g., if there are errors associated with transmitting CRC value 370 via EDC channel 320. In some examples, memory system 310 may store data received from host system 305 to a memory array of memory system 310 (e.g., and temporarily store received CRC value 350).

[0048] The memory system 310 may calculate a CRC value 340 based on the data 330 (e.g., which may correspond to data received from the host system 305 or data stored to and retrieved from a memory array of the memory system 310) and may compare the CRC value 340 with the CRC value 350. For example, the memory system 310 may input the data 330 into a CRC calculator 335. The CRC calculator 335 may utilize the data 330 to generate the CRC value 340. For example, the CRC calculator 335 may use a function that uses the data 330 as an input to the function to output the CRC value 340. The memory system 310 may input the CRC value 340 and the CRC value 350 to an error detector 355, and the error detector 355 may compare the CRC value 340 with the CRC value 350. If CRC value 340 is not the same as CRC value 350 (e.g., does not match), then one or more errors may have occurred before CRC values ​​340 and 350 were compared, such as during the transmission of data via data channel 315, during the storage of data 330 to a memory array of memory system 310, during the retrieval of data from the memory array, during the transmission of CRC value 370 via EDC channel 320, or a combination thereof.

[0049] The host system 305 and the memory system 310 may support determining the location where one or more errors occurred with finer granularity. For example, in response to detecting a CRC error (e.g., CRC values ​​340 and 350 are different), the memory system 310 (e.g., the error detector 355) may store the CRC value 340 to a storage device 345 of the memory system 310. In some examples, the storage device 345 may be a temporary storage device of the memory system 310, a register of the memory system 310, a cache of the memory system 310, and other possible types of storage devices of the memory system 310. In addition, the memory system 310 may indicate the error to the host system 305. For example, in response to detecting the error, the error detector 355 may transmit a CRC error flag 360 indicating that the CRC values ​​340 and 350 are different (e.g., do not match) to the host system 305. In some examples, if a CRC error is not detected (e.g., error detector 355 determines that CRC values ​​340 and 350 are the same), CRC error flag 360 is not transmitted and CRC value 340 may be discarded (e.g., memory system 310 may not store CRC value 340). In some other examples, CRC value 340 may initially be stored to storage device 345 prior to an error determination by error detector 355 and discarded (e.g., deleted from storage device 345) when a CRC error is not detected.

[0050] The memory system 310 may transmit a CRC value 340 (e.g., a calculated CRC value) to the host system 305. For example, in response to receiving the CRC error flag 360, the host system 305 may transmit a command 325 to the memory system 310 via the CA channel 312. The command 325 may request the memory system 310 to transmit a CRC value 340 (e.g., a CRC value stored to the storage device 345, a calculated CRC value) to the host system 305. The memory system 310 may receive the command 325 and in response may transmit the CRC value 340 to an error detector 365 of the host system 305. For example, in response to receiving the command, the memory system 310 may read the CRC value 340 from the storage device 345 and may transmit the CRC value 340 (e.g., from the storage device 345) to the host system 305. Alternatively, the memory system 310 may transmit the CRC value 340 to the host system 305 in response to detecting a CRC error (e.g., determining that the CRC values ​​340 and 350 are different). For example, the memory system 310 may transmit the CRC value 340 to the host system 305 in response to detecting the CRC error without receiving the command 325. In some examples, the memory system 310 may not store the CRC value 340 to the storage device 345 if the memory system 310 transmits the CRC value 340 in response to detecting the CRC error.

[0051] In some examples, the memory system 310 (e.g., the error detector 355) may transmit the CRC value 340 to the host system 305 via one or more of the data channels 315. In some other examples, the memory system 310 may transmit the CRC value 340 to the host system 305 via the EDC channel 320 and may utilize an interface (e.g., a serial interface). The memory system 310 may transmit the CRC value 340 to the host system 305 at a rate that is slower than the rate at which data is transferred from the host system 305 to the memory system 310, which may reduce the likelihood of errors associated with the transmission of the CRC value 340 to the host system 305. For example, the memory system 310 may transmit the CRC value 340 to the host system 305 at a first rate that is slower than a second rate at which data is received from the host system 305 and / or slower than a third rate at which the host system 305 transmits the CRC value 370.

[0052] The host system 305 may receive the CRC value 340 from the memory system 310 and may determine the type of CRC error indicated by the CRC error flag 360 (e.g., the cause of the CRC error) based on whether the CRC value 340 is different from the CRC value originally transmitted to the memory system 310 (e.g., CRC value 370). For example, an error detector 365 of the host system 305 may receive the CRC value 340 and may compare the CRC value 340 to the CRC value 370 (e.g., the CRC value originally transmitted to the memory system 310). If the error detector 365 determines that the CRC value 340 is not the same as the CRC value 370, the host system 305 (e.g., the error detector 365) may determine that one or more errors may have occurred at least along the data path from the host system 305 to the CRC calculator 335, such as a portion of the transmission of data from the host system 305 to the memory system 310 via the data channel 315, a portion of the storage of the data 330 to the memory array of the memory system 310, a portion of the retrieval of the data 330 from the memory array to the CRC calculator 335, or a combination thereof. For example, if CRC values ​​340 and 370 are different, then the corresponding data used to calculate CRC values ​​340 and 370 are different. Thus, the difference in CRC values ​​340 and 370 may indicate one or more errors associated with a data path, including data channel 315, one or more circuits associated with storing data to a memory array, one or more circuits associated with reading data from a memory array (e.g., column decoder 225, row decoder 220, input / output 255, sense component 245), or a combination thereof.

[0053] If error detector 365 determines that CRC value 340 is not the same as CRC value 370, then another error may have occurred as part of (e.g., during) the transmission of CRC value 370 from host system 305 to memory system 310 via EDC channel 320. In some cases, it may not be clear whether such an error occurred because it may not be known whether CRC values ​​350 and 370 are the same. However, the fact that CRC values ​​340 and 370 are different may indicate that one or more errors occurred at least along the data path.

[0054] In some examples, if the host system 305 determines that the CRC values ​​340 and 370 are different, the host system 305 may determine which bits of the CRC value 340 are different from the bits of the CRC value 370, how many bits of the CRC value 340 are different, or both to determine the location of the error along the data path. For example, the host system 305 may compare each bit of the received CRC value 340 to each bit of the CRC value 370 and may record the number and / or location of the bits of the CRC value 340 that are different from the bits of the CRC value 370. The host system 305 may then use the number and location of the bits to help determine where the error occurred. For example, if the same one or more bits of the CRC value 340 are always incorrect (e.g., different from the corresponding one or more bits of the CRC value 370) when transmitting the same data to the memory system 310 (e.g., multiple transmissions of the same data and subsequent transmissions of the same incorrect CRC value 340) and all other bits of the CRC value 340 are correct, then this pattern of incorrect CRC bits may indicate the first location of the error along the path. Additionally or alternatively, if all bits of CRC value 340 are incorrect but always in the same way, then this pattern of incorrect CRC bits may indicate a second location of the error along the path. Additionally or alternatively, if half of the bits of CRC value 340 are incorrect, then this pattern of incorrect CRC bits may indicate a third location along the path (e.g., corresponding to specific circuitry for storing and / or retrieving bits used to generate the half of the incorrect bits).

[0055] Alternatively, the host system 305 may receive the CRC value 340 from the memory system 310 and may determine that the CRC value 340 is the same as the CRC value originally transmitted to the memory system 310 (e.g., CRC value 370). For example, the error detector 365 of the host system 305 may receive the CRC value 340 and may compare the CRC value 340 to the CRC value 370 (e.g., the CRC value originally transmitted to the memory system 310). If the error detector 365 may determine that the CRC value 340 is the same as the CRC value 370, the host system 305 (e.g., the error detector 365) may determine that an error may have occurred as part of (e.g., during) the transmission of the CRC value 370 from the host system 305 to the memory system 310 via the EDC channel 320 and determine that the error may not have occurred along the path of the data 330. For example, if the CRC values ​​340 and 370 are the same, then the corresponding data used to calculate the CRC values ​​340 and 370 are the same. Therefore, there is no error that occurred along the path of the data from the host system 305 to the CRC calculator 335. Conversely, host system 305 may determine that an error is associated with the transmission of CRC value 370 , such that CRC value 350 received by memory system 310 is different from CRC value 370 .

[0056] Figure 4 An example of a system 400 supporting CRC comparison for error detection according to examples disclosed herein is shown. The system 400 may be provided by reference to Figures 1 to 3 The described system 100, architecture 200, system 300, or one or more components thereof (e.g., host system 105, memory system 110, local memory controller 260, memory system 310, and host system 305) may support relatively finer-grained determination of CRC error causes associated with reading data from a memory system.

[0057] In some examples, system 400 can include a memory system 410, which can be any of the memory systems described herein (including reference Figure 1 and 3 ) is an example of a memory system described in the foregoing. The memory system 410 can include a CRC calculator 420. The memory system 410 can input data 415 into the CRC calculator 420, and the CRC calculator 420 can generate (e.g., calculate) a calculated CRC value 425 associated with (e.g., based on, using) the data 415. In some examples, the system 400 can include a host system 405, which can be a computer system described herein (including references to Figures 1 to 3) is an example of a host system described in the foregoing description. Host system 405 may include a CRC calculator 440. Host system 405 may input data received from memory system 410 into CRC calculator 440, and CRC calculator 440 may generate (e.g., calculate) a calculated CRC value 445 associated with (e.g., based on, using) data 415. Host system 405 may also include an error detector 435. Error detector 435 may compare various CRC values ​​(e.g., CRC value 425, CRC value 445, expected CRC value 430) to detect one or more errors and determine the cause of one or more errors (e.g., the location where one or more errors may have occurred). In addition, although the non-limiting examples of system 400 herein are generally described in terms of application to a memory system, a memory subsystem, a memory device, or a combination thereof, examples of system 400 are not limited thereto. For example, aspects of the present disclosure may be equally applicable to any computing system, computing subsystem, processing system, processing subsystem, component, device, structure, or other type of system or subsystem used for applications such as data collection, data processing, data storage, networking, communications, power, artificial intelligence, single-chip system, control, telemetry, sensing and monitoring, digital entertainment, or any combination thereof.

[0058] According to the examples described herein, the host system 405 may receive the CRC value 425 and may generate the CRC value 445 and the CRC value 430 for determining where an error may have occurred as part of a read operation (e.g., during a read operation). For example, the host system 405 may transmit a read command requesting data 415 to the memory system 410. The memory system 410 may receive the read command and may retrieve the data 415 associated with the read command from the memory array of the memory system 410. The memory system 410 may input the data 415 into the CRC calculator 420, and the CRC calculator 420 may generate the CRC value 425. The memory system 410 may transmit the CRC value 425 (e.g., via an EDC channel) and the data 415 to the host system 405 (e.g., via one or more data channels). The host system 405 may receive the data 415 and the CRC value 425. The host system 405 may calculate the CRC value 445 based on (e.g., using) the received data 415. The host system 405 can generate (eg, calculate) a CRC value 430 based on the data that the host system 405 expects to receive in response to the transport read command. Thus, the CRC value 430 can be referred to as an expected CRC value 430.

[0059] The host system 405 may compare the CRC values ​​associated with the data 415 to determine whether an error associated with reading the data has occurred and where a detected error may have occurred as part of the data read. For example, the host system 405 may input the CRC value 425, the CRC value 430, and the CRC value 445 into the error detector 435 to determine whether an error may exist and to determine the type of error (e.g., to determine where an error may have occurred). If the CRC values ​​425, 430, and 445 are the same, the host system 405 may determine that no error has occurred.

[0060] If the error detector 435 can determine, based on comparing the CRC values, that the CRC value 430 may not be the same as the CRC value 425 and the CRC value 445, while the CRC value 425 and the CRC value 445 may be the same, the host system 405 (e.g., the error detector 435) can determine that an error may have occurred on the path of the data 415 before the data 415 is input to the CRC calculator 420 (e.g., during the retrieval of the data 415 from the memory array of the memory system 410). For example, the CRC values ​​425 and 445 being the same may indicate that no errors occurred as part of the transmission of the CRC values ​​425 and 445 via the EDC channel and the data channel, respectively. However, because the CRC values ​​425 and 445 are not the same as the expected CRC value 430, the host system 405 can determine that an error has occurred before the CRC value 425 is calculated using the CRC calculator 420, such as part of the retrieval of the data 415 from the memory array (e.g., at one or more locations along the path of the data 415 from the memory array to the CRC calculator 420). This error may cause data 415 to be incorrect, thereby resulting in incorrect CRC values ​​425 and 445 calculated using data 415.

[0061] If error detector 435 may determine (e.g., based on comparing CRC values) that CRC value 430 may be the same as CRC value 425 while CRC value 445 may not be the same as CRC value 425 and CRC value 430, host system 405 may determine that an error may have occurred as part of (e.g., during) the transmission of data 415 to host system 405. For example, CRC values ​​425 and 430 being the same may indicate that no error occurred as part of retrieving data 415 from the memory array, calculating CRC value 425 using data 415, and transmitting CRC value 425 via the EDC channel. However, because CRC value 445 is not the same as CRC values ​​425 and 430, host system 405 may determine that an error has occurred as part of the transmission of data 415 via one or more data channels. For example, such an error may result in incorrect data being input into CRC calculator 440 at host system 405, thereby causing CRC value 445 to be incorrect.

[0062] If error detector 435 may determine (e.g., based on comparing CRC values) that CRC value 430 may be the same as CRC value 445 while CRC value 425 may not be the same as CRC value 430 and CRC value 445, host system 405 may determine that an error may have occurred during the transmission of CRC value 425 from memory system 410 to host system 405 (e.g., via an EDC channel). For example, CRC values ​​430 and 445 being the same may indicate that no errors occurred as part of the retrieval of data 415 from the memory array and the transmission of data 415 via one or more data channels because data 415 received at host system 405 and used to calculate CRC value 445 resulted in a correct CRC value (e.g., a CRC value that matches expected CRC value 430). However, because CRC value 425 is not the same as CRC values ​​430 and 445, host system 405 may determine that an error has occurred as part of the transmission of CRC value 425 via the EDC channel, causing CRC value 425 to be incorrect.

[0063] If error detector 435 can determine (e.g., based on comparing CRC values) that CRC value 430, CRC value 425, and CRC value 445 are each different from one another (e.g., may not be the same), then host system 405 can determine that two or more errors (e.g., at least two errors) may have occurred as part of reading the data, such as: as part of the transmission of CRC value 425 from memory system 410 to host system 405; on the path of data 415 before data 415 is input to CRC calculator 420 (e.g., during retrieval of data 415 from a memory array of memory system 410 to CRC calculator 420); as part of the transmission of data 415 to host system 405; or a combination thereof.

[0064] By determining the root cause of an error, the host system 405 may be enabled to take more efficient and corrective actions to reduce (eg, avoid) the likelihood of future errors.

[0065] Figure 5 A block diagram 500 is shown of a host system 520 that supports CRC comparison for error detection according to examples disclosed herein. The host system 520 may be a reference Figures 1 to 4 5. The host system 520 or its various components may be examples of means for performing various aspects of CRC comparisons for error detection, as described herein. For example, the host system 520 may include a transmission component 525, an error indication component 530, a receiver component 535, a calculation component 540, an error detection component 545, a command component 550, a storage component 555, or any combination thereof. Components of each of these components or subcomponents thereof (e.g., one or more processors, one or more memories) may communicate directly or indirectly with each other (e.g., via one or more buses).

[0066] The transmission component 525 may be configured or otherwise support means for transmitting data via a set of data channels and transmitting a first indication of a first CRC value corresponding to the data via an error detection channel. The error indication component 530 may be configured or otherwise support means for receiving a second indication of an error associated with the first CRC value. The receiver component 535 may be configured or otherwise support means for receiving a third indication of a second CRC value corresponding to the data based at least in part on receiving the second indication of the error.

[0067] In some examples, error detection component 545 can be configured or otherwise support means for determining an error type based at least in part on a comparison of the first CRC value and the second CRC value.

[0068] In some examples, to support determining an error type, the error detection component 545 may be configured to or otherwise support components for determining that an error is associated with at least a data path based at least in part on a first CRC value being different from a second CRC value, the data path comprising a data channel group, one or more circuits associated with storing data to a memory cell of a memory array, one or more circuits associated with reading data from a memory cell, or a combination thereof.

[0069] In some examples, to support determining an error type, error detection component 545 may be configured or otherwise support means for determining a location of an error along a data path based at least in part on determining which bits of the first CRC value differ from corresponding bits of the second CRC value.

[0070] In some examples, to support determining an error type, error detection component 545 may be configured or otherwise support means for determining that an error is associated with communicating a first indication of a first CRC value via an error detection channel based at least in part on the first CRC value being the same as a second CRC value.

[0071] In some examples, command component 550 can be configured or otherwise support means for transmitting a command to transmit a third indication of a second CRC value based at least in part on receiving a second indication of an error, wherein the third indication is received based at least in part on the command.

[0072] In some examples, to support receiving a third indication of a second CRC value, the receiver component 535 may be configured to or otherwise support means for receiving a third indication of the second CRC value via an error detection channel, wherein the third indication of the second CRC value is received at a first rate that is slower than a second rate at which the first indication of the first CRC value is transmitted.

[0073] In some examples, to support receiving a third indication of a second CRC value, the receiver component 535 may be configured to or otherwise support means for receiving a third indication of a second CRC value via a data channel group, wherein the third indication of the second CRC value is received at a first rate that is slower than a second rate at which the first indication of the first CRC value is transmitted.

[0074] Additionally or alternatively, command component 550 may be configured to or otherwise support means for transmitting to a memory system a command to read data from the memory system. In some examples, receiver component 535 may be configured to or otherwise support means for receiving data via a set of data channels and receiving a first indication of a first CRC value associated with the data via an error detection channel. Calculation component 540 may be configured to or otherwise support means for calculating a second CRC value based at least in part on the data. Error detection component 545 may be configured to or otherwise support means for determining an error type associated with the data based at least in part on a comparison of a first CRC value associated with the data, a second CRC value, and an expected CRC value.

[0075] In some examples, to support determining an error type, the error detection component 545 may be configured to or otherwise support components for determining that an error is associated with data prior to calculating a first CRC value using the data at the memory system based at least in part on the first CRC value being the same as the second CRC value and the expected CRC value being different from the first CRC value and the second CRC value.

[0076] In some examples, to support determining an error type, the error detection component 545 may be configured or otherwise support means for determining that an error is associated with communicating data via the data channel group based at least in part on the first CRC value being the same as the expected CRC value and the second CRC value being different from the first CRC value and the expected CRC value.

[0077] In some examples, to support determining an error type, the error detection component 545 may be configured as or otherwise support means for determining that an error is associated with a first indication of a first CRC value communicated via an error detection channel based at least in part on the second CRC value being the same as an expected CRC value and the first CRC value being different from the second CRC value and the expected CRC value.

[0078] In some examples, to support determining an error type, the error detection component 545 may be configured to or otherwise support means for determining at least two errors based at least in part on each of the first CRC value, the second CRC value, and the expected CRC value being different, each of the at least two errors being associated with data prior to calculation of the first CRC value at the memory system, associated with data communicated via a data channel group, or associated with a first indication of a first CRC value communicated via an error detection channel.

[0079] In some examples, storage component 555 may be configured as or otherwise support means for storing a table of a set of error types, wherein determining the error type comprises reading an entry of the table corresponding to the error type based on one or more differences between a first CRC value, a second CRC value, an expected CRC value, or a combination thereof.

[0080] In some examples, calculation component 540 can be configured or otherwise support means for calculating an expected CRC value based at least in part on expected data associated with a command.

[0081] In some examples, the described functionality of the host system 520 or its various components may be supported by or may refer to at least a portion of at least one processor, where such at least one processor may include one or more processing elements (e.g., a controller, a microprocessor, a microcontroller, a digital signal processor, a state machine, discrete gate logic, discrete transistor logic, discrete hardware components, or any combination of one or more of such elements). In some examples, the described functionality of the host system 520 or its various components may be implemented at least in part by instructions (e.g., stored in a memory, a non-transitory computer-readable medium) that are executable by such at least one processor.

[0082] Figure 6 A block diagram 600 is shown of a memory system 620 supporting CRC comparison for error detection according to examples disclosed herein. The memory system 620 may be a reference Figures 1 to 4 6. Memory system 620 or its various components may be examples of means for performing various aspects of CRC comparisons for error detection, as described herein. For example, memory system 620 may include receiver component 625, computation component 630, error indication component 635, transmission component 640, command receiver component 645, storage component 650, or any combination thereof. Components of each of these components or subcomponents thereof (e.g., one or more processors, one or more memories) may communicate directly or indirectly with each other (e.g., via one or more buses).

[0083] Receiver component 625 may be configured to or otherwise support means for receiving data via a set of data channels and receiving a first indication of a first CRC value corresponding to the data via an error detection channel. Calculation component 630 may be configured to or otherwise support means for calculating a second CRC value based at least in part on the data. Error indication component 635 may be configured to or otherwise support means for transmitting a second indication of an error based at least in part on the first CRC value being different from the second CRC value. Transmission component 640 may be configured to or otherwise support means for transmitting a third indication of a second CRC value based at least in part on the second indication of an error.

[0084] In some examples, command receiver component 645 can be configured or otherwise support means for receiving a command to transmit a third indication of a second CRC value at least partially based on a second indication of an error, wherein the third indication is transmitted based at least in part on the command.

[0085] In some examples, to support transmitting a third indication of a second CRC value, the transmission component 640 may be configured to or otherwise support means for transmitting a third indication of the second CRC value via an error detection channel, wherein the third indication of the second CRC value is transmitted at a first rate that is slower than a second rate at which the first indication of the first CRC value is received.

[0086] In some examples, to support transmitting a third indication of a second CRC value, the transmission component 640 may be configured to or otherwise support means for transmitting a third indication of a second CRC value via a data channel group, wherein the third indication of the second CRC value is transmitted at a first rate that is slower than a second rate at which the first indication of the first CRC value is received.

[0087] In some examples, storage component 650 may be configured or otherwise support means for storing the second CRC value based at least in part on the first CRC value being different from the second CRC value, wherein the third indication of the second CRC value is transmitted based at least in part on the storing.

[0088] In some examples, receiver component 625 may be configured to or otherwise support means for receiving second data via the data channel group and receiving a fourth indication of a third CRC value corresponding to the second data via the error detection channel. In some examples, calculation component 630 may be configured to or otherwise support means for calculating a fourth CRC value based at least in part on the second data. In some examples, storage component 650 may be configured to or otherwise support means for not storing the fourth CRC value based at least in part on the third CRC value being the same as the fourth CRC value.

[0089] In some examples, the described functionality of the memory system 620 or its various components may be supported by or may refer to at least a portion of at least one processor, where such at least one processor may include one or more processing elements (e.g., a controller, a microprocessor, a microcontroller, a digital signal processor, a state machine, discrete gate logic, discrete transistor logic, discrete hardware components, or any combination of one or more of such elements). In some examples, the described functionality of the memory system 620 or its various components may be implemented at least in part by instructions (e.g., stored in a memory, a non-transitory computer-readable medium) that are executable by such at least one processor.

[0090] Figure 7 A flowchart illustrating a method 700 for supporting CRC comparison for error detection according to examples disclosed herein is shown. The operations of the method 700 may be implemented by a host system or components thereof as described herein. For example, the operations of the method 700 may be implemented by reference to Figures 1 to 5 The host system described herein performs. In some examples, the host system may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the host system may use dedicated hardware to perform aspects of the described functions.

[0091] At 705, the method may include transmitting data via a set of data channels and transmitting a first indication of a first CRC value corresponding to the data via an error detection channel. In some examples, aspects of operation 705 may be referred to as Figure 5 The described transport component 525 executes.

[0092] At 710, the method may include receiving a second indication of an error associated with the first CRC value. In some examples, aspects of operation 710 may be referred to as Figure 5 The described error indication component 530 executes.

[0093] At 715, the method may include receiving a third indication of a second CRC value corresponding to the data based at least in part on receiving the second indication of an error. In some examples, aspects of operation 715 may be referred to as Figure 5 The receiver component 535 described executes.

[0094] In some examples, the apparatus described herein may perform one or several methods, such as method 700. The apparatus may include features, circuitry, logic, means, or instructions (such as a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure, or any combination thereof:

[0095] Aspect 1: A method, apparatus, or non-transitory computer-readable medium comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: transmitting data via a set of data channels and transmitting a first indication of a first CRC value corresponding to the data via an error detection channel; receiving a second indication of an error associated with the first CRC value; and receiving a third indication of a second CRC value corresponding to the data based at least in part on receiving the second indication of the error.

[0096] Aspect 2: The method, apparatus, or non-transitory computer-readable medium of Aspect 1, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for determining the type of the error based at least in part on a comparison of the first CRC value with the second CRC value.

[0097] Aspect 3: A method, apparatus, or non-transitory computer-readable medium according to Aspect 2, wherein determining the error type includes operations, features, circuit systems, logic, components, or instructions for the following, or any combination thereof: determining that the error is associated with at least a path of the data based at least in part on the first CRC value being different from the second CRC value, the path including the set of data channels, one or more circuits associated with storing the data in a memory cell of the memory array, one or more circuits associated with reading the data from the memory cell, or a combination thereof.

[0098] Aspect 4: A method, apparatus, or non-transitory computer-readable medium according to Aspect 3, wherein determining the error type includes operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for determining the location of the error along the path of the data based at least in part on determining which bits of the first CRC value differ from corresponding bits of the second CRC value.

[0099] Aspect 5: A method, apparatus, or non-transitory computer-readable medium according to Aspect 2, wherein determining the error type includes operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for determining that the error is associated with the first indication of the first CRC value communicated via the error detection channel based at least in part on the first CRC value being the same as the second CRC value.

[0100] Aspect 6: The method, apparatus, or non-transitory computer-readable medium of any one of Aspects 1 to 5, further comprising the following operations, features, circuit systems, logic, components, or instructions, or any combination thereof: at least partially receiving the second indication of the error and transmitting a command for transmitting the third indication of the second CRC value, wherein the third indication is received at least partially based on the command.

[0101] Aspect 7: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 6, wherein receiving the third indication of the second CRC value includes operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: receiving the third indication of the second CRC value via the error detection channel, wherein the third indication of the second CRC value is received at a first rate that is slower than a second rate at which the first indication of the first CRC value is transmitted.

[0102] Aspect 8: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 6, wherein receiving the third indication of the second CRC value includes operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: receiving the third indication of the second CRC value via the set of data channels, wherein the third indication of the second CRC value is received at a first rate that is slower than a second rate at which the first indication of the first CRC value is transmitted.

[0103] Figure 8 A flowchart illustrating a method 800 for supporting CRC comparison for error detection according to examples disclosed herein is shown. The operations of the method 800 may be implemented by the memory system or components thereof described herein. For example, the operations of the method 800 may be implemented by reference to Figures 1 to 4 In some examples, the memory system may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the memory system may use dedicated hardware to perform aspects of the described functions.

[0104] At 805, the method may include receiving data via a set of data channels and receiving a first indication of a first CRC value corresponding to the data via an error detection channel. In some examples, aspects of operation 805 may be referred to as Figure 6 The receiver component 625 described performs.

[0105] At 810, the method may include calculating a second CRC value based at least in part on the data. In some examples, aspects of operation 810 may be referred to as Figure 6 The computing component 630 described performs.

[0106] At 815, the method may include transmitting a second indication of an error based at least in part on the first CRC value being different from the second CRC value. In some examples, aspects of operation 815 may be referred to as Figure 6 The described error indication component 635 executes.

[0107] At 820, the method may include transmitting a third indication of the second CRC value based at least in part on the second indication of the transmission error. In some examples, aspects of operation 820 may be referred to as Figure 6 The described transport component 640 performs.

[0108] In some examples, the apparatus described herein may perform one or several methods, such as method 800. The apparatus may include features, circuitry, logic, means, or instructions (such as a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure, or any combination thereof:

[0109] Aspect 9: A method, apparatus, or non-transitory computer-readable medium comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: receiving data via a set of data channels and receiving a first indication of a first CRC value corresponding to the data via an error detection channel; calculating a second CRC value based at least in part on the data; transmitting a second indication of an error based at least in part on the first CRC value being different from the second CRC value; and transmitting a third indication of the second CRC value based at least in part on transmitting the second indication of the error.

[0110] Aspect 10: The method, apparatus, or non-transitory computer-readable medium of Aspect 9, further comprising the following operations, features, circuit systems, logic, components, or instructions, or any combination thereof: at least partially transmitting the second indication of the error and receiving a command to transmit the third indication of the second CRC value, wherein the third indication is transmitted at least partially based on the command.

[0111] Aspect 11: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 9 to 10, wherein the third indication of transmitting the second CRC value includes operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: transmitting the third indication of the second CRC value via the error detection channel, wherein the third indication of the second CRC value is transmitted at a first rate that is slower than a second rate at which the first indication of the first CRC value is received.

[0112] Aspect 12: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 9 to 10, wherein transmitting the third indication of the second CRC value includes operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: transmitting the third indication of the second CRC value via the set of data channels, wherein the third indication of the second CRC value is transmitted at a first rate that is slower than a second rate at which the first indication of the first CRC value is received.

[0113] Aspect 13: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 9 to 12, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for storing the second CRC value based at least in part on the first CRC value being different from the second CRC value, wherein the third indication of the second CRC value is transmitted based at least in part on the storage.

[0114] Aspect 14: The method, apparatus, or non-transitory computer-readable medium of any one of Aspects 9 to 13, further comprising the following operations, features, circuit systems, logic, components, or instructions, or any combination thereof: receiving second data via the set of data channels and receiving a fourth indication of a third CRC value corresponding to the second data via the error detection channel; calculating a fourth CRC value based at least in part on the second data; and not storing the fourth CRC value based at least in part on the third CRC value being the same as the fourth CRC value.

[0115] Fig. 9 A flowchart illustrating a method 900 for supporting CRC comparison for error detection according to examples disclosed herein is shown. The operations of the method 900 may be implemented by a host system or components thereof as described herein. For example, the operations of the method 900 may be implemented by reference to Figures 1 to 5 The host system described herein performs. In some examples, the host system may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the host system may use dedicated hardware to perform aspects of the described functions.

[0116] At 905, the method may include transmitting a command to the memory system to read data from the memory system. In some examples, aspects of operation 905 may be referred to as Figure 5 The described transport component 525 executes.

[0117] At 910, the method may include receiving data via a set of data channels and receiving a first indication of a first CRC value associated with the data via an error detection channel. In some examples, aspects of operation 910 may be referred to as Figure 5 The receiver component 535 described executes.

[0118] At 915, the method may include calculating a second CRC value based at least in part on the data. In some examples, aspects of operation 915 may be referred to as Figure 5 The computing component 540 described performs.

[0119] At 920, the method may include determining an error type associated with the data based at least in part on a comparison of a first CRC value associated with the data, a second CRC value, and an expected CRC value. In some examples, aspects of operation 920 may be described with reference to Figure 5 The error detection component 545 described above performs the above.

[0120] In some examples, the apparatus described herein may perform one or several methods, such as method 900. The apparatus may include features, circuitry, logic, means, or instructions (such as a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure, or any combination thereof:

[0121] Aspect 15: A method, apparatus, or non-transitory computer-readable medium comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: transmitting a command to a memory system to read data from the memory system; receiving the data via a set of data channels and receiving a first indication of a first CRC value associated with the data via an error detection channel; calculating a second CRC value based at least in part on the data; and determining an error type associated with the data based at least in part on a comparison of the first CRC value associated with the data, the second CRC value, and an expected CRC value.

[0122] Aspect 16: A method, apparatus, or non-transitory computer-readable medium according to Aspect 15, wherein determining the error type includes operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for determining that an error is associated with the data before the first CRC value is calculated using the data at the memory system based at least in part on the first CRC value being the same as the second CRC value and the expected CRC value being different from the first CRC value and the second CRC value.

[0123] Aspect 17: A method, apparatus, or non-transitory computer-readable medium according to Aspect 15, wherein determining the error type includes operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for determining that an error is associated with communicating the data via the set of data channels based at least in part on the first CRC value being the same as the expected CRC value and the second CRC value being different from the first CRC value and the expected CRC value.

[0124] Aspect 18: A method, apparatus, or non-transitory computer-readable medium according to Aspect 15, wherein determining the error type includes operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for determining that an error is associated with the first indication of the first CRC value communicated via the error detection channel based at least in part on the second CRC value being the same as the expected CRC value and the first CRC value being different from the second CRC value and the expected CRC value.

[0125] Aspect 19: A method, apparatus, or non-transitory computer-readable medium according to Aspect 15, wherein determining the error type includes operations, features, circuit systems, logic, components, or instructions for the following, or any combination thereof: determining at least two errors based at least in part on the first CRC value, the second CRC value, and each of the expected CRC values ​​being different, each of the at least two errors being associated with the data before the first CRC value is calculated at the memory system, associated with communicating the data via the set of data channels, or associated with communicating the first indication of the first CRC value via the error detection channel.

[0126] Aspect 20: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 15 to 19, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for storing a table of a set of error types, wherein determining the error type comprises reading an entry of the table corresponding to the error type based on one or more differences between the first CRC value, the second CRC value, the expected CRC value, or a combination thereof.

[0127] Aspect 21: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 15 to 20, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for calculating the expected CRC value based at least in part on expected data associated with the command.

[0128] It should be noted that the aspects described herein describe possible implementations, and that operations and steps may be rearranged or otherwise modified and other implementations are possible. Furthermore, portions from two or more of the methods may be combined.

[0129] The information and signals described herein may be represented using any of a variety of different techniques and technologies. For example, data, instructions, commands, information, signals, bits, or signaling symbols that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some figures may illustrate a signal as a single signal; however, a signal may represent a signal bus, where the bus may have various bit widths.

[0130] The term "coupled" (e.g., "electrically coupled") may refer to a condition that transitions from an open-circuit relationship between components, where signals cannot currently be communicated between the components (e.g., via conductive paths), to a closed-circuit relationship between the components, where signals can be communicated between the components (e.g., via conductive paths). When a component, such as a controller, couples other components together, the component may induce a change that allows signals to flow between the other components via conductive paths that previously did not allow signals to flow.

[0131] The switch components (e.g., transistors) discussed herein may be field effect transistors (FETs) and may include a source (e.g., a source terminal), a drain (e.g., a drain terminal), a channel between the source and the drain, and a gate (e.g., a gate terminal). The conductivity of the channel may be controlled (e.g., modulated) by applying a voltage to the gate, which may, in some examples, cause the channel to become conductive. The switch component may be an example of an n-type FET or a p-type FET.

[0132] The description set forth herein describes example configurations in conjunction with the accompanying drawings and does not represent all examples that may be implemented or within the scope of the claims. The "Detailed Description" includes specific details for providing an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0133] In the accompanying drawings, similar components or features may have the same reference label. Similar components may be distinguished by following the reference label with one or more dashes and an additional label that distinguishes the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components with the same first reference label, regardless of the additional reference labels.

[0134] The functions described herein may be implemented in hardware, software executed by a processing system (e.g., one or more processors, one or more controllers, control circuitry, processing circuitry, logic circuitry), firmware, or any combination thereof. If implemented in software executed by a processing system, the functions may be stored on or transmitted over a computer-readable medium as one or more instructions (e.g., code). Due to the nature of software, the functions described herein may be implemented using software executed by a processing system, hardware, firmware, hardwiring, or a combination of any of these. Features implementing the functions may be physically located at various locations, including distributed such that portions of the functions are implemented at different physical locations.

[0135] The illustrative blocks and modules described herein may be implemented or executed with one or more processors (e.g., DSPs, ASICs, FPGAs, discrete gate logic, discrete transistor logic, discrete hardware components, other programmable logic devices, or any combination thereof) designed to perform the functions described herein. A processor may be an example of a microprocessor, a controller, a microcontroller, a state machine, or other type of processor. A processor may also be implemented as at least one of one or more computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0136] As used herein (including in the claims), "or" used in a list of items (e.g., a list of items preceded by a phrase such as "at least one of" or "one or more of") indicates an inclusive list, so that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Moreover, as used herein, the phrase "based on" should not be interpreted as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0137] As used herein (including in the claims), the article "a" before a noun is open-ended and should be understood to refer to "at least one" of those nouns or "one or more" of those nouns. Therefore, the terms "one", "at least one", "one or more", and "at least one of one or more" are interchangeable. For example, if a claim recites "a component" that performs one or more functions, each of the individual functions may be performed by a single component or any combination of multiple components. Therefore, the term "a component" having a characteristic or performing a function may refer to "at least one of one or more components" having a specific characteristic or performing a specific function. The subsequent use of the term "the / said" to refer to the component introduced with the article "a" may refer to any or all of the one or more components. For example, a component introduced with the article "a" may be understood to mean "one or more components", and the subsequent reference to "the component" in the claim may be understood to be equivalent to referring to "at least one of one or more components". Similarly, a component introduced as "one or more components" subsequently referenced using the term "the / said" may refer to any or all of the one or more components. For example, a subsequent reference to "one or more components" in a claim may be understood to be equivalent to referring to "at least one of the one or more components."

[0138] Computer-readable media include both non-transitory computer storage media and communication media, including any media that facilitates the transfer of a computer program from one location to another. Non-transitory storage media may be any available media or a combination of multiple media that can be accessed by a computer. For example, but not limited to, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disk storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media or combination of media that can be used to carry or store desired program code components in the form of instructions or data structures and can be accessed by a computer or processor.

[0139] The description and drawings are provided to enable one of ordinary skill in the art to make or use the present disclosure. One of ordinary skill in the art will appreciate the various modifications of the present disclosure, and the techniques disclosed herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but should be given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method comprising: transmitting data via a set of data channels and transmitting a first indication of a first cyclic redundancy check (CRC) value corresponding to the data via an error detection channel; receiving a second indication of an error associated with the first CRC value; and A third indication of a second CRC value corresponding to the data is received based at least in part on receiving the second indication of the error.

2. The method according to claim 1, further comprising: The type of error is determined based at least in part on a comparison of the first CRC value and the second CRC value.

3. The method of claim 2, wherein determining the error type comprises: The error is determined to be associated with at least a path of the data based at least in part on the first CRC value being different from the second CRC value, the path comprising the set of data channels, one or more circuits associated with storing the data to a memory cell of a memory array, one or more circuits associated with reading the data from the memory cell, or a combination thereof.

4. The method of claim 3, wherein determining the error type comprises: A location of the error along the path of the data is determined based at least in part on determining which bits of the first CRC value differ from corresponding bits of the second CRC value.

5. The method of claim 2, wherein determining the error type comprises: The error is determined to be associated with communicating the first indication of the first CRC value via the error detection channel based at least in part on the first CRC value being the same as the second CRC value.

6. The method according to claim 1, further comprising: A command to transmit the third indication of the second CRC value is transmitted based at least in part on receiving the second indication of the error, wherein the third indication is received based at least in part on the command.

7. The method of claim 1 , wherein receiving the third indication of the second CRC value comprises: The third indication of the second CRC value is received via the error detection channel, wherein the third indication of the second CRC value is received at a first rate that is slower than a second rate at which the first indication of the first CRC value is transmitted.

8. The method of claim 1 , wherein receiving the third indication of the second CRC value comprises: The third indication of the second CRC value is received via the set of data lanes, wherein the third indication of the second CRC value is received at a first rate that is slower than a second rate at which the first indication of the first CRC value is transmitted.

9. A method comprising: receiving data via a set of data channels and receiving a first indication of a first cyclic redundancy check (CRC) value corresponding to the data via an error detection channel; calculating a second CRC value based at least in part on the data; transmitting a second indication of an error based at least in part on the first CRC value being different from the second CRC value; and A third indication of the second CRC value is transmitted based at least in part on transmitting the second indication of the error.

10. The method according to claim 9, further comprising: A command to transmit the third indication of the second CRC value is received based at least in part on transmitting the second indication of the error, wherein the third indication is transmitted based at least in part on the command.

11. The method of claim 10, wherein transmitting the third indication of the second CRC value comprises: The third indication of the second CRC value is transmitted via the error detection channel, wherein the third indication of the second CRC value is transmitted at a first rate that is slower than a second rate at which the first indication of the first CRC value is received.

12. The method of claim 10, wherein transmitting the third indication of the second CRC value comprises: The third indication of the second CRC value is transmitted via the set of data channels, wherein the third indication of the second CRC value is transmitted at a first rate that is slower than a second rate at which the first indication of the first CRC value is received.

13. The method according to claim 9, further comprising: Based at least in part on the first CRC value being different from the second CRC value, the second CRC value is stored, wherein the third indication of the second CRC value is transmitted based at least in part on the storing.

14. The method according to claim 9, further comprising: receiving second data via the set of data channels and receiving a fourth indication of a third CRC value corresponding to the second data via the error detection channel; calculating a fourth CRC value based at least in part on the second data; and Not storing the fourth CRC value based at least in part on the third CRC value being the same as the fourth CRC value.

15. A method comprising: transmitting to the memory system a command to read data from the memory system; receiving the data via a set of data channels and receiving a first indication of a first cyclic redundancy check (CRC) value associated with the data via an error detection channel; calculating a second CRC value based at least in part on the data; and An error type associated with the data is determined based at least in part on a comparison of the first CRC value, the second CRC value, and an expected CRC value associated with the data.

16. The method of claim 15, wherein determining the error type comprises: An error is determined to be associated with the data prior to calculating the first CRC value using the data at the memory system based at least in part on the first CRC value being the same as the second CRC value and the expected CRC value being different from the first CRC value and the second CRC value.

17. The method of claim 15, wherein determining the error type comprises: An error is determined to be associated with communicating the data via the set of data channels based at least in part on the first CRC value being the same as the expected CRC value and the second CRC value being different from the first CRC value and the expected CRC value.

18. The method of claim 15, wherein determining the error type comprises: An error is associated with communicating the first indication of the first CRC value via the error detection channel based at least in part on the second CRC value being the same as the expected CRC value and the first CRC value being different from the second CRC value and the expected CRC value.

19. The method of claim 15, wherein determining the error type comprises: At least two errors are determined based at least in part on each of the first CRC value, the second CRC value, and the expected CRC value being different, each of the at least two errors being associated with the data before the first CRC value is calculated at the memory system, associated with communicating the data via the set of data channels, or associated with communicating the first indication of the first CRC value via the error detection channel.

20. The method of claim 15, further comprising: A table is stored that stores a set of error types, wherein determining the error type comprises reading an entry of the table that corresponds to the error type based on one or more differences between the first CRC value, the second CRC value, the expected CRC value, or a combination thereof.

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