A random hardware fault location method, system and storage medium

Abstract

The present invention provides a random hardware fault location method, system and storage medium, which screen out vulnerable units from the circuit modules of a chip; perform fault detection operations on each of the vulnerable units based on a pre-established test simulation platform to obtain fault detection results, and establish a compressed sensing equation based on the fault detection results; solve the compressed sensing equation, and locate the vulnerable units where random hardware faults occur according to the solution results. Since the present application first screens out vulnerable units from a microscopic perspective, then performs fault detection on each vulnerable unit, establishes and solves the compressed sensing equation, and then locates the vulnerable units where random hardware faults occur, the method of the present invention can reveal security vulnerabilities existing in automotive-grade chips with a small number of observations, obtain accurate evaluation results of chip functions, and improve the accuracy and efficiency of chip detection.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit testing technology, and in particular to a random hardware fault locating method, system, and storage medium for automotive-grade chips. Background Art

[0002] Currently used chips can be categorized by industry into military-grade, automotive-grade, industrial-grade, and consumer-grade chips. Automotive-grade chips are used for automotive control. As vehicles become increasingly intelligent, the functional safety of automotive-grade chips is a key issue in automotive development.

[0003] As automotive-grade chips shift from single-function, large-size to multi-function, highly integrated, small-size, the failure rate of hardware has also increased. However, the current testing of chip functional safety is still at the macro level, and there is a lack of testing methods proposed from the micro perspective of functional safety, so the goal of accurate assessment cannot be achieved.

[0004] Therefore, the prior art needs to be further improved. Summary of the Invention

[0005] In view of the above-mentioned deficiencies in the prior art, the present invention provides a method, system and storage medium for locating random hardware faults for automotive-grade chips, aiming to overcome the defect in the prior art that the functional safety of automotive-grade chips cannot be accurately tested.

[0006] The technical solutions adopted by the present invention to solve the technical problems are as follows:

[0007] In the first aspect, this application proposes a random hardware fault location method for automotive-grade chips, which includes:

[0008] Analyze the circuit structure of the automotive-grade chip to be tested and extract the circuit modules associated with the preset safety goals;

[0009] screening out fragile units from the circuit module;

[0010] In a random hardware fault detection platform, fault detection operations are performed on the automotive-grade chip to be tested, and the fault detection results of each vulnerable unit are obtained. Based on the fault detection results, a compressed sensing equation is established;

[0011] The compressed sensing equation is solved, and the vulnerable unit where the random hardware failure occurs is located according to the solution result.

[0012] Optionally, the step of analyzing the circuit structure of the automotive-grade chip to be tested and extracting circuit modules associated with preset safety targets includes:

[0013] Determine the safety objectives of the automotive-grade chip to be tested based on the chip type and chip function;

[0014] Determining, based on the safety goal, a calculation logic for an output signal in the automotive-grade chip to be tested;

[0015] According to the calculation logic of the output signal in the target detection automotive-grade chip, circuit information associated with the safety target is extracted from the circuit of the automotive-grade chip to be tested.

[0016] Optionally, the step of screening out fragile units from the circuit module includes:

[0017] Obtaining event symbols, logic gate symbols, and transfer symbols corresponding to the causal relationships between various events in the circuit module;

[0018] Determining a progressive relationship between logic events based on the event symbols, logic gate symbols, and transfer symbols;

[0019] Establish a fault tree model based on the progressive relationship between logical events;

[0020] The vulnerable units in the circuit module are screened out based on the fault tree model.

[0021] Optionally, the step of screening out vulnerable units in the circuit module based on the fault tree model includes:

[0022] The fault tree model is solved by using Boolean operations to determine the minimum cut set of the fault tree model, and the circuit logic unit combination corresponding to the minimum cut set is used as the fragile unit.

[0023] Optionally, the steps of performing a fault detection operation on the automotive-grade chip to be tested in the random hardware fault detection platform, obtaining a fault detection result of each vulnerable unit, and establishing a compressed sensing equation based on the fault detection result include:

[0024] Build a detection platform for random hardware failures;

[0025] Perform fault injection on the automotive-grade chip to be tested on the testing platform, input preset test vectors and test protocols, and start the test operation on the automotive-grade chip to be tested;

[0026] Obtain observation matrix and test results based on test operations;

[0027] A compressed sensing equation is established according to the measurement matrix and the test results.

[0028] Optionally, the step of establishing a compressed sensing equation according to the measurement matrix and the test result includes:

[0029] Generate an observation matrix based on the fault status corresponding to each fragile unit in the test results;

[0030] The compressed sensing equation is established based on the observation matrix sequence obtained from multiple test results.

[0031] Optionally, the step of solving the compressed sensing equation and locating the vulnerable unit where the random hardware failure occurs according to the solution result includes:

[0032] The convex optimization method is used to solve the compressed sensing equation and obtain the sparse signal solution of the compressed sensing equation;

[0033] determining whether a corresponding fragile unit has issued a random hardware fault according to a value corresponding to the sparse signal solution, and obtaining a random hardware fault determination result;

[0034] The vulnerable unit where the fault occurs is located based on the random hardware fault determination results.

[0035] Optionally, after the step of solving the compressed sensing equation and locating the vulnerable unit where the random hardware failure occurs according to the solution result, the method further includes:

[0036] Analyze the random hardware fault determination results to identify the vulnerable units corresponding to permanent faults and the vulnerable units corresponding to transient faults;

[0037] The fragile units corresponding to permanent faults are removed from the random hardware fault judgment results to obtain the fragile units corresponding to transient faults.

[0038] In a second aspect, the present application provides a random hardware fault location system for automotive-grade chips, which includes:

[0039] The circuit analysis module is used to analyze the circuit structure of the automotive-grade chip to be tested and extract the circuit modules associated with the preset safety goals;

[0040] A vulnerable point screening module, configured to screen out vulnerable units from the circuit module;

[0041] The test module is used to perform fault detection operations on the automotive-grade chip to be tested in the random hardware fault detection platform, obtain the fault detection results of each vulnerable unit, and establish a compressed sensing equation based on the fault detection results;

[0042] The fault point location module is used to solve the compressed sensing equation and locate the vulnerable unit where the random hardware failure occurs according to the solution result.

[0043] In a third aspect, the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores one or more computer-readable programs, and the one or more computer-readable programs can be executed by one or more processors. When the computer-readable program is executed by the processor, the hardware fault location method for automotive-grade chips is implemented.

[0044] Beneficial effect: The present invention provides a method, system and storage medium for locating random hardware faults for automotive-grade chips. By analyzing the circuit structure of the automotive-grade chip to be tested, the circuit module associated with the preset security target is extracted; the vulnerable unit is screened out from the circuit module; a fault detection operation is performed on the automotive-grade chip to be tested in a detection platform for random hardware faults to obtain the fault detection results of each vulnerable unit, and a compressed sensing equation is established based on the fault detection results, the compressed sensing equation is solved, and the vulnerable unit where the random hardware fault occurs is located according to the solution result. The present application starts from a microscopic perspective and first screens out the vulnerable units in the circuit module, then performs fault detection on each vulnerable unit, and locates the vulnerable unit where the random hardware fault occurs based on the fault detection result. Therefore, the method of the present application can locate the security vulnerabilities existing inside the automotive-grade chip through a small number of observations, realize accurate evaluation of the chip function, and improve the accuracy and efficiency of chip detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 This is a flowchart of the steps of a random hardware fault locating method for automotive-grade chips provided by an embodiment of the present invention;

[0046] Figure 2 Schematic diagram of the relationship between incoherent observation and compressed sensing equation in an embodiment of the present invention;

[0047] Figure 3 Schematic diagram of the principle of a random hardware fault detection system according to an embodiment of the present invention;

[0048] Figure 4 1 is a schematic diagram of the random hardware fault location results of the MCU chip in an embodiment of the present invention;

[0049] Figure 5 It is a principle structure block diagram of the random hardware fault locating system in an embodiment of the present invention. DETAILED DESCRIPTION

[0050] In order to make the purpose, technical solutions and advantages of the present invention more clear and distinct, the present invention is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to illustrate the present invention and are not intended to limit the present invention.

[0051] It will be understood by those skilled in the art that, unless expressly stated otherwise, the singular forms "a", "an", "said" and "the" used herein may also include the plural forms. It should be further understood that the term "comprising" used in the description of the present invention refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. It should be understood that when we refer to an element as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be intermediate elements. In addition, "connected" or "coupled" as used herein may include wireless connections or wireless couplings. The term "and / or" used herein includes all or any units and all combinations of one or more associated listed items.

[0052] With the rapid development of intelligent connected vehicles (ICVs) both domestically and internationally, the functional safety of automotive-grade chips has become a key issue in the development of ICVs. Automotive-grade chips must operate in diverse pressure and dynamic environments, including temperatures ranging from -40°C to 155°C, high vibration, dust, radiation, and electromagnetic interference. Furthermore, there are concerns about personal safety, and automotive chips have higher reliability and safety requirements, with a typical design life of 10 to 15 years. Therefore, automotive-grade chips must meet reliability, consistency, and stability requirements. As automotive-grade chips evolve from traditional large size and single function to smaller size, high integration, high computing power, and multi-function, their random hardware failure rate is also increasing, necessitating urgent improvements in functional safety.

[0053] The functional safety of automotive-grade chips means that chips used in automotive electronic systems must strictly comply with a series of functional safety standards and specifications to ensure that even in the event of a random hardware failure event inside the chip, they can still stably and reliably perform the corresponding functions, thereby effectively preventing accidents or potential dangers caused by failures. Functional safety standards and requirements usually include specifications for chip design, development, testing and verification processes to ensure that various potential failure conditions are taken into account in the chip design phase and that a high degree of reliability and safety can be maintained in actual use. In order to ensure the safety of vehicle electronic systems, the international functional safety standard ISO 26262: Road vehicles—Functional safety and the national standard GB / T 34590 functional safety standard "Road vehicles—Functional safety" came into being, which clearly include chip analysis and testing requirements.

[0054] Chip functional safety primarily revolves around failures, which are primarily categorized as systematic failures and random hardware failures. Systematic failures refer to unpredictable failures during the chip's lifecycle and are the focus of chip functional safety analysis. Random hardware failures are unexpected and random hardware failures that occur during the hardware's lifecycle due to factors such as physical processes or environmental stress. The timing of these failures is unpredictable, but they follow a certain probability distribution, such as an exponential distribution. Random hardware failures are typically caused by various degradation mechanisms, such as component aging, fatigue, physical degradation, and external environmental stress. Random hardware failures are primarily categorized as permanent failures and transient failures. Permanent failures are typically caused by issues with the chip manufacturing process and physical processes, such as open circuits and short circuits. Transient failures are typically caused by the chip's packaging materials or environmental factors, such as bit flips caused by single event effects (SEEs) induced by high-energy radiation particles in the automotive driving environment. Random hardware failures are the root cause of functional safety failures in chips. Efficient security vulnerability detection methods will help identify negligence or weak links in the functional safety design of chips, which is of great significance for targeted security mechanism optimization and accurate and objective security assessment.

[0055] In order to accurately locate random hardware failures that may occur in automotive-grade chips, the present application provides a random fault location method. By first analyzing the circuit structure of the automotive-grade chip to be tested, the chip's security goals are mapped to the signals transmitted in the circuit module to screen out vulnerable units that may have random hardware failures, and faults are injected into each vulnerable unit. A compressed sensing equation is established based on the detection results, and the vulnerable units corresponding to the random hardware failures are located according to the calculation results of the compressed sensing equation, thereby achieving an assessment of security vulnerabilities inside the chip from a microscopic perspective, providing technical support for the optimization of chip structure and accurate evaluation of chip functions.

[0056] The embodiments of the present invention are further described below with reference to the accompanying drawings.

[0057] First, this embodiment proposes a random hardware fault location method for automotive-grade chips, such as Figure 1 ,include:

[0058] Step S1: Analyze the circuit structure of the automotive-grade chip to be tested and extract the circuit modules associated with the preset safety goals.

[0059] For the automotive-grade chip to be tested, its circuit structure is obtained and analyzed to extract the circuit modules related to the preset safety goals.

[0060] Specifically, methods for obtaining the circuit structure of an automotive-grade chip can include: searching for the product model of the automotive-grade chip to be tested, and searching for relevant information based on the product model. For example, technical documentation related to the automotive-grade chip can be found on the chip manufacturer's official website. This technical documentation contains detailed information related to the chip's circuit structure. Information related to the automotive-grade chip's circuit structure can also be obtained by browsing technical analysis, review articles, or related materials related to the automotive-grade chip on professional websites. The detailed circuit structure of the chip can also be obtained by studying the automotive-grade chip's circuit diagram and understanding the connection methods and signal transmission paths between the various components.

[0061] In detail, this step includes:

[0062] Step S11: Determine the safety target of the automotive-grade chip to be tested based on the chip type and chip function.

[0063] First, thoroughly understand the type and functionality of the automotive-grade chip to be tested. This ensures the chip's specific type and functionality. For example, automotive-grade chips can include computing and control chips (such as MCUs and SOCs), power chips (such as MOSFETs and IGBTs), sensor chips, memory chips, and positioning chips. Chip functions include data processing, storage, control, communication, and sensing.

[0064] Because automotive-grade chips need to have failure risks under extreme temperature ranges, high vibrations, and high magnetic fields. Failure risks may include: system failures, data leakage, etc., which pose threats to the safety and stability of the vehicle. Therefore, based on the type and functional characteristics of the automotive-grade chip to be tested, the possible risks of the chip in specific applications are analyzed, and the risk level is evaluated, and then the functional safety goals are determined based on the possible risks and risk levels. The safety goal can be to determine the safety integrity level, and the safety integrity level reflects the safety importance of the chip in the system. The safety goal can also be reflected by customizing safety function requirements. Safety function requirements can be: the chip's fault detection and response capabilities, data protection capabilities, and redundant design requirements. Determine the safety goal based on the above-mentioned safety integrity level requirements and / or safety function requirements.

[0065] Specifically, the safety goal can be to achieve a safety integrity level of any level from ASIL-A to ASIL-D, or the safety functional requirement can be to meet specified data protection requirements. In specific implementations, circuit failures that violate safety objectives are considered top events, and transient faults that cause them are considered bottom events.

[0066] Step S12: Determine the calculation logic of the output signal in the automotive-grade chip to be tested based on the safety goal.

[0067] Based on the defined safety objectives, the calculation logic is determined from the output signals of each component in the circuit corresponding to the automotive-grade chip under test. Because the output signals of each circuit module in the automotive-grade chip contain logical relationships, it is possible to start with the top event and analyze it in sequence from top to bottom, representing the previous level event with the next level until the bottom-level circuit logic is analyzed.

[0068] Step S13: Extract circuit information associated with the safety target from the circuit of the automotive-grade chip to be tested according to the calculation logic of the output signal in the target detection automotive-grade chip.

[0069] Based on the calculation logic of the circuit's output signals, the circuit modules relevant to the safety target are extracted from the chip's overall circuitry, resulting in a circuit structure relevant to the top event. Because the circuit structure of automotive-grade chips contains some circuit structures that are irrelevant to the preset safety target, this step extracts circuit information relevant to the set safety target from the circuit structure based on the calculation logic of the chip's output signals.

[0070] Step S2: Screen out fragile units from the circuit module.

[0071] Vulnerable units that may fail are screened from the extracted circuit modules. Specifically, vulnerable units are logic units that are propagative in a faulty state and, if they fail, will directly violate chip safety objectives. These units pose a potential threat to chip functional safety and are the source of security vulnerabilities. Vulnerable units are based on the chip's logical implementation, not the physical circuit layout or the physical properties of the components themselves. From a microscopic circuit perspective, not all circuit faults will cause chip failure, nor will all failures be relevant to vehicle safety. Whether a circuit unit is considered vulnerable is closely related to its specific functional implementation and is primarily reflected in two aspects: first, analyzing whether the failure effects of the logic unit can be shielded by other logic units or system-level design, thereby preventing fault propagation; second, assessing whether the circuit failure caused by the unit's failure is directly related to safety, that is, whether it violates the pre-defined safety objectives. Vulnerable units are the focus of testing, so identifying them during the analysis phase can achieve optimal testing results.

[0072] Specifically, this step includes:

[0073] Step S21: Acquire event symbols, logic gate symbols, and transfer symbols corresponding to the causal relationships between various events in the circuit module.

[0074] Based on the logical relationships between the output signals of various components in a circuit module, the causal relationships between various events in the circuit module are derived. The corresponding event symbols, logic gate symbols, and transition symbols are then determined based on the causal relationships between these events. Event symbols are used to represent events or states occurring in a circuit. Logic gate symbols are basic elements in digital circuits, used to represent logical operations. Transition symbols are used to represent state transitions in state machines or sequential circuits.

[0075] Step S22: Determine the progressive relationship between logic events according to the event symbols, logic gate symbols, and transfer symbols.

[0076] The event symbols, logic gate symbols and transfer symbols determined according to the above steps can determine the progressive relationship between logic events.

[0077] Step S23: Establish a fault tree model based on the progressive relationship between logical events.

[0078] A fault tree model is established based on the progressive relationship between logical events. Because Fault Tree Analysis (FTA) is an inverted tree-like logical causal relationship diagram that describes the causal relationship between various events in a system using event symbols, logic gate symbols, and transition symbols, it can be used to reflect the failure mechanisms in chips. In a fault tree model, events that violate safety goals in the chip are considered top events, and vulnerable units are considered bottom events. Random hardware faults are located by identifying vulnerable units in the system that may cause safety violations.

[0079] Step S24: Screen out vulnerable units in the circuit module based on the fault tree model.

[0080] The fault tree model established in the above steps is calculated, and based on the calculation results, vulnerable units in the circuit module are screened. In one implementation, the fault tree model is solved using Boolean operations to determine the minimum cut set of the fault tree model, and the circuit logic unit combination corresponding to the minimum cut set is used as the vulnerable unit. Since the minimum cut set of the fault tree is found through calculation, the simplest combination of logic units where the top event occurs is determined, and the set of these simplest combinations is the vulnerable unit, thereby screening the vulnerable units in the circuit module.

[0081] Step S3: performing a fault detection operation on each of the fragile units based on a pre-established test simulation platform to obtain a fault detection result, and establishing a compressed sensing equation based on the fault detection result.

[0082] After screening out the vulnerable units, the chip is subjected to fault detection operations using a test simulation platform, and a compressed sensing equation is established based on the test results.

[0083] Since any given matrix has a large incoherence with the random matrix, the random matrix can be used as the observation matrix to collect data in compressed sensing technology. The random Gaussian matrix, random Bernoulli matrix and some Fourier matrices meet the isometry constraint.

[0084] In this embodiment, an incoherent observation model of a fragile unit is first established. The physical meaning of the mapping signal is defined in the incoherent observation model. The mapping signal includes: a signal to be measured, an observation matrix, and an observation signal.

[0085] The signal to be tested is represented as X, where X is the fault state of the fragile unit inside the chip to be tested, and X is If x j =1, indicating that the vulnerable unit is a faulty unit, i.e., a security vulnerability unit. If x j =0, indicating that the fragile unit C j It is not a faulty unit, that is, the vulnerable unit is safe.

[0086] The measurement matrix Φ: the elements of Φ are denoted as a ij (i∈1,2,LM,j∈1,2,LN), i represents the i-th observation, j represents the j-th vulnerable unit tested. If the coefficient a corresponding to the observation matrix ij =1, it means that the fragile unit is observed and its fault status is counted in the i-th observation result; if the coefficient a of the observation matrix ij =0, it means that this unit is not observed and its fault status will not be reflected in the i-th observation result.

[0087] Observation signal Y: Y is a column vector whose element y i (i∈1,2,...,M) represents the total number of faults corresponding to each incoherent observation, which is obtained by scanning the test results.

[0088] Since the measured signal represents the fault state of the logic unit, the measured signal x j Is a discrete signal distributed between 0 and 1, the test result y i is an integer greater than or equal to 0. The observation matrix indicates whether the vulnerable unit has been observed, so the coefficients in the observation matrix are integers with a 0-1 distribution. Based on the above analysis, a 0-1 Bernoulli random matrix satisfies the two constraints mentioned above. The lower bound of the observation matrix, i.e., the number of observations, requires theoretical and data analysis methods to determine.

[0089] In this embodiment, the concept of random measurement matrix in compressed sensing is transformed into an effective selection of test nodes in the testability design method to generate corresponding incoherent test vectors, such as Figure 2As shown, the result of each observation is used as a set of data test vectors, and the M sets of data of the Mth observation constitute a random sequence of the observation matrix. That is, each row of the observation matrix corresponds to an incoherent observation, and the result of each observation y i represents the total number of faulty units detected in the i-th observation, which can be obtained by analyzing the output test vector, where the coefficient of the incoherent observation matrix Φ is recorded as a ij , i represents the i-th observation, and j represents the j-th observed fragile unit.

[0090] If the coefficient a corresponding to the observation matrix ij = 1, it means that the fragile unit is observed in the i-th observation, that is, the test vector set corresponding to this observation needs to include the test vector for testing this unit. Accordingly, the fault state of this fragile unit will be reflected in the total number of faults y obtained in the i-th random observation i On the contrary, if the coefficient a of the observation matrix ij = 0, it means that this fragile unit is not observed in the i-th observation, that is, the test vector set does not need to include the vector for testing this fragile unit. Accordingly, the fault status of this fragile unit will not be reflected in the total number of faults y obtained in this observation. i In the statistics, as in the compressed sensing imaging technology, the light of the pixel is not included in the measurement value. According to the measurement matrix and the M-times observation result y i , we can establish a compressed sensing equation Y=ΦX.

[0091] Specifically, this step includes:

[0092] Build a detection platform for random hardware failures; inject faults into the automotive-grade chip to be tested on the detection platform, input preset test vectors and test protocols, and start the test operation on the automotive-grade chip to be tested; obtain an observation matrix and test results based on the test operation; and establish a compressed sensing equation based on the observation matrix and test results.

[0093] Combine Figure 3 As shown, first, a random hardware fault detection platform must be established. Faults are then injected into the chip, and the test results are observed. Compressed sensing equations are then established based on these results. The automotive-grade chip to be tested is then unsealed and removed to allow for soft fault injection. The exposed automotive-grade chip to be tested is then securely placed on a compressed sensing observation platform, connected to the fault injection equipment, and faults are injected into the chip. Simultaneously, pre-set test vectors and test protocols are input for testing. Finally, the compressed sensing equations are established based on the observation matrix and test results.

[0094] Specifically, the step of establishing a compressed sensing equation based on the observation matrix and test results includes: generating an observation matrix based on the fault state corresponding to each vulnerable unit in the test results; and establishing a compressed sensing equation based on a sequence of observation matrices obtained from multiple test results. In this step, M incoherent observations are performed, resulting in M ​​equations, i.e., a compressed sensing equation.

[0095] Step S4: Solve the compressed sensing equation and locate the vulnerable unit where the random hardware failure occurs according to the solution result.

[0096] In this step, the problem of solving the observed compressed sensing method is to locate random hardware faults in the automotive-grade chip under test. Based on the calculated solution of the compressed sensing equation, it is possible to identify security vulnerability units that violate the safety goals in the automotive-grade chip under test. Due to the sparsity and incoherence of the observed signal, convex optimization methods with high reconstruction accuracy can be used to solve the compressed sensing equation, thereby locating the random hardware faults that cause the safety goals to fail.

[0097] Specifically, the step of solving the compressed sensing equation and locating the vulnerable unit where the random hardware failure occurs according to the solution result includes:

[0098] A convex optimization method is used to solve the compressed sensing equation to obtain a sparse signal solution to the compressed sensing equation. Based on the value corresponding to the sparse signal solution, it is determined whether the corresponding fragile unit has issued a random hardware fault, thereby obtaining a random hardware fault determination result. Based on the random hardware fault determination result, the fragile unit that has failed is located. Solving the compressed sensing equation is to obtain the value of the signal to be measured, X. If the value of X is 1, it means that the fragile unit will issue a random hardware fault. If the value of X is 0, it means that the fragile unit will not issue a hardware fault.

[0099] In this embodiment, the feasibility of the solution is verified by taking the safety failure event of abnormal acceleration and deceleration of the MCU chip as an example. The simulation tool uses VCS and the test vector generation tool uses TetraMax TM . Figure 4 The figure shows the random hardware fault location diagram of the MCU chip.

[0100] In order to more accurately locate the vulnerable unit corresponding to the random hardware failure, after solving the compressed sensing equation and locating the vulnerable unit where the random hardware failure occurs according to the solution result, the method further includes:

[0101] Analyze the random hardware fault determination results to identify the vulnerable units corresponding to permanent faults and the vulnerable units corresponding to transient faults;

[0102] The fragile units corresponding to permanent faults are removed from the random hardware fault judgment results to obtain the fragile units corresponding to transient faults.

[0103] Because the random hardware fault distribution obtained under fault injection conditions includes contributions from both permanent and transient faults, further refinement is required by testing them under non-fault injection conditions using the same observation method to identify only permanent faults. By removing permanent faults from the total random hardware fault distribution, transient faults can be precisely identified, providing solid data support and improvement directions for subsequent chip design and safety protection strategies.

[0104] The method disclosed in this embodiment establishes a fault tree model based on possible failure modes in automotive-grade chips, and analyzes and locates the causes of failures in the chip based on the fault tree model.

[0105] First, based on the chip type and main functions, determine the chip's safety goals and top events (safety hazards that may be caused by the chip's failure). Failure problems in the circuit that violate the safety goals are regarded as top events, and transient faults that cause top events are regarded as bottom events.

[0106] Secondly, analyze the circuit structure of the automotive-grade chip to be tested and extract the circuit modules that are only related to the determined safety goals from the entire circuit of the chip.

[0107] Next, the output signals of the extracted circuit modules are analyzed to establish a fault tree model. During the output signal analysis, based on the logical relationship between the output signals and the various circuit modules within the circuit, starting from the top event, the previous level event is represented by the next level event from top to bottom until the bottom level circuit logic unit is reached.

[0108] Finally, an incoherent observation model of the vulnerable unit is established, and a compressed sensing equation is established based on the incoherent observation model. The compressed sensing method is used to solve the problem and locate the vulnerable unit corresponding to the random hardware failure.

[0109] Specifically, a bare integrated circuit is securely placed on a compressed sensing observation platform, connected to a fault injection device, and faults are injected into the chip. Pre-set test vectors and test protocols are then input for testing. Ultimately, a compressed sensing equation is established based on the observation matrix and test results. By performing multiple incoherent observations, multiple equations can be established, creating a single compressed sensing equation. By resolving these equations, random hardware faults that cause safety goal failures can be located.

[0110] Based on the above random hardware fault location method, this application also provides a random hardware fault location system for automotive-grade chips, such as Figure 5As shown, the random hardware fault locating system includes:

[0111] The circuit analysis module 510 is used to analyze the circuit structure of the automotive-grade chip to be tested and extract the circuit modules associated with the preset safety goals; its function is as described in step S1.

[0112] The vulnerable point screening module 520 is used to screen out vulnerable units from the circuit module; its function is as described in step S2.

[0113] The test module 530 is used to perform fault detection operations on the automotive-grade chip to be tested in the random hardware fault detection platform, obtain the fault detection results of each vulnerable unit, and establish a compressed sensing equation based on the fault detection results; its function is as described in step S3.

[0114] The fault point location module 540 is used to solve the compressed sensing equation and locate the vulnerable unit where the random hardware failure occurs according to the solution result. Its function is as described in step S4.

[0115] Furthermore, the circuit analysis module includes: a safety target determination unit, a signal logic calculation unit and a circuit information extraction unit.

[0116] The safety target determination unit is used to determine the safety target of the automotive-grade chip to be tested based on the chip type and chip function.

[0117] A signal logic calculation unit is used to determine the calculation logic of the output signal in the automotive-grade chip to be tested according to the safety goal.

[0118] A circuit information extraction unit is used to extract circuit information associated with the safety target from the circuit of the automotive-grade chip to be tested based on the calculation logic of the output signal in the target detection automotive-grade chip.

[0119] Furthermore, the vulnerability screening module includes: a symbol information acquisition unit, an event logic analysis unit, a fault tree model establishment unit and a screening unit.

[0120] A symbol information acquisition unit, configured to acquire event symbols, logic gate symbols, and transfer symbols corresponding to causal relationships between various events in a circuit module;

[0121] an event logic analysis unit, configured to determine a progressive relationship between logic events based on the event symbols, logic gate symbols, and transfer symbols;

[0122] A fault tree model building unit is used to build a fault tree model based on the progressive relationship between logical events;

[0123] A screening unit is used to screen out vulnerable units in a circuit module based on the fault tree model.

[0124] Furthermore, the screening unit includes: a fault tree calculation subunit;

[0125] The fault tree calculation subunit is used to solve the fault tree model using Boolean operations, determine the minimum cut set of the fault tree model, and use the circuit logic unit combination corresponding to the minimum cut set as the fragile unit.

[0126] Furthermore, the test module includes: a platform building unit, a test operation unit, a test result unit and an equation building unit.

[0127] Platform building unit, used to build a detection platform for random hardware failures;

[0128] The test operation unit is used to inject faults into the automotive-grade chip to be tested on the detection platform, and at the same time input preset test vectors and test protocols to start the test operation on the automotive-grade chip to be tested.

[0129] The test result unit is used to obtain the observation matrix and test results based on the test operation.

[0130] An equation building unit is used to build a compressed sensing equation according to the observation matrix and the test results.

[0131] Furthermore, the equation construction unit includes: an observation matrix generation subunit and an equation establishment subunit.

[0132] The observation matrix generation subunit is used to generate an observation matrix according to the fault state corresponding to each fragile unit in the test results;

[0133] The equation building subunit is used to build a compressed sensing equation based on the observation matrix sequence obtained from multiple test results.

[0134] Furthermore, the fault point location module includes: an equation solving unit, a fault judgment unit and a vulnerable point location unit.

[0135] An equation solving unit, used for solving the compressed sensing equation by using a convex optimization method to obtain a sparse signal solution of the compressed sensing equation;

[0136] a fault judgment unit, configured to determine, based on a value corresponding to the sparse signal solution, whether a corresponding fragile unit has issued a random hardware fault, and obtain a random hardware fault judgment result;

[0137] The vulnerable point location unit is used to locate the vulnerable unit where the fault occurs based on the random hardware fault determination result.

[0138] Optionally, the system further includes: a result analysis unit and a fault screening unit.

[0139] A result analysis unit is used to analyze the random hardware fault determination results and identify the fragile units corresponding to permanent faults and the fragile units corresponding to transient faults;

[0140] The fault screening unit is used to remove the fragile units corresponding to permanent faults from the random hardware fault determination results to obtain the fragile units corresponding to transient faults.

[0141] Based on the disclosure of the above-mentioned method and system, the present application also provides a computer-readable storage medium, wherein the computer-readable storage medium stores one or more computer-readable programs, and the one or more computer-readable programs can be executed by one or more processors. When the computer-readable program is executed by the processor, the hardware fault location method for automotive-grade chips is implemented.

[0142] Existing automotive-grade chip testing methods mostly focus on macro-level testing and lack the ability to analyze and expose security vulnerabilities at the micro level, thus limiting targeted design and accurate safety assessments. This invention addresses the inadequacy of current automotive-grade chip functional safety testing methods and the difficulty in locating random hardware faults. By cleverly utilizing the sparse distribution of faulty units within the chip, the invention integrates compressed sensing technology with testability technology to construct an incoherent observation model. This model performs incoherent observations on vulnerable units within the chip, thereby revealing faulty units within the chip that affect functional safety with a small number of observations. This new method and model for functional safety testing of automotive-grade chips is established.

[0143] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A random hardware fault location method for automotive-grade chips, characterized by: include: Analyze the circuit structure of the automotive-grade chip to be tested and extract the circuit modules associated with the preset safety goals; screening out fragile units from the circuit module; In a random hardware fault detection platform, fault detection operations are performed on the automotive-grade chip to be tested, and the fault detection results of each vulnerable unit are obtained. Based on the fault detection results, a compressed sensing equation is established; Solving the compressed sensing equation and locating the vulnerable unit where the random hardware failure occurs according to the solution result; The step of screening out fragile units from the circuit module includes: Obtaining event symbols, logic gate symbols, and transfer symbols corresponding to the causal relationships between various events in the circuit module; Determining a progressive relationship between logic events based on the event symbols, logic gate symbols, and transfer symbols; Establish a fault tree model based on the progressive relationship between logical events; Screening out vulnerable units in a circuit module based on the fault tree model; The steps of performing a fault detection operation on the automotive-grade chip to be tested in the random hardware fault detection platform, obtaining a fault detection result of each vulnerable unit, and establishing a compressed sensing equation based on the fault detection result include: Build a detection platform for random hardware failures; Perform fault injection on the automotive-grade chip to be tested on the testing platform, input preset test vectors and test protocols, and start the test operation on the automotive-grade chip to be tested; Obtain observation matrix and test results based on test operations; A compressed sensing equation is established according to the measurement matrix and the test results.

2. The random hardware fault location method for automotive-grade chips according to claim 1 is characterized in that: The step of analyzing the circuit structure of the automotive-grade chip to be tested and extracting the circuit modules associated with the preset safety goals includes: Determine the safety objectives of the automotive-grade chip to be tested based on the chip type and chip function; Determining, based on the safety goal, a calculation logic for an output signal in the automotive-grade chip to be tested; According to the calculation logic of the output signal in the automotive-grade chip to be tested, circuit information associated with the safety target is extracted from the circuit of the automotive-grade chip to be tested.

3. The random hardware fault location method for automotive-grade chips according to claim 2 is characterized in that: The step of screening out vulnerable units in the circuit module based on the fault tree model includes: The fault tree model is solved by using Boolean operations to determine the minimum cut set of the fault tree model, and the circuit logic unit combination corresponding to the minimum cut set is used as the fragile unit.

4. The random hardware fault location method for automotive-grade chips according to claim 3 is characterized in that: The step of establishing a compressed sensing equation according to the measurement matrix and the test results comprises: Generate an observation matrix based on the fault status corresponding to each fragile unit in the test results; The compressed sensing equation is established based on the observation matrix sequence obtained from multiple test results.

5. The random hardware fault location method for automotive-grade chips according to claim 1 is characterized in that: The step of solving the compressed sensing equation and locating the vulnerable unit where the random hardware failure occurs according to the solution result includes: The convex optimization method is used to solve the compressed sensing equation and obtain the sparse signal solution of the compressed sensing equation; determining whether a corresponding fragile unit has issued a random hardware fault according to a value corresponding to the sparse signal solution, and obtaining a random hardware fault determination result; The vulnerable unit where the fault occurs is located based on the random hardware fault determination results.

6. The random hardware fault location method for automotive-grade chips according to claim 5 is characterized in that: After the step of solving the compressed sensing equation and locating the vulnerable unit where the random hardware failure occurs according to the solution result, the method further includes: Analyze the random hardware fault determination results to identify the vulnerable units corresponding to permanent faults and the vulnerable units corresponding to transient faults; The fragile units corresponding to permanent faults are removed from the random hardware fault judgment results to obtain the fragile units corresponding to transient faults.

7. A random hardware fault location system for automotive-grade chips, characterized by: include: The circuit analysis module is used to analyze the circuit structure of the automotive-grade chip to be tested and extract the circuit modules associated with the preset safety goals; A vulnerable point screening module, used to screen out vulnerable units from the circuit module; The test module is used to perform fault detection operations on the automotive-grade chip to be tested in the random hardware fault detection platform, obtain the fault detection results of each vulnerable unit, and establish a compressed sensing equation based on the fault detection results; a fault point location module, configured to solve the compressed sensing equation and locate the vulnerable unit where the random hardware failure occurs according to the solution result; The step of screening out fragile units from the circuit module includes: Obtaining event symbols, logic gate symbols, and transfer symbols corresponding to the causal relationships between various events in the circuit module; Determining a progressive relationship between logic events based on the event symbols, logic gate symbols, and transfer symbols; Establish a fault tree model based on the progressive relationship between logical events; Screening out vulnerable units in a circuit module based on the fault tree model; The steps of performing a fault detection operation on the automotive-grade chip to be tested in the random hardware fault detection platform, obtaining a fault detection result of each vulnerable unit, and establishing a compressed sensing equation based on the fault detection result include: Build a detection platform for random hardware failures; Perform fault injection on the automotive-grade chip to be tested on the testing platform, input preset test vectors and test protocols, and start the test operation on the automotive-grade chip to be tested; Obtain observation matrix and test results based on test operations; A compressed sensing equation is established according to the measurement matrix and the test results.

8. A computer-readable storage medium, characterized in that The computer-readable storage medium stores one or more computer-readable programs, and the one or more computer-readable programs can be executed by one or more processors. When the computer-readable program is executed by the processor, the random hardware fault locating method for automotive-grade chips as described in any one of claims 1-6 is implemented.

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