A multi-level coverage collection system

Abstract

The present application relates to the field of chip verification technologies, and particularly to a multi-level coverage collection system. This system determines whether other verification methods need to be used to update the coverage for modules with incomplete coverage collection by presetting a verification duration, avoiding a decrease in the overall chip verification efficiency caused by the excessive time-consuming coverage collection of deep-level modules. Moreover, based on the module complexity of the current module and the verification environment complexity of the preset verification environment, a suitable verification method is selected to update the coverage of the current module, thereby improving the flexibility and reliability of deep-level module coverage collection, effectively enhancing the efficiency of deep-level module coverage collection, enabling the rapid collection of deep-level module coverage, and thus improving the chip verification efficiency.

Description

Technical Field

[0001] The present invention relates to the field of chip verification technology, and in particular to a multi-level coverage collection system. Background Art

[0002] In the chip verification scenario, a more complex design to be tested will contain more levels. For modules at a deeper level, if more scenarios need to be involved when collecting coverage, it will be difficult to collect all scenarios due to the deep levels and multiple instantiations. The collected coverage is difficult to meet expectations. For example, the verification of the cache module involves the status of various instructions such as reading data, writing data, and forcing writing to the next level of storage, as well as the status of hits and misses in different ways, resulting in a large number of scenarios that need to be covered in the verification of the cache module.

[0003] To address the above issues, when faced with the situation where full coverage cannot be collected for deep modules, existing methods usually require manual construction of specific stimuli to input into the top-level module of the design to be tested. However, due to the complexity of the design to be tested, manually constructing stimuli to collect coverage for deep modules takes a long time, and it is even difficult to construct effective stimuli, resulting in low chip verification efficiency.

[0004] Therefore, how to quickly collect the coverage of deep modules to improve the efficiency of chip verification has become an urgent problem to be solved. Summary of the invention

[0005] In view of the above technical problems, the technical solution adopted by the present invention is:

[0006] A multi-level coverage collection system, the system comprising: a design to be verified, a processor and a memory storing a computer program, wherein the design to be verified comprises M modules {a 1 , a 2 , …, a m , …, a M}, a m is the mth module in the design to be verified, where m is an integer in the range [1, M], and a m Corresponding to a m The level b in the design to be verified m , when the computer program is executed by a processor, the following steps are implemented:

[0007] S101, verifying the design to be verified under a preset verification environment, and recording the coverage rate of each module under a preset verification time.

[0008] S102. When there is at least one module with a coverage rate less than the preset coverage rate threshold, for any module with a coverage rate less than the coverage rate threshold, if the level to which the current module belongs is greater than the preset level threshold and the preset verification duration meets the preset first condition, obtain the module complexity corresponding to the current module.

[0009] S103. If the module complexity corresponding to the current module is less than the preset first complexity threshold, update the coverage rate of the current module using the first verification method.

[0010] S104. If the module complexity corresponding to the current module is greater than or equal to the first complexity threshold and the verification environment complexity corresponding to the preset verification environment is less than the preset second complexity threshold, update the coverage rate of the current module using the second verification method.

[0011] S105. If the module complexity corresponding to the current module is greater than or equal to the first complexity threshold and the verification environment complexity corresponding to the preset verification environment is greater than or equal to the second complexity threshold, update the coverage rate of the current module using the third verification method.

[0012] Compared with the prior art, the present invention has obvious beneficial effects. By means of the above technical solutions, a multi-level coverage rate collection system provided by the present invention can achieve considerable technical progressiveness and practicality, and has wide utilization value in the industry. It has at least the following beneficial effects:

[0013] The present invention provides a multi-level coverage rate collection system, which includes: a design to be verified, a processor, and a memory storing a computer program. Among them, the design to be verified includes M modules {a 1 , a 2 , …, a m , …, a M}, where a m is the m-th module in the design to be verified, m is an integer within the range of [1, M], and a m corresponds to the level b m to which a m, when the computer program is executed by a processor, the following steps are implemented: S101, verifying the design to be verified in a preset verification environment, and recording the coverage rate corresponding to each module under a preset verification duration; S102, when there is at least one module whose corresponding coverage rate is less than a preset coverage rate threshold, for any module whose coverage rate is less than the coverage rate threshold, if the level to which the current module belongs is greater than a preset level threshold and the preset verification duration meets a preset first condition, then obtain the module complexity corresponding to the current module; S103, if the module complexity corresponding to the current module is less than a preset first complexity threshold, then update the coverage rate of the current module using a first verification method; S104, if the module complexity corresponding to the current module is greater than or equal to the first complexity threshold and the verification environment complexity corresponding to the preset verification environment is less than a preset second complexity threshold, then update the coverage rate of the current module using a second verification method; S105, if the module complexity corresponding to the current module is greater than or equal to the first complexity threshold and the verification environment complexity corresponding to the preset verification environment is greater than or equal to the second complexity threshold, then update the coverage rate of the current module using a third verification method.

[0014] It can be seen that by using the preset verification duration to determine whether it is necessary to use other verification methods to update the coverage rate for modules with insufficiently collected coverage rates, it avoids the decrease in the overall chip verification efficiency caused by the excessive time-consuming for collecting the coverage rates of deep-level modules. And based on the module complexity of the current module and the verification environment complexity of the preset verification environment, a suitable verification method is selected to update the coverage rate of the current module, thereby improving the flexibility and reliability of collecting the coverage rates of deep-level modules, effectively improving the efficiency of collecting the coverage rates of deep-level modules, enabling the rapid collection of the coverage rates of deep-level modules, and thus improving the chip verification efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0016] Figure 1 It is a flowchart of the computer program executed by a processor in a multi-level coverage rate collection system provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0017] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present invention.

[0018] This embodiment provides a multi-level coverage rate collection system. Refer to Figure 1 , which is a schematic flowchart of a computer program executed by a processor in a multi-level coverage rate collection system provided by an embodiment of the present invention. The system includes: a design to be verified, a processor, and a memory storing a computer program. Among them, the design to be verified includes M modules {a 1 , a 2 , …, a m , …, a M}, where a m is the m-th module in the design to be verified, m is an integer within the range of [1, M], and a m corresponds to the level b m to which a m belongs in the design to be verified. When the computer program is executed by the processor, the following steps are implemented:

[0019] S101, verify the design to be verified in a preset verification environment, and record the coverage rate corresponding to each module under the preset verification duration;

[0020] S102, when there is at least one module whose corresponding coverage rate is less than the preset coverage rate threshold, for any module whose coverage rate is less than the coverage rate threshold, if the level to which the current module belongs is greater than the preset level threshold, and the preset verification duration meets the preset first condition, then obtain the module complexity corresponding to the current module;

[0021] S103, if the module complexity corresponding to the current module is less than the preset first complexity threshold, then update the coverage rate of the current module using the first verification method;

[0022] S104, if the module complexity corresponding to the current module is greater than or equal to the first complexity threshold, and the verification environment complexity corresponding to the preset verification environment is less than the preset second complexity threshold, then update the coverage rate of the current module using the second verification method;

[0023] S105, if the module complexity corresponding to the current module is greater than or equal to the first complexity threshold, and the verification environment complexity corresponding to the preset verification environment is greater than or equal to the second complexity threshold, then update the coverage rate of the current module using the third verification method.

[0024] Among them, the design to be verified usually includes a top-level module, which may include several second-level modules, and each second-level module may further include several third-level modules, and so on.

[0025] The preset verification environment may refer to an integrated test system built to ensure the correctness of the chip design, aiming to verify whether the chip can work according to the expected function and performance requirements through various excitation and inspection mechanisms. The preset test environment corresponds to the top-level module in the design to be verified.

[0026] The preset verification duration may refer to the duration experienced from the starting time point of verifying the design to be verified to the preset time point. There can be multiple preset time points. Correspondingly, the coverage rate corresponding to each module under each preset verification duration can be recorded.

[0027] The coverage rate can be represented by the ratio of the number of collected scenarios to the number of all expected scenarios. The coverage rate threshold can be used to determine whether the collected coverage rate of the corresponding module meets the expectation. Usually, in chip verification, it is expected that the coverage rate collected for each module reaches 1, that is, each module can cover all its corresponding scenarios.

[0028] The preset first condition can be used to determine whether the verification duration of the top-level module is too long, thus affecting the efficiency of the overall verification process.

[0029] The module complexity can be evaluated from multiple dimensions such as the number of function points of the module, the interactivity between functions, the scalability of functions, the number of interface signals, the types of interface signals, the complexity of interface protocols, the data volume, the data type, the data storage and access methods, the number of clock domains involved, and the strictness of timing constraints. In this embodiment, the module complexity can be normalized by combining the module complexities of each module, and the normalization process can adopt the min-max normalization method.

[0030] The verification environment complexity can be evaluated from multiple dimensions such as the number of verification components, the types of verification components, the number of excitation modes, the complexity of excitation timing, the excitation correlation, the number of checkpoints, the depth and breadth of checks, the number of check methods, the number of configurable parameters, the mutual relationship of configuration parameters, and the flexibility and scalability of configuration. In this embodiment, the verification environment complexity can be normalized by combining the verification environment complexities of other known verification environments, and the normalization process can also adopt the min-max normalization method.

[0031] Specifically, when the condition that there is at least one module with a coverage rate less than a preset coverage rate threshold is not met, and for any module with a coverage rate less than the coverage rate threshold, the level to which the module belongs is greater than a preset level threshold, and the preset verification duration meets the preset first condition, continue to verify the design to be verified in the preset verification environment.

[0032] In a specific implementation manner, the preset first condition is that the preset verification duration is greater than a preset verification duration threshold.

[0033] Among them, when the preset verification duration is greater than the preset verification duration threshold, it can indicate that the verification duration of the top-level module is too long, which will lead to a decrease in the efficiency of the overall verification process, or it can be considered that it is difficult to update the coverage rate from the verification of the top-level module.

[0034] In a specific implementation manner, the preset verification duration corresponds to the number of verification stimuli;

[0035] Correspondingly, the preset first condition is that the preset verification duration is greater than a preset verification duration threshold, or the number of verification stimuli corresponding to the preset verification duration is greater than a preset number-of-stimuli threshold.

[0036] Among them, the number of verification stimuli corresponding to the preset verification duration being greater than the preset number-of-stimuli threshold can also characterize that it is difficult to update the coverage rate from the verification of the top-level module. In this case, the modules with unsatisfactory coverage rates can be independently verified, so that the coverage rates of such modules can reach the expectation more quickly.

[0037] In a specific implementation manner, a m contains several ports. Updating the coverage rate of the current module using the first verification method includes:

[0038] For any port in the current module, configure the reference signal corresponding to the current port to the current port in a forced assignment manner to update the coverage rate of the current module.

[0039] Among them, if the module complexity corresponding to the current module is less than a preset first complexity threshold, it can indicate that the design of the current module is relatively simple, and the current module can be driven by directly forcing (forcing) the port signals of the current module to collect missing scenarios and improve the coverage rate of the current module. A set of reference signals corresponding to each port can be used to collect a missing scenario.

[0040] Specifically, by forcibly specifying the port signals of the current module to drive the current module, it is possible to quickly update the coverage rate of the current module in a preset verification environment. Moreover, all components in the preset verification environment can be reused, with higher credibility, and only one verification database (Verification Database, vdb) needs to be generated.

[0041] In a specific implementation manner, the updating of the coverage rate of the current module by using the second verification method includes:

[0042] Construct a module verification sequencer in the preset verification environment and define interface components;

[0043] Through the module verification sequencer, assign the reference signals corresponding to each port in the current module to the interface components in the preset verification environment;

[0044] Use the interface components to configure the reference signals corresponding to each port in the current module to the corresponding ports in a forcibly specified manner to update the coverage rate of the current module.

[0045] Among them, the module verification sequencer can be used to assign the reference signals corresponding to each port in the current module to the interface components, and then through the interface components, configure the reference signals corresponding to each port in the current module to the corresponding ports in a forcibly specified manner.

[0046] Specifically, in a scenario where the module complexity is high and the verification environment complexity is low, that is, in a scenario where the module complexity corresponding to the current module is greater than or equal to the first complexity threshold, and the verification environment complexity corresponding to the preset verification environment is less than the preset second complexity threshold, the scenarios that the current module needs to cover are relatively complex. If there are many scenarios that the current module needs to cover, when using the first verification method to verify the current module, it is necessary to perform forced specification operations on many ports one by one, and the flexibility and reusability of the verification are poor, which will still lead to a reduction in verification efficiency. Therefore, in this embodiment, by defining interface components, the reference signals corresponding to each port in the current module are configured to the corresponding ports in a forcibly specified manner through the interface components at the same time, avoiding driving the current module multiple times. Compared with the first verification method, the second verification method has better reusability and randomness, and better applicability to complex scenarios and multiple scenarios, but the complexity of the verification process will also increase accordingly.

[0047] In a specific implementation manner, the preset verification environment corresponds to an inspector;

[0048] The updating of the coverage rate of the current module by using the third verification method includes:

[0049] Construct a reference verification environment corresponding to the current module, and the reference verification environment includes the inspector;

[0050] Verify the current module in the reference verification environment to update the coverage rate of the current module.

[0051] Among them, for the verification of the current module in the reference verification environment, at this time the current module is equivalent to a new design to be tested. When constructing the reference verification environment, the checker in the verification environment can be reused.

[0052] Specifically, when adopting the first verification method and the second verification method, the forced specification method may affect the normal function coverage. For example, if there is a design error in a certain module that causes the scenarios of another module not to be fully collected, the scenarios of the other module can be fully collected through the forced specification method, but it cannot be guaranteed that the functions of the design to be tested can be executed normally.

[0053] Moreover, the forced specification method requires additional processing of some special signals. For example, if the input of a certain module is configured through the forced specification method, and this module should originally receive input from another module, and the output of this module needs to be returned to another module, special processing is required in such cases, such as forcing the input of another module to be invalid, etc.

[0054] If the module complexity corresponding to the current module is greater than or equal to the first complexity threshold, and the verification environment complexity corresponding to the preset verification environment is greater than or equal to the second complexity threshold, then it can be considered that using the forced specification method is more likely to affect the normal functions of the design to be tested. Therefore, in this embodiment, the third verification method is adopted, that is, an independent reference verification environment is constructed for the current module. The reference verification environment and the preset verification environment are independent of each other and do not affect each other. Therefore, it will not affect the normal functions of the design to be tested. Moreover, there is no need to perform additional processing on special signals, which can fully guarantee the credibility of the preset verification environment. In addition, it can intuitively reflect whether the scenarios are collected through the top-level module or through the current module, and the credibility of the coverage rate is higher, which is more friendly to the subsequent analysis of the design to be tested. However, the third verification method requires additional maintenance of the reference verification environment, which increases the workload of the verification personnel. Moreover, it is necessary to move the code of the checker, coverage group, etc. in the preset verification environment, which also brings a certain amount of workload. And it is necessary to ensure the consistency between the reference verification environment and the preset verification environment. In addition, due to the existence of multiple verification environments, multiple verification databases need to be generated correspondingly.

[0055] In a specific implementation manner, the preset verification environment corresponds to a checker;

[0056] Updating the coverage rate of the current module using the third verification method includes:

[0057] Initialize the temporary level k = 2 and obtain the level corresponding to the current module;

[0058] If the level corresponding to the current module is less than K, determine the temporary module to which the current module belongs, and the level corresponding to this temporary module is k;

[0059] Construct a temporary verification environment corresponding to this temporary module, and the temporary verification environment includes the checker;

[0060] Verify this temporary module in the temporary verification environment to update the coverage rate of the current module, and record the temporary coverage rate corresponding to the current module at the temporary verification duration;

[0061] If the temporary coverage rate is less than the coverage rate threshold and the temporary verification duration meets the second preset condition, then update k = k + 1, and return to execute the step of determining the temporary module to which the current module belongs if the level corresponding to the current module is less than K.

[0062] Among them, directly using the method of constructing a reference verification environment corresponding to the current module to verify the current module will sacrifice the authenticity of some scenarios compared with the forced designation method. However, the test link expects that the simulated scenarios are all real and can occur. Therefore, in this embodiment, the layer-by-layer verification method is applied to the third verification method to retain the authenticity of the scenario as much as possible. However, this method will further increase the workload of the verification personnel.

[0063] Specifically, the condition for terminating the iteration in this embodiment is that the temporary coverage rate is greater than or equal to the coverage rate threshold, which indicates that the coverage rate of the current module has met the expectation at this time, or the level corresponding to the current module is equal to K, which indicates that the reference verification environment corresponding to the current module has been directly constructed at this time.

[0064] In a specific implementation manner, the second preset condition is:

[0065] The temporary verification duration is greater than the preset temporary duration threshold, where the temporary duration threshold corresponding to the temporary level k = k 1 is greater than the temporary duration threshold corresponding to the temporary level k = k 2 when, k 1 < k 2 and k 1 and k 2 both belong to integers within the range of [2, K].

[0066] Among them, when using the layer-by-layer verification method, compared with directly verifying the current module, additional module verification may be added. For example, if the current module cannot collect full coverage in the modules at each level to which it belongs, it will obviously affect the overall verification efficiency. Therefore, this embodiment sets different temporary duration thresholds for module verification at different levels. The temporary level k = k 1The corresponding temporary duration threshold when is greater than the temporary level k = k 2 The corresponding temporary duration threshold. It can mean that the deeper the level, the shorter the temporary duration threshold, thereby reducing the impact of the layer-by-layer verification method on the module verification time consumption.

[0067] Specifically, when adopting the layer-by-layer verification method, the implementer can also adjust the verification duration threshold to further reduce the impact of the layer-by-layer verification method on the module verification time consumption.

[0068] It can be seen that by presetting the verification duration to determine whether other verification methods need to be used to update the coverage rate for modules with insufficiently collected coverage rates, it avoids the decrease in the overall chip verification efficiency caused by the excessive time consumption of collecting the coverage rate of deep-layer modules. And through the module complexity of the current module and the verification environment complexity of the preset verification environment, an appropriate verification method is selected to update the coverage rate of the current module, thereby improving the flexibility and reliability of collecting the coverage rate of deep-layer modules, and also effectively improving the efficiency of collecting the coverage rate of deep-layer modules, enabling the coverage rate of deep-layer modules to be quickly collected, thus improving the chip verification efficiency.

[0069] Although some specific embodiments of the present invention have been described in detail by way of examples, those skilled in the art should understand that the above examples are only for illustration and not for limiting the scope of the present invention. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the present invention. The scope disclosed by the present invention is defined by the appended claims.

Claims

1. A multi-level coverage collection system, characterized in that: The system comprises: a design to be verified, a processor and a memory storing a computer program, wherein the design to be verified comprises M modules {a1, a2, ..., a m , …, a M }, a m is the mth module in the design to be verified, where m is an integer in the range [1, M], and a m Corresponding to a m The level b in the design to be verified m , a m The computer program comprises a plurality of ports, and when the computer program is executed by a processor, the following steps are implemented: S101, verifying the design to be verified under a preset verification environment, and recording the coverage rate of each module under a preset verification time; S102, when there is at least one module whose corresponding coverage is less than a preset coverage threshold, for any module whose coverage is less than the coverage threshold, if the level to which the current module belongs is greater than the preset level threshold and the preset verification time meets the preset first condition, then obtain the module complexity corresponding to the current module; S103: If the module complexity corresponding to the current module is less than a preset first complexity threshold, the coverage of the current module is updated using the first verification method, wherein the updating of the coverage of the current module using the first verification method includes: For any port in the current module, the reference signal corresponding to the current port is configured to the current port by forced designation to update the coverage of the current module; S104: If the module complexity corresponding to the current module is greater than or equal to the first complexity threshold, and the verification environment complexity corresponding to the preset verification environment is less than the preset second complexity threshold, the coverage of the current module is updated using the second verification method, wherein the updating of the coverage of the current module using the second verification method includes: Constructing a module verification sequencer in the preset verification environment and defining interface components; By means of the module verification sequencer, in the preset verification environment, the reference signal corresponding to each port in the current module is assigned to the interface component; Using the interface component, the reference signal corresponding to each port in the current module is configured to the corresponding port in a mandatory designated manner to update the coverage of the current module; S105, if the module complexity corresponding to the current module is greater than or equal to the first complexity threshold, and the verification environment complexity corresponding to the preset verification environment is greater than or equal to the second complexity threshold, then use a third verification method to update the coverage of the current module, wherein the preset verification environment corresponds to a checker; The use of the third verification method to update the coverage of the current module includes: Constructing a reference verification environment corresponding to the current module, wherein the reference verification environment includes the checker; The current module is verified under the reference verification environment to update the coverage of the current module.

2. The multi-level coverage collection system according to claim 1, characterized in that: The preset first condition is: the preset verification time length is greater than a preset verification time length threshold.

3. The multi-level coverage collection system according to claim 2, characterized in that: The preset verification time length corresponds to the verification incentive amount; Correspondingly, the preset first condition is: the preset verification time is greater than the preset verification time threshold, or the verification incentive quantity corresponding to the preset verification time is greater than the preset incentive quantity threshold.

4. The multi-level coverage collection system according to claim 1, characterized in that: The preset verification environment corresponds to a checker; The use of the third verification method to update the coverage of the current module includes: Initialize the temporary level K=2 and obtain the level corresponding to the current module; If the level corresponding to the current module is less than K, determine the temporary module to which the current module belongs, and the level corresponding to the temporary module is K; Constructing a temporary verification environment corresponding to the temporary module, wherein the temporary verification environment includes the checker; Verify the temporary module in the temporary verification environment to update the coverage rate of the current module, and record the temporary coverage rate corresponding to the current module under the temporary verification duration; If the temporary coverage rate is less than the coverage rate threshold and the temporary verification duration meets the second preset condition, update K = K + 1, and return to execute the step of determining the temporary module to which the current module belongs if the level corresponding to the current module is less than K.

5. The multi-level coverage collection system according to claim 4, characterized in that: The second preset condition is: The temporary verification duration is greater than the preset temporary duration threshold, where the temporary duration threshold corresponding to the temporary level k1 is greater than the temporary duration threshold corresponding to the temporary level k2, k1 < k2, and both k1 and k2 are integers within the range of [2, K].

Images