Hardware simulation test system

Abstract

The invention discloses a hardware simulation test system. The system comprises an upper computer; the lower computer is connected with the upper computer and used for being connected with the tested domain controller and conducting simulation testing on the tested domain controller; when the lower computer receives the trigger signals sent by the tested domain controller in the preset window period, it is considered that synchronization of the trigger signals is completed, and simulation data are requested to the upper computer; the upper computer responds to the request of the lower computer and sends simulation data to the lower computer so as to carry out simulation test on the tested domain controller; wherein the window period is the difference of the product of the total amount of data needing to be transmitted in the first sampling period and the second sampling period and the second sampling period, the first sampling period is the sampling period of the sensor corresponding to the simulation data, and the second sampling period is the sampling period of the lower computer. In this way, whether all paths of trigger signals are synchronous or not can be determined.

Description

Technical Field

[0001] The present application relates to the field of hardware simulation testing, and in particular to a hardware simulation testing system. Background Art

[0002] During the hardware-in-the-loop test, the lower computer, as a dedicated simulation hardware device, needs to start the transmission of simulation data according to the trigger signal sent by the ECU under test. However, when the ECU sends a trigger signal to the hardware device, it is limited by the connection of the physical interface, resulting in a time difference between the trigger data of each channel, and the hardware device cannot determine whether the trigger signals of each channel can be considered synchronized. If the time difference between the trigger signals of each channel is too large, the simulation data received by the hardware device will not accurately reflect the actual situation, resulting in distortion of the test results; if it is too small, it is easy to cause the normally transmitted trigger signal to be identified as not synchronized, and thus the test cannot be performed. Summary of the invention

[0003] The present application mainly provides a hardware simulation test system to solve the problem that it is impossible to determine whether the trigger signals of various channels are synchronized in the simulation test.

[0004] In order to solve the above technical problems, a technical solution adopted in the present application is: to provide a hardware simulation test system, including: an upper computer; a lower computer, connected to the upper computer, used to connect to the domain controller under test, and perform simulation test on the domain controller under test; when the lower computer receives various trigger signals sent by the domain controller under test within a preset window period, it is considered that the synchronization of each trigger signal is completed, and then requests simulation data from the upper computer; the upper computer responds to the request of the lower computer and sends simulation data to the lower computer to perform simulation test on the domain controller under test; wherein the window period is the difference between the total amount of data to be transmitted in the first sampling period and the second sampling period and the product of the second sampling period, the first sampling period is the sampling period of the sensor corresponding to the simulation data, and the second sampling period is the sampling period of the lower computer.

[0005] By setting the window period to determine whether the trigger signal is synchronized, it is ensured that the signals of each simulation test remain synchronized.

[0006] In some embodiments, the formula for calculating the window period is:

[0007]

[0008] Among them, t is the window period, f is the sampling frequency of the sensor corresponding to the simulation data, and f c is the sampling frequency of the lower computer, and D is the total amount of data that needs to be transmitted by the sensor corresponding to the simulation data within the second sampling period.

[0009] By calculating the simulation sampling frequency, the length of the window period can be adapted to the type of sensor being simulated, thereby making the synchronization determination of the trigger signal more reasonable.

[0010] In some embodiments, the sampling frequency of the lower computer is not less than twice the sampling frequency of the sensor corresponding to the simulation data.

[0011] In some embodiments, the sampling frequency of the lower computer is not less than the product of the sampling frequency of the sensor and the total amount of data, and not greater than the upper limit of the clock frequency of the lower computer interface.

[0012] In some embodiments, each path of the trigger signal corresponds to a path of simulation data, and each path of simulation data corresponds to two storage spaces in the lower computer. The lower computer requests each path of simulation data from the upper computer in response to the synchronization of each path of the trigger signal; the upper computer writes the simulation data into the two storage spaces corresponding to each path of simulation data in the lower computer in turn in response to the requests for each path of simulation data from the lower computer; the lower computer reads the simulation data in the storage space where the writing is completed from the two storage spaces in turn to output the simulation data to the device under test controller.

[0013] By using two storage spaces to write and read alternately to perform ping-pong transmission of simulation data between the upper computer and the lower computer, it is beneficial to reduce the data delay caused by data transmission between the upper computer and the lower computer.

[0014] In some embodiments, the upper computer determines the first storage space corresponding to each path of simulation data in response to the requests for each path of simulation data from the lower computer, and writes the simulation data into the first storage space and the second storage space in turn starting from the first storage space, and in response to the completion of writing in one of the first storage space and the second storage space, writes the simulation data into the other.

[0015] By specifying the storage space that is written first in the two storage spaces, the order in which the upper computer writes simulation data to the lower computer is determined.

[0016] In some embodiments, the lower computer reads the simulation data from the first storage space and the second storage space in turn starting from the first storage space in response to the completion of writing in the first storage space, and reads the simulation data stored in the other in response to the completion of reading in one of the first storage space and the second storage space.

[0017] By specifying the storage space that is written first in the two storage spaces, the order in which the lower computer reads simulation data from the storage space is determined.

[0018] In some embodiments, the slave computer is further configured to connect to the domain controller under test through a physical input / output interface and a real communication protocol.

[0019] In some embodiments, the slave computer also receives various trigger signals generated by the hardware simulation test system within a preset window period.

[0020] In some embodiments, if the slave computer does not receive all the trigger signals within the window period, the slave computer sends an error signal to the master computer to display an error warning message on the master computer.

[0021] The beneficial effects of this application are as follows: Different from the prior art, this application discloses a hardware simulation test system, including a master computer; a slave computer, connected to the master computer, for connecting to the domain controller under test and performing simulation tests on the domain controller under test; when the slave computer receives various trigger signals sent by the domain controller under test within a preset window period, it is considered that the synchronization of various trigger signals is completed, and then the slave computer requests simulation data from the master computer; the master computer responds to the request of the slave computer and sends simulation data to the slave computer to perform simulation tests on the domain controller under test; where the window period is the difference between the product of the total amount of data to be transmitted within the first sampling period and the second sampling period and the second sampling period, the first sampling period is the sampling period of the sensor corresponding to the simulation data, and the second sampling period is the sampling period of the slave computer, so that various trigger signals with similar arrival times are recognized as synchronized through the window period, avoiding the influence of delays caused by physical interfaces on the transmission of simulation data. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings, where:

[0023] Figure 1 is a schematic structural diagram of an embodiment of the hardware simulation test system provided by the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0024] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the protection scope of the present application.

[0025] The terms "first", "second", and "third" in the embodiments of the present application are only for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first", "second", and "third" may explicitly or implicitly include at least one of such features. In the description of the present application, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise specifically defined. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but optionally further includes unlisted steps or units, or optionally further includes other steps or units inherent to these processes, methods, products, or devices.

[0026] Reference to "embodiment" herein means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0027] Refer to Figure 1 , Figure 1 is a schematic structural diagram of an embodiment of a hardware simulation test system provided by the present application. The hardware simulation test system 100 includes:

[0028] A host computer 110, which usually uses a PC host and is responsible for controlling the slave computer 120. The tester configures simulation sensor data for testing on the host computer 110, including sensor type, data range, sampling frequency, etc. According to the configured simulation sensor data, the host computer 110 generates corresponding setting parameters, and these parameters will be used to control the simulation module on the slave computer 120.

[0029] The host computer 110 sends the setting parameters and test instructions to the slave computer 120 through a communication interface such as a serial port, Ethernet, etc.

[0030] A slave computer 120, connected to the host computer 110, is used to connect to the domain controller under test and perform simulation tests on the domain controller under test.

[0031] The slave computer 120 is a dedicated hardware test device, which is an intermediate device connecting the host computer 110 and the domain controller under test and is used to execute the instructions and data sent by the host computer 110. In the hardware simulation test, the slave computer 120 is responsible for simulating the external sensor input of the domain controller under test and collecting the response data of the domain controller under test.

[0032] Specifically, the lower computer 120 receives the set parameters and test instructions sent by the upper computer 110 through the communication interface. According to the received set parameters, the lower computer 120 simulates the external sensor inputs of the domain controller to be tested, such as images, temperature, pressure, speed, distance, etc. At the same time, the lower computer 120 collects the response data of the domain controller to be tested to the simulated sensor inputs, such as control signals, status information, etc.

[0033] If the lower computer 120 receives the trigger signals of each channel sent by the domain controller to be tested within the preset window period, it is considered that the synchronization of the trigger signals of each channel is completed, and then the lower computer 120 requests simulation data from the upper computer 110. In response to the request of the lower computer 120, the upper computer 110 sends set parameters to the lower computer 120 to perform a simulation test on the domain controller to be tested.

[0034] Among them, the window period is the difference between the product of the total amount of data to be transmitted within the first sampling period and the second sampling period and the second sampling period. The first sampling period is the sampling period of the sensor corresponding to the simulation data, and the second sampling period is the sampling period of the lower computer 120.

[0035] The simulation data is used to simulate the real environment or sensor devices. The external sensors are simulated to be connected to the domain controller to be tested through the simulation data, and the commands sent by the domain controller to be tested are executed or the sensing information of the feedback response is provided.

[0036] When the domain controller synchronously triggers multiple simulations, due to transmission delay, there will be some slight differences in the moments when the trigger signals are received by each channel of the lower computer 120. The window period is a time range used to allow a certain time deviation when the trigger signals are received by each channel. If the rising edges of the trigger signals are detected by each channel of the lower computer 120 within the window period, it is considered that these channels are synchronously triggered.

[0037] Specifically, on each device of the lower computer 120, a timer or interrupt is configured to detect the rising edge of the trigger signal. When the rising edge is detected, the current timestamp is recorded. The timestamps recorded by each channel are compared with the trigger window. If the timestamps of all channels are within the window period, it is considered that these channels are synchronously triggered.

[0038] Specifically, the formula for calculating the window period is:

[0039]

[0040] Among them, t is the window period, f is the sampling frequency of the sensor corresponding to the simulation data, f c is the sampling frequency of the lower computer 120, and D is the total amount of data to be transmitted within the second sampling period of the sensor corresponding to the simulation data.

[0041] Among them, the window period t is the additional time difference that the lower computer 120 can tolerate after considering the transmission delay before receiving the trigger signal and starting sampling, to ensure that sufficient data, i.e., the D data volume, can be received within the first complete sampling period Tc of the lower computer 120.

[0042] The total data volume D is determined according to the type of data transmitted and is a fixed value for each channel. For example, when a channel is used to transmit image data, the D corresponding to this channel represents the size of the image, such as 3840*2160 or 1920*1080, etc.

[0043] The sampling frequency f of the sensor refers to the number of times the real sensor simulated by the lower computer 120 actually collects data per unit time, which determines the fineness of the signal changes that the sensor can capture. The higher the sampling frequency, the more data points the sensor collects in the same time, and the stronger the ability to capture signal changes.

[0044] The sampling frequency f of the lower computer 120 c is the sampling frequency used by the lower computer 120 when restoring sensor data. If f c is lower than f, it will cause the loss of high-frequency components, thus affecting the accuracy of data restoration. An appropriate f c can ensure that the lower computer 120 can accurately restore sensor data and avoid unnecessary data processing burdens at the same time.

[0045] For example, the lower computer 120 conducts simulation tests based on an image sensor such as a camera. The actual sampling frequency of the camera is 30 frames of pictures transmitted per second, and the period for transmitting one frame of picture is about 33 ms. Then the period corresponding to one frame of picture is 33 ms. Set the sampling frequency fc of the lower computer 120 to 100 MHz, and the corresponding sampling period is 10 ns. At this time, it takes 10 ns to transmit a complete picture. The total picture data volume D is 1920*1080, then At this time, calculating the window period t is about 33 - 20.7 = 12.3 ms.

[0046] Among them, the sampling frequency of the lower computer 120 is not less than twice the sampling frequency of the sensor corresponding to the simulation data.

[0047] f c is the sampling frequency used by the lower computer 120 when restoring sensor data. To ensure the accurate restoration of data, f c must be high enough to satisfy the Nyquist sampling theorem. To satisfy the Nyquist sampling theorem, the sampling frequency f of the lower computer 120 c must be at least twice the sampling frequency f of the sensor.

[0048] Specifically, the sampling frequency of the lower computer 120 is not less than the product of the sampling frequency and the total amount of data of the sensor, and is not greater than the upper limit of the clock frequency of the interface of the lower computer 120.

[0049] Specifically, the sampling frequency f of the lower computer 120 c has a value range expressed as f limit ≥ f c ≥ f * D.

[0050] Among them, f limit is the upper limit of the clock frequency of the interface of the lower computer 120, which is obtained by restricting the interface rate of the lower computer 120. f c is the sampling frequency of the lower computer 120, f is the sampling frequency of the sensor corresponding to the simulation data, and D is the total amount of data that the sensor corresponding to the simulation data needs to transmit in the second sampling period.

[0051] f * D represents a minimum sampling frequency that the lower computer 120 needs to satisfy. For example, if f is 30 hz and the total amount of data D is the size of an image, which is 1920 * 1080, then the minimum sampling frequency f * D of the lower computer 120 is 1920 * 1080 * 30 hz = 62 MHz.

[0052] By comprehensively considering information such as the characteristics of sensor data, the capabilities and parameters of the lower computer 120, a suitable sampling frequency fc is selected, and this sampling frequency needs to satisfy the Nyquist sampling theorem to ensure that the lower computer 120 can accurately restore the sensor data.

[0053] Furthermore, each trigger signal corresponds to a path of simulation data, and each path of simulation data corresponds to two storage spaces in the lower computer 120. The lower computer 120 requests each path of simulation data from the upper computer 110 in response to the synchronization of each trigger signal.

[0054] The lower computer 120 sends requests for each path of simulation data to the upper computer 110 in response to the synchronization of each trigger signal. After receiving the request from the lower computer 120, the upper computer 110 writes the simulation data into the two storage spaces corresponding to each path of simulation data in the lower computer 120 in a ping-pong transmission manner. Ping-pong transmission is a commonly used data transmission technology that uses two buffers to alternately receive and send data, so as to realize continuous processing of data without interrupting data transmission.

[0055] The upper computer 110 writes the simulation data into the two storage spaces corresponding to each path of simulation data in the lower computer 120 in turn in response to the requests for each path of simulation data from the lower computer 120. The lower computer 120 reads the simulation data in the storage space that has completed writing in the two storage spaces in turn to output the simulation data to the device under test controller.

[0056] After receiving the simulation data sent by the host computer 110, the slave computer 120 alternately reads the simulation data that has been written in the two storage spaces. This ensures the continuity and real-time nature of the data. The slave computer 120 outputs the read simulation data to the device under test controller for simulating real environments or device behaviors.

[0057] Further, in response to the various simulation data requests of the slave computer 120, the host computer 110 determines the first storage space corresponding to each path of simulation data, and starts writing simulation data into the first storage space and the second storage space alternately from the first storage space, and in response to the completion of writing in one of the first storage space and the second storage space, writes simulation data into the other.

[0058] Based on the received request information, the host computer 110 determines the first storage space corresponding to each path of simulation data by looking up the internal data structure or mapping table, and the host computer 110 starts writing simulation data into the first storage space and the second storage space alternately from the first storage space, that is, while writing into the first storage space, the host computer 110 will prepare the next batch of simulation data, and immediately write into the second storage space after the writing in the first storage space is completed.

[0059] When the host computer 110 finishes writing a storage space, it sends a write completion notification to the slave computer 120. This notification usually contains the storage space identifier of the written data and possible other status information. After sending the write completion notification, the host computer 110 switches to another storage space to write the next batch of simulation data.

[0060] In response to the completion of writing in the first storage space, the slave computer 120 alternately reads the simulation data from the first storage space and the second storage space starting from the first storage space, and in response to the completion of reading in one of the first storage space and the second storage space, reads the simulation data stored in the other.

[0061] The slave computer 120 first waits for the host computer 110 to complete the writing of the first storage space by listening to the communication interface or receiving the write completion notification from the host computer 110. Once the host computer 110 completes the writing of the first storage space, the slave computer 120 immediately starts reading the simulation data from the first storage space. While the slave computer 120 reads the first storage space, it will continue to listen to the write completion notification from the host computer 110 to prepare to read data from the second storage space. When the host computer 110 completes the writing of the second storage space and sends a write completion notification to the slave computer 120, the slave computer 120 will switch to the second storage space to read data.

[0062] The above process is repeated between the host computer 110 and the slave computer 120 until the system receives a stop signal or completes the transmission of all simulation data.

[0063] For example, in the lower computer 120, two storage spaces are allocated for a data stream, which are respectively called storage space 0 and storage space 1; after the lower computer 120 confirms that the trigger signal is synchronized, it sends an event signal 0 to the upper computer 110; when the upper computer 110 receives the event signal 0, it writes simulation data to the storage space 0 of the lower computer 120. At the same time, the lower computer 120 retrieves the written simulation data from the storage space 1.

[0064] Similarly, if the upper computer 110 receives the event signal 1, it writes simulation data to the storage space 1 of the lower computer 120. At the same time, the lower computer 120 retrieves the written simulation data from the storage space 0.

[0065] The ping-pong transmission technology can make full use of the bandwidth of the communication interface and improve the efficiency of data transmission. By alternately reading the data in the two storage spaces, the real-time output of the simulation data can be ensured, meeting the real-time requirements of the DUT (Device Under Test) domain controller. At the same time, the alternating use of the two storage spaces can reduce the risk of data loss and improve the reliability of the system.

[0066] Optionally, the lower computer 120 is also used to connect to the DUT domain controller through the physical input / output interface and the real communication protocol.

[0067] The connection between the lower computer 120 and the DUT domain controller adopts the physical interfaces used by real peripherals, such as serial communication interfaces such as RS-232, RS-485, USB, etc., Ethernet interfaces, CAN bus interfaces, etc. These interfaces are consistent with the peripheral interfaces in the real environment, thus avoiding additional delays or errors introduced by interface mismatches.

[0068] In addition to the physical interface, the communication between the lower computer 120 and the DUT domain controller also follows the communication protocols used by real peripherals. These protocols may include, but are not limited to, industrial communication protocols such as Modbus, CANopen, EtherCAT, PROFINET, etc., as well as custom communication protocols. By following the real protocols, the lower computer 120 can accurately simulate the behavior of real peripherals and send the simulation data to the DUT domain controller in a manner that meets the protocol requirements.

[0069] By connecting using the interfaces and protocols of real peripherals, the lower computer 120 can reduce the sources of delay that do not match the real environment, avoid having a negative impact on the test results, and thus improve the accuracy and authenticity of the simulation environment. Connecting using the interfaces and protocols of real peripherals can also improve the credibility of the simulation environment. During the test, the DUT domain controller can perceive communication behaviors and data formats similar to those of real peripherals, thereby more accurately evaluating its performance and reliability in the real environment.

[0070] Optionally, the slave computer 120 also receives various trigger signals generated by the hardware simulation test system 100 within a preset window period.

[0071] If, during a simulation test process, the domain controller is not used to send a trigger signal to the slave computer 120 to indicate the start of simulation data transmission, the hardware simulation test system 100, such as the master computer 110, generates a general trigger signal to the slave computer 120 as an indication to start transmitting simulation data.

[0072] Optionally, the slave computer 120 also sends an error signal to the master computer 110 in response to not receiving all trigger signals within the window period, so as to display an error warning message on the master computer 110.

[0073] If the slave computer 120 fails to receive all expected trigger signals within the window period, an error signal is generated. This signal contains information about the missing trigger signals, such as the type, quantity, and possible timestamps of the missing signals. After receiving the error signal sent by the slave computer 120, the master computer 110 parses this signal and displays the corresponding error warning message. These messages are usually presented to the user in the form of text, graphics, or sound, so that the user can quickly identify and handle errors in the system.

[0074] Different from the prior art, the present application provides a hardware simulation test system 100. By setting a window period as the determination basis for trigger signal synchronization, the time error range for performing simulation data transmission can be accurately delimited to start the simulation test and ensure that the domain controller under test completely receives the simulation data transmitted by the slave computer 120. At the same time, the master computer 110 and the slave computer 120 transmit instructions and signals in a ping-pong transmission manner, making full use of the bandwidth of the communication interface, improving the data transmission efficiency, and eliminating the influence of data transmission delay from the master computer 110 to the slave computer 120 on the simulation link.

[0075] The above are only embodiments of the present application, and thus do not limit the patent scope of the present application. Any equivalent structural or equivalent process transformation made by using the content of the specification and drawings of the present application, or directly or indirectly applied to other related technical fields, shall be equally included in the patent protection scope of the present application.

Claims

1. A hardware simulation test system, characterized in that: include: Host computer; A lower computer, connected to the upper computer, used to connect to the domain controller under test and perform simulation test on the domain controller under test; When the lower computer receives the trigger signals sent by the domain controller under test within a preset window period, it is considered that the trigger signals are synchronized and then requests simulation data from the upper computer; the upper computer responds to the request of the lower computer and sends simulation data to the lower computer to perform a simulation test on the domain controller under test; wherein the window period is the difference between the total amount of data to be transmitted within the first sampling period and the second sampling period multiplied by the second sampling period, the first sampling period is the sampling period of the sensor corresponding to the simulation data, and the second sampling period is the sampling period of the lower computer.

2. The hardware simulation test system according to claim 1, characterized in that: The formula for calculating the window period is: Among them, t is the window period, f is the sampling frequency of the sensor corresponding to the simulation data, and f c is the sampling frequency of the lower computer, and D is the total amount of data that needs to be transmitted by the sensor corresponding to the simulation data within the second sampling period.

3. The hardware simulation test system according to claim 2, characterized in that: The sampling frequency of the lower computer is not less than twice the sampling frequency of the sensor corresponding to the simulation data.

4. The hardware simulation test system according to claim 3, characterized in that: The sampling frequency of the lower computer is not less than the product of the sampling frequency of the sensor and the total amount of data, and is not greater than the upper limit of the clock frequency of the lower computer interface.

5. The hardware simulation test system according to claim 1, characterized in that: Each of the trigger signals corresponds to one channel of simulation data, and each of the simulation data corresponds to two storage spaces in the lower computer. The lower computer requests each channel of simulation data from the upper computer in response to synchronization of each of the trigger signals; The upper computer responds to the simulation data requests of each channel of the lower computer, and writes the simulation data into two storage spaces corresponding to each channel of the simulation data in the lower computer in turn; The lower computer reads the simulation data of the storage spaces that have been written in the two storage spaces in turn, so as to output the simulation data to the domain controller under test.

6. The hardware simulation test system according to claim 5, characterized in that: The upper computer responds to the simulation data requests of each channel of the lower computer, determines the first storage space corresponding to each channel of the simulation data, and writes the simulation data to the first storage space and the second storage space alternately starting from the first storage space, and writes the simulation data to the other one in response to the completion of writing to one of the first storage space and the second storage space.

7. The hardware simulation test system according to claim 6, characterized in that: In response to completion of writing to the first storage space, the lower computer reads the simulation data from the first storage space and the second storage space alternately starting from the first storage space, and in response to completion of reading one of the first storage space and the second storage space, reads the simulation data stored in the other storage space.

8. The hardware simulation test system according to claim 1, characterized in that: The lower computer is also used to connect to the tested domain controller through a physical input and output interface and a real communication protocol.

9. The hardware simulation test system according to claim 1, characterized in that: The lower computer also receives the trigger signals generated by the hardware simulation test system within a preset window period.

10. The hardware simulation test system according to claim 1, characterized in that: In response to not receiving all of the trigger signals within the window period, the lower computer also sends an error signal to the upper computer, so as to display error warning information on the upper computer.

Images