Performance test system and method of memory access system, electronic equipment and storage medium

Abstract

The embodiment of the invention provides a performance test system and method of a memory access system, electronic equipment and a storage medium. The system comprises a configuration module, a test starting module and a universal verification methodology UVM memory access performance test platform, wherein the configuration module is used for configuring and forming a data file according to a test requirement of a user; the test starting module is used for acquiring the data file and generating a test case set according to the data file; and calling the UVM memory access performance test platform to construct a verification environment according to the test cases in the test case set and perform performance test on the memory access system, and the UVM memory access performance test platform is used for constructing a verification environment according to the test cases in the test case set, carrying out performance test on the memory access system and outputting a UVM test log.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a performance testing system and method for a memory access system, an electronic device, and a storage medium. Background Art

[0002] With the rapid development of the digital integrated circuit industry and the continuous advancement of ultra-large-scale integrated circuit technology, the complexity of SOC (System on Chip) design has increased day by day. Chip verification, as an important part of reliability assurance in the chip R&D stage, has become the focus of attention of more and more companies. At a time when products are rapidly iterating, the rate of R&D has become an important factor affecting product competitiveness. The time for chip verification accounts for about 70% of the time in the entire chip R&D cycle, and the memory access system is an important component of a chip, playing an important role in reading and writing transmission data, code, etc. If the performance test efficiency of the memory access system is improved, the efficiency of chip verification can be greatly improved.

[0003] However, in the current memory access system performance test, users are required to rewrite the entire verification system according to different scenarios, which results in low automation and verification efficiency and high development costs required for verification. Summary of the invention

[0004] The embodiments of the present application provide a performance testing system and method for a memory access system, an electronic device, and a storage medium, which can separate the configuration of scenario requirements from the test environment, eliminating the need for users to rewrite the performance testing system of the memory access system multiple times according to different scenarios, thereby improving the degree of automation and verification efficiency while reducing verification costs.

[0005] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0006] In a first aspect, an embodiment of the present application provides a performance test system for a memory access system, characterized in that it includes: a configuration module, a test startup module and a universal verification methodology UVM memory access performance test platform; wherein

[0007] The configuration module is used to configure and form a data file according to user test requirements, wherein the data file includes: at least one set of test data mode configuration information and at least one set of performance mode configuration information;

[0008] The test startup module is used to obtain the data file and generate a test case set according to the data file; and call the UVM memory access performance test platform to build a verification environment according to the test cases in the test case set and perform performance testing on the memory access system, wherein the test case set includes at least one test case, and one of the test cases includes a memory access system performance configuration determined based on a set of performance mode configuration information and a data mode determined based on a set of test data mode configuration information;

[0009] The UVM memory access performance test platform is used to build a verification environment according to the test cases in the test case set and perform performance testing on the memory access system, and output a UVM test log, wherein the UVM test log includes: memory access system performance configuration and corresponding memory access performance results.

[0010] In a second aspect, an embodiment of the present application provides a performance testing method for a memory access system, including:

[0011] The data file is configured according to the user's test requirements, wherein the data file includes: at least one set of test data mode configuration information and at least one set of performance mode configuration information;

[0012] The data file is obtained, and a test case set is generated according to the data file; and the UVM memory access performance test platform is called to build a verification environment according to the test cases in the test case set and perform a performance test on the memory access system; wherein the test case set includes at least one test case, and one of the test cases includes a memory access system performance configuration determined based on a set of performance mode configuration information and a data mode determined based on a set of test data mode configuration information; the UVM memory access performance test platform is used to build a verification environment according to the test cases in the test case set and perform a performance test on the memory access system, and output a UVM test log, wherein the UVM test log includes: memory access system performance configuration information and corresponding memory access performance results.

[0013] In a third aspect, an embodiment of the present application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the following method when executing the program:

[0014] The data file is configured according to the user's test requirements, wherein the data file includes: at least one set of test data mode configuration information and at least one set of performance mode configuration information;

[0015] The data file is obtained, and a test case set is generated according to the data file; and the UVM memory access performance test platform is called to build a verification environment according to the test cases in the test case set and perform a performance test on the memory access system; wherein the test case set includes at least one test case, and one of the test cases includes a memory access system performance configuration determined based on a set of performance mode configuration information and a data mode determined based on a set of test data mode configuration information; the UVM memory access performance test platform is used to build a verification environment according to the test cases in the test case set and perform a performance test on the memory access system, and output a UVM test log, wherein the UVM test log includes: memory access system performance configuration information and corresponding memory access performance results.

[0016] In a fourth aspect, an embodiment of the present application provides a non-transitory computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the following method is implemented:

[0017] The data file is configured according to the user's test requirements, wherein the data file includes: at least one set of test data mode configuration information and at least one set of performance mode configuration information;

[0018] The data file is obtained, and a test case set is generated according to the data file; and the UVM memory access performance test platform is called to build a verification environment according to the test cases in the test case set and perform a performance test on the memory access system; wherein the test case set includes at least one test case, and one of the test cases includes a memory access system performance configuration determined based on a set of performance mode configuration information and a data mode determined based on a set of test data mode configuration information; the UVM memory access performance test platform is used to build a verification environment according to the test cases in the test case set and perform a performance test on the memory access system, and output a UVM test log, wherein the UVM test log includes: memory access system performance configuration information and corresponding memory access performance results.

[0019] The embodiments of the present application provide a performance testing system and method for a memory access system, an electronic device, and a storage medium. A data file is formed by configuring according to user test requirements, and then the data file is converted into a test case set. The UVM memory access performance testing platform is called to build a verification environment according to the test cases in the test case set and to perform a performance test on the memory access system. This allows users to directly configure according to different scenarios without having to rewrite the performance testing system of the memory access system according to different scenarios. The automation level and portability of the platform can be improved, and the potential verification risks caused by user errors can be reduced, thereby improving the degree of automation and verification efficiency, while reducing verification costs.

[0020] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0022] Figure 1 A schematic diagram of the structure of a performance test system for a memory access system provided in an embodiment of the present application;

[0023] Figure 2 A schematic diagram of the structure of another performance testing system for a memory access system provided in an embodiment of the present application;

[0024] Figure 3 A schematic diagram of a test path of a performance test system for a memory access system provided in an embodiment of the present application;

[0025] Figure 4 A flowchart of a performance testing method for a memory access system provided in an embodiment of the present application;

[0026] Figure 5 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solution and advantages of the present application clearer, the technical solution of the present application will be clearly and completely described below in combination with the specific embodiments of the present application and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.

[0028] The technical solutions provided by various embodiments of the present application are described in detail below in conjunction with the accompanying drawings.

[0029] In the embodiments of the present application, words such as "first" and "second" are used to distinguish between identical or similar items with basically the same functions and effects. This is only for the purpose of clearly describing the technical solutions of the embodiments of the present application, and shall not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.

[0030] In the embodiments of the present application, “plurality” means two or more, and “at least one” means one or more, unless otherwise clearly defined.

[0031] The current mainstream storage system verification method requires the following steps: 1. Build a verification platform. 2. Write a test case to determine the stimulus to be sent. 3. Perform simulation to control the packet sender to send packets to the memory access system. 4. Use a monitor to detect the data in each interface or memory to verify that the data written and transmitted is correctly written and the data read and transmitted can obtain the correct result. However, in the current memory access system performance test, the entire verification system needs to be rewritten every time according to different scenarios, and the development cost required for verification is high and the verification efficiency is low. The degree of automation is low, and the entire verification environment needs to be written independently by the user, which will lead to high costs for writing, learning, and transplanting the verification environment. It is not only laborious and time-consuming to use and debug, but there may also be manual negligence, resulting in unexpected omissions. The costs of the entire verification cycle are relatively high.

[0032] Based on this, the embodiment of the present application provides a performance testing system for a memory access system, referring to Figure 1 As shown, the performance test system includes: a configuration module 101, a test start module 102 and a Universal Verification Methodology (UVM) memory access performance test platform 103. Among them,

[0033] The configuration module 101 is used to configure and form a data file according to user test requirements, wherein the data file includes: at least one set of test data mode configuration information and at least one set of performance mode configuration information.

[0034] The test start module 102 is used to obtain the data file and generate a test case set according to the data file; and call the UVM memory access performance test platform to build a verification environment according to the test cases in the test case set and perform performance testing on the memory access system, wherein the test case set includes at least one test case, and one of the test cases includes test data of a memory access system performance configuration determined based on a set of performance mode configuration information and a data mode determined based on a set of test data mode configuration information.

[0035] The UVM memory access performance test platform 103 is used to build a verification environment according to the test cases in the test case set and perform performance testing on the memory access system, and output a UVM test log, wherein the UVM test log includes: memory access system performance configuration and corresponding memory access performance results.

[0036] It should be understood that after receiving the test case transmitted by the test startup module, the UVM memory access performance test platform 103 can build a verification environment according to the test case, configure the memory access system for performance, and perform performance testing, and then output the memory access system performance configuration and memory access performance results corresponding to the test case. In general, the memory access performance results may include bandwidth information and delay information of valid data transmitted by the memory access system.

[0037] The embodiments of the present application provide a performance testing system and method for a memory access system, an electronic device, and a storage medium. A data file is formed by configuring according to user test requirements, and then the data file is converted into a test case set. The UVM memory access performance testing platform is called to build a verification environment according to the test cases in the test case set and to perform a performance test on the memory access system. This allows users to directly configure according to different scenarios without having to rewrite the performance testing system of the memory access system according to different scenarios. The automation level and portability of the platform can be improved, and the potential verification risks caused by user errors can be reduced, thereby improving the degree of automation and verification efficiency, while reducing verification costs.

[0038] Figure 2 A schematic diagram of the structure of another performance test system for a memory access system provided in an embodiment of the present application. Figure 2 As shown, the performance testing system may further include: a data acquisition processing module 104 .

[0039] The data collection and processing module 104 is used to parse the UVM test log to determine whether there is a problem with the memory access system, determine the memory access performance result, and output the optimal memory access performance result and the corresponding memory access system performance configuration.

[0040] In an embodiment of the present application, by parsing the UVM test log, determining whether there is a problem with the memory access system, determining the memory access performance result, and outputting the optimal memory access performance result and the corresponding memory access system performance configuration, the automation level and portability of the platform can be improved, and the potential verification risks caused by user errors can be reduced, thereby improving the degree of automation and verification efficiency, while reducing verification costs.

[0041] Furthermore, in the embodiment of the present application, the UVM memory access performance test platform 103 may include: a memory access system, a packet sender submodule and a monitor submodule.

[0042] The memory access system may refer to the memory access system in the prior art, such as the memory access system in the existing UVM memory access performance test platform.

[0043] The packet sender submodule is used to convert the test cases in the test case set generated by the test startup module 102 into ABMA protocol data packets, and to perform performance configuration on the memory access system through the ABMA interface of the memory access system to build a verification environment, and to perform performance testing on the memory access system.

[0044] The monitor submodule is used to monitor the ABMA protocol data packet through the ABMA interface and monitor the test operation result of the memory access system through the JEDEG interface of the memory access system to output the UVM test log.

[0045] Optionally, the packet sender submodule may further include:

[0046] The first packet sender is used to convert the memory access system performance configuration in the test case into an ABMA protocol data packet to perform performance configuration on the memory access system. Specifically, the first packet sender can configure at least one of the following performance parameters in the memory access system: port priority, data packet timeout duration, register bit width configuration, register access address, register access address selection range, etc.

[0047] A plurality of second packet senders are used to convert the data pattern in the test case into an ABMA protocol data packet and transmit it to the memory access system for traversal testing or orthogonal testing.

[0048] Optionally, the monitor submodule is specifically used for:

[0049] Monitor the AMBA interface and the JEDEG interface of the memory access system under different requirements through protocol configuration, bit width configuration and frequency configuration to obtain the time and data volume of data packets passing through each interface of the memory access system;

[0050] Determine the bandwidth and average delay of valid data according to the time and data volume of data packets passing through each interface of the memory access system;

[0051] The bandwidth and average delay of the valid data corresponding to each memory access system performance configuration are output to the UVM test log.

[0052] To facilitate understanding of the technical solution of the embodiment of the present application, Figure 3 Provide explanation. Figure 3 Schematic diagram of the test path of the performance test system of the memory access system provided by the embodiment of the present application. Figure 3 As shown, the UVM memory access performance test platform 300 may include: a memory access system 310, a first packet sender 320, a second packet sender 330 and a monitor 340. The memory access system 310 may include a memory controller 11, a memory 12 and a configuration register 13.

[0053] like Figure 3 As shown in the test path diagram, the method may include:

[0054] S301, configure data file.

[0055] In the embodiment of the present description, the test user of the memory access system can configure the data file according to the user's test requirements. The data file includes: at least one set of test data mode configuration information and at least one set of performance mode configuration information.

[0056] It should be understood that in an embodiment of the present application, the test user of the memory access system only needs to configure the data file according to the test requirements. The test user can configure the test data pattern (Data Pattern) configuration information and the performance mode configuration information of the memory access system in the data file according to the test requirements. One or more groups of test data pattern configuration information and one or more groups of performance mode configuration information of the memory access system can be configured in one data file. Among them, the memory access requirements of the memory access system can be abstracted into a data pattern to simulate the actual application scenario. A data pattern corresponds to an application scenario and is represented by a set of test data pattern configuration information. The performance configuration of the memory access system can be represented by a performance pattern, and a set of performance pattern configuration information is used to represent a performance pattern.

[0057] It should be understood that in the embodiments of the present application, application scenarios can be divided into two categories: conventional application scenarios and extreme application scenarios. Conventional application scenarios are generally some application scenarios that occur at a relatively high frequency. Extreme application scenarios are generally significantly different from conventional scenarios in one or several indicators, for example: a high-priority register port continuously sends data within a preset time and the amount of data sent is greater than the preset data amount threshold; the duration of continuous data transmission by the high-priority register port is greater than the preset duration threshold; the address span between the memory access addresses accessed by at least two adjacent data packets is greater than the preset address span threshold; the frequency of switching to send data between register ports is greater than the preset switching frequency threshold, and so on. Of course, it should be understood that in actual application scenarios, extreme application scenarios are not limited to the above-mentioned contents, and there may be other application scenarios, which are not limited to the embodiments of the present application.

[0058] Of course, it should be understood that the test data mode configuration information in the data file and the performance mode configuration information of the memory access system can be a one-to-one relationship, a one-to-many relationship, or a many-to-many relationship, and the embodiments of the present application do not limit this. For example, the test data mode configuration information D1 can correspond to the performance mode configuration information P1, the test data mode configuration information D2 can correspond to the performance mode configuration information P2 and P3, the test data mode configuration information D3 and D4 can correspond to the performance mode configuration information P3 and P4, and so on.

[0059] In addition, other parameters may be configured in the data file, for example, a memory access address corresponding to the memory access system performance configuration may be configured, etc. This embodiment of the application does not limit this.

[0060] To facilitate understanding of the configuration of the data file, the register configuration of the memory access system is used as an example for explanation. Assuming that the memory access system to be tested uses a 32-bit register, the user only needs to configure it as a 32-bit register in the attribute configuration corresponding to the register in the data file, and the memory access system can be configured as a 32-bit register memory access system in subsequent configuration operations. In addition, it should be understood that the data file can use a variety of data formats, and the embodiments of the present application are not limited to this. For example, the data file can be in txt format or ods format, etc.

[0061] The above performance configuration attributes can be configured by the test user in the data file according to the relevant configuration of the configuration register. For example, the performance configuration attribute can be a port priority or a packet timeout duration, a register bit width configuration, etc. Of course, it can also be other performance configuration attributes, which will not be repeated here. The memory access address corresponding to the above performance configuration attribute includes a register address and an optional range.

[0062] S302, start the test script.

[0063] In the embodiment of the present application, the data file can be obtained through the test script, and a test case set can be generated according to the data file; and the UVM memory access performance test platform 300 is called to build a verification environment according to the test cases in the test case set and perform performance testing on the memory access system 310. It should be understood that in the embodiment of the present application, the test script can use the following scripting languages ​​to implement its functions: Python language, Perl language, Ruby language, etc.

[0064] It should be understood that in step S302 , the test script needs to pass the register configuration information and the data mode to the UVM memory access performance test platform 300 , so as to construct a verification environment and perform performance testing on the UVM memory access performance test platform 300 .

[0065] In an embodiment of the present application, the test script first needs to obtain a data file and parse the data file to obtain the at least one set of test data pattern configuration information and the at least one set of performance pattern configuration information, and then construct a test case set based on the at least one set of test data pattern configuration information and the at least one set of performance pattern configuration information. The test case set includes at least one test case, and each test case in the test case set includes a memory access system performance configuration determined based on a set of performance pattern configuration information and a data pattern determined based on a set of test data pattern configuration information.

[0066] It should be understood that in the embodiment of the present application, the test case set includes a set of test cases that need to be used in the performance test, and may include a test case constructed by a set of test data pattern configuration information and a set of performance pattern configuration information, may include a test case constructed by a set of test data pattern configuration information and multiple sets of performance pattern configuration information, may include a test case constructed by multiple sets of test data pattern configuration information and a set of performance pattern configuration information, and may also include a test case constructed by multiple sets of test data pattern configuration information and multiple sets of performance pattern configuration information. It should be understood that in traditional test cases, a testcase can only execute a set of Pattern configuration information under a set of register configurations. In the embodiment of the present application, a test case set including at least one set of pattern configurations and at least one set of register configurations can be automatically generated by a script. When the number of testcases in the test case set is greater than 1, the above-mentioned test case set may also be referred to as a regression test stimulus set, the above-mentioned performance test may also be referred to as a regression simulation test, and the above-mentioned UVM test log may also be referred to as a regression log.

[0067] It should be understood that a performance test can be performed on the memory access system using one test case. If the test case set includes multiple test cases, multiple test cases can be used to perform multiple performance tests. Each time a performance test is performed, the UVM memory access performance test platform can output a UVM test log; or, after all performance tests are completed, the UVM memory access performance test platform outputs all UVM test logs.

[0068] Of course, it should be understood that at least one test case in the above test case set generally includes at least one conventional test case corresponding to a conventional application scenario and at least one extreme test case corresponding to an extreme application scenario. Optionally, the extreme application scenario may include an application scenario corresponding to at least one of the following data modes:

[0069] The high priority register port continuously sends data within a preset time and the amount of data sent is greater than a preset data amount threshold;

[0070] The duration of continuous data transmission by the high priority register port is greater than the preset duration threshold;

[0071] The address span between the memory access addresses accessed by at least two adjacent data packets is greater than a preset address span threshold;

[0072] The frequency of switching data between register ports is greater than a preset switching frequency threshold.

[0073] After the test script passes the test case to the UVM memory access performance test platform 300, the UVM memory access performance test platform 300 activates the first packet sender and the second packet sender respectively according to the received test case. Figure 3 In the process, multiple second packet senders simulate the memory access behavior of the SoC master, and the first packet sender configures various related configurations of the memory access system, such as the priority of the port and the length of the data packet timeout. Figure 3 In order to distinguish various paths, the path through which the packet sender simulates the interaction between the master and the memory access system is represented by a bold solid line with double arrows, the related paths of the test startup module and the data acquisition and processing module are represented by a solid line with a single arrow, and other paths that do not occupy simulation time are represented by dotted lines with arrows.

[0074] The first packet transmitter configures the memory access system according to the memory access system performance configuration in the test case. The first packet transmitter converts the data packet carrying the memory access system performance configuration in the test case into a data packet of the Advanced Microcontroller Bus Architecture (AMBA) protocol, and sends it to the memory access system 310 for configuration through the configuration register in the memory access system 310.

[0075] The second packet sender performs a performance test on the memory access system according to the data pattern in the test case. The second data packet converts the data packet carrying the data pattern in the test case into a data packet of the AMBA protocol and sends it to the memory access system 310 for performance testing, which may include traversal testing, orthogonal testing, etc.

[0076] After the test script passes the test case to the UVM memory access performance test platform 300 for performance testing, the monitor 340 in the UVM memory access performance test platform 300 monitors the performance test process to output a UVM test log. In an embodiment of the present application, the UVM test log may include: memory access system performance configuration information and corresponding memory access performance results.

[0077] Memory access system performance configuration information, such as various configuration parameters of registers in the memory access system, etc. Memory access performance results may include the bandwidth and average latency of effective data of the memory access system. In practical applications, memory access performance results often need to consider the average bandwidth and average latency of the memory access system. These two indicators reflect the average time and average rate required to write or read memory from the protocol interface end of the memory controller of the memory access system, such as the AMBA protocol interface end, to the memory interface end, such as the JEDEC (Joint Electron Device Engineering Council) interface end, which can serve as an important reflection of the performance of the memory access system.

[0078] In addition, the monitor 340 can monitor the AMBA interface and JEDEG interface of the memory access system under different requirements through protocol configuration, bit width configuration and frequency configuration to obtain the time and data volume of the data packet passing through each interface of the memory access system; determine the bandwidth and average delay of the valid data according to the time and data volume of the data packet passing through each interface of the memory access system; output the bandwidth and average delay of the valid data corresponding to each memory access system performance configuration to the UVM test log. Of course, it should be understood that the monitor can also monitor whether there are bugs or risks in the memory access system itself.

[0079] S303, data collection and processing.

[0080] In an embodiment of the present application, the UVM test log can be parsed by a data acquisition script to determine whether there is a problem with the memory access system, determine the memory access performance result, and output the optimal memory access performance result and the corresponding memory access system performance configuration.

[0081] When determining whether there is a problem with the memory access system, the main focus is on determining whether there is a bug or risk in the memory access system.

[0082] When determining the memory access performance results, it is necessary to determine whether the latency and bandwidth in various situations meet user requirements. In particular, it is necessary to determine whether the latency and bandwidth of the test cases corresponding to extreme application scenarios meet user requirements.

[0083] In addition, the data collection script can also output the memory access performance configuration that can theoretically achieve the best delay and bandwidth performance, as well as the bandwidth and latency corresponding to the optimal memory access performance configuration, by comparing various memory access performance configurations and the corresponding bandwidth and latency.

[0084] It should be understood that if the bandwidth and latency corresponding to the above-mentioned optimal memory access performance configuration meet user requirements, the bandwidth and latency corresponding to the optimal memory access performance configuration can be output to the back-end or other relevant departments of the chip design; if it does not meet user requirements, it is necessary to optimize it synchronously and repeat the above process after optimization.

[0085] The following is an illustration using a specific example.

[0086] In a certain Soc memory access system, there are 8 hosts (masters) that need to access the memory. Each master corresponds to an IP address, and each master has a set of corresponding AMBA protocol interfaces in the memory access system. The user's requirements are: confirm the correctness of the Soc memory access system, confirm that the memory access system can meet the average delay and average bandwidth requirements under all configurations, and output a set of theoretically optimal configurations for average delay and average bandwidth performance.

[0087] The performance test system of the memory access system provided in the embodiment of the present application is used for testing, and its workflow includes:

[0088] Step 1: Determine the memory access requirements of the eight masters based on their own information and abstract them into test data mode configuration information.

[0089] Step 2, consider an extreme case where there is data of a lower priority port in the cache area while a higher priority port continuously sends a large amount of data, and abstract the extreme case into extreme data mode configuration information.

[0090] Step 3, based on the actual register design, extracts sixteen performance configuration attributes related to memory access performance, namely the priorities of eight ports and the duration of the data packet timeout of eight ports, and sets the register address and optional range of each configuration attribute according to the register address description document of the memory access system.

[0091] Step 4: Call the test startup script and specify the data files generated in the first three steps to be processed.

[0092] Step 5, the test startup script will automatically generate a regression test stimulus set (i.e., a test case set), and control the UVM memory access performance test platform to automatically perform regression simulation (i.e., performance testing); after all simulations are completed, the UVM test log will be output.

[0093] Step 6: The data collection script collects information in the UVM test log and outputs the overall regression results: whether there is a bug in the memory access system, whether the memory access performance of each data mode meets the requirements, and if the requirements are met, output the theoretically optimal memory access performance data and controller configuration.

[0094] Step 7: Obtain the corresponding results based on the log output by the data collection script to confirm whether the storage access system meets the requirements.

[0095] Of course, it should be understood that the aforementioned steps 1-7 are merely illustrative, and in actual applications, some of the steps may be added, deleted, or combined, or the order of the steps may be adjusted, and the embodiments of the present application are not limited to this.

[0096] Figure 4 1 is a flow chart of a performance test method for a memory access system according to an embodiment of the present application. Figure 4 As shown, the performance testing method may include:

[0097] S401, configuring and forming a data file according to user test requirements.

[0098] Wherein, the data file includes: at least one set of test data mode configuration information and at least one set of performance mode configuration information.

[0099] S402, obtaining the data file, and generating a test case set according to the data file; and calling the UVM memory access performance test platform to build a verification environment according to the test cases in the test case set and perform performance testing on the memory access system.

[0100] Among them, the test case set includes at least one test case, one of the test cases includes a memory access system performance configuration determined based on a set of performance mode configuration information and a data mode determined based on a set of test data mode configuration information; the UVM memory access performance test platform is used to build a verification environment according to the test cases in the test case set and perform performance testing on the memory access system, and output a UVM test log, and the UVM test log includes: memory access system performance configuration information and corresponding memory access performance results.

[0101] Alternatively, if Figure 4 As shown, the test method may also include:

[0102] S403, parsing the UVM test log to determine whether there is a problem with the memory access system, and determining a memory access performance result, and outputting an optimal memory access performance result and a corresponding memory access system performance configuration.

[0103] Figure 4 The specific implementation of each step in the embodiment shown can be referred to Figure 1 , Figure 2 The specific implementation of the corresponding modules in the embodiment shown, or refer to Figure 3 The specific implementation of the corresponding steps S301, S302 and S303 in the illustrated embodiment will not be described in detail in the embodiment of the present application.

[0104] Figure 5 This is a schematic diagram of the structure of an electronic device provided in one embodiment of this specification, see Figure 5 , the electronic device includes a processor, an internal bus, a network interface, a memory and a non-volatile memory, and of course may also include hardware required for other services. The processor reads the corresponding computer program from the non-volatile memory into the memory and then runs it, forming a performance test device or performance test system for the memory access system at the logical level. Of course, in addition to the software implementation method, this specification does not exclude other implementation methods, such as logic devices or a combination of software and hardware, etc., that is to say, the execution subject of the following processing flow is not limited to each logic unit, but can also be hardware or logic devices.

[0105] The network interface, processor and memory can be connected to each other through a bus system. The bus can be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 5 Only one bidirectional arrow is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0106] The memory is used to store programs. Specifically, the program may include program code, and the program code includes computer operation instructions. The memory may include read-only memory and random access memory, and provide instructions and data to the processor. The memory may include high-speed random access memory (RAM), and may also include non-volatile memory (non-volatile memory), such as at least one disk storage.

[0107] The processor is used to execute the program stored in the memory, and specifically performs the following steps:

[0108] The data file is configured according to the user's test requirements, wherein the data file includes: at least one set of test data mode configuration information and at least one set of performance mode configuration information;

[0109] The data file is obtained, and a test case set is generated according to the data file; and the UVM memory access performance test platform is called to build a verification environment according to the test cases in the test case set and perform a performance test on the memory access system; wherein the test case set includes at least one test case, and one of the test cases includes a memory access system performance configuration determined based on a set of performance mode configuration information and a data mode determined based on a set of test data mode configuration information; the UVM memory access performance test platform is used to build a verification environment according to the test cases in the test case set and perform a performance test on the memory access system, and output a UVM test log, wherein the UVM test log includes: memory access system performance configuration information and corresponding memory access performance results.

[0110] Optionally, the processor may further perform the following steps:

[0111] The UVM test log is parsed to determine whether there is a problem with the memory access system, and to determine a memory access performance result, and to output an optimal memory access performance result and a corresponding memory access system performance configuration.

[0112] The above application Figure 3 , 4 The performance test method disclosed in the illustrated embodiment can be applied to a processor or implemented by a processor. The processor may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by an integrated logic circuit of hardware in the processor or an instruction in the form of software. The above processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The methods, steps and logic block diagrams disclosed in the embodiments of this specification can be implemented or executed. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc. The steps of the method disclosed in the embodiments of this specification can be directly embodied as a hardware decoding processor for execution, or a combination of hardware and software modules in the decoding processor for execution. The software module can be located in a storage medium mature in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.

[0113] The present application further provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the above Figure 3 , Figure 4 Performance testing method shown.

[0114] It should be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of further restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0115] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0116] The term "one embodiment", "embodiment" or "one or more embodiments" herein means that a particular feature, structure or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present application. In addition, please note that the examples of the term "in one embodiment" here do not necessarily all refer to the same embodiment.

[0117] In the specification provided herein, a large number of specific details are described. However, it is understood that the embodiments of the present application can be practiced without these specific details. In some examples, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this specification. Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application is described in detail with reference to the aforementioned embodiments, a person of ordinary skill in the art should understand that the technical solutions described in the aforementioned embodiments can still be modified, or some of the technical features can be replaced by equivalents; and these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application.

Claims

1. A performance test system for a memory access system, characterized in that: include: Configuration module, test startup module and universal verification methodology UVM memory access performance test platform; in The configuration module is used to configure and form a data file according to user test requirements, wherein the data file includes: at least one set of test data mode configuration information and at least one set of performance mode configuration information; The test startup module is used to obtain the data file and generate a test case set according to the data file; and call the UVM memory access performance test platform to build a verification environment according to the test cases in the test case set and perform performance testing on the memory access system, wherein the test case set includes at least one test case, and one of the test cases includes a memory access system performance configuration determined based on a set of performance mode configuration information and a data mode determined based on a set of test data mode configuration information; The UVM memory access performance test platform is used to build a verification environment according to the test cases in the test case set and perform performance testing on the memory access system, and output a UVM test log, wherein the UVM test log includes: memory access system performance configuration and corresponding memory access performance results.

2. The performance testing system according to claim 1, characterized in that: The performance testing system also includes: The data acquisition and processing module is used to parse the UVM test log to determine whether there is a problem with the memory access system, determine the memory access performance result, and output the optimal memory access performance result and the corresponding memory access system performance configuration.

3. The performance testing system according to claim 1 or 2, characterized in that: The memory access performance result includes bandwidth information and delay information of valid data transmitted by the memory access system.

4. The performance testing system according to claim 1, characterized in that: The UVM memory access performance test platform includes: Access system; A packet sender submodule, used for converting the test cases in the test case set into ABMA protocol data packets, and performing performance configuration on the memory access system through the ABMA interface of the memory access system to build a verification environment, and performing performance testing on the memory access system; The monitor submodule is used to monitor the ABMA protocol data packet through the ABMA interface and monitor the test operation result of the memory access system through the JEDEG interface of the memory access system to output the UVM test log.

5. The performance testing system according to claim 4, characterized in that: The packet sender submodule includes: A first packet sender, used for converting the memory access system performance configuration in the test case into an ABMA protocol data packet to perform performance configuration on the memory access system; A plurality of second packet senders are used to convert the data pattern in the test case into an ABMA protocol data packet and transmit it to the memory access system for traversal testing or orthogonal testing.

6. The performance testing system according to claim 5, characterized in that: The first packet sender is specifically used to configure at least one of the following performance parameters in the memory access system: Port priority, data packet timeout, register width configuration, and register address.

7. The performance testing system according to claim 4, characterized in that: The monitor submodule is specifically used for: Monitor the AMBA interface and the JEDEG interface of the memory access system under different requirements through protocol configuration, bit width configuration and frequency configuration to obtain the time and data volume of data packets passing through each interface of the memory access system; Determine the bandwidth and average delay of valid data according to the time and data volume of data packets passing through each interface of the memory access system; The bandwidth and average delay of the valid data corresponding to each memory access system performance configuration are output to the UVM test log.

8. The performance testing system according to claim 1, characterized in that: The at least one test case includes a test case corresponding to an extreme application scenario, and the extreme application scenario includes at least one of the following data modes: The high priority register port continuously sends data within a preset time and the amount of data sent is greater than a preset data amount threshold; The duration of continuous data transmission by the high priority register port is greater than the preset duration threshold; The address span between the memory access addresses accessed by at least two adjacent data packets is greater than a preset address span threshold; The frequency of switching data between register ports is greater than a preset switching frequency threshold.

9. A system testing method for a memory access system, characterized in that: include: The data file is configured according to the user's test requirements, wherein the data file includes: at least one set of test data mode configuration information and at least one set of performance mode configuration information; The data file is obtained, and a test case set is generated according to the data file; and the UVM memory access performance test platform is called to build a verification environment according to the test cases in the test case set and perform a performance test on the memory access system; wherein the test case set includes at least one test case, and one of the test cases includes a memory access system performance configuration determined based on a set of performance mode configuration information and a data mode determined based on a set of test data mode configuration information; the UVM memory access performance test platform is used to build a verification environment according to the test cases in the test case set and perform a performance test on the memory access system, and output a UVM test log, wherein the UVM test log includes: memory access system performance configuration information and corresponding memory access performance results.

10. The method according to claim 9, characterized in that Also includes: The UVM test log is parsed to determine whether there is a problem with the memory access system, and to determine a memory access performance result, and to output an optimal memory access performance result and a corresponding memory access system performance configuration.

11. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the performance testing method as described in any one of claims 9 to 10 is implemented.

12. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the performance testing method according to any one of claims 9 to 10 is implemented.

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