An FPGA-based SFP and RJ45 data interaction device

Abstract

An FPGA-based SFP and RJ45 data interaction device is disclosed. The FPGA chip is connected to the SFP interface via multiple optical ports and to the RJ45 interface via multiple PHY chips on an FMC daughterboard for data interaction. The FMC daughterboard is connected to the FPGA development board via multi-pin I / O expansion ports, where the FPGA chip processes the received data. The FPGA chip's internal logic design implements data flow control, data protocol conversion, and data synchronization control, ensuring that data received from both the SFP and RJ45 interfaces can be transmitted correctly to the other end, thus achieving data interconnection between the two interfaces. This allows devices connected to both interfaces to communicate in real-time at gigabit speeds via Ethernet. Furthermore, LED indicators can be used to indicate the system's operating status. This data interaction device enables hardware-programmable data interaction between the SFP and RJ45 interfaces, offering significant advantages in practicality, real-time performance, and flexibility.

Description

Technical Field

[0001] This invention relates to the field of high-speed communication, and more particularly to an FPGA-based SFP and RJ45 data interaction device. Background Technology

[0002] Ethernet is now widely used, with a large amount of Ethernet data communication occurring in various production and daily life scenarios. Most Ethernet devices use RJ45 interfaces via twisted-pair cables for data exchange. Furthermore, with the development of optical communication, more and more systems are using SFP interfaces on optical fibers for Ethernet data transmission. These two different interfaces use different data transmission protocols, have different data formats, and different numbers of interface signals, making direct communication between them impossible.

[0003] Currently, to solve this problem, the common approach is to simultaneously equip communication devices with both RJ45 and SFP interfaces to enable communication with devices using different interfaces. However, this method increases the number of I / O interfaces, raising system complexity and redundancy. Furthermore, the increased variety and number of interfaces significantly increases system setup costs and difficulty, while also increasing the size and footprint of the equipment.

[0004] Secondly, it cannot be guaranteed that all communication devices have both types of interfaces. In particular, most older Ethernet communication devices do not have SFP interfaces, making it impossible for them to conduct normal Ethernet communication with SFP interface devices.

[0005] Furthermore, while communication devices with both interfaces can communicate over Ethernet via both twisted-pair RJ45 and fiber optic SFP interfaces, there is a possibility that one of the communication interfaces may not be effectively connected during Ethernet communication. This idleness of the communication interface can lead to unexpected malfunctions, thereby affecting the operation of the entire communication system.

[0006] Therefore, there is an urgent need for a flexible and easy-to-use hardware device and logic design for SFP and RJ45 data interaction. Summary of the Invention

[0007] This invention provides an FPGA-based SFP and RJ45 data interaction device to solve the problems of different interfaces not being able to communicate normally and interface redundancy in the prior art.

[0008] To achieve the above objectives, the present invention adopts the following technical solution:

[0009] An FPGA-based SFP and RJ45 data interaction device includes an FMC daughterboard with an RJ45 interface, an FPGA development board with an FPGA chip and an SFP interface; wherein, the FPGA chip is connected to the SFP interface through multiple optical ports and to the RJ45 interface through multiple physical layer chips (PHY) on the FMC daughterboard for data interaction; the FMC daughterboard is connected to the FPGA development board through a multi-pin I / O expansion port, and the FPGA chip processes the received data.

[0010] Specifically, data flow control, data protocol conversion, and data synchronization control are implemented through the internal logic design of the FPGA chip. The data flow control ensures that data from different interfaces reaches another interface in an orderly manner for data transmission. The data protocol conversion converts data of different formats to be transmitted from the application to the interface into a data format supported by the interface for interface matching. The data synchronization control synchronizes data from different interfaces for effective transmission.

[0011] Furthermore, it also includes an LED indicator module to display whether the logic circuit is working properly, providing fault indication.

[0012] Furthermore, both the RJ45 and SFP interfaces are 4-channel interfaces, with each channel corresponding to the other for data exchange.

[0013] Furthermore, the data flow control specifically includes: controlling the direction of data flow inside the FPGA development board, so that the received data from the SFP interface on the FPGA development board is transmitted to the transmitter of the corresponding RJ45 interface on the FPGA development board; and so that the received data from the RJ45 interface on the FMC daughterboard is transmitted to the transmitter of the corresponding SFP interface on the FPGA development board.

[0014] Furthermore, the logic design includes RGMII and GMII modules, and GMII and GTX modules; the RGMII and GMII modules perform conversion between RGMII format data and GMII format data through single-sided and double-sided edge sampling of data, and transmit the processed data signals to their respective positions for further circuit processing; the GMII and GTX modules perform conversion between GMII format data and GTX format data through high-speed parallel-to-serial / serial-to-parallel conversion and 4B / 5B encoding and decoding, and transmit the processed data signals to their respective positions for further circuit processing.

[0015] Furthermore, the logic design includes a clock module for generating a system reference clock.

[0016] Furthermore, the logic design includes a FIFO module; the FIFO module performs clock synchronization between the two interfaces through read and write operations of the foreign domain clock, ensuring the synchronization of the data to be transmitted and the transmission clock at both interfaces.

[0017] Furthermore, the data protocol conversion specifically includes: converting RGMII format data from the RJ45 interface to GMII format data by converting it from dual-edge sampling to single-edge sampling; then converting the obtained GMII format data to GTX format data by parallel-to-serial conversion and 8B / 10B encoding, so that the SFP interface on the FPGA development board can transmit the data; and converting GTX format data from the SFP interface to GMII format data by serial-to-parallel conversion and 10B / 8B decoding; then converting the obtained GMII format data to RGMII format data by single-edge sampling to dual-edge sampling, so that the RJ45 interface on the FPGA development board can transmit the data.

[0018] Furthermore, the data synchronization control specifically includes: synchronizing asynchronous data from the SFP interface and the RJ45 interface respectively. For the data to be transmitted from the RJ45 interface on the FMC daughterboard, the data source is the SFP receiving interface on the FPGA development board. Therefore, the SFP synchronization clock is used for data transmission to achieve data synchronization of the RJ45 interface. For the data to be transmitted from the SFP interface on the FPGA development board, the data source is the RJ45 receiving interface on the FMC daughterboard. The SFP uses a channel-bound clock and a FIFO read / write module. Data is read in using the RJ45 interface synchronization clock and written out using the SFP channel-bound clock synchronization clock to achieve data clock synchronization. The written data is sent from the SFP transmitting interface on the FPGA development board using the SFP channel-bound clock to achieve data synchronization of the SFP interface.

[0019] A data interaction method using the FPGA-based SFP and RJ45 data interaction device, comprising: implementing data flow control using the internal logic design of the FPGA chip to transfer data from the SFP interface to the corresponding RJ45 interface, and transferring data from the RJ45 interface to the corresponding SFP interface; implementing data protocol conversion using the internal logic design of the FPGA chip to convert data to be transmitted in different formats from the application and the interface to be transmitted into a data format supported by the interface for interface matching; and implementing data synchronization control using the internal logic design of the FPGA chip to synchronize data from different interface sources for effective transmission.

[0020] In some embodiments, this invention provides an FPGA-based hardware device for SFP and RJ45 data interaction, comprising an FMC daughterboard containing four PHY chips, four SFP interfaces, and an FPGA development board. The FMC daughterboard is connected to the FPGA development board via a 40-pin I / O expansion port. The other end of the PHY chips has four RJ45 interfaces for connecting Ethernet devices with RJ45 interfaces. The SFP interfaces are integrated into the FPGA development board and are used to connect Ethernet devices with SFP interfaces. Based on this hardware, the SFP interface devices and RJ45 interface devices are hardware-connected via the FPGA development board.

[0021] Optionally, the FPGA development board is model KINTEX-7AX7325B, which provides a 40-pin I / O expansion port, 4 SFP interfaces and 4 LED indicators.

[0022] Optionally, the PHY chip is model FL9031, which provides 4 PHY chips and 4 RJ45 interfaces.

[0023] In some embodiments, the FPGA-based SFP and RJ45 data interaction logic design includes a data flow control module, a data protocol conversion module, a clock synchronization module, and an LED indicator module.

[0024] The data flow control module is used to control the direction of data flow inside the FPGA development board, so that the received data from the SFP interface on the FPGA development board is transmitted to the transmitter of the corresponding RJ45 interface on the FPGA development board; and so that the received data from the RJ45 interface on the FMC daughterboard is transmitted to the transmitter of the corresponding SFP interface on the FPGA development board.

[0025] The data protocol conversion module is used to perform protocol conversion on data from different interface types. The logical process is as follows: RGMII format data from the RJ45 interface is converted to GMII format data by dual-edge sampling to single-edge sampling, and then the obtained GMII format data is converted to GTX format data by parallel-to-serial conversion and 8B / 10B encoding, so that the SFP interface on the FPGA development board can transmit this data; GTX format data from the SFP interface is converted to GMII format data by serial-to-parallel conversion and 10B / 8B decoding, and then the obtained GMII format data is converted to RGMII format data by single-edge sampling to dual-edge sampling, so that the RJ45 interface on the FPGA development board can transmit this data.

[0026] The clock synchronization module is used to synchronize asynchronous data from the SFP interface and the RJ45 interface respectively. For the data to be transmitted from the RJ45 interface on the FMC daughterboard, the data source is the SFP receiving interface on the FPGA development board. Therefore, the SFP synchronous clock is used for data transmission to achieve data synchronization of the RJ45 interface. For the data to be transmitted from the SFP interface on the FPGA development board, the data source is the RJ45 receiving interface on the FMC daughterboard. Since the SFP uses a channel-bound clock, a FIFO read / write module is used to read data using the RJ45 interface synchronous clock and write data using the SFP channel-bound clock synchronous clock to achieve data clock synchronization. The SFP transmitting interface on the FPGA development board uses the SFP channel-bound clock to send the written data to achieve data synchronization of the SFP interface.

[0027] The LED indicator module is used to indicate whether the current pair of RJ45 interfaces and SFP interfaces on the FPGA development board are working properly. If the current pair of RJ45 interfaces and SFP interfaces can communicate normally via Gigabit Ethernet, and the data flow control module, data protocol conversion module, and clock synchronization module are all functioning normally, then the LED will light up.

[0028] In some embodiments, a method for using an FPGA-based SFP and RJ45 data interaction device is also provided, comprising the following steps:

[0029] Step 1: Connect the communication device with the RJ45 interface to the RJ45 interface on the FMC daughterboard via a twisted pair cable; Step 2: Connect the communication device with the SFP interface to the corresponding SFP interface on the FPGA development board via an optical fiber; Step 3: The device receives signals from both interfaces, transmits and sends signals to each other, and indicates whether the system is working properly via corresponding LEDs.

[0030] The present invention has the following beneficial effects:

[0031] This invention provides an FPGA-based SFP and RJ45 data interaction device. This device enables data received via both the SFP and RJ45 interfaces to be transmitted normally to the other end, satisfying the data interconnection needs between the two interfaces. This allows devices connected to the two interfaces to communicate in real-time at gigabit speeds via Ethernet. The device can implement data interaction between the SFP and RJ45 interfaces in a hardware-programmable manner, offering advantages in practicality, real-time performance, and flexibility.

[0032] This invention enables data interaction and conversion between RJ45 and SFP interfaces, allowing communication devices with two different interfaces to connect to each other, reducing equipment costs, improving system flexibility, and increasing the number of available devices in the Ethernet network, enabling more devices to be interconnected.

[0033] Compared with the prior art, the significant advantage of the present invention is that it enables any two data devices with SFP or RJ45 interfaces to communicate via Gigabit Ethernet. It can connect older Ethernet devices with only RJ45 interfaces to fiber optic networks, and can also transmit information transmitted in fiber optics in Ethernet RGMII format via RJ45 interfaces, enabling more devices to be used in fiber optic networks and Ethernet.

[0034] The advantages of the embodiments of the present invention are also as follows:

[0035] 1. This invention includes 4 pairs of SFP interfaces and RJ45 interfaces, which can simultaneously perform 4-channel data conversion and transmission, and support the normal data exchange operation of four sets of different interface devices.

[0036] 2. This invention provides FPGA processing logic that ensures normal data flow transmission, correct data format conversion, and correct clock synchronization. Its programmability and high data processing efficiency increase the flexibility and reliability of the entire system.

[0037] 3. This invention significantly saves I / O interface resources for communication equipment and reduces the number of data input and output paths on the PCB board of the communication equipment.

[0038] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a schematic diagram of the hardware structure of an FPGA-based SFP and RJ45 data interaction device according to the present invention.

[0041] Figure 2 This is a schematic diagram of the internal logic interface of an FPGA-based SFP and RJ45 data interaction device according to the present invention.

[0042] Figure 3 This is a schematic diagram of the structure of an FPGA-based SFP and RJ45 data interaction device provided in Embodiment 1 of the present invention;

[0043] Figure 4This is a flowchart of the steps provided in Embodiment 1 of the present invention;

[0044] Figure 5 This is a schematic diagram of the structure of an FPGA-based SFP and RJ45 data interaction device provided in Embodiment 2 of the present invention;

[0045] Figure 6 The flowchart is provided for Embodiment 2 of the present invention. Detailed Implementation

[0046] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0047] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0048] This invention provides an FPGA-based SFP and RJ45 data interaction device, comprising an FMC daughterboard with an RJ45 interface, an FPGA development board with an FPGA chip and an SFP interface; wherein the FPGA chip is connected to the SFP interface via multiple optical ports, and connected to the RJ45 interface via multiple PHY chips on the FMC daughterboard for data interaction; the FMC daughterboard is connected to the FPGA development board via a multi-pin I / O expansion port, and the FPGA chip processes the received data; wherein data flow control, data protocol conversion, and data synchronization control are implemented through the internal logic design of the FPGA chip; wherein the data flow control ensures that data from different interfaces arrives at another interface in an orderly manner for data transmission; the data protocol conversion converts data of different formats to be transmitted into a data format supported by the interface for interface matching; and the data synchronization control synchronizes data from different interfaces for effective transmission.

[0049] This invention presents an FPGA-based SFP and RJ45 data interaction device that enables data communication between an SFP optical interface and an RJ45 electrical interface. This effectively solves the compatibility problem between devices with different interfaces, improving the flexibility and reliability of data communication. Based on the hardware design, data flow control, protocol conversion, and clock synchronization are implemented through FPGA internal logic design, ensuring accurate data transmission. Compared with existing technologies, this invention's data interaction device enables any two devices with SFP or RJ45 interfaces to communicate via Gigabit Ethernet, supports multi-channel data conversion and transmission, saves I / O interface resources, and improves system flexibility and reliability.

[0050] In a preferred embodiment, the data flow control specifically includes: controlling the direction of data flow inside the FPGA development board, so that the received data from the SFP interface on the FPGA development board is transmitted to the transmitter of the corresponding RJ45 interface on the FPGA development board; and so that the received data from the RJ45 interface on the FMC daughterboard is transmitted to the transmitter of the corresponding SFP interface on the FPGA development board.

[0051] In a preferred embodiment, the logic design includes RGMII and GMII modules, and GMII and GTX modules. The RGMII and GMII modules perform conversion between RGMII and GMII format data through single-sided and double-edge sampling, transmitting the processed data signals to their respective locations for further circuit processing. The GMII and GTX modules perform conversion between GMII and GTX format data through high-speed parallel-to-serial / serial-to-parallel conversion and 4B / 5B encoding / decoding, transmitting the processed data signals to their respective locations for further circuit processing. The logic design also includes a clock module and a FIFO module. The clock module generates a system reference clock. The FIFO module synchronizes the clocks of the two interfaces through read / write operations of the cross-domain clock, ensuring synchronization between the data to be transmitted and the transmission clock at both interfaces.

[0052] In a preferred embodiment, the data protocol conversion specifically includes: converting RGMII format data from the RJ45 interface to GMII format data by converting it from dual-edge sampling to single-edge sampling; then converting the obtained GMII format data to GTX format data through parallel-to-serial conversion and 8B / 10B encoding, enabling the SFP interface on the FPGA development board to transmit this data; and converting GTX format data from the SFP interface to GMII format data through serial-to-parallel conversion and 10B / 8B decoding; then converting the obtained GMII format data to RGMII format data through single-edge sampling to dual-edge sampling, enabling the RJ45 interface on the FPGA development board to transmit this data. This data protocol conversion scheme can efficiently and accurately convert data formats from different interfaces, ensuring data compatibility and correct transmission between SFP and RJ45 interfaces.

[0053] In a preferred embodiment, the data synchronization control specifically includes: synchronizing asynchronous data from the SFP interface and the RJ45 interface respectively. For data to be transmitted from the RJ45 interface on the FMC daughterboard, the data source is the SFP receiving interface on the FPGA development board; therefore, the SFP synchronization clock is used for data transmission to achieve data synchronization of the RJ45 interface. For data to be transmitted from the SFP interface on the FPGA development board, the data source is the RJ45 receiving interface on the FMC daughterboard. The SFP uses a channel-bonded clock and a FIFO read / write module. Data is read in using the RJ45 interface synchronization clock and written out using the SFP channel-bonded clock synchronization clock for data clock synchronization. Data is then sent out using the SFP channel-bonded clock on the SFP transmitting interface of the FPGA development board to achieve data synchronization of the SFP interface. This data synchronization control scheme can accurately handle asynchronous data from different interfaces, ensuring the timing consistency and synchronization of data during high-speed transmission, thereby improving the reliability of communication.

[0054] In this embodiment of the invention, the FPGA chip implements logic functions such as data flow control from different sources, conversion between GTX and RGMII protocols, and clock synchronization management through a hardware description language. This ensures that data received through the SFP interface and the RJ45 interface can be transmitted normally to the other end, satisfying the data interconnection between the two interfaces. Devices connected to these two interfaces can then communicate in real-time at gigabit speeds via Ethernet. Furthermore, LED indicators can be controlled to show the system's operating status. The device proposed in this invention enables data interaction between the SFP and RJ45 interfaces in a hardware-programmable manner, offering advantages in practicality, real-time performance, and flexibility.

[0055] The following describes specific embodiments of the present invention.

[0056] An FPGA-based SFP and RJ45 data interaction device includes an FPGA chip, four SFP interfaces, and four RJ45 interfaces, wherein the four SFP interfaces correspond one-to-one with the four RJ45 interfaces. The FPGA chip is connected to the four Gigabit Ethernet RJ45 interfaces via a PHY chip and to the four SFP interfaces via optical ports.

[0057] Figure 1 This is a schematic diagram of the hardware structure of an FPGA-based SFP and RJ45 data interaction device according to the present invention. Figure 1 As shown, this embodiment of the invention proposes an interface conversion device for four pairs of SFP and RJ45 interfaces, including an FPGA development board and an FMC daughterboard. The logic circuits arranged on the FPGA development board are used to implement data flow control and protocol conversion; the RJ45 interfaces on the FMC daughterboard are used to connect Ethernet devices with RJ45 interfaces. When this invention is working, information sent by the connected Ethernet devices with RJ45 interfaces will be output from the corresponding SFP interfaces on the FPGA development board; the SFP interfaces on the FPGA development board are used to connect Ethernet devices with SFP interfaces. When this invention is working, information sent by the connected Ethernet devices with SFP interfaces will be output from the corresponding SFP interfaces on the FPGA development board.

[0058] In this way, the present invention realizes the data interaction and conversion function between RJ45 interface and SFP interface, enabling communication devices with two different interfaces to be interconnected through the present invention, reducing equipment costs, improving system flexibility, and increasing the number of available devices in Ethernet, enabling more devices to be interconnected.

[0059] Optionally, each pair of RJ46 and SFP interfaces corresponds to an LED indicator on the FPGA development board. The LED indicator lights up when gigabit Ethernet communication is normal at both ends of the system and the FPGA development board is functioning correctly. Therefore, those skilled in the art can determine whether the device is working properly based on the status of the LED indicator, facilitating technical work.

[0060] Figure 2 This is a schematic diagram of the internal logic interface of an FPGA-based SFP and RJ45 data interaction device according to the present invention. Figure 2 As shown, the logic design of this invention can obtain the transmitted data from different interfaces on the other end through two data protocol conversions, internal interface links, and FIFO buffering, thereby enabling the FPGA development board to control the overall data flow, protocol conversion, and clock synchronization.

[0061] Optionally, the RGMII and GMII modules are used to receive the RGMII signal output from the RJ45 interface and transform the RGMII signal from double-edge sampling to single-edge sampling to obtain the GMII signal for subsequent processing. At the same time, this module can also transform the GMII data from single-edge sampling to double-edge sampling to obtain RGMII data, which is the data to be transmitted by the RJ45 interface.

[0062] Understandably, FPGA development boards cannot directly process RGMII signals sampled on both sides. Therefore, conversion between RGMII and GMII format data is necessary so that the FPGA development board can further process the data.

[0063] Optionally, the GMII and GTX modules are used to convert the obtained GMII data into GTX data to be transmitted via the SFP interface. Specifically, the GMII data is first converted from serial to parallel to obtain a high-speed serial data stream. Then, the high-speed data stream is 4B / 5B encoded to prevent long strings of 0s or 1s, making the data easier to transmit via fiber optics. Simultaneously, the module also performs 4B / 5B decoding and serial-to-parallel conversion on the data received from the SFP interface to obtain GMII data for subsequent processing.

[0064] Optionally, a FIFO module is used to synchronize two types of asynchronous data from the RJ45 interface and the SFP interface. For the converted GMII data to be transmitted from the RJ45 interface, it is synchronized with the RJ45 interface clock. Through FIFO read / write operations and reset logic, GMII data to be transmitted synchronized with the SFP interface reference clock is obtained, ensuring the system operates normally in synchronized timing.

[0065] In addition, for the converted GMII data to be transmitted from the SFP interface, the SFP reference clock is directly used for conversion and transmission between the RGMII and GMII modules to achieve clock synchronization.

[0066] A method for using an FPGA-based SFP and RJ45 data interaction device includes the following steps:

[0067] Step 1: Connect the communication device with the RJ45 interface to the RJ45 interface on the FMC daughterboard via a twisted pair cable; Step 2: Connect the communication device with the SFP interface to the corresponding SFP interface on the FPGA development board via an optical fiber; Step 3: The device receives signals from both interfaces, transmits and sends signals to each other, and indicates whether the system is working properly via corresponding LEDs.

[0068] Example 1

[0069] Figure 3 This is a schematic diagram of the structure of an FPGA-based SFP and RJ45 data interaction device provided in Embodiment 1 of the present invention, as shown below. Figure 3 As shown, the Ethernet device with the RJ45 interface is connected to the FPGA development board with the FMC daughterboard via a twisted pair cable, and the corresponding SFP interface on the FPGA development board is connected to other devices.

[0070] Figure 4 This is a flowchart illustrating the steps of Embodiment 1 of the present invention. Specifically, the information transmitted by the Ethernet device with the RJ45 interface is transmitted to the RJ45 interface on the FMC daughterboard via a twisted pair cable. This is the RGMII data to be transmitted on the RJ45 interface. After passing through the logic circuits arranged on the FPGA development board, the data to be transmitted is converted into GTX data and then transferred to the corresponding SFP interface on the FPGA development board, becoming the SFP interface data to be transmitted.

[0071] The SFP interface on the FPGA development board sends the data to be transmitted in a high-speed serial data format and interacts with the device connected to the SFP interface.

[0072] The FPGA-based SFP and RJ45 data interaction device provided in this embodiment of the invention includes an Ethernet device with an RJ45 interface as the RJ45 interface signal source, an FMC daughterboard providing a PHY chip, an FPGA development board as the data processing means, and an SFP interface for connecting to other devices. The FPGA-based SFP and RJ45 data interaction device provided in this embodiment of the invention achieves interface conversion through data format conversion and data flow control, eliminating the need for complex circuit design and possessing programmability. This reduces overall cost, improves system flexibility, and facilitates large-scale use.

[0073] Example 2

[0074] Figure 5 This is a schematic diagram of the structure of an FPGA-based SFP and RJ45 data interaction device provided in Embodiment 2 of the present invention, as shown below. Figure 4 As shown, Ethernet devices with SFP interfaces are connected to the SFP interfaces on the FPGA development board via twisted-pair cables, while the corresponding RJ45 interfaces on the FMC daughterboard are connected to other devices.

[0075] Figure 6This is a flowchart illustrating the steps of Embodiment 2 of the present invention. Specifically, the information transmitted by the Ethernet device with the SFP interface is transmitted via optical fiber to the SFP interface on the FPGA development board, which is the GTX data to be transmitted on the SFP interface. After passing through the logic circuits arranged on the FPGA development board, the data to be transmitted is converted into RGMII data and then transferred to the corresponding RJ45 interface on the FMC daughterboard, becoming the RJ45 interface data to be transmitted.

[0076] The RJ45 interface on the FMC daughterboard sends the data to be transmitted in a multi-parallel data format, and interacts with the device connected to the RJ45 interface.

[0077] The FPGA-based SFP and RJ45 data interaction device provided in this embodiment of the invention includes an Ethernet device with an SFP interface as the SFP interface signal source, an FPGA development board as the means of data processing and providing an SFP interface for connection with other devices, and an FMC daughterboard providing a PHY chip and an RJ45 interface for transmitting the converted SFP interface data to be transmitted.

[0078] The RJ45 and SFP interfaces involved in this invention are four pairs, which can simultaneously provide connection and communication for four pairs of communication devices with different interface types.

[0079] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0080] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A data interaction device for SFP and RJ45 based on FPGA, characterized in that, It includes an FMC daughterboard with an RJ45 interface, an FPGA development board with an FPGA chip and an SFP interface; wherein, the FPGA chip is connected to the SFP interface through multiple optical ports, and is connected to the RJ45 interface through multiple physical layer chips (PHY) on the FMC daughterboard for data interaction; the FMC daughterboard is connected to the FPGA development board through a multi-pin I / O expansion port, and the FPGA chip processes the data received from it. The system utilizes internal logic design within the FPGA chip to implement data flow control, data protocol conversion, and data synchronization control. Specifically, data flow control ensures that data from different interfaces reaches another interface in an orderly manner for data transmission. Data protocol conversion converts data of different formats to be transmitted into a format supported by the interface for matching. Data synchronization control synchronizes data from different interfaces for efficient transmission. The logic design includes RGMII and GMII modules, and GMII and GTX modules. The RGMII and GMII modules perform conversion between RGMII and GMII format data through single-sided and double-sided edge sampling, transmitting the processed data signals to their respective locations for further circuit processing. The GMII and GTX modules utilize high-speed parallel-to-serial / serial-to-parallel... The conversion and 4B / 5B encoding / decoding processes perform the conversion between GMII and GTX format data, transmitting the processed data signals to their respective locations for further circuit processing. Specifically, the data protocol conversion includes: converting RGMII format data from the RJ45 interface to GMII format data through dual-edge sampling to single-edge sampling; then converting the obtained GMII format data to GTX format data through parallel-to-serial conversion and 8B / 10B encoding, enabling the SFP interface on the FPGA development board to transmit this data; and converting GTX format data from the SFP interface to GMII format data through serial-to-parallel conversion and 10B / 8B decoding; then converting the obtained GMII format data to RGMII format data through single-edge sampling to dual-edge sampling, enabling the RJ45 interface on the FPGA development board to transmit this data.

2. The FPGA-based SFP and RJ45 data interaction device according to claim 1, characterized in that, It also includes an LED indicator module to show whether the logic circuit is working properly and to display faults.

3. The FPGA-based SFP and RJ45 data interaction device according to claim 1 or 2, characterized in that, Both the RJ45 and SFP interfaces are 4-channel interfaces, with each channel corresponding to another for data exchange.

4. The FPGA-based SFP and RJ45 data interaction device according to any one of claims 1 to 2, characterized in that, The data flow control specifically includes: controlling the direction of data flow inside the FPGA development board, so that the received data from the SFP interface on the FPGA development board is transmitted to the transmitter of the corresponding RJ45 interface on the FPGA development board; and so that the received data from the RJ45 interface on the FMC daughterboard is transmitted to the transmitter of the corresponding SFP interface on the FPGA development board.

5. The FPGA-based SFP and RJ45 data interaction device according to any one of claims 1 to 2, characterized in that, The logic design includes a clock module, which is used to generate a system reference clock.

6. The FPGA-based SFP and RJ45 data interaction device according to any one of claims 1 to 2, characterized in that, The logic design includes a FIFO module; the FIFO module synchronizes the clocks of the two interfaces through read and write operations of the foreign domain clock, ensuring the synchronization of the data to be transmitted and the transmission clock at the two interfaces.

7. The FPGA-based SFP and RJ45 data interaction device according to claim 1 or 2, characterized in that, The data synchronization control specifically includes: synchronizing asynchronous data from the SFP interface and the RJ45 interface respectively. For the data to be transmitted from the RJ45 interface on the FMC daughterboard, the data source is the SFP receiving interface on the FPGA development board. Therefore, the SFP synchronization clock is used for data transmission to achieve data synchronization of the RJ45 interface. For the data to be transmitted from the SFP interface on the FPGA development board, the data source is the RJ45 receiving interface on the FMC daughterboard. The SFP uses a channel-bound clock and a FIFO read / write module. Data is read in using the RJ45 interface synchronization clock and written out using the SFP channel-bound clock synchronization clock to achieve data clock synchronization. The written data is sent from the SFP transmitting interface on the FPGA development board using the SFP channel-bound clock to achieve data synchronization of the SFP interface.

8. A data interaction method using an FPGA-based SFP and RJ45 data interaction device according to any one of claims 1 to 7, characterized in that, include: Data flow control is implemented using the internal logic design of the FPGA chip to transfer data from the SFP interface to the corresponding RJ45 interface, and data from the RJ45 interface to the corresponding SFP interface; data protocol conversion is implemented using the internal logic design of the FPGA chip to convert data of different formats to be transmitted into the data format supported by the interface for interface matching; and data synchronization control is implemented using the internal logic design of the FPGA chip to synchronize data from different interface sources for effective transmission.

Images