FPGA (Field Programmable Gate Array) loading, refreshing and on-orbit reconstruction method in on-satellite real-time information processing system

Abstract

The invention belongs to the field of on-satellite intelligent information processing, and discloses an FPGA loading, refreshing and on-orbit reconstruction method in an on-satellite real-time information processing system, and the system comprises a power supply unit, a measurement and control and configuration management unit, an interface unit, an image processing unit and a bus backboard. Aiming at an on-satellite real-time information processing system based on a dynamic redundancy architecture, a parallel architecture of configuring and managing an FPGA (Field Programmable Gate Array) to be matched with a Nor Flash, an NAND Flash, an SDRAM (Synchronous Dynamic Random Access Memory) and a plurality of SRAM type FPGAs is provided, so that the simultaneous loading and refreshing of the plurality of SRAM type FPGAs can be realized, the loading efficiency is improved, the on-orbit reconstruction time is shortened, the potential hidden danger of a sneak path possibly existing in the system is solved, the scale of the system is simplified, and the reliability of the system is improved. And the cost-effectiveness ratio of the system is improved.

Description

Technical Field

[0001] The present invention relates to the field of on-board intelligent information processing, and in particular to a method for loading, refreshing and on-orbit reconfiguration of an FPGA in an on-board real-time information processing system. Background Art

[0002] With the rapid development of aerospace technology, satellites with low cost, low weight and low power consumption are becoming more and more popular. Therefore, new challenges are posed to on-board real-time information processing technology. On-board real-time information processing systems based on dynamic redundant architecture can not only meet the functional requirements of high throughput, big data processing capabilities and high reliability, but also achieve low system costs. SRAM-type FPGAs have the characteristics of rich resources, excellent performance and repeated programming, and have been widely used in on-board real-time information processing systems. In order to cope with the complex environment of space, one SRAM-type FPGA usually needs to be matched with one refresh chip, and the refresh chip is externally connected with two Nor Flashes to realize the loading, refreshing and on-orbit reconstruction of FPGA configuration items. The entire processing system requires 4n Nor Flash chips. As we all know, the unit price of aerospace-grade Nor Flash is about 100,000. If the entire system requires 40 Nor Flashes, the cost of this chip alone exceeds four million. In addition, the complex detection processing of high-throughput and large-field-of-view images will inevitably introduce regional block processing, and multiple image processing unit FPGAs will share pre-detection configuration items, so the conventional FPGA plus refresh chip and Nor Flash method will waste resources. In addition, the communication rate of the radiation-resistant readback refresh chip is usually only 115200bps, which will cause the upload software to write to its external Nor Flash slowly, occupying the fast upload channel for a long time and affecting other satellite operations. Therefore, it is extremely important to develop low-cost SRAM-based FPGAs with short loading, refreshing and on-orbit reconstruction time. Summary of the invention

[0003] In order to solve the above technical problems, the present invention provides a method for FPGA loading, refreshing and on-orbit reconstruction in an on-board real-time information processing system. For the on-board real-time information processing system based on a dynamic redundant architecture, it is proposed to configure and manage FPGA in combination with Nor Flash, NAND Flash, SDRAM memory and a parallel architecture of multiple SRAM-type FPGAs, so that multiple SRAM-type FPGAs can be loaded and refreshed at the same time, thereby improving loading efficiency, shortening on-orbit reconstruction time, solving potential hidden dangers of potential paths in the system, streamlining the system scale, and improving the system cost-effectiveness.

[0004] The present invention provides a satellite real-time information processing system, which comprises five parts: a power supply unit, a measurement and control and configuration management unit, an interface unit, an image processing unit and a bus backplane.

[0005] Preferably, the measurement, control and configuration management unit includes: an RS422 receiver, a measurement, control and data transmission FPGA, a read-back refresh chip, Nor Flash, NAND Flash, SDRAM, and a configuration management FPGA;

[0006] The image processing unit comprises: a plurality of image processing unit FPGAs;

[0007] The RS422 receiver is used to receive the fast injection data sent by the satellite, and transmit the received injection data to the measurement and control and data transmission FPGA for on-orbit reconstruction and upgrading;

[0008] The measurement, control and data transmission FPGA is used to receive the fast injection data of the RS422 receiver and send the fast injection data to the configuration management FPGA; it is also used to receive the fast injection data of the RS422 receiver and control the read-back refresh chip to store the fast injection data in the Nor Flash plug-in of the read-back refresh chip to realize the on-track reconstruction of the configuration management FPGA; it is also used to directly control the read-back refresh chip to realize the loading and refreshing of the configuration management FPGA;

[0009] The readback refresh chip is used to load and regularly refresh the configuration item software stored in the Nor Flash to the configuration management FPGA through the SelectMAP interface through the control of the measurement and control and data transmission FPGA; at the same time, it can also receive fast injection data, perform read and write operations on the external Nor Flash, and store new configuration item software;

[0010] The Nor Flash is used to store the underlying software configuration items required for normal operation on the satellite;

[0011] The NAND Flash serves as a backup for the Nor Flash and is responsible for storing some configuration items.

[0012] The SDRAM is used for caching fast data for on-track reconstruction;

[0013] The configuration management FPGA is used to simultaneously load and refresh different configuration item software in multiple external Nor Flashes to multiple image processing unit FPGAs through the SelectMAP interface, and the loaded configuration items and the number of loaded image processing unit FPGAs are arbitrarily combined; it is also used to receive fast injection data, update and upgrade the configuration items stored in the external Nor Flash and NANDFlash; it is also used to save the injection data in SDRAM;

[0014] The image processing unit FPGA is used to receive the configuration item software data of the configuration management FPGA through the SelectMAP interface and run the corresponding configuration item function.

[0015] The present invention also provides an FPGA loading method in a satellite real-time information processing system, which is implemented by applying the above-mentioned satellite real-time information processing system. The loading method includes:

[0016] Step 1: After the 42V bus is connected, the measurement and control and data transmission FPGA work normally;

[0017] Step 2: The measurement and control and data transmission FPGA controls the read-back refresh chip through the UART interface, and loads the configuration item software in the main Nor Flash plug-in of the read-back refresh chip into the configuration management FPGA through the SelectMAP interface;

[0018] Step 3: The successfully loaded configuration management FPGA starts to work normally, and loads each configuration item software stored in the external Nor Flash to each image processing unit FPGA through the SelectMAP interface;

[0019] Step 4: After each image processing unit FPGA is loaded normally, the entire system starts to execute the corresponding task.

[0020] Preferably, in step 3, the successfully loaded configuration management FPGA starts to work normally, and the configuration item software stored in the external NorFlash is loaded into each image processing unit FPGA through the SelectMAP interface, including:

[0021] Step 3.1, realize simultaneous loading of multiple image processing unit FPGAs by configuring the management FPGA with multiple external Nor Flash memories;

[0022] Step 3.2: The number of Nor Flashes required by the system has no correlation with the number of image processing unit FPGAs, but only with the number of configuration items of the system image processing unit FPGA;

[0023] In step 3.3, any image processing unit FPGA can load any one of the m configuration item software stored in Nor Flash 1 to Nor Flash m, that is, there is no one-to-one correspondence between the image processing unit FPGA and the configuration item.

[0024] The present invention also provides a method for refreshing an FPGA in a satellite real-time information processing system, which is implemented by applying the above-mentioned satellite real-time information processing system. The refreshing method comprises:

[0025] Step 1: After the loading process is completed, the system starts to work normally. The read-back refresh chip reads the software configuration items in the Nor Flash master and the software loaded in the configuration register of the configuration management FPGA back to the refresh chip for comparison;

[0026] Step 2: The configuration item software loaded by the configuration management FPGA instantiates multiple modules with read-back refresh function, which can read back m configuration items into the configuration management FPGA, and read back the successfully loaded image processing unit configuration items at the same time, and verify them one by one.

[0027] Preferably, in step 1, after the loading process is completed, the system starts to work normally, and the read-back refresh chip reads the software configuration items in the NorFlash master and the software loaded in the configuration management FPGA configuration register back to the refresh chip for comparison, including:

[0028] Step 1.1: If no abnormality is found, do not perform any operation and repeat step 1 after 5 seconds.

[0029] Step 1.2: If an exception is found, repeat step 2 of the loading process to reload the software configuration items in the Nor Flash into the configuration management FPGA. After the reload is successful, repeat step 1.

[0030] Preferably, in step 2, the configuration item software loaded by the configuration management FPGA instantiates multiple modules with read-back refresh function, which can read back m configuration items into the configuration management FPGA, and read back the image processing unit configuration items that have been successfully loaded, and verify them one by one, including:

[0031] Step 2.1: If no abnormality is found, do not perform any operation and repeat step 1 after 5 seconds.

[0032] Step 2.2, if an abnormality is found, repeat step 2 of the loading process, reload the software configuration items in the Nor Flash corresponding to the image processing unit FPGA with the abnormality into the corresponding image processing unit FPGA, and repeat step 1 after the reload is successful.

[0033] The present invention also provides an on-orbit reconstruction method of FPGA in an on-board real-time information processing system, which is implemented by applying the on-board real-time information processing system. The on-orbit reconstruction method includes:

[0034] Step 1: The measurement, control and data transmission FPGA receives the fast uplink data sent by the satellite through the RS422 receiving chip JSR26C32, with a code rate of 5Mbps;

[0035] Step 2: After the measurement and control and data transmission FPGA receives the fast injection data and the corresponding injection instruction, it makes a judgment: if the corresponding configuration item of the configuration management FPGA needs to be reconstructed on-orbit, proceed to step 3; if the configuration item of the image processing unit FPGA needs to be reconstructed on-orbit, proceed to step 6;

[0036] Step 3, the measurement and control and data transmission FPGA sends the received injection software data to the digital read-back refresh chip through the UART interface, with a baud rate of 115200;

[0037] Step 4, the read-back refresh chip writes the software data into the external Nor Flash, and writes it into the main Nor Flash or the backup Nor Flash according to the instruction requirements;

[0038] Step 5, the read-back refresh chip reads the software data from the written Nor Flash and reloads it into the configuration management FPGA through the SelectMAP interface. After the reload is successful, the refresh step 1 is performed;

[0039] Step 6: The measurement, control and data transmission FPGA forwards the received fast injection data to the configuration management FPGA, with a communication rate of 20Mbps.

[0040] Step 7, after receiving the fast injection data, the configuration management FPGA can write the injection data into three different memories, namely, Nor Flash, NAND Flash or SDRAM, through instructions;

[0041] Step 8: The configuration management FPGA reads the software data from the written SDRAM and reloads the specific image processing unit FPGA through the SelectMAP interface. After reloading, the system function test is performed. After the test meets the requirements, the software data in the SDRAM is written into the Nor Flash or NAND Flash.

[0042] Step 9, the configuration management FPGA reads the software data from the written Nor Flash, and reloads the specific image processing unit FPGA through the SelectMAP interface. After the reload is successful, the refresh step 2 is performed;

[0043] Step 10, the configuration management FPGA reads the software data from the written NAND Flash, and reloads the specific image processing unit FPGA through the SelectMAP interface. After the reload is successful, the refresh step 2 is performed.

[0044] Preferably, in step 7, after receiving the fast injection data, the configuration management FPGA can write the injection data into three different memories, namely, specific Nor Flash, NAND Flash or SDRAM, through instructions, including:

[0045] Step 7.1, according to the instruction, quickly write the data into the Nor Flash at a rate of about 12.5kbps;

[0046] Step 7.2, the configuration management FPGA writes the fast injection data into the NAND Flash, and the NAND Flash serves as a backup for the NorFlash, and then proceeds to step 9;

[0047] Step 7.3, the configuration management FPGA writes the fast injection data into the SDRAM, and the SDRAM write rate is up to 80Mbps.

[0048] Compared with the prior art, the present invention has the following beneficial effects:

[0049] (1) In contrast to the traditional solution of one SRAM FPGA with one refresh chip and two NOR Flashes, the present invention adopts a configuration management FPGA with a multi-processor parallel architecture, which reduces the number of system refresh chips and NOR Flashes used, and significantly improves the cost-effectiveness;

[0050] (2) There is no binding relationship between the SRAM FPGA and the Nor Flash that stores configuration items. The number of loaded FPGAs and software configuration items can be switched arbitrarily according to instructions, making the system more flexible and convenient. It has good expansion capabilities. If the processing power needs to be further improved after being in orbit, more processing units can be activated for expansion.

[0051] (3) Use SDRAM cache to quickly upload data, further shortening the on-orbit reconstruction time;

[0052] (4) Through the design of multi-channel bidirectional transceivers and peripheral hardware circuits, the risks of crosstalk and hidden paths that may exist in the SelectMAP interface between the primary and standby configuration management FPGAs and the SRAM-type FPGAs in the processing unit in the dynamic redundant architecture are resolved. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the technical solution of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0054] Figure 1It is a block diagram of the principles of SRAM-type FPGA loading, refreshing and on-orbit reconstruction in the on-board real-time information processing system of an embodiment of the present invention;

[0055] Figure 2 A hardware schematic diagram of the SelectMAP interface implemented in the on-board real-time information processing system based on the cold standby solution according to an embodiment of the present invention;

[0056] Figure 3 The hardware schematic diagram of the SelectMAP interface of the on-board real-time information processing system based on the dynamic redundant backup solution according to the embodiment of the present invention is shown.

[0057] Description of the drawings: 100—measurement, control and configuration management unit, 200—image processing unit, 300—bus backplane, 110—RS422 receiver, 120—measurement, control and data transmission FPGA, 130—readback refresh chip, 140—Nor Flash, 150—NAND Flash, 160—SDRAM, 170—configuration management FPGA, 210—image processing unit FPGA. DETAILED DESCRIPTION

[0058] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0059] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Including" or "comprising" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0060] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0061] Embodiment 1

[0062] The embodiment of the present invention provides a satellite real-time information processing system for target detection, which includes five parts: a power supply unit, a measurement and control and configuration management unit, an interface unit, an image processing unit and a bus backplane.

[0063] The power supply unit, the measurement and control and configuration management unit, the interface unit, and the image processing unit are four different PCB printed boards, which are all inserted into the bus backplane through the backplane connector to realize signal transmission between the four parts. Here, only the measurement and control and configuration management unit 100, the image processing unit 200, and the bus backplane 300 related to loading, refreshing, and on-track reconstruction are described in detail.

[0064] Below Figure 1 The functions of each module of the principle block diagram of SRAM-type FPGA loading, refreshing and on-orbit reconstruction in the real-time information processing system on the satellite and the specific loading, refreshing and on-orbit reconstruction process are described in more detail.

[0065] Specifically, the RS422 receiver 110 uses the JSR26C32 of the China Electronics 58 Institute, and its main function is to receive the fast injection data sent by the satellite, usually at a code rate of 5Mbps, and transmit the received injection data to the measurement, control and data transmission FPGA 120; it is used for on-orbit reconstruction and upgrading on the satellite, and this module is not required for normal loading and refreshing. The measurement, control and data transmission FPGA 120 uses the anti-fuse FPGA JRTAX2000-LG624 of the China Electronics 58 Institute, and its three main functions include: first, receiving the fast injection data of the RS422 receiver 110, and sending the fast injection data to the configuration management FPGA 170; second, receiving the fast injection data of the RS422 receiver 110, and controlling the read-back refresh chip 130 to store the fast injection data in the Nor Flash 140 plug-in of the read-back refresh chip 130, so as to realize the on-orbit reconstruction of the configuration management FPGA 170; third, directly controlling the read-back refresh chip 130 to realize the loading and refreshing of the configuration management FPGA. The read-back refresh chip 130 uses Fudan Microelectronics' JFMRS01RH. Through the control of the measurement and control and data transmission FPGA120, the configuration item software stored in Nor Flash140 is loaded and regularly refreshed on the configuration management FPGA170 through the SelectMAP interface; at the same time, it can also receive fast injection data, perform read and write operations on the plug-in Nor Flash140, and store new configuration item software. Nor Flash140 uses Fudan Microelectronics' JFM29GL256RH, which is mainly used to store software configuration items. In view of its fast reading speed and direct execution of instructions, Nor Flash140 is mainly used to store the underlying software configuration items required for normal operation on the satellite. NAND Flash150 has faster writing and erasing speeds than Nor Flash140 and has a larger capacity. Therefore, when upgrading on-orbit applications, it is limited by the number of Nor Flash140. NAND Flash150 uses Orbit's VDNF128G08RS50MS8V25-G, which can be used as a backup for Nor Flash140 and is responsible for storing some configuration items. Taking advantage of the fast reading speed of SDRAM160, SDRAM160 is mainly used for caching fast data for on-track reconstruction, and Orbit's VDSD2G40RS70SS5V75-G is selected.Configuration management FPGA170 uses Fudan Microelectronics' JFM7K325T-C, and its specific functions include: it can simultaneously load and refresh different configuration item software in multiple external Nor Flash140 chips to multiple image processing unit FPGA210 chips through the SelectMAP interface, and the loaded configuration items and the number of loaded image processing unit FPGA210 chips can be arbitrarily combined; it can receive fast injection data and update the configuration items stored in the external Nor Flash140 and NAND Flash150; it can quickly save the injection data in SDRAM to shorten the injection time. Image processing unit FPGA210 uses Fudan Microelectronics' JFM7VX690T36A-RT, receives the configuration item software data of the configuration management FPGA through the SelectMAP interface, and runs the corresponding configuration item functions.

[0066] Embodiment 2

[0067] Based on the same inventive concept, corresponding to any of the above-mentioned embodiments, this embodiment discloses an FPGA loading method in a satellite real-time information processing system, which is implemented by applying the above-mentioned satellite real-time information processing system. The loading method includes:

[0068] Step 1: After the 42V bus is connected, the measurement, control and data transmission FPGA 120 works normally;

[0069] Step 2, the measurement and control and data transmission FPGA 120 controls the read-back refresh chip 130 through the UART interface, and can load the configuration item software in the main Nor Flash 140 externally mounted to the read-back refresh chip 130 into the configuration management FPGA 170 through the SelectMAP interface;

[0070] Step 3, the successfully loaded configuration management FPGA 170 starts to work normally, and loads each configuration item software stored in the external Nor Flash 140 to each image processing unit FPGA 210 through the SelectMAP interface;

[0071] Step 4: After each image processing unit FPGA210 is loaded normally, the entire system starts to execute the corresponding task.

[0072] In this embodiment, in step 3, the successfully loaded configuration management FPGA 170 starts to work normally, and the configuration item software stored in the external Nor Flash 140 is loaded to each image processing unit FPGA 210 through the SelectMAP interface, including:

[0073] Step 3.1, unlike the traditional image processing unit FPGA210 with the read-back refresh chip 130 and NorFlash140, the configuration management FPGA170 with multiple external Nor Flash140 memories can realize the simultaneous loading of multiple image processing unit FPGA210s; greatly shortening the loading time of the system program;

[0074] Step 3.2, the number of Nor Flash 140 required by the system has no correlation with the number of image processing unit FPGA 210, but only with the number of configuration items of the system image processing unit FPGA 210. This is because: the complex detection processing of high-throughput, large-field-of-view images will inevitably introduce sub-regional block processing, and multiple image processing unit FPGA 210 will share the pre-detection configuration software. If the number of configuration items of the image processing unit 200 is m, the number of Nor Flash 140 can be 2m (including backup);

[0075] In step 3.3, any image processing unit FPGA210 can load any one of the m configuration item software stored in Nor Flash 1 to Nor Flash m, that is, there is no one-to-one correspondence between the image processing unit FPGA210 and the configuration item. The number of image processing unit FPGA210 loaded and the number of image processing unit FPGA210 loaded with different configuration item software can be adjusted in real time according to task requirements to improve the flexibility of the system.

[0076] Since SRAM-type FPGAs are sensitive devices, they are easily affected by high-energy particles on orbit, including total ionizing dose effects (TID) and single event effects (SEE). The impact of single event upset (SEU) on SRAM-type FPGAs is particularly obvious, so the loaded configuration item software needs to be refreshed periodically.

[0077] Embodiment 3

[0078] Based on the same inventive concept, corresponding to any of the above-mentioned embodiments, this embodiment discloses an FPGA refresh method in a satellite real-time information processing system, which is implemented by applying the above-mentioned satellite real-time information processing system. The refresh method includes:

[0079] Step 1, after the above-mentioned loading process is completed, the system starts to work normally. At this time, the read-back refresh chip 130 reads back the software configuration items in the Nor Flash master 140 and the software loaded in the configuration register of the configuration management FPGA 170 to the refresh chip, and the refresh chip compares the two;

[0080] Step 2: The configuration item software loaded by the configuration management FPGA 170 instantiates multiple modules with read-back refresh function, which can read back m configuration items into the configuration management FPGA, and read back the successfully loaded image processing unit configuration items, and verify them one by one.

[0081] In this embodiment, in step 1, after the loading process is completed, the system starts to work normally, and the read-back refresh chip 130 reads back the software configuration items in the Nor Flash master 140 and the software loaded in the configuration register of the configuration management FPGA 170 to the refresh chip for comparison, including:

[0082] Step 1.1: If no abnormality is found, do not perform any operation and repeat step 1 after 5 seconds.

[0083] Step 1.2, if an abnormality is found, it means that the FPGA is affected by high-energy particles, then repeat step 2 of the above loading process to reload the software configuration items in Nor Flash 140 into the configuration management FPGA 170. After the reload is successful, repeat step 1.

[0084] In the present embodiment, in step 2, the configuration item software loaded by the configuration management FPGA 170 instantiates multiple modules with read-back refresh function, which can read back m configuration items into the configuration management FPGA, and read back the image processing unit configuration items that have been successfully loaded, and verify them one by one, including:

[0085] Step 2.1: If no abnormality is found, do not perform any operation and repeat step 1 after 5 seconds.

[0086] Step 2.2, if an abnormality is found, repeat step 2 of the above loading process, reload the software configuration items in Nor Flash 140 corresponding to the image processing unit FPGA 210 with the abnormality into the corresponding image processing unit FPGA 210, and repeat step 1 after the reload is successful.

[0087] Embodiment 4

[0088] Based on the same inventive concept, corresponding to any of the above-mentioned embodiments, this embodiment discloses an on-orbit reconstruction method of FPGA in a satellite real-time information processing system, which solves the problem of long injection time of multiple configuration items of the image processing unit by configuring the management FPGA210 with Nor Flash, SDRAM, and NAND Flash architecture, and is implemented by applying the on-orbit real-time information processing system. The on-orbit reconstruction method includes:

[0089] Step 1, the measurement, control and data transmission FPGA 120 receives the fast uplink data sent by the satellite through the RS422 receiving chip JSR26C32, with a code rate of 5Mbps;

[0090] Step 2, after the measurement and control and data transmission FPGA 120 receives the fast injection data and the corresponding injection instruction, it makes a judgment: if the corresponding configuration item of the configuration management FPGA 170 needs to be reconstructed on-orbit, then proceed to step 3; if the configuration item of the image processing unit FPGA 210 needs to be reconstructed on-orbit, then proceed to step 6;

[0091] Step 3, the measurement and control and data transmission FPGA 120 sends the received injection software data to the digital read-back refresh chip 130 through the UART interface, with a baud rate of 115200;

[0092] Step 4, the read-back refresh chip 130 writes the software data into its external Nor Flash 140, which can be written into the main Nor Flash 140 or the backup Nor Flash 140 according to the instruction requirement;

[0093] Step 5, the read-back refresh chip 130 reads the software data from the just written Nor Flash 140, and reloads it into the configuration management FPGA 170 through the SelectMAP interface. After the reload is successful, the refresh process step 1 is performed;

[0094] Step 6, the measurement, control and data transmission FPGA 120 forwards the received fast injection data to the configuration management FPGA 170, and the communication rate is 20Mbps;

[0095] Step 7, after receiving the fast injection data, the configuration management FPGA 170 can write the injection data into three different memories, namely, the specific Nor Flash 140, the NAND Flash 150 or the SDRAM 160, through instructions, and respectively transfer to step 7.1, step 7.2, and step 7.3;

[0096] Step 7.1, according to the instruction, quickly write the data into Nor Flash 140 at a rate of about 12.5kbps;

[0097] Step 7.2, the configuration management FPGA 170 writes the fast injection data into the NAND Flash 150, and the NAND Flash 150 can be used as a backup of the Nor Flash 140 to shorten the injection time, and then proceed to step 9;

[0098] Step 7.3, the configuration management FPGA 170 writes the fast injection data into the SDRAM 160. The write rate of the SDRAM 160 is as high as 80Mbps, which can greatly shorten the on-track injection time. The on-track reconstruction time is limited by the rate of the fast injection data.

[0099] Step 8, configuration management FPGA170 reads the software data from the SDRAM160 just written, and reloads the specific image processing unit FPGA210 through the SelectMAP interface, performs system function test after reloading, and writes the software data in SDRAM160 into Nor Flash140 or NAND Flash150 after the test meets the requirements. This is because: after the SDRAM160 loses power, the data cannot be saved and can only temporarily store software configuration items, but its write rate is faster than NorFlash140, making on-track testing more convenient;

[0100] Step 9, the configuration management FPGA 170 reads the software data from the just written Nor Flash 140, and reloads the specific image processing unit FPGA 210 through the SelectMAP interface. After the reload is successful, the refresh process step 2 is performed;

[0101] Step 10, the configuration management FPGA 170 reads the software data from the NAND Flash 150 just written, and reloads the specific image processing unit FPGA 210 through the SelectMAP interface. After the reload is successful, the refresh process step 2 is performed.

[0102] Embodiment 5

[0103] like Figure 2 As shown, the present invention provides a hardware schematic diagram of a SelectMAP interface for a satellite real-time information processing system with a complete cold standby architecture. Figure 2 Only the hardware schematic diagram of the SelectMAP interface between the configuration management FPGA in the measurement and control and configuration management unit 100 and the image processing unit 1 200 is listed. Taking the configuration management FPGA and the FPGA in the image processing unit 1 as an example, the configuration management FPGA loads and refreshes the configuration items of an image processing unit FPGA through 15 signal lines. Specifically:

[0104] The signal line controls the input and output direction of the CL1_FR_A_CK_FPGA_DATA_DIR level conversion isolation chip to achieve bidirectional transmission of the eight data signals CL1_FR_A_CK_FPGA_DATA[7:0]. The eight data signals CL1_FR_A_CK_FPGA_DATA[7:0] and the six control signals CL1_FR_A_CK_FPGA_CCLK, CL1_FR_A_CK_FPGA_PROGRAM_B, CL1_FR_A_CK_FPGA_RDWR_R, CL1_FR_A_CK_FPGA_CSI_B, CL1_FR_A_CK_FPGA_INIT_B, and CL1_FR_A_CK_FPGA_DONE form the SelectMAP loading signal line. The 14 SelectMAP signal lines between the configuration management FPGA and the image processing unit FPGA are electrically connected through the level conversion isolation chips U1 and U2 in the measurement and control and configuration management unit 100, the bus backplane 300, and the level conversion isolation chips U1 and U2 in the image processing unit 200. The A_CK_VCCA and A_CK_VCCB of the level conversion isolation chips U1 and U2 in the measurement and control and configuration management unit 100, and the CL_VCCA and CL_VCCB of the level conversion isolation chips U1 and U2 in the image processing unit 200 can be consistent or different, and the level range is 1.8V to 5.0V. A_CK_VCCA is the same as the bank voltage of the corresponding IO pin of the configuration management FPGA; A_CK_VCCB is consistent with the CL_VCCA level of the level conversion isolation chips U1 and U2 in the image processing unit; CL_VCCB is consistent with the level of a specific IO pin of the image processing unit FPGA, which is determined by the model of the selected FPGA. In the present invention, the image processing unit FPGA is JFM7VX690T36A-RT, and CL_VCCB is 1.8V.

[0105] When the configuration item is loaded, CL1_FR_A_CK_FPGA_DATA_DIR is high level, and the directions of U2 in the measurement and control and configuration management unit and U2 in the image processing unit are both from A to B. At this time, the configuration item software data is injected into the image processing unit FPGA through the eight data signals CL1_FR_A_CK_FPGA_DATA[7:0] of the IO port of the configuration management FPGA, the measurement and control and configuration management unit U2, and the image processing unit U2, thereby completing the loading.

[0106] When refreshing, CL1_FR_A_CK_FPGA_DATA_DIR is at a low level, and the directions of U2 in the measurement, control and configuration management unit and U2 in the image processing unit are both from B to A. At this time, the configuration item software data loaded in the image processing unit is read back to the configuration management FPGA through the eight data signals CL1_FR_A_CK_FPGA_DATA[7:0] of the image processing unit SelectMAP interface, the image processing unit U2, and the measurement, control and configuration management unit U2.

[0107] Since the image processing unit FPGA has the SelectMAP loading function, a specific IO pin must be selected, and there is only a single copy. In order to realize that both the active and standby measurement and control and configuration management units 100 in the dynamic redundant architecture can load the image processing unit FPGA, the level conversion isolation chip plays a vital role. Figure 3 The hardware schematic diagram of the SelectMAP interface implemented in the on-board real-time information processing system based on the dynamic redundant backup solution is given. Port A of the level conversion isolation chip in the image processing unit 200 receives the SelectMAP signal of the primary and standby configuration management FPGAs respectively, and connects the shaped and isolated SelectMAP signal to the processing unit FPGA at port B. The power-on status of port A and port B of the level conversion isolation chip and the control of OE achieve a double insurance effect, which not only avoids the interference between the signal lines of the primary and standby SelectMAP interfaces causing loading failures, but also realizes electrical isolation between the primary and standby configuration management FPGAs to avoid the occurrence of sneak paths. Taking the configuration management FPGA and the FPGA in the image processing unit 1 as an example, the configuration management FPGA loads and refreshes the configuration items of an image processing unit FPGA through 15 signal lines. Specifically:

[0108] When the main measurement, control and configuration management unit is working normally, A_CK_VCC controlled by the main measurement, control and configuration management unit and CL_VCC controlled by the image processing unit are powered on normally, usually at 1.8V; when the standby measurement, control and configuration management unit is not working, the B_CK_VCC level controlled by the standby measurement, control and configuration management unit is zero. At this time, the power supply of VCCA and VCCB of the level conversion isolation chip U1 is normal, and the OE connected to B_CK_VCC is low, and U1 works normally; VCCA of the level conversion isolation chip U2 is low, and OE connected to A_CK_VCC is high, U2 does not work, and is equivalent to a high impedance state, avoiding interference with the output signal of the standby configuration management FPGA. When the configuration item is loaded, CL1_FR_A_CK_FPGA_DATA_DIR is high, and the direction of U1 in the image processing unit is A to B. At this time, the configuration item software data is injected into the image processing unit FPGA through the eight data signals CL1_FR_A_CK_FPGA_DATA[7:0] of the IO port of the configuration management FPGA and the image processing unit U1, thereby completing the loading. When refreshing, CL1_FR_A_CK_FPGA_DATA_DIR is low, and the direction of U1 in the image processing unit is from B to A. At this time, the configuration item software data loaded in the image processing unit is read back to the configuration management FPGA through the eight data signals CL1_FR_A_CK_FPGA_DATA[7:0] of the image processing unit SelectMAP interface and the image processing unit U1.

[0109] Similarly, when the standby measurement, control and configuration management unit works normally, B_CK_VCC controlled by the standby measurement, control and configuration management unit and CL_VCC controlled by the image processing unit are powered on normally, usually at 1.8V; when the main measurement, control and configuration management unit does not work, the A_CK_VCC level controlled by the main measurement, control and configuration management unit is zero. At this time, the VCCA and VCCB of the level conversion isolation chip U2 are powered normally, and the OE connected to A_CK_VCC is low, and U2 works normally; the VCCA of the level conversion isolation chip U1 is low, and the OE connected to B_CK_VCC is high, U1 does not work, and is equivalent to a high impedance state, avoiding interference with the output signal of the standby configuration management FPGA. When the configuration item is loaded, CL1_FR_B_CK_FPGA_DATA_DIR is high, and the direction of U2 in the image processing unit is A to B. At this time, the configuration item software data is injected into the image processing unit FPGA through the eight data signals CL1_FR_B_CK_FPGA_DATA[7:0] of the IO port of the configuration management FPGA and the image processing unit U2, thereby completing the loading. When refreshing, CL1_FR_B_CK_FPGA_DATA_DIR is low, and the direction of U2 in the image processing unit is from B to A. At this time, the configuration item software data loaded in the image processing unit is read back to the configuration management FPGA through the eight data signals CL1_FR_B_CK_FPGA_DATA[7:0] of the image processing unit SelectMAP interface and the image processing unit U1.

[0110] According to this solution, the number y of common IOs of the configuration management FPGA should satisfy:

[0111] y≥15*2n

[0112] Wherein: 2n is the number of image processing units 200.

[0113] Similarly, the model and quantity of the backplane connector selected by the measurement, control and configuration management unit 100 must also meet this requirement.

[0114] The embodiments of the present disclosure are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present disclosure should be included in the scope of protection of the present disclosure.

Claims

1. A real-time information processing system on a satellite, characterized in that: The system comprises five parts: a power supply unit, a measurement, control and configuration management unit (100), an interface unit, an image processing unit (200) and a busbar backplane (300).

2. The system according to claim 1, characterized in that The measurement, control and configuration management unit (100) comprises: an RS422 receiver (110), a measurement, control and data transmission FPGA (120), a read-back refresh chip (130), a Nor Flash (140), a NAND Flash (150), an SDRAM (160), and a configuration management FPGA (170); The image processing unit (200) comprises: a plurality of image processing unit FPGAs (210); The RS422 receiver (110) is used to receive the rapid injection data sent by the satellite, and transmit the received injection data to the measurement, control and data transmission FPGA (120) for on-orbit reconstruction and upgrading on the satellite; The measurement, control and data transmission FPGA (120) is used to receive the fast injection data of the RS422 receiver (110) and send the fast injection data to the configuration management FPGA (170); it is also used to receive the fast injection data of the RS422 receiver (110) and control the read-back refresh chip (130) to store the fast injection data in the Nor Flash (140) external to the read-back refresh chip (130) to achieve on-track reconstruction of the configuration management FPGA (170); it is also used to directly control the read-back refresh chip (130) to achieve loading and refreshing of the configuration management FPGA (170); The read-back refresh chip (130) is used to load and regularly refresh the configuration item software stored in the Nor Flash (140) to the configuration management FPGA (170) through the SelectMAP interface under the control of the measurement and control and data transmission FPGA (120); at the same time, it can also receive fast injection data, perform read and write operations on the external Nor Flash (140), and store new configuration item software; The Nor Flash (140) is used to store the underlying software configuration items required for normal operation on the satellite; The NAND Flash (150) serves as a backup of the Nor Flash (140) and is responsible for storing some configuration items; The SDRAM (160) is used for caching fast injection data for on-track reconstruction; The configuration management FPGA (170) is used to simultaneously load and refresh different configuration item software in multiple external Nor Flash (140) chips to multiple image processing unit FPGAs (210) through a SelectMAP interface, and the number of loaded configuration items and loaded image processing unit FPGAs (210) can be combined arbitrarily; it is also used to receive fast injection data, and update and upgrade the configuration items stored in the external NorFlash (140) and NAND Flash (150); it is also used to store the injection data in SDRAM; The image processing unit FPGA (210) is used to receive configuration item software data of the configuration management FPGA through a SelectMAP interface and run corresponding configuration item functions.

3. A method for loading FPGA in a satellite real-time information processing system, implemented by applying a satellite real-time information processing system according to any one of claims 1 to 2, characterized in that: The loading method comprises: Step 1, after the 42V bus is connected, the measurement, control and data transmission FPGA (120) works normally; Step 2, the measurement and control and data transmission FPGA (120) controls the read-back refresh chip (130) through the UART interface, and loads the configuration item software in the main Nor Flash (140) external to the read-back refresh chip (130) into the configuration management FPGA (170) through the SelectMAP interface; Step 3, the successfully loaded configuration management FPGA (170) starts to work normally, and loads each configuration item software stored in the external Nor Flash (140) to each image processing unit FPGA (210) through the SelectMAP interface; Step 4: After each image processing unit FPGA (210) has been loaded normally, the entire system starts to execute the corresponding task.

4. The method according to claim 3, characterized in that In step 3, the successfully loaded configuration management FPGA (170) starts to work normally, and loads each configuration item software stored in the external Nor Flash (140) to each image processing unit FPGA (210) through the SelectMAP interface, including: Step 3.1, realizing simultaneous loading of multiple image processing unit FPGAs (210) by configuring the management FPGA (170) and the architecture of multiple external Nor Flash (140) memories; Step 3.2, the number of Nor Flashes (140) required by the system has no correlation with the number of image processing unit FPGAs (210), but is only related to the number of configuration items of the system image processing unit FPGAs (210); Step 3.3: any image processing unit FPGA (210) can load any configuration item of the m configuration item software stored in Nor Flash 1 to Nor Flash m, that is, there is no one-to-one correspondence between the image processing unit FPGA (210) and the configuration item.

5. A method for refreshing FPGA in a satellite real-time information processing system, implemented by applying a satellite real-time information processing system according to any one of claims 1 to 2, characterized in that: The refreshing method comprises: Step 1: After the loading process is completed, the system starts to work normally, and the read-back refresh chip (130) reads the software configuration items in the Nor Flash main (140) and the software loaded in the configuration register of the configuration management FPGA (170) back to the refresh chip for comparison; Step 2: In the configuration item software loaded by the configuration management FPGA (170), a plurality of modules with read-back refresh function are instantiated, which can read back m configuration items into the configuration management FPGA, and read back the image processing unit configuration items that have been successfully loaded, and verify them one by one.

6. The method according to claim 5, characterized in that In step 1, after the loading process is completed, the system starts to work normally, and the read-back refresh chip (130) reads back the software configuration items in the Nor Flash master (140) and the software loaded in the configuration register of the configuration management FPGA (170) into the refresh chip for comparison, including: Step 1.1: If no abnormality is found, do not perform any operation and repeat step 1 after 5 seconds. Step 1.2: If an abnormality is found, repeat step 2 of the loading process to reload the software configuration items in the Nor Flash (140) into the configuration management FPGA (170). After the reload is successful, repeat step 1.

7. The method according to claim 5, characterized in that In the step 2, a plurality of modules with read-back and refresh function are instantiated in the configuration item software loaded by the configuration management FPGA (170), which can read back m configuration items into the configuration management FPGA, and read back the image processing unit configuration items that have been successfully loaded, and verify them one by one, including: Step 2.1: If no abnormality is found, do not perform any operation and repeat step 1 after 5 seconds. Step 2.2, if an abnormality is found, repeat step 2 of the loading process, reload the software configuration items in the Nor Flash (140) corresponding to the image processing unit FPGA (210) with the abnormality into the corresponding image processing unit FPGA (210), and after the reload is successful, repeat step 1.

8. An on-orbit FPGA reconfiguration method in an on-board real-time information processing system, implemented by applying an on-board real-time information processing system according to any one of claims 1-2, characterized in that: The on-orbit reconstruction method comprises: Step 1, the measurement, control and data transmission FPGA (120) receives the fast injection data sent by the satellite through the RS422 receiving chip JSR26C32, with a code rate of 5Mbps; Step 2, after the measurement and control and data transmission FPGA (120) receives the fast injection data and the corresponding injection instruction, it makes a judgment: if the corresponding configuration item of the configuration management FPGA (170) needs to be reconstructed on-orbit, it proceeds to step 3; if the configuration item of the image processing unit FPGA (210) needs to be reconstructed on-orbit, it proceeds to step 6; Step 3, the measurement, control and data transmission FPGA (120) sends the received injection software data to the digital read-back refresh chip (130) through the UART interface, with a baud rate of 115200; Step 4, the read-back refresh chip (130) writes the software data into the external Nor Flash (140), and writes the software data into the main Nor Flash (140) or the backup Nor Flash (140) according to the instruction requirements; Step 5, the read-back refresh chip (130) reads the software data from the written Nor Flash (140), and reloads it into the configuration management FPGA (170) through the SelectMAP interface. After the reload is successful, the refresh step 1 is performed again; Step 6, the measurement, control and data transmission FPGA (120) forwards the received fast injection data to the configuration management FPGA (170), and the communication rate is 20Mbps; Step 7, after receiving the fast injection data, the configuration management FPGA (170) can write the injection data into three different memories, namely, a specific Nor Flash (140), a NAND Flash (150) or an SDRAM (160) through instructions; Step 8, the configuration management FPGA (170) reads the software data from the written SDRAM (160), and reloads the specific image processing unit FPGA (210) through the SelectMAP interface, performs a system function test after the reload, and writes the software data in the SDRAM (160) into the Nor Flash (140) or the NAND Flash (150) after the test meets the requirements; Step 9, the configuration management FPGA (170) reads the software data from the written Nor Flash (140), and reloads the specific image processing unit FPGA (210) through the SelectMAP interface, and then performs the refresh step 2 after the reload is successful; Step 10, the configuration management FPGA (170) reads the software data from the written NAND Flash (150), and reloads the specific image processing unit FPGA (210) through the SelectMAP interface, and then performs the refresh step 2 after the reload is successful.

9. The method according to claim 8, characterized in that In step 7, after receiving the fast injection data, the configuration management FPGA (170) can write the injection data into three different memories, namely, a specific Nor Flash (140), a NAND Flash (150) or an SDRAM (160) through instructions, including: Step 7.1, according to the instruction, quickly write the data into the Nor Flash (140) at a rate of about 12.5 kbps; Step 7.2, the configuration management FPGA (170) writes the fast injection data into the NAND Flash (150), and the NAND Flash (150) serves as a backup of the Nor Flash (140), and then proceeds to step 9; Step 7.3, the configuration management FPGA (170) writes the fast injection data into the SDRAM (160), and the writing rate of the SDRAM (160) is as high as 80Mbps.

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