A method for constructing a thermal resistance simulation model for power MOSFET devices

Abstract

The invention discloses a method for constructing a thermal resistance simulation model of a power MOSFET device. The method draws a corresponding three-dimensional model according to the packaging structure of the power device, imports the three-dimensional model on a thermal simulation analysis platform to simulate and analyze the heat distribution inside the power device, and uses a multi-layer equivalent simplification method to equivalently simplify the chip structure inside the power device into five layers of thin films, and sets equivalent characteristic parameters of each layer to construct a finite element simulation model of the chip as a heat source of the power device; a thermal resistance test environment is built, and the temperature of each layer of thin film is simulated in a set temperature environment to obtain a temperature change model of the chip finite element simulation model; and the thermal resistance simulation model of the power device is obtained according to the temperature change model and the heat distribution inside the power device. The finite element simulation method is adopted to systematically consider the influencing factors such as the internal structure of the power device and the packaging process parameters, and the multi-layer equivalent simplification method is used to construct a thermal resistance simulation model that accurately reflects the internal thermal characteristics of the device.

Description

Technical Field

[0001] The invention relates to the field of semiconductor testing technology, and in particular to a method for constructing a thermal resistance simulation model of a power MOSFET device. Background Art

[0002] Power devices are core components of electronic devices that process and convert large currents / voltages. When switching or conducting, they generate a lot of energy consumption, and most of the lost energy is converted into heat energy. If the heat cannot be dissipated quickly, it will cause the performance of the power device to drift or even fail. The device structure design of the power device determines how much heat it generates when it is working, and the material parameters and process conditions of the chip package determine the efficiency of heat transfer to the outside, that is, the package thermal resistance. Moreover, as power devices develop towards high power and high integration, the impact of package thermal resistance on the performance of power devices is becoming more and more important. Power metal oxide semiconductor field effect transistors (MOSFETs) are widely used in power management, motor drive, DC-DC conversion, load switching and other fields due to their efficient and fast switching capabilities. The accurate analysis of their package thermal resistance is crucial to improving device performance. However, establishing an accurate package thermal resistance model for power MOSFETs has become an important technical problem in studying the internal mechanism of package thermal resistance and optimizing the design of packaging processes.

[0003] In recent years, the study of package thermal resistance of power MOSFET devices has attracted extensive research interest. Due to the limitations of preparation technology and cost in experimental research, only a few specific package structures can be studied for thermal resistance, which is not scalable and difficult to study the intrinsic package thermal resistance of power devices in depth and comprehensively. For this reason, the study of package thermal resistance has emerged. Existing simulation modeling methods include establishing a simple simulation model of power semiconductor module packaging through the typical Fluent finite element analysis method, exploring the thermal characteristics distribution inside the module, and analyzing the influence of package structure design on package thermal resistance; using the three-dimensional temperature calculation module MosfetTemp to establish a MOSFET thermal simulation model, roughly simplifying the chip as a heat source into a single-layer film, which cannot reflect the actual thermal behavior of the device; constructing a Cauer-type thermal simulation model of SiC MOSFET to reveal the temperature characteristics of each package layer and predict the thermal distribution of the device under high temperature conditions. However, although the model takes into account the device structure inside the chip, it simply defines the upper third of the chip volume as the heat source, which is quite different from the structure of the actual chip and cannot accurately simulate the complex thermal changes of the device during operation. In order to solve the problem of long calculation time for complex finite element simulation models, there is also a numerical heat transfer model of a double-panel panel-level packaging structure. The variable separation method is used to characterize the thermal characteristics such as junction temperature and thermal resistance, and the results are compared with the finite element simulation results to verify the correctness of the numerical model. However, in the process of establishing the two models, the chip structure is idealized, and the results lack physical test verification.

[0004] In summary, in the current thermal simulation modeling research of power MOSFET devices, the chip as the heat source of the power device is treated as an overly simple equivalent, and there is still a lack of an accurate package thermal resistance model based on the specific internal structure of the device and its thermal characteristics. Summary of the invention

[0005] The purpose of the present invention is to provide a method for constructing a thermal resistance simulation model of a power MOSFET device. The finite element simulation method is adopted to systematically consider the influencing factors such as the internal structure of the power MOSFET device and the packaging process parameters, and the multi-layer equivalent simplification method is used to construct a thermal resistance simulation model that accurately reflects the internal thermal characteristics of the device.

[0006] To achieve the above objectives, this application adopts the following scheme:

[0007] A method for constructing a thermal resistance simulation model of a power MOSFET device, specifically comprising the following steps:

[0008] S1. Draw a corresponding three-dimensional model according to the packaging structure of the power MOSFET device, and import the three-dimensional model into the ANSYS Icepak thermal simulation analysis platform;

[0009] S2. According to the three-dimensional model, simulate and analyze the heat distribution inside the power MOSFET device, use the multi-layer equivalent simplification method to equivalently simplify the chip structure inside the power MOSFET device into five layers of thin films, set equivalent characteristic parameters of each layer, and construct a finite element simulation model of the chip as a heat source of the power MOSFET device;

[0010] S3. Build a thermal resistance test environment, apply thermal power consumption to the chip finite element simulation model, and simulate the temperature of each film layer in a set temperature environment to obtain a temperature change model of the chip finite element simulation model;

[0011] S4. According to the temperature variation model and the heat distribution inside the power MOSFET device, a thermal resistance simulation model of the power MOSFET device is obtained.

[0012] In some specific embodiments, the five-layer film includes: a PN junction device equivalent layer formed by epitaxial doping, an interconnect protection layer of dielectric interlayer metal, a silicon substrate layer, a gate / source top metal layer and a drain bottom metal layer.

[0013] In some specific implementation schemes, the specific process of constructing the chip finite element simulation model in step S2 is:

[0014] S21, simplifying the chip structure inside the power MOSFET device into five different thin films according to the actual functional layer structure;

[0015] S22, setting the physical dimensions of each layer of film according to the manufacturing process of the chip structure;

[0016] S23, setting equivalent characteristic parameters of each layer of the film, the equivalent characteristic parameters including material parameters of each layer of the film and doping type and doping concentration of each region of the equivalent layer of the PN junction device, to obtain a finite element simulation model of the chip.

[0017] In some specific implementation schemes, the temperature change model of the chip finite element simulation model in step S3 includes the temperature change caused by conduction of each film layer, and the calculation process is:

[0018]

[0019]

[0020] in, It indicates the temperature change caused by the heat generated by each layer of film in the chip structure and dissipated through conduction. It indicates the temperature change caused by the material of the first thin film layer from the chip surface downward. represents the temperature change caused by the material of the nth film layer, k i ,ρ i , C i ,s, h i Respectively represent the equivalent material parameters of the i-th film layer: thermal conductivity, density, specific heat capacity, surface area, thickness, p d represents the applied heat power dissipation, x j represents the distance from the jth point on the i-th film layer to the heat source, x ( n- 1) represents the distance from the n-1th point on the i-th film layer to the heat source, x Represents the coordinates of points on the heat conduction path in the chip structure x value.

[0021] In some specific embodiments, for the PN junction device equivalent layer, the thermal conductivity is calculated as:

[0022]

[0023]

[0024] in, m To consider the electron concentration of the equivalent layer material of the PN junction device after the doping concentration is considered, is the N-type doping concentration, is the P-type doping concentration, is the hole concentration of the material; Indicates that the equivalent layer material of the PN junction device has an electron concentration of m The thermal conductivity at is the thermal conductivity of the material without doping.

[0025] In some specific embodiments, a method for quickly obtaining the thermal resistance of a power MOSFET device using the thermal resistance simulation model is also included, and the specific steps are:

[0026] S01, obtaining the measured ambient temperature range where the thermal resistance simulation model is located, and expanding the measured ambient temperature range to obtain the simulated ambient temperature range;

[0027] S02, dividing the simulation environment temperature range according to fixed gradient change intervals to obtain multiple simulation temperature ranges;

[0028] S03. On the ANSYS Icepak thermal simulation analysis platform, each simulation temperature range is set respectively, and each simulation temperature range is brought into the thermal resistance simulation model for simulation to obtain a thermal resistance-temperature influence curve of the power MOSFET device under different ambient temperatures;

[0029] S04. Obtain the actual measured ambient temperature of the power MOSFET device to be tested, and find the thermal resistance value corresponding to the actual measured ambient temperature in the thermal resistance-temperature influence curve.

[0030] The present invention has the beneficial effects:

[0031] In order to construct an accurate device thermal resistance model, this application analyzes the internal structure of the power MOSFET in detail, simplifies the internal chip of the power MOSFE into five different layers of thin films, and effectively reduces the complexity of modeling calculations by setting equivalent characteristic parameters of each layer of material, while accurately describing the thermal channel inside the device and achieving accurate modeling of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A schematic diagram of a method for constructing a thermal resistance simulation model of a power MOSFET device provided in an embodiment of the present invention;

[0033] Figure 2 It is a schematic diagram of the structure of an existing simple simulation model;

[0034] Figure 3 A schematic diagram of the thermal resistance inside a power MOSFET device provided by an embodiment of the present invention;

[0035] Figure 4 A schematic diagram of the thermal resistance simulation model structure provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0036] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. The following description of at least one exemplary embodiment is actually only illustrative and is by no means intended to limit the present invention and its application or use. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0037] The relative arrangement of components and steps, the numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.

[0038] At the same time, it should be understood that for the convenience of description, the sizes of the various parts shown in the drawings are not drawn according to the actual proportional relationship.

[0039] Additionally, descriptions of well-known structures, functions, and configurations may be omitted for clarity and conciseness.One of ordinary skill in the art will recognize that various changes and modifications may be made to the examples described herein without departing from the spirit and scope of the present disclosure.

[0040] Technologies, methods, and apparatus known to ordinary technicians in the relevant field may not be discussed in detail, but where appropriate, such technologies, methods, and apparatus should be considered part of the authorization specification.

[0041] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0042] Example 1

[0043] like Figure 1 As shown, this embodiment provides a method for constructing a thermal resistance simulation model of a power MOSFET device, which specifically includes the following steps:

[0044] S1. Draw a corresponding three-dimensional model according to the packaging structure of the power MOSFET device, and import the three-dimensional model into the ANSYS Icepak thermal simulation analysis platform;

[0045] S2. According to the three-dimensional model, simulate and analyze the heat distribution inside the power MOSFET device, use the multi-layer equivalent simplification method to equivalently simplify the chip structure inside the power MOSFET device into five layers of thin films, set equivalent characteristic parameters of each layer, and construct a finite element simulation model of the chip as a heat source of the power MOSFET device;

[0046] Specifically, the five-layer film includes: a PN junction device equivalent layer formed by epitaxial doping, an interconnect protection layer of dielectric interlayer metal, a silicon substrate layer, a gate / source top metal layer and a drain bottom metal layer.

[0047] Further, the specific process of constructing the chip finite element simulation model in step S2 is:

[0048] S21, simplifying the chip structure inside the power MOSFET device into five different thin films according to the actual functional layer structure;

[0049] S22, setting the physical dimensions of each layer of film according to the manufacturing process of the chip structure;

[0050] S23, setting equivalent characteristic parameters of each layer of the film, the equivalent characteristic parameters including material parameters of each layer of the film and doping type and doping concentration of each region of the equivalent layer of the PN junction device, to obtain a finite element simulation model of the chip.

[0051] S3. Build a thermal resistance test environment, apply thermal power consumption to the chip finite element simulation model, and simulate the temperature of each film layer in a set temperature environment to obtain a temperature change model of the chip finite element simulation model;

[0052] The temperature change model of the chip finite element simulation model in step S3 includes the temperature change caused by conduction of each film layer, and the calculation process is:

[0053]

[0054] in, It indicates the temperature change caused by the heat generated by each layer of film in the chip structure and dissipated through conduction. It indicates the temperature change caused by the material of the first thin film layer from the chip surface downward. represents the temperature change caused by the material of the nth film layer, k i , ρ i , C i ,s, h i Respectively represent the equivalent material parameters of the i-th film layer: thermal conductivity, density, specific heat capacity, surface area, thickness, p d represents the applied heat power dissipation, x j represents the distance from the jth point on the i-th film layer to the heat source, x ( n- 1) represents the distance from the n-1th point on the i-th film layer to the heat source, x Represents the coordinates of points on the heat conduction path in the chip structure x value.

[0055] More specifically, for the PN junction device equivalent layer, the thermal conductivity is calculated as:

[0056]

[0057]

[0058] in, m To consider the electron concentration of the equivalent layer material of the PN junction device after the doping concentration is considered, is the N-type doping concentration, is the P-type doping concentration, is the hole concentration of the material; Indicates that the equivalent layer material of the PN junction device has an electron concentration of m The thermal conductivity at is the thermal conductivity of the material without doping.

[0059] S4. According to the temperature variation model and the heat distribution inside the power MOSFET device, a thermal resistance simulation model of the power MOSFET device is obtained.

[0060] After obtaining the above thermal resistance simulation model, a method for quickly obtaining the thermal resistance of a power MOSFET device using the thermal resistance simulation model is also included, and the specific steps are:

[0061] S01, obtaining the measured ambient temperature range where the thermal resistance simulation model is located, and expanding the measured ambient temperature range to obtain the simulated ambient temperature range;

[0062] S02, dividing the simulation environment temperature range according to fixed gradient change intervals to obtain multiple simulation temperature ranges;

[0063] S03. On the ANSYS Icepak thermal simulation analysis platform, each simulation temperature range is set respectively, and each simulation temperature range is brought into the thermal resistance simulation model for simulation to obtain a thermal resistance-temperature influence curve of the power MOSFET device under different ambient temperatures;

[0064] S04. Obtain the actual measured ambient temperature of the power MOSFET device to be tested, and find the thermal resistance value corresponding to the actual measured ambient temperature in the thermal resistance-temperature influence curve.

[0065] In order to better illustrate the solution of this embodiment, the following specific reasoning process is given:

[0066] This application adopts the finite element simulation method, systematically considers the influencing factors such as the internal structure of the power MOSFET device, packaging process parameters and ambient temperature, and uses the multi-layer equivalent simplification method and temperature compensation to construct a 3D simulation model that accurately reflects the internal thermal characteristics of the device. And adopts a research method that combines experimental testing with simulation analysis to verify the accuracy of the simulation model, and the model is used for thermal resistance analysis of power MOSFET devices of different packaging types. Taking the specific structural dimensions of the TO247 package of the power MOSFET device (SG100R60CFD-B8, MCPC) as an example, the specific process is:

[0067] Step 1: Draw the 3D structure: Use Solidworks software to build a 3D model of the device. The model describes the internal structure of the device in detail, including the plastic layer, solder layer, frame, chip, and heat sink.

[0068] Step 2: Import the 3D model of the device on the ANSYS Icepak thermal simulation analysis platform. By configuring the simulation environment, setting boundary conditions and material parameters, the key parameters of the main materials are set as shown in Table 1, including density, specific heat capacity SHC, thermal conductivity λ and elastic modulus E. The thermal distribution inside the plastic-encapsulated device is simulated and analyzed. The internal structure of the chip is divided into the PN junction device equivalent layer, interconnect protection layer, silicon substrate layer, gate / source top metal layer and drain bottom metal layer by using the multi-layer equivalent simplification method, and a detailed model of the chip as the heat source of the device is constructed. Under different input power conditions (10, 50, 90, 120, 160 W), the junction temperature and thermal resistance between the detailed model and the simplified model are compared. The influence of external temperature on thermal resistance simulation is further studied, and the data is temperature compensated according to the difference between the simulation setting temperature and the actual test environment temperature. The accurate thermal simulation model of the chip is used to study the variation of thermal resistance of different package types (TO247, TO247L, TO220 and TO220F), and the influence of packaging process on thermal resistance is analyzed through simulation temperature cloud diagram.

[0069] When constructing the chip finite element simulation model in this embodiment, in order to demonstrate the necessity of establishing a detailed model for the chip, the following reasoning process is proposed:

[0070] Step 2.1: Create Figure 2 Thermal analysis of the simple simulation model shown: In ANSYS software, by configuring the simulation environment and setting boundary conditions, a simple simulation model is established based on the existing common chip rough equivalent method. The simple simulation model mainly consists of two parts: packaging device and heat sink. The packaging device takes into account the influence of packaging processes and materials such as plastic packaging materials, chips, solders, frames and pins. Since the chip accounts for a small relative volume in the device, it is replaced by silicon materials of equal thickness; the heat sink uses composite metal materials for rapid transfer of chip heat, which quickly reduces the chip temperature and facilitates the simulation of the thermal resistance of the packaging device.

[0071] But as Figure 2 As shown in the figure, the simple simulation model simplifies the inside of the chip into a single-layer silicon substrate, does not consider the impact of material doping and other treatments on its thermal properties, and uniformly regards the chip as a structure of Si material structure, top metal Al, bottom back silver (Ag) layer, etc. In the simulation based on this model, the substrate part is used as the heat source of the entire device. At this time, thermal analysis of the simple model shows that the chip surface temperature is the highest, which is the heat source when the device is working; the chip shell temperature is slightly lower than the chip surface, because the heat can easily reach the shell through the heat transfer channel of the welding layer and the frame; and the upper surface temperature of the device is lower, because the thermal conductivity of the plastic packaging material is poor, and it is difficult for heat to transfer upward.

[0072] Step 2.2: When the ambient temperature is 25.0℃, load the MOSFET device with a dissipated power of 4W, and simulate and analyze the temperature distribution cloud diagram inside the device under this condition. Figure 3 As shown in the figure, the main heat transfer channel of the device is from the junction on the surface of the chip, down to the solder layer and frame, and then to the case layer on the back of the device. Therefore, the package junction-to-case thermal resistance of the MOSFET device is defined as:

[0073]

[0074] Where T J is the junction temperature of the chip surface, T C is the case temperature on the back of the device, P d is the input power, and R JC Refers to the junction-to-case thermal resistance of the device. Assuming that under certain conditions, T J is 30.87℃, shell temperature T C is 28.51℃. The thermal resistance R of the device under this condition can be calculated by formula 1. JC It is 0.59℃ / W.

[0075] Step 3, multi-layer equivalent detailed model thermal analysis: In order to construct an accurate device thermal resistance model, the internal structure of the power MOSFET is analyzed in detail. The device is mainly composed of a PN junction device equivalent layer formed by epitaxial doping, an interconnection layer of dielectric interlayer metal, a silicon substrate, a gate / source top metal, and a drain bottom metal layer. If the various details of the device are completely replicated, the complexity of the modeling will be greatly increased, resulting in too much simulation calculation. Therefore, according to the specific structure and function of the device, its internal structure is equivalently simplified into five different layers of thin films. By setting the "equivalent" characteristic parameters of each layer of material, the complexity of the modeling calculation is effectively reduced, while accurately describing the thermal channel inside the device, and realizing accurate modeling of the device.

[0076] Step 3.1, analyze the internal structure of the device: To solve the simulation-measurement comparison error problem of the simple simulation model, the simplified model is optimized by considering the detailed internal structure of the MOSFET. The internal structure of the existing typical MOSFET device mainly includes the top and bottom metal layers for realizing the conductive connection of the chip; the semiconductor substrate layer for realizing the switching function of the device (doping regions with different concentrations: N heavily doped region, N lightly doped region, P lightly doped region, gate region, substrate Si region, etc.); and the protective layer for realizing the protective insulation function.

[0077] Step 3.2, divide the multi-layer structure: If all the details of the device are completely replicated in the finite element analysis platform, the complexity of modeling will be greatly increased, resulting in too much simulation calculation. It is necessary to consider both the model complexity and model accuracy (the internal heat channel of the device refers to the various structural layers on the path that heat is transferred from the device surface to the shell). Therefore, this application simplifies the chip structure into five different thin films, corresponding to the actual structure of each functional layer, mainly including the PN junction device equivalent layer formed by epitaxial doping, the interconnection protection layer of the dielectric interlayer metal, the silicon substrate, the gate / source top metal and the drain bottom metal layer (back silver layer), such as Figure 4 When modeling, the N region and P region are simplified to be equivalent to a PN junction device equivalent layer, and the source and gate are equivalent to the top metal layer in order to reduce the calculation amount of the model.

[0078] Step 3.3, determine the size of each thin film layer: refer to the preparation process of the power MOSFET chip, and set the physical size of each layer of the chip as shown in Table 1 below.

[0079] Table 1 Physical dimensions of each chip layer

[0080]

[0081] Step 3.4, set equivalent parameters: set the doping type and doping concentration of each region in the equivalent layer of the PN junction device as shown in Table 2 below.

[0082] Table 2 Doping type and doping concentration settings

[0083]

[0084] According to the material doping theory, thermal properties, especially thermal conductivity, will change with the change of doping concentration and type. Based on the relationship diagram of doping concentration and thermal conductivity function obtained by previous experimental fitting data, the material parameter table of each thin film layer is set as shown in Table 3 below.

[0085] Table 3 Material equivalent parameter settings for power MOSFET

[0086]

[0087] Among them, according to the above material equivalent parameter settings, the corresponding test standard formula is: R jc =(T j -T c) / Pd, a more detailed thermal channel model is established on the thermal simulation platform to obtain more accurate junction temperature and shell temperature, and a thermal resistance simulation model that is closer to the actual situation is obtained. The subdivided five-layer structure is equivalent to refining the path of heat conduction absorption. Because the thermal resistance is calculated by temperature and the thermal power consumption is known, only the accurate temperature rise caused by the chip operation needs to be considered. According to heat conduction and related theories, the temperature change model caused by conduction of each layer in ANSYS calculation is as follows:

[0088] On the heat conduction path, the temperature of each point in the object will vary due to the different distances between them, and the temperature of each point will also change over time.

[0089]

[0090]

[0091]

[0092] in, It indicates the temperature change (i.e. chip junction temperature) caused by the heat generated by each layer of film in the chip structure after being dissipated through conduction. Indicates changes in temperature; T j Refers to the temperature of the equivalent layer of the PN junction device in the chip structure. T c Refers to the temperature of the package shell surface, It indicates the temperature change caused by the material of the first thin film layer from the chip surface downward. represents the temperature change caused by the material of the nth film layer, k i , ρ i , C i ,s, h i Respectively represent the equivalent material parameters of the i-th film layer: thermal conductivity, density, specific heat capacity, surface area, thickness, p d represents the applied heat power dissipation, x j Represents the distance from the jth point on the i-th film layer to the heat source.

[0093] For the equivalent layer of a PN junction device, the thermal conductivity is calculated as:

[0094]

[0095]

[0096] in, mTo consider the electron concentration of the equivalent layer material of the PN junction device after the doping concentration is considered, is the N-type doping concentration, is the P-type doping concentration, is the hole concentration of the material; Indicates that the equivalent layer material of the PN junction device has an electron concentration of m The thermal conductivity at is the thermal conductivity of the material without doping.

[0097] Step 4, analysis of the impact of ambient temperature: Since thermal resistance is an inherent property of a certain transistor product, simulation and actual measurement have proved that thermal resistance will change with changes in the test environment temperature. Since the thermal resistance in the semiconductor specification and JEDCE standard is obtained under the condition of Tc=25℃, it must be used at a reduced rating when it exceeds 25℃, that is, the impact of ambient temperature must be considered. The ambient temperature only knows the range during each actual measurement, and there is no temperature curve. Therefore, this application also studies the influence of external temperature on thermal resistance simulation. According to the difference between the simulation set temperature and the actual test environment temperature, the influence of temperature on thermal resistance (the higher the temperature, the greater the thermal resistance) and its influence curve are explored through simulation, and temperature compensation analysis is achieved through simulation. The steps are as follows:

[0098] Step 4.1, determine the possible range of the measured ambient temperature: 20-35℃, to provide a reference for the simulation temperature setting of the influence of temperature on thermal resistance;

[0099] Step 4.2, set the simulation environment gradient: 15-40℃, with a gradient change interval of 5℃, and expand the ambient temperature appropriately to facilitate the study of the influence of temperature on thermal resistance;

[0100] Step 4.3, bring different ambient temperature settings into the established accurate thermal resistance simulation model for simulation;

[0101] Step 4.4: Analyze and obtain the temperature influence curve of thermal resistance, and you can know the change of thermal resistance of power MOSFET under different ambient temperatures;

[0102] Step 4.5, determine the measured ambient temperature: 28.1℃, find the corresponding thermal resistance value in the ambient temperature-thermal resistance curve, and complete the temperature compensation of thermal resistance; not only that, but also the thermal resistance at different temperatures can be directly derived;

[0103] In summary, this application aims at the construction and experimental verification of an accurate thermal resistance simulation model for power MOSFET devices, and establishes a 3D simulation model using Solidworks and ANSYS Icepak. After thermal simulation analysis, the necessity of establishing an accurate chip simulation model is demonstrated. By analyzing the internal structure of the power MOSFET chip, an equivalent method is used to establish a thermal resistance simulation model that reflects the internal structure of the chip. Compared with the existing simplified model, the model more accurately describes the chip junction temperature and thermal resistance. At the same time, the influence of external temperature on the thermal resistance test is also found, and the simulation results are temperature compensated. After compensation, the thermal resistance simulation value is highly consistent with the actual measured value. Using the accurate thermal resistance simulation model, the thermal resistance influence mechanism of different packaging types is compared and analyzed, and the influence of plastic package volume, pin length and back heat dissipation volume on thermal resistance is analyzed. This study establishes an accurate 3D model for thermal resistance simulation of power devices, providing strong technical support for the optimization design of packaging processes.

[0104] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. According to the technical essence of the present invention, within the spirit and principles of the present invention, any simple modification, equivalent replacement and improvement made to the above embodiment still falls within the protection scope of the technical solution of the present invention.

Claims

1. A method for constructing a thermal resistance simulation model of a power MOSFET device, characterized in that: The specific steps include: S1. Draw a corresponding three-dimensional model according to the packaging structure of the power MOSFET device, and import the three-dimensional model into the ANSYS Icepak thermal simulation analysis platform; S2. According to the three-dimensional model, simulate and analyze the heat distribution inside the power MOSFET device, use the multi-layer equivalent simplification method to equivalently simplify the chip structure inside the power MOSFET device into five layers of thin films, set equivalent characteristic parameters of each layer, and construct a finite element simulation model of the chip as a heat source of the power MOSFET device; The five layers of thin films include: a PN junction device equivalent layer formed by epitaxial doping, an interconnect protection layer of the dielectric interlayer metal, a silicon substrate layer, a gate / source top metal layer, and a drain bottom metal layer; The specific process of constructing the chip finite element simulation model in step S2 is: S21, simplifying the chip structure inside the power MOSFET device into five different thin films according to the actual functional layer structure; S22, setting the physical dimensions of each layer of film according to the manufacturing process of the chip structure; S23, setting equivalent characteristic parameters of each layer of thin film, the equivalent characteristic parameters including material parameters of each layer of thin film and doping type and doping concentration of each region of the equivalent layer of the PN junction device, to obtain a finite element simulation model of the chip; S3. Build a thermal resistance test environment, apply thermal power consumption to the chip finite element simulation model, and simulate the temperature of each film layer in a set temperature environment to obtain a temperature change model of the chip finite element simulation model; S4. According to the temperature variation model and the heat distribution inside the power MOSFET device, a thermal resistance simulation model of the power MOSFET device is obtained.

2. The method for constructing a thermal resistance simulation model of a power MOSFET device according to claim 1, characterized in that: The temperature change model of the chip finite element simulation model in step S3 includes the temperature change caused by conduction of each film layer, and the calculation process is: in, It indicates the temperature change caused by the heat generated by each layer of film in the chip structure and dissipated through conduction. It indicates the temperature change caused by the material of the first thin film layer from the chip surface downward. represents the temperature change caused by the material of the nth film layer, k i , ρ i , C i ,s, h i Respectively represent the equivalent material parameters of the i-th film layer: thermal conductivity, density, specific heat capacity, surface area, thickness, p d represents the applied heat power dissipation, x j represents the distance from the jth point on the i-th film layer to the heat source, x ( n- 1) represents the distance from the n-1th point on the i-th film layer to the heat source, x Represents the coordinates of points on the heat conduction path in the chip structure x value.

3. The method for constructing a thermal resistance simulation model of a power MOSFET device according to claim 1, characterized in that: For the equivalent layer of a PN junction device, the thermal conductivity is calculated as: in, m To consider the electron concentration of the equivalent layer material of the PN junction device after the doping concentration is considered, is the N-type doping concentration, is the P-type doping concentration, is the hole concentration of the material; Indicates that the equivalent layer material of the PN junction device has an electron concentration of m The thermal conductivity at is the thermal conductivity of the material without doping.

4. The method for constructing a thermal resistance simulation model of a power MOSFET device according to claim 2, characterized in that: The invention also includes a method for quickly obtaining the thermal resistance of a power MOSFET device by using the thermal resistance simulation model, the specific steps of which are: S01, obtaining the measured ambient temperature range where the thermal resistance simulation model is located, and expanding the measured ambient temperature range to obtain the simulated ambient temperature range; S02, dividing the simulation environment temperature range according to fixed gradient change intervals to obtain multiple simulation temperature ranges; S03. On the ANSYS Icepak thermal simulation analysis platform, each simulation temperature range is set respectively, and each simulation temperature range is brought into the thermal resistance simulation model for simulation to obtain a thermal resistance-temperature influence curve of the power MOSFET device under different ambient temperatures; S04. Obtain the actual measured ambient temperature of the power MOSFET device to be tested, and find the thermal resistance value corresponding to the actual measured ambient temperature in the thermal resistance-temperature influence curve.

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