Signal positioning method, device and equipment in circuit design file and medium

Abstract

The application provides a signal positioning method and device in a circuit design file, electronic equipment and a readable storage medium, comprising: obtaining a signal name of a signal to be debugged; determining a target source code module and a target compiled code module matched with the signal name of the signal to be debugged according to a first correspondence relationship among a source code module, a compiled code module and the signal name of the signal; determining a target source code file and a target compiled code file matched with the target source code module according to a second correspondence relationship between a source code file and the source code module and a third correspondence relationship between a compiled code file and the compiled code module; performing syntax analysis to obtain a first line number of the signal to be debugged in the target source code file and a second line number of the signal to be debugged in the target compiled code file; and displaying the signal name of the signal to be debugged, the first line number and the second line number in a display area for waveform debugging of the signal to be debugged, so as to improve the efficiency of waveform debugging.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computers, and in particular to a signal positioning method and device in a circuit design file, an electronic device, and a computer readable storage medium. BACKGROUND

[0002] A hardware construction language (Chisel, Constructing Hardware in a Scala Embedded Language) embedded in a high-level programming language Scala allows designers to use the features and abstractions of a high-level programming language to generate hardware descriptions. For a Chisel source code file written, it is necessary to compile it into a Verilog code file, and then simulate the Verilog code file through a simulation tool to generate a waveform.

[0003] In related technologies, when debugging a waveform, the waveform can be mapped to a Verilog code, so that the Chisel source code corresponding to the Verilog code is manually searched according to the Verilog code, so as to adjust the Chisel source code.

[0004] However, when manually searching for the Chisel source code corresponding to the Verilog code, a lot of time is consumed and the efficiency is low. SUMMARY

[0005] Embodiments of the present application provide a signal positioning method and device in a circuit design file, an electronic device, and a computer readable storage medium to solve the problems in related technologies.

[0006] In a first aspect, embodiments of the present application provide a signal positioning method in a circuit design file, and the method comprises:

[0007] Obtaining a signal name of a signal to be debugged in a circuit design file, and determining a target source code module and a target compiled code module matched with the signal name of the signal to be debugged according to a first correspondence relationship of a signal belonging to a source code module, a signal belonging to a compiled code module, and the signal name of the signal.

[0008] According to a second correspondence relationship of a source code file and a source code module, a target source code file matched with the target source code module is determined, and according to a third correspondence relationship of a compiled code file and a compiled code module, a target compiled code file matched with the target compiled code module is determined.

[0009] The target source code file and the target compiled code file are respectively subjected to syntax analysis, and a first line number of the signal to be debugged in the target source code file and a second line number of the signal to be debugged in the target compiled code file are obtained.

[0010] The signal name of the signal to be debugged, the first line number, and the second line number are displayed in a display area for waveform debugging of the signal to be debugged.

[0011] In a second aspect, an embodiment of the present application provides a signal positioning device in a circuit design file, and the device comprises:

[0012] A first determining module is configured to acquire a signal name of a signal to be debugged in a circuit design file, and determine a target source code module and a target compiled code module matched with the signal name of the signal to be debugged according to a first correspondence relationship among a source code module to which the signal belongs, a compiled code module to which the signal belongs, and the signal name of the signal.

[0013] A second determining module is configured to determine a target source code file matched with the target source code module according to a second correspondence relationship between a source code file and a source code module, and determine a target compiled code file matched with the target compiled code module according to a third correspondence relationship between a compiled code file and a compiled code module.

[0014] A first syntax analysis module is configured to perform syntax analysis on the target source code file and the target compiled code file respectively, and obtain a first line number of the signal to be debugged in the target source code file and a second line number of the signal to be debugged in the target compiled code file.

[0015] A display module is configured to display the signal name of the signal to be debugged, the first line number, and the second line number in a display area for waveform debugging of the signal to be debugged.

[0016] In a third aspect, an embodiment of the present application further provides an electronic device, comprising a processor, and a memory configured to store instructions executable by the processor, wherein the processor is configured to execute the instructions to implement the method in the first aspect.

[0017] In a fourth aspect, an embodiment of the present application further provides a computer readable storage medium, when instructions in the computer readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to execute the method in the first aspect.

[0018] In the embodiment of the present application, according to the first correspondence relationship of the source code module to which the signal belongs, the compiled code module to which the signal belongs, and the signal name of the signal, the target source code module and the target compiled code module matching the signal name of the signal to be debugged are determined, and according to the second correspondence relationship of the source code file and the source code module, the target source code file matching the target source code module is determined, and according to the third correspondence relationship of the compiled code file and the compiled code module, the target compiled code file matching the target compiled code module is obtained, so as to obtain the target source code file and the target compiled code file to which the signal to be debugged belongs. Then, the target source code file and the target compiled code file are respectively subjected to syntax analysis, the first line number of the signal to be debugged in the target source code file and the second line number of the signal to be debugged in the target compiled code file are obtained, and the signal name, the first line number, and the second line number of the signal to be debugged are displayed in the display area, so as to perform waveform debugging on the signal to be debugged. By intuitively displaying the signal to be debugged in the source code file and the signal to be debugged in the compiled code, manual searching for the source code corresponding to the compiled code is not needed, and the efficiency of waveform debugging can be greatly improved.

[0019] The above description is only a summary of the technical solutions of the present application. In order to more clearly understand the technical means of the present application, the content of the specification can be implemented, and in order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the following specific embodiments of the present application are described. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0021] Figure 1 is a step flow chart of a signal positioning method in a circuit design file provided by the embodiment of the present application;

[0022] Figure 2 is a display interface diagram provided by the embodiment of the present application;

[0023] Figure 3 is a specific step flow chart of a signal positioning method in a circuit design file provided by the embodiment of the present application;

[0024] Figure 4 is a step flow chart of displaying a signal to be debugged provided by the embodiment of the present application;

[0025] Figure 5is a step flow chart of adding a to-be-debugged signal into a waveform region provided by an embodiment of the present application;

[0026] Figure 6 is a block diagram of a signal positioning device in a circuit design file provided by an embodiment of the present application;

[0027] Figure 7 is a block diagram of an electronic device provided by an embodiment of the present application;

[0028] Figure 8 is a block diagram of another electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0030] The terms "first", "second", and the like in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally a category, not limited to the number of objects, for example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B can represent: A exists alone, A and B exist together, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects. The term "multiple" in the embodiments of the present application means two or more, and other quantifiers are similar.

[0031] Figure 1 is a step flow chart of a signal positioning method in a circuit design file provided by an embodiment of the present application, as shown in Figure 1 The method can include the following steps.

[0032] In step 101, the signal name of a to-be-debugged signal in a circuit design file is acquired, and a target source code module and a target compiled code module matched with the signal name of the to-be-debugged signal are determined according to a first correspondence relationship of a source code module to which the signal belongs, a compiled code module to which the signal belongs, and the signal name of the signal.

[0033] In an example, in digital circuit design and hardware description language, a signal is a basic element for passing data between modules. A signal can represent various types of data, including but not limited to bits, vectors, registers, etc. Signals transmit data within and between modules, and are the basis for building complex digital systems.

[0034] In an example, the source code can be written using the Chisel language to describe hardware construction. Chisel is an open source hardware construction language released by the University of Berkeley, which is built on the Scala language and is an application of Scala domain-specific language, with highly parameterized generators that can support high-level hardware design. The advantage of writing code using Chisel is that complex hardware design can be more conveniently implemented, and the pattern matching and function composition features of Scala enable Chisel to conveniently reuse code to improve development efficiency. The compiled code can be written using the Verilog language. The register transfer level (RTL) written in Chisel is an abstraction level in hardware design, between gate level description and high-level hardware description language (such as Verilog). At the RTL level, designers can define registers, combinational logic, state machines, etc. without delving into specific gate level implementation details. Usually, the file written in Chisel language needs to be compiled into a Verilog file, so that the simulation tool simulates the Verilog file to generate waveforms.

[0035] In an example, the first correspondence includes a correspondence between a source code module to which the signal belongs and a signal name of the signal, and a correspondence between a compiled code module to which the signal belongs and the signal name of the signal. According to the correspondence between the source code module to which the signal belongs and the signal name of the signal, the target source code module matching the signal name of the to-be-debugged signal is determined. According to the correspondence between the compiled code module to which the signal belongs and the signal name of the signal, the target compiled code module matching the signal name of the to-be-debugged signal is determined.

[0036] In an example, the source code module can be a source code module name, or can include a source code module name and a source code instantiation name. The compiled code module can be a compiled code module name, or can include a compiled code module name and a compiled code instantiation name. The module name is a name used when defining a module, which is an identifier used to describe the function and interface of the module, and the same module name can be used repeatedly in multiple places. The instantiation name is a name specified for an already defined module when instantiating it in a top-level module or other module, which is an identifier, and different instantiation names can be specified for the same module in the same design to distinguish different instances of the same module, and each instance of the module is uniquely identified during simulation and debugging.

[0037] In step 102, a target source code file matching the target source code module is determined according to the second correspondence between the source code files and the source code modules, and a target compiled code file matching the target compiled code module is determined according to the third correspondence between the compiled code files and the compiled code modules.

[0038] In an example, the source code module includes a source code module name and a source code instantiation name, and the source code file is taken as an example of a source code file name. The second correspondence can be a correspondence between the module name and the instantiation name and the source code file name. Specifically, a syntax analysis tool is used to perform syntax analysis on the source code file to obtain all the module names and instantiation names in the source code file. After obtaining all the module names and instantiation names in the source code file, the second correspondence between the module name and the instantiation name and the source code file name is established. In this way, after obtaining the module name of the to-be-debugged signal, the target source code file name is obtained according to the second correspondence between the module name and the instantiation name and the source code file name, so that the target source code file is found according to the target source code file name.

[0039] In an example, after the syntax analysis tool is used to perform syntax analysis on the source code file to obtain all the module names and instantiation names in the source code file, a mapping relationship of a signal hierarchy structure of the source code file is generated. The signal hierarchy structure refers to an organization manner of signals in a module and a hierarchical design, and a hierarchical path is used to uniquely identify a signal or a module in the hierarchy structure. The path is usually composed of a module instantiation name and a signal name, and is separated by a dot. For example, the instantiation name of the top-level module is top, the top instantiates a counter, and the counter has a signal clk. The hierarchy structure of the signal clk is top.counter.clk, which is unique in the entire waveform. By taking top.counter as a key of the map and taking the Verilog file name as a value, a mapping relationship between top.counter and Verilog is established, which facilitates analysis.

[0040] In an example, the compiled code module includes a compiled code module name and a compiled code instantiation name, and the compiled code file is a compiled code file name. The third correspondence relationship can be a correspondence relationship between the module name and the instantiation name and the compiled code file name. Specifically, a syntax analysis tool is used to perform syntax analysis on the compiled code file to obtain all module names and instantiation names in the compiled code file. After obtaining all the module names and instantiation names in the compiled code file, the third correspondence relationship between the module name and the instantiation name and the compiled code file name is established. In this way, after obtaining the module name of the to-be-debugged signal, the target compiled code file name is obtained according to the third correspondence relationship between the module name and the instantiation name and the compiled code file name, so that the target compiled code file is found according to the target compiled code file name.

[0041] In an example, after the syntax analysis tool is used to perform syntax analysis on the compiled code file to obtain all the module names and instantiation names in the compiled code file, a mapping relationship of a signal hierarchy structure of the compiled code file is generated. For example, the instantiation name of the top-level module is top, the top instantiates the counter, the counter has the signal clk, and the hierarchy structure of the signal clk is top.counter.clk, which is unique in the entire waveform. By taking top.counter as the key of the map and taking the file name of Chisel as the value, a mapping relationship between top.counter and Chisel is established, so that analysis can be conveniently performed.

[0042] In step 103, the target source code file and the target compiled code file are respectively subjected to syntax analysis to obtain a first line number of the to-be-debugged signal in the target source code file and a second line number of the to-be-debugged signal in the target compiled code file.

[0043] In an example, the syntax analysis can be to obtain the line number of the signal according to a syntax tree, and generally needs to combine a visitor mode or a listener mode parsed by a syntax analysis tool to traverse the syntax tree and extract the required line number information. For example, the syntax analysis tool can be an ANTLR tool.

[0044] In an example, the syntax analysis process includes generating a syntax tree, defining a syntax rule, traversing the syntax tree, and extracting a variable name and a line number. In the step of generating the syntax tree, first, an ANTLR syntax analysis tool is used to generate a lexical analyzer and a syntax analyzer according to a syntax rule of a language.

[0045] Then, the code is input into the generated parser to generate a syntax tree. In defining the syntax rules, the syntax rules of variable declaration are defined in the syntax rule file (such as a.g4 file). For example, variableDeclaration : type IDENTIFIER ';';, where type represents the variable type and IDENTIFIER represents the variable name. In traversing the syntax tree, the variable information is extracted by implementing the visitor interface to traverse the syntax tree. By implementing the listener interface, an event is triggered when entering or exiting a specific syntax node. In extracting the variable name and line number, the variable declaration node is identified when traversing the syntax tree, and the variable name and line number are extracted.

[0046] At step 104, the signal name of the to-be-debugged signal, the first line number, and the second line number are displayed in a display area for waveform debugging of the to-be-debugged signal.

[0047] For example, after obtaining the first line number of the to-be-debugged signal in the target source code file and the second line number of the to-be-debugged signal in the target compiled code file, the cursor is automatically jumped to the positions of the first line number and the second line number of the signal, and the positions of the first line number and the second line number are highlighted. That is, the signal name of the to-be-debugged signal is highlighted at the positions of the first line number and the second line number. For details, refer to Figure 2 The highlighted part is represented by a shadow box, and the shadow box part is the to-be-debugged signal A.

[0048] In summary, in the embodiment of the present application, the target source code module and the target compiled code module matching the signal name of the to-be-debugged signal are determined according to the first correspondence relationship of the signal name, the source code module to which the signal belongs, and the compiled code module to which the signal belongs. The target source code file matching the target source code module is determined according to the second correspondence relationship of the source code file and the source code module, and the target compiled code file matching the target compiled code module is obtained according to the third correspondence relationship of the compiled code file and the compiled code module, so as to obtain the target source code file and the target compiled code file to which the to-be-debugged signal belongs. Then, the target source code file and the target compiled code file are subjected to syntax analysis respectively to obtain the first line number of the to-be-debugged signal in the target source code file and the second line number of the to-be-debugged signal in the target compiled code file. The signal name of the to-be-debugged signal, the first line number, and the second line number are displayed in a display area for waveform debugging of the to-be-debugged signal. By intuitively displaying the to-be-debugged signal in the source code file and the to-be-debugged signal in the compiled code, manual searching for the source code corresponding to the compiled code is not needed, and the efficiency of waveform debugging can be greatly improved.

[0049] Figure 3is a specific step flow chart of a signal positioning method in a circuit design file provided by the embodiment of the present application, as shown in the figure, the method can include: Figure 3

[0050] Step 201, the signal name of the signal to be debugged in the circuit design file is obtained, and according to the first corresponding relationship of the signal name of the signal belonging to the source code module, the signal belonging to the compiled code module and the signal, the target source code module and the target compiled code module matched with the signal name of the signal to be debugged are determined.

[0051] This step can refer to the above-mentioned step 101, and will not be described in detail here.

[0052] Step 202, according to the second corresponding relationship between the source code file and the source code module, the target source code file matched with the target source code module is determined, and according to the third corresponding relationship between the compiled code file and the compiled code module, the target compiled code file matched with the target compiled code module is determined.

[0053] This step can refer to the above-mentioned step 102, and will not be described in detail here.

[0054] Step 203, respectively, the target source code file and the target compiled code file are subjected to syntax analysis, and the first line number of the signal to be debugged in the target source code file and the second line number of the signal to be debugged in the target compiled code file are obtained.

[0055] This step can refer to the above-mentioned step 103, and will not be described in detail here.

[0056] Step 203 can specifically include:

[0057] Substep 2031, obtaining the first syntax tree corresponding to the first design language of the target source code file and the second syntax tree corresponding to the second design language of the target compiled code file;

[0058] Substep 2032, in the first syntax tree, the first position where the node corresponding to the signal to be debugged is located is found, and the first line number is determined according to the first position;

[0059] Substep 2033, in the second syntax tree, the second position where the node corresponding to the signal to be debugged is located is found, and the second line number is determined according to the second position.

[0060] ​For sub-step 2031-sub-step 2033, the first design language can be Chisel language, and the second design language can be Verilog language. For the generation process of the second syntax tree, first, a verilog lexer object is created, then the input Verilog code is decomposed into a series of lexical units, and finally the lexical unit stream is parsed and the second syntax tree is generated. The generation of the first syntax tree is similar to the generation of the second syntax tree, and is not described in detail. Specifically, a syntax analysis tool such as ANTLR is used to generate a lexical analyzer and a syntax analyzer according to the language syntax rules, and the source code is input into the generated lexical analyzer and syntax analyzer to parse the source code and generate a syntax tree.

[0061] After the first syntax tree and the second syntax tree are generated, the first line number and the second line number can be obtained according to the first syntax tree and the second syntax tree. Specifically, taking the first line number obtained according to the first syntax tree as an example, it is usually necessary to combine a syntax analysis tool and a visitor pattern or a listener pattern to traverse the syntax tree and extract the required information. The visitor interface is implemented through the visitor pattern, the syntax tree is traversed and the variable information is extracted. The listener interface is implemented through the listener pattern, and an event is triggered when entering or exiting a specific syntax node. When traversing the syntax tree, the variable declaration node is identified, and the variable name and the line number are extracted.

[0062] Step 204, opening the target source code file in the first display area, and automatically jumping to the position of the first line number, and highlighting the signal name of the to-be-debugged signal at the position of the first line number for waveform debugging of the to-be-debugged signal.

[0063] For example, after the server obtains the target source code file and the first line number of the to-be-debugged signal, the server sends the target source code file and the first line number to the client. After the client receives the response from the server, the Chisel code is displayed, and the cursor automatically jumps to the position of the first line number corresponding to the signal. The Chisel code highlights the position of the first line number in response, that is, the signal name of the to-be-debugged signal is highlighted at the position of the first line number. Referring to Figure 2 , the first display area can be located Figure 2 lower left, for displaying source code. Figure 2 The shadow box part is the corresponding signal A in the Chisel source code.

[0064] For example, the upper area of the first display area has a search button 21. In response to a click operation on the search button 21 of the upper area of the first display area, the signal name of the signal to be queried is input into the search box corresponding to the first display area, and then the source code file to which the signal to be queried belongs is opened in the first display area, and the signal to be queried is automatically jumped to the position of the signal to be queried, and the signal name of the signal to be debugged and the context content of the signal to be debugged are highlighted at the position of the signal to be queried.

[0065] Step 205, opening the target compiled code file in the second display area, and automatically jumping to the position of the second line number, and highlighting the signal name of the signal to be debugged at the position of the second line number for waveform debugging of the signal to be debugged.

[0066] For example, after the server obtains the target source code file to which the signal to be debugged belongs and the second line number, the target source code file and the second line number are sent to the client. After the client receives the response of the server, the Verilog code is displayed, and the cursor is automatically jumped to the position of the second line number corresponding to the signal. The Verilog code highlights the position of the second line number, that is, the signal name of the signal to be debugged is highlighted at the position of the second line number. Referring to Figure 2 The second display area can be located Figure 2 in the lower right corner of the Verilog code display area, and is used to display the compiled code. In the figure, the shaded box represents the highlighted part, and the shaded box part is the corresponding signal A in the Verilog compiled code.

[0067] For example, the upper area of the second display area has a search button 21. In response to a click operation on the search button 21 of the upper area of the second display area, the signal name of the signal to be queried is input into the search box corresponding to the second display area, and then the source code file to which the signal to be queried belongs is opened in the first display area, and the signal to be queried is automatically jumped to the position of the signal to be queried, and the signal name of the signal to be debugged and the context content of the signal to be debugged are highlighted at the position of the signal to be queried.

[0068] Optionally, the method further comprises:

[0069] Step 206, obtaining a source code file and a compiled code file; the compiled code file is generated by compiling the source code in the source code file;

[0070] Step 207, performing syntax analysis on the source code file and the compiled code file respectively to obtain a source code module corresponding to the source code file and a compiled code module corresponding to the compiled code file;

[0071] Step 208, establishing a first correspondence relationship among the source code module, the compiled code module, and the signal name of the signal;

[0072] Step 209, establishing a second correspondence relationship between the source code file and the source code module, and a third correspondence relationship between the compiled code file and the compiled code module.

[0073] For steps 206-209, the source code file can be a Chisel file, and the compiled code file can be a Verilog file. The Verilog file is obtained by converting the code in the Chisel file. Syntax analysis has various tools, including but not limited to self-developed code for parsing, using tools such as ANTLR, bison, flex, pyparsing, etc. Take ANTLR as an example for a simple explanation. Create an ANTLR grammar file, i.e. a g4 file, to define the syntax structure of the language to be parsed. Use the ANTLR tool to generate parser code, which will be used to parse Scala code and build an abstract syntax tree. Write code to traverse the generated syntax tree to extract module information, signal names, instantiation information, etc.

[0074] For example, after generating the source code module and the compiled code module, a first correspondence relationship among the source code module, the compiled code module, and the signal name of the signal is established, a second correspondence relationship between the source code file and the source code module is established, and a third correspondence relationship between the compiled code file and the compiled code module is established, so that according to the first, second, and third correspondence relationships, the target source code file and the target compiled code file to which the to-be-debugged signal belongs are obtained.

[0075] Optionally, step 206 can specifically include:

[0076] Sub-step 2061, obtaining the path of the source code file and the path of the compiled code file;

[0077] Sub-step 2062, finding the source code file according to the path of the source code file, and finding the compiled code file according to the path of the compiled code file.

[0078] For sub-steps 2061-2062, a web application usually adopts a browser / server (B / S, Browser / Server) architecture, under which a user accesses an application through a browser, and a server handles all business logic and data storage. This architecture makes the web application have good scalability and maintainability. If a web application is used, the waveform is displayed on the browser side, the browser can send an http request to the server, and the server uses a programming language to obtain the path of the source code file and the path of the compiled code file through syntax analysis tools according to the parameters carried by the http request.

[0079] Specifically, the http request is used to obtain the source code file and the compiled code file. The http request can include a request parameter filelist and a request parameter chiselfilelist. The request parameter filelist contains paths of all the compiled code files, and the request parameter chiselfilelist contains paths of all the source code files. The http request can also include a signal name of a signal to be debugged. After obtaining the paths of the source code files and the paths of the compiled code files, the source code files and the compiled code files are found according to the paths of the source code files and the paths of the compiled code files.

[0080] The common application usually adopts a client / server (C / S) architecture, a user directly runs an application program on a local device, a server mainly processes data storage and part of business logic, and the server can also run in an offline state. The application can be developed by using a language such as c++ or rust, and an interface and a service are completed in one application. When a user selects a signal to be debugged, a corresponding function can be called in the application, and a path of a source code file and a path of a compiled code file are obtained through syntax analysis by using a syntax analysis tool.

[0081] Optionally, step 207 can specifically include:

[0082] Substep 2071, a first syntax tree corresponding to a first design language of the target source code file and a second syntax tree corresponding to a second design language of the target compiled code file are obtained.

[0083] Substep 2072, in the first syntax tree, a module node and a file node to which a node corresponding to the signal to be debugged belongs are found, a module corresponding to the module node is taken as the source code module, and a file corresponding to the file node is taken as the source code file.

[0084] Substep 2073, in the second syntax tree, a module node and a file node to which a node corresponding to the signal to be debugged belong are found, a module corresponding to the module node is taken as the compiled code module, and a file corresponding to the file node is taken as the compiled code file.

[0085] For sub-step 2071-sub-step 2073, the first design language can be Chisel language, and the second design language can be Verilog language. For the generation process of the syntax tree, first, a verilog lexer object is created, then the input Verilog code is decomposed into a series of lexical units, and finally, the lexical unit stream is parsed and the second syntax tree is generated. Specifically, a syntax analysis tool such as ANTLR is used to generate a lexical analyzer and a syntax analyzer according to the language syntax rules, and the source code is input into the generated lexical analyzer and syntax analyzer to parse the source code and generate a syntax tree.

[0086] For example, after generating the first syntax tree and the second syntax tree, the first syntax tree and the second syntax tree are traversed respectively to obtain the corresponding modules in the first syntax tree and the second syntax tree respectively. Specifically, a custom visitor class can be defined to traverse the modules corresponding to the first syntax tree and the second syntax tree respectively through the ANTLR tool to obtain the module nodes and file nodes to which the nodes corresponding to the signals to be debugged in the first syntax tree belong, and the module nodes and file nodes to which the nodes corresponding to the signals to be debugged in the second syntax tree belong. The module nodes can include module information and instantiation information. The module information and instantiation information corresponding to the module nodes in the first syntax tree are taken as source code modules, the file corresponding to the file nodes is taken as a source code file, and the module information and instantiation information corresponding to the module nodes in the second syntax tree are taken as compiled code modules, and the file corresponding to the file nodes is taken as a compiled code file.

[0087] Optionally, step 207 can further include:

[0088] Sub-step 2074: obtaining a first temporary file corresponding to the source code file and a second temporary file corresponding to the compiled code file; the first temporary file is a file generated by replacing the hyperparameter values in the source code file; and the second temporary file is a file generated by replacing the hyperparameter values in the compiled code file;

[0089] Sub-step 2075: performing syntax analysis on the first temporary file to obtain the source code module;

[0090] Sub-step 2076: performing syntax analysis on the second temporary file to obtain the compiled code module.

[0091] For sub-step 2074-sub-step 2076, after obtaining the source code file and the compiled code file, the source code file and the compiled code file are preprocessed according to the include information and the define information to generate a first temporary file and a second temporary file. For example, there are two files, a top.v file and a defines.vh file. The defines.vh file defines some macros. The preprocessing is to replace the macros in the top.v file with the actual values in the defines.vh file according to the included file. For example, the macros defined in the defines.vh file can be as follows:

[0092] / / defines.vh

[0093] `define CLK_PERIOD 10

[0094] `define RESET_HOLD_TIME 10

[0095] `define SIMULATION_TIME 100

[0096] The content of the top.v file can include:

[0097] top.v

[0098] / / top.v

[0099] `include "defines.vh"

[0100] For example, the temporary file is divided into modules. According to the syntax analysis, all module names and instantiation names, file names are parsed and cached. According to chiselfilelist, all Scala files are parsed, each class is parsed, all module names and instantiation names, file names are parsed and cached. According to the signal name, the signal hierarchy is divided, it is found which module the signal belongs to, the.v or.sv file corresponding to the module is found in the cache, syntax analysis is performed, and the file name and line number corresponding to the signal are parsed. According to the signal hierarchy, the corresponding class is found, the Chisel file is parsed, the signal name corresponding file and line number are obtained, and the Chisel file and the Verilog file are returned to the front end.

[0101] Optionally, the method further includes:

[0102] Step 210, according to a preset configuration, determining a target signal in all signals as a to-be-debugged signal;

[0103] Step 211: In response to the selection operation of all signals except the target signal, the selected signal is taken as the new signal to be debugged and the new signal to be debugged is displayed in the display area.

[0104] For steps 210-211, the preset configuration includes the signals already displayed in the display area, and these displayed signals are identified as signals to be debugged. Taking signals A and B as an example, if signal C is to be displayed, signal C is designated as a new signal to be debugged, and a double-click operation is performed to display signal C in the display area. This application eliminates the need for manual searching of signals in Chisel files or Verilog files to add signals to the display area when viewing the Chisel source code.

[0105] Optionally, the display area includes a signal name area, a signal value display area, and a waveform display area; the signal name area displays the signal names of each existing signal in the circuit design document; step 211 may specifically include:

[0106] Sub-step 2111: Select a signal from the signal name region as a new signal to be debugged;

[0107] Sub-step 2112: Display the signal name and value of the new signal to be debugged in the signal value display area, and display the waveform of the new signal to be debugged in the waveform display area.

[0108] For sub-steps 2111-2112, such as Figure 2 As shown, Figure 2 The waveform display includes three areas: a signal name area, a signal value display area, and a waveform display area. The signal value display area shows the signal's value, and the waveform display area shows the signal's value at different times; the graph formed by these values ​​is the signal's waveform. Selecting a signal as a new signal to be debugged in the signal name area allows you to double-click the new signal to be debugged and add it to the waveform display area. The signal value display area shows the value of the newly selected signal to be debugged at a specified time. When adding a signal from Chisel source code to the waveform, the signal hierarchy is obtained through syntax parsing, and then the signal is added to the waveform. Simultaneously, the corresponding Verilog source code file and line number are located based on the signal hierarchy, and the waveform display area will jump to and highlight the corresponding Verilog source code file and line number. Similarly, when adding a signal from a Verilog source file to the waveform, the signal hierarchy is obtained through syntax parsing, and then the signal is added to the waveform. The Chisel source code file and line number are located based on the signal hierarchy, and the waveform display area will jump to and highlight the corresponding Chisel source code file and line number.

[0109] For example, the waveform file records the change of each signal in the simulation process, and the waveform needs to be debugged and verified. The signal of interest is added to the waveform tool to check whether the signal change meets the expectation.

[0110] Optionally, the method further comprises:

[0111] In step 212, if the to-be-debugged signal is an intermediate variable, the signal to which the to-be-debugged signal is assigned is found from all signals according to the assignment relationship, the signal to which the to-be-debugged signal is assigned is determined as the to-be-debugged signal, and the step of obtaining the signal name of the to-be-debugged signal in the circuit design file is entered.

[0112] For example, the intermediate variable is a variable in the Verilog code that is not present in the Chisel code and is not a name converted according to a certain rule, but is a variable generated additionally in the conversion process. If the signal is an intermediate variable generated by Verilog, the target variable to which the variable is assigned is found according to syntax analysis, and the Chisel file is searched. If the Chisel file is not found, the process is looped.

[0113] In summary, in the embodiments of the present application, the target source code module and the target compiled code module matched with the signal name of the to-be-debugged signal are determined according to the first correspondence relationship of the signal name, the source code module to which the signal belongs, and the compiled code module to which the signal belongs, the target source code file matched with the target source code module is determined according to the second correspondence relationship of the source code file and the source code module, and the target compiled code file matched with the target compiled code module is obtained according to the third correspondence relationship of the compiled code file and the compiled code module, so as to obtain the target source code file and the target compiled code file to which the to-be-debugged signal belongs. Then, the target source code file and the target compiled code file are subjected to syntax analysis respectively, the first line number of the to-be-debugged signal in the target source code file and the second line number of the to-be-debugged signal in the target compiled code file are obtained, and the signal name, the first line number, and the second line number of the to-be-debugged signal are displayed in the display area, so as to perform waveform debugging on the to-be-debugged signal. By directly displaying the to-be-debugged signal in the source code file and the to-be-debugged signal in the compiled code, the source code corresponding to the compiled code does not need to be searched manually, and the efficiency of waveform debugging can be greatly improved.

[0114] Figure 4 is a step flowchart for displaying a to-be-debugged signal provided by the embodiments of the present application, referring to Figure 4 The step can specifically include:

[0115] Step S1, load the waveform file to the display area. The format of the waveform file can be vcd format, fst format or other formats, which are not limited in the present application.

[0116] Step S2, select the signal to be debugged and obtain the source code file and the compiled code file.

[0117] Step S3, preprocess and syntax analyze the source code file and the compiled code file to obtain the signal hierarchy structure corresponding to the source code file and the compiled code file respectively.

[0118] Step S4, obtain the target compiled code file corresponding to the signal to be debugged and the second line number according to the signal hierarchy structure of the compiled code file.

[0119] Step S5, judge whether the signal to be debugged is an intermediate signal, if yes, jump to step S6, otherwise, jump to step S9.

[0120] Step S6, find the signal assigned by the signal to be debugged according to the syntax analysis.

[0121] Step S7, judge whether the signal assigned by the signal to be debugged is found, if yes, jump to step S8, otherwise, jump to step S6.

[0122] Step S8, determine the signal assigned by the signal to be debugged as the signal to be debugged.

[0123] Step S9, obtain the target source code file corresponding to the signal to be debugged and the first line number according to the signal hierarchy structure of the source code file.

[0124] Step S10, open the target source code file in the display area, automatically jump to the position of the first line number, highlight the signal name of the signal to be debugged at the position of the first line number, open the target compiled code file, automatically jump to the position of the second line number, and highlight the signal name of the signal to be debugged at the position of the second line number.

[0125] Figure 5 is a step flow chart provided by the embodiment of the present application for adding the signal to be debugged to the waveform area, referring to Figure 5 , the step can specifically include:

[0126] Step M1, obtain the signal to be debugged in the source code file.

[0127] Step M2, syntax analyze the source code file to obtain the hierarchy structure of the signal to be debugged.

[0128] Step M3, according to the hierarchy of the to-be-debugged signal, obtaining the compiled code module corresponding to the to-be-debugged signal, and performing syntax analysis on the compiled code file to which the compiled code module belongs to obtain a second line number.

[0129] Step M4, adding the to-be-debugged signal to the waveform, and jumping to the position of the second line number to display the signal name of the to-be-debugged signal and the second line number.

[0130] In the embodiment of the application, according to the first correspondence relationship among the source code module to which the signal belongs, the compiled code module to which the signal belongs, and the signal name of the signal, the target source code module and the target compiled code module matched with the signal name of the to-be-debugged signal are determined, and according to the second correspondence relationship between the source code file and the source code module, the target source code file matched with the target source code module is determined, and according to the third correspondence relationship between the compiled code file and the compiled code module, the target compiled code file matched with the target compiled code module is obtained, so that the target source code file and the target compiled code file to which the to-be-debugged signal belongs are obtained. Then, the target source code file and the target compiled code file are subjected to syntax analysis respectively to obtain the first line number of the to-be-debugged signal in the target source code file and the second line number of the to-be-debugged signal in the target compiled code file, and the signal name, the first line number, and the second line number of the to-be-debugged signal are displayed in the display area to facilitate the waveform debugging of the to-be-debugged signal. By intuitively displaying the to-be-debugged signal in the source code file and the to-be-debugged signal in the compiled code, the source code corresponding to the compiled code does not need to be manually searched, and the efficiency of the waveform debugging can be greatly improved.

[0131] Figure 6 is a block diagram of a signal positioning device 30 in a circuit design file provided by the embodiment of the application, and the device comprises:

[0132] The first determination module 301 is configured to obtain the signal name of the to-be-debugged signal in the circuit design file, and determine the target source code module and the target compiled code module matched with the signal name of the to-be-debugged signal according to the first correspondence relationship among the source code module to which the signal belongs, the compiled code module to which the signal belongs, and the signal name of the signal.

[0133] The second determination module 302 is configured to determine the target source code file matched with the target source code module according to the second correspondence relationship between the source code file and the source code module, and determine the target compiled code file matched with the target compiled code module according to the third correspondence relationship between the compiled code file and the compiled code module.

[0134] The first syntax analysis module 303 is configured to perform syntax analysis on the target source code file and the target compiled code file respectively to obtain a first line number of the to-be-debugged signal in the target source code file and a second line number of the to-be-debugged signal in the target compiled code file.

[0135] The display module 304 is configured to display the signal name of the to-be-debugged signal, the first line number and the second line number in a display area for waveform debugging of the to-be-debugged signal.

[0136] Optionally, the first syntax analysis module comprises:

[0137] The first obtaining sub-module is configured to obtain a first syntax tree corresponding to a first design language of the target source code file and a second syntax tree corresponding to a second design language of the target compiled code file.

[0138] The first determining sub-module is configured to find a first position where a node corresponding to the to-be-debugged signal is located in the first syntax tree, and determine the first line number according to the first position.

[0139] The second determining sub-module is configured to find a second position where a node corresponding to the to-be-debugged signal is located in the second syntax tree, and determine the second line number according to the second position.

[0140] Optionally, the display area comprises a first display area and a second display area, and the display module comprises:

[0141] The first display sub-module is configured to open the target source code file in the first display area, automatically jump to a position of the first line number, and highlight the signal name of the to-be-debugged signal at the position of the first line number.

[0142] The second display sub-module is configured to open the target compiled code file in the second display area, automatically jump to a position of the second line number, and highlight the signal name of the to-be-debugged signal at the position of the second line number.

[0143] Optionally, the apparatus further comprises:

[0144] The obtaining module is configured to obtain a source code file and a compiled code file, wherein the compiled code file is generated by compiling source code in the source code file.

[0145] The second syntax analysis module is configured to perform syntax analysis on the source code file and the compiled code file respectively to obtain a source code module corresponding to the source code file and a compiled code module corresponding to the compiled code file.

[0146] a first establishing module, configured to establish a first correspondence relationship among the source code module, the compiled code module and a signal name of the signal;

[0147] a second establishing module, configured to establish a second correspondence relationship between the source code file and the source code module, and a third correspondence relationship between the compiled code file and the compiled code module.

[0148] Optionally, the second syntax analysis module comprises:

[0149] a second obtaining sub-module, configured to obtain a first syntax tree corresponding to a first design language of the target source code file and a second syntax tree corresponding to a second design language of the target compiled code file;

[0150] a third determining sub-module, configured to find a module node and a file node to which a node corresponding to the signal to be debugged belongs in the first syntax tree, and take a module corresponding to the module node as the source code module and take a file corresponding to the file node as the source code file;

[0151] a fourth determining sub-module, configured to find a module node and a file node to which a node corresponding to the signal to be debugged belongs in the second syntax tree, and take a module corresponding to the module node as the compiled code module and take a file corresponding to the file node as the compiled code file.

[0152] Optionally, the apparatus further comprises:

[0153] a third determining module, configured to determine a target signal in all signals as the signal to be debugged according to a preset configuration;

[0154] a selecting module, configured to, in response to a selection operation on a signal other than the target signal in all signals, take the selected signal as a new signal to be debugged and display the new signal to be debugged in a display area.

[0155] Optionally, the display area comprises a signal name area, a signal value display area and a waveform display area; the signal name area displays signal names of each existing signal of a circuit design file; and the selecting module comprises:

[0156] a selecting sub-module, configured to select a signal from the signal name area as the new signal to be debugged;

[0157] a third display sub-module, configured to display a signal name of the new signal to be debugged and a value of the new signal to be debugged in the signal value display area, and display a waveform of the new signal to be debugged in the waveform display area.

[0158] Optionally, the acquisition module comprises:

[0159] a third acquisition submodule, configured to acquire a path of the source code file and a path of the compiled code file;

[0160] a fifth determination submodule, configured to find the source code file according to the path of the source code file, and find the compiled code file according to the path of the compiled code file.

[0161] Optionally, the device further comprises:

[0162] a sixth determination submodule, configured to, if the to-be-debugged signal is an intermediate variable, find a signal to which the to-be-debugged signal is assigned from all signals according to an assignment relationship, determine the signal to which the to-be-debugged signal is assigned as the to-be-debugged signal, and enter a step of acquiring a signal name of the to-be-debugged signal in the circuit design file.

[0163] Optionally, the second syntax analysis module comprises:

[0164] a fourth acquisition submodule, configured to acquire a first temporary file corresponding to the source code file and a second temporary file corresponding to the compiled code file; the first temporary file is a file generated by replacing a hyperparameter value in the source code file; the second temporary file is a file generated by replacing a hyperparameter value in the compiled code file;

[0165] a seventh determination submodule, configured to perform syntax analysis on the first temporary file to obtain the source code module;

[0166] an eighth determination submodule, configured to perform syntax analysis on the second temporary file to obtain the compiled code module.

[0167] In summary, in the embodiments of the present application, according to the first correspondence relationship of the signal name of the signal, the source code module to which the signal belongs, and the compiled code module to which the signal belongs, the target source code module and the target compiled code module matching the signal name of the signal to be debugged are determined, and according to the second correspondence relationship of the source code file and the source code module, the target source code file matching the target source code module is determined, and according to the third correspondence relationship of the compiled code file and the compiled code module, the target compiled code file matching the target compiled code module is obtained, so as to obtain the target source code file and the target compiled code file to which the signal to be debugged belongs. Then, the target source code file and the target compiled code file are subjected to syntax analysis respectively, the first line number of the signal to be debugged in the target source code file and the second line number of the signal to be debugged in the target compiled code file are obtained, and the signal name, the first line number, and the second line number of the signal to be debugged are displayed in the display area, so as to perform waveform debugging on the signal to be debugged. By intuitively displaying the signal to be debugged in the source code file and the signal to be debugged in the compiled code, manual searching for the source code corresponding to the compiled code is not needed, and the efficiency of waveform debugging can be greatly improved.

[0168] For the device embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the related parts are described in the part of the description of the method embodiments.

[0169] Each embodiment in the present specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same and similar parts of each embodiment can be referred to each other.

[0170] For the device in the above embodiments, the specific manner in which each module performs the operation has been described in detail in the embodiments related to the method, and will not be described in detail here.

[0171] The embodiments of the present application provide a circuit design file signal positioning device, including a memory, and one or more programs, wherein the one or more programs are stored in the memory, and are configured to be executed by one or more processors to perform the method described in one or more embodiments.

[0172] Figure 7 is a block diagram of an electronic device 400 provided by the embodiments of the present application. For example, the electronic device 400 can be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0173] Reference Figure 7The electronic device 400 can include one or more of the following components: a processing component 402, a memory 404, a power supply component 406, a multimedia component 408, an audio component 410, an input / output (I / O) interface 412, a sensor component 414, and a communication component 416.

[0174] The processing component 402 typically controls overall operations of the electronic device 400, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 402 can include one or more processors 420 to execute instructions to complete all or part of steps of the above methods. In addition, the processing component 402 can include one or more modules to facilitate

[0175] The memory 404 is used to store various types of data to support operations of the electronic device 400. Examples of these data include instructions for any application or method operating on the electronic device 400, contact data, phonebook data, messages, pictures, multimedia, and so on. The memory 404 can be implemented by any type of volatile or non-volatile storage devices or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read only memory (EEPROM), erasable programmable read only memory (EPROM), programmable read only memory (PROM), read only memory (ROM), magnetic storage, flash memory, magnetic or optical disk.

[0176] The power supply component 406 supplies electrical power for the various components of the electronic device 400. The power supply component 406 can include a power supply management system, one or more power supplies, and other components associated with generating, managing and distributing electrical power for the electronic device 400.

[0177] The multimedia component 408 includes a screen to provide an output interface between the electronic device 400 and a user. In some embodiments, the screen can include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen can be implemented as a touch screen to receive input signals from a user. The touch panel includes one or more touch sensors to sense touch, slide and gesture on the touch panel. The touch sensor can not only sense a boundary of a touching or sliding action, but also detect duration and pressure related to the touching or sliding action. In some embodiments, the multimedia component 408 includes a front camera and / or a rear camera. When the electronic device 400 is in an operation mode, such as a camera mode or a multimedia mode, the front camera and / or the rear camera can receive external multimedia data. Each of the front and rear camera can be a fixed optical lens system or have a focal length and optical zoom capability.

[0178] The audio component 410 is configured to output and / or input audio signals. For example, the audio component 410 includes a microphone (MIC) to receive an external audio signal when the electronic device 400 is in an operation mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signal can be further stored in the memory 404 or transmitted via the communication component 416. In some embodiments, the audio component 410 further includes a speaker to output audio signals.

[0179] The input / output interface 412 provides an interface between the processing component 402 and peripheral interface modules, which can include a keypad, click wheel, button, and the like. The buttons can include, but are not limited to, a home button, a volume button, a start button, and a lock button.

[0180] The sensor component 414 includes one or more sensors to provide various state assessments for the electronic device 400. For example, the sensor component 414 can detect an open / closed position of the electronic device 400, relative positioning of components, such as a display and a keypad of the electronic device 400, a change in position of the electronic device 400 or a component of the electronic device 400, presence or absence of user contact with the electronic device 400, orientation or acceleration / deceleration of the electronic device 400, and a temperature change of the electronic device 400. The sensor component 414 can include a proximity sensor configured to detect presence of a nearby object without any physical touch. The sensor component 414 can further include a light sensor such as a CMOS or CCD image sensor for use in an imaging application. In some embodiments, the sensor component 414 can further include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0181] The communication component 416 is configured to facilitate wired or wireless communication between the electronic device 400 and other devices. The electronic device 400 can access a wireless network based on a communication standard, such as WiFi, a cellular network (e.g., 2G, 3G, 4G or 5G), or a combination thereof. In an example embodiment, the communication component 416 receives broadcast signals or broadcast-related information from external broadcast management systems via a broadcast channel. In an example embodiment, the communication component 416 can further include a Near Field Communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on Radio Frequency Identification (RFID) techniques, infrared data association (IrDA) techniques, ultra-wideband (UWB) techniques, Bluetooth (BT) techniques and other techniques.

[0182] In an example embodiment, the electronic device 400 can be implemented with one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, micro-controllers, microprocessors or other electronic elements, to implement methods provided by embodiments of the present application.

[0183] In an example embodiment, a non-transitory computer-readable storage medium, such as the memory 404 including instructions, is also provided. The instructions can be executed by the processor 420 of the electronic device 400 to complete the above-described methods. For example, the non-transitory storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disc, and an optical data storage device, etc.

[0184] Figure 8 is a block diagram of another electronic device 500 provided by embodiments of the present application. For example, the electronic device 500 can be provided as a server. Referring to Figure 8 The electronic device 500 includes a processing component 522, which further includes one or more processors, and a memory resource represented by a memory 532, for storing instructions, such as application programs, executable by the processing component 522. The application programs stored in the memory 532 can include one or more than one module each corresponding to a set of instructions. In addition, the processing component 522 is configured to execute the instructions to perform methods provided by embodiments of the present application.

[0185] The electronic device 500 can also include a power supply component 526 configured to perform power management of the electronic device 500, a wired or wireless network interface 550 configured to connect the electronic device 500 to a network, and an input / output interface 558. The electronic device 500 can operate based on an operating system stored in the memory 532, such as Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™, or the like.

[0186] The embodiments of the present application further provide a computer program product, comprising a computer program, wherein the computer program is executed by a processor to implement the method described in the above embodiments.

[0187] Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. It is intended that the present application cover any and all variations of the application that come within the scope of the present application, along with all of the equivalents thereof. It is intended that the specification and examples be considered exemplary only, with the true scope and spirit of the application being indicated by the following claims.

[0188] It is to be understood that the application is not limited to the precise details of construction and the arrangement of components described above and illustrated in the drawings, and that various modifications and changes can be made without departing from the scope thereof. The scope of the application is limited only by the claims that follow.

Claims

1. A method of locating a signal in a circuit design file, characterized by, The method comprises: acquiring a signal name of a signal to be debugged in a circuit design file, and determining a target source code module and a target compiled code module matched with the signal name of the signal to be debugged according to a first correspondence relationship among the signal name of the signal, a source code module to which the signal belongs, and a compiled code module to which the signal belongs; determining a target source code file matched with the target source code module according to a second correspondence relationship between a source code file and a source code module, and determining a target compiled code file matched with the target compiled code module according to a third correspondence relationship between a compiled code file and a compiled code module; the source code file is used for describing a hardware structure; performing syntax analysis on the target source code file and the target compiled code file respectively to obtain a first line number corresponding to the target source code file and a second line number corresponding to the target compiled code file; displaying the signal name of the signal to be debugged, the first line number, and the second line number in a display area to facilitate waveform debugging of the signal to be debugged.

2. The method of claim 1, wherein, The syntax analysis on the target source code file and the target compiled code file respectively to obtain the first line number corresponding to the target source code file and the second line number corresponding to the target compiled code file comprises: acquiring a first syntax tree corresponding to a first design language of the target source code file and a second syntax tree corresponding to a second design language of the target compiled code file; finding a first position where a node corresponding to the signal to be debugged is located in the first syntax tree, and determining the first line number according to the first position; finding a second position where a node corresponding to the signal to be debugged is located in the second syntax tree, and determining the second line number according to the second position.

3. The method of claim 1, wherein, The display area comprises a first display area and a second display area; The display of the signal name of the signal to be debugged, the first line number, and the second line number in the display area comprises: opening the target source code file in the first display area, automatically jumping to a position of the first line number, and highlighting the signal name of the signal to be debugged at the position of the first line number; opening the target compiled code file in the second display area, automatically jumping to a position of the second line number, and highlighting the signal name of the signal to be debugged at the position of the second line number.

4. The method of claim 1, wherein, The method further comprises: acquiring a source code file and a compiled code file; the compiled code file is generated by compiling source code in the source code file; performing syntax analysis on the source code file and the compiled code file respectively to obtain a source code module corresponding to the source code file and a compiled code module corresponding to the compiled code file; establishing a first correspondence relationship among the source code module, the compiled code module, and a signal name of the signal; establishing a second correspondence relationship between the source code file and the source code module, and a third correspondence relationship between the compiled code file and the compiled code module.

5. The method of claim 4, wherein, The syntax analysis on the source code file and the compiled code file respectively obtains a source code module corresponding to the source code file and a compiled code module corresponding to the compiled code file, and the syntax analysis comprises the following steps of: obtaining a first syntax tree corresponding to a first design language of the target source code file and a second syntax tree corresponding to a second design language of the target compiled code file; in the first syntax tree, finding a module node and a file node to which a node corresponding to the signal to be debugged belongs, and taking a module corresponding to the module node as the source code module and taking a file corresponding to the file node as the source code file; in the second syntax tree, finding a module node and a file node to which a node corresponding to the signal to be debugged belongs, and taking a module corresponding to the module node as the compiled code module and taking a file corresponding to the file node as the compiled code file.

6. The method of claim 1, wherein, The method further comprises: determining a target signal in all signals as the signal to be debugged according to a preset configuration; in response to a selection operation on a signal other than the target signal in all signals, taking the selected signal as a new signal to be debugged and displaying the new signal to be debugged in a display area.

7. The method of claim 6, wherein, The display area comprises a signal name area, a signal value display area and a waveform display area; the signal name area displays signal names of each existing signal of the circuit design file; the taking of the selected signal as the new signal to be debugged and the displaying of the new signal to be debugged in the display area comprises: selecting a signal from the signal name area as the new signal to be debugged; displaying the signal name of the new signal to be debugged and the value of the new signal to be debugged in the signal value display area and displaying the waveform of the new signal to be debugged in the waveform display area.

8. The method of claim 4, wherein, The obtaining of the source code file and the compiled code file comprises: obtaining a path of the source code file and a path of the compiled code file; finding the source code file according to the path of the source code file and finding the compiled code file according to the path of the compiled code file.

9. The method of claim 1, wherein, The method further comprises: if the signal to be debugged is an intermediate variable, finding a signal to which the signal to be debugged is assigned from all signals according to an assignment relationship, determining the signal to which the signal to be debugged is assigned as the signal to be debugged, and entering a step of obtaining a signal name of the signal to be debugged in the circuit design file.

10. The method of claim 4, wherein, The syntax analysis on the source code file and the compiled code file respectively obtains a source code module corresponding to the source code file and a compiled code module corresponding to the compiled code file, and the syntax analysis comprises the following steps of: obtaining a first temporary file corresponding to the source code file and a second temporary file corresponding to the compiled code file; the first temporary file is a file generated by replacing a hyperparameter value of the source code file; the second temporary file is a file generated by replacing a hyperparameter value of the compiled code file; performing syntax analysis on the first temporary file to obtain the source code module; performing syntax analysis on the second temporary file to obtain the compiled code module.

11. A signal location device in a circuit design document, characterized in that, The device comprises: The first determining module is configured to acquire a signal name of a to-be-debugged signal in a circuit design file, and determine a target source code module and a target compiled code module matched with the signal name of the to-be-debugged signal according to a first correspondence relationship among source code modules to which the signal belongs, compiled code modules to which the signal belongs, and the signal name of the signal. The second determining module is configured to determine a target source code file matched with the target source code module according to a second correspondence relationship between source code files and source code modules, and determine a target compiled code file matched with the target compiled code module according to a third correspondence relationship between compiled code files and compiled code modules; the source code file is used to describe a hardware structure. The first syntax analysis module is configured to perform syntax analysis on the target source code file and the target compiled code file respectively, and obtain a first line number of the to-be-debugged signal in the target source code file and a second line number of the to-be-debugged signal in the target compiled code file. The display module is configured to display the signal name of the to-be-debugged signal, the first line number, and the second line number in a display area, so as to perform waveform debugging on the to-be-debugged signal.

12. An electronic device, comprising: The processor, the memory, and the program or the instructions stored in the memory and executable on the processor are provided, and the program or the instructions are executed by the processor to implement the steps of the signal positioning method in the circuit design file according to any one of claims 1 to 10.

13. A readable storage medium, characterized by, The readable storage medium stores the program or the instructions, and the program or the instructions are executed by the processor to implement the steps of the signal positioning method in the circuit design file according to any one of claims 1 to 10.

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