FPGA Design Method Based on EDA Software System and EDA Software System

Abstract

The present invention relates to the technical field of FPGA design, and an FPGA design method and an EDA software system based on an EDA software system, including: starting the EDA software system, setting the project path, creating user source code, starting the synthesis process module, obtaining a synthesis netlist, starting the placement and routing process module, performing placement and routing operations on the synthesis netlist to obtain a placement and routing netlist, obtaining a design bitstream file, obtaining a target FPGA chip and information of the target FPGA chip, querying the compatibility result between the information of the target FPGA chip and the design bitstream file in the database, if it is confirmed that the compatibility result between the information of the target FPGA chip and the design bitstream file is compatible, then downloading the design bitstream file to the target FPGA chip to obtain an adapted FPGA device and information on the download operation process, saving the information on the download operation process to obtain a download operation log, and completing the FPGA design based on the EDA software system based on the adapted FPGA device and the download operation log. The present invention can improve the design efficiency and optimize the design process.

Description

Technical Field

[0001] The present invention relates to the technical field of FPGA design, and particularly to an FPGA design method based on an EDA software system and an EDA software system. Background Art

[0002] An EDA software system refers to a system that optimizes the design process and improves design efficiency through innovative algorithms and a modern user interface. An FPGA is a flexible and powerful digital circuit widely used in many fields such as communication, data processing, image, and signal processing. Its main advantage lies in being able to program logical functions at the hardware level, thus providing high-performance customized hardware solutions for specific applications.

[0003] With the progress of technology and the changing demands of the market, traditional EDA tools can no longer fully meet the needs of modern FPGA design. Especially during the process of program writing, synthesis, placement and routing, and downloading the program to the FPGA chip, designers face many challenges such as design optimization, timing analysis, resource management, and power consumption control. These challenges require EDA tools to not only provide an efficient design process but also be highly user-friendly and flexible to support rapid design iteration and complexity management. Summary of the Invention

[0004] The present invention provides an FPGA design method based on an EDA software system and an EDA software system, whose main purpose is to improve design efficiency and optimize the design process.

[0005] To achieve the above object, an FPGA design method based on an EDA software system provided by the present invention includes:

[0006] Receiving an FPGA design instruction, starting a pre-built EDA software system according to the FPGA design instruction, setting a project path according to the started EDA software system, and creating user source code according to the project path, wherein the EDA software system includes: an intelligent parser, a download process management, a database, a synthesis process module, and a placement and routing process module;

[0007] Starting the synthesis process module, and obtaining a synthesis netlist based on the started synthesis process module and the user source code;

[0008] Starting the placement and routing process module, and performing placement and routing operations on the synthesis netlist by using the started placement and routing process module to obtain a placement and routing netlist, wherein the placement and routing process module includes: an advanced placement algorithm and a path planning algorithm;

[0009] Obtain the design bitstream file according to the layout and routing netlist. The design bitstream file is a binary file and includes all the information required to configure the FPGA.

[0010] Obtain the target FPGA chip and the information of the target FPGA chip, and query the compatibility result between the information of the target FPGA chip and the design bitstream file in the database. The compatibility result includes: compatible and incompatible.

[0011] If it is confirmed that the compatibility result between the information of the target FPGA chip and the design bitstream file is compatible, download the design bitstream file to the target FPGA chip to obtain the FPGA device adaptation and download operation process information. The download operation process information includes: time, date, device information, and download result.

[0012] Use the pre-built log file to save the download operation process information to obtain the download operation log, and complete the FPGA design based on the EDA software system based on the FPGA device adaptation and the download operation log.

[0013] Optionally, the obtaining of the synthesis netlist based on the started synthesis process module and the user source code includes:

[0014] Read the user source code based on the started synthesis process module, and use the intelligent parser to parse the read user source code to obtain the source code data. The intelligent parser includes: Verilog and SystemVerilog.

[0015] Perform a syntax check on the source code data to obtain the verified source code data, and perform data initialization on the verified source code data to obtain the initialized source code data.

[0016] Perform a technology mapping operation on the initialized source code data and standardize the structure of the initialized source code data after mapping to obtain the standard structure source code. The technology mapping operation includes: DSP, memory mapping, register mapping, LUT mapping, and other device mappings.

[0017] Use the pre-built optimization algorithm to perform an optimization operation on the standard structure source code to obtain the initial optimized circuit. The optimization operation includes: circuit optimization and clock optimization. The optimization algorithm includes: constant propagation, dead code elimination, logic simplification, and area-vs-speed trade-off optimization.

[0018] Perform a final check operation on the initial optimized circuit to obtain the final check result. When the final check result of the initial optimized circuit is the preset pass result, confirm the initial optimized circuit as the optimized circuit. The final check operation includes: circuit connection check, driver unit check, hierarchical structure check, and timing check.

[0019] Generate a comprehensive netlist based on an optimized circuit.

[0020] Optionally, perform placement and routing operations on the comprehensive netlist using the started placement and routing process module to obtain a placement and routing netlist, including:

[0021] Use the started placement and routing process module to read and parse the comprehensive netlist to obtain a set of logic units;

[0022] Perform a physical mapping stage on the set of logic units to obtain a set of physical devices with determined connection relationships, where the physical mapping stage includes: device mapping and local connection;

[0023] Perform a placement stage operation on the set of physical devices to determine the spatial positions of each physical device in the set of physical devices, obtain an optimal placement set, and perform device position checks on each optimal placement set in the optimal placement set to obtain a standard optimal placement set;

[0024] Obtain the standard thermal distribution map of the FPGA design chip;

[0025] Perform a routing stage operation on the standard optimal placement set according to the standard thermal distribution map to obtain an optimal placement and routing set, where the routing stage operation includes: initializing the model, forward routing, reverse routing check, netlist connection check, and timing analysis;

[0026] Generate a placement and routing netlist according to the optimal placement and routing set.

[0027] Optionally, performing a physical mapping stage on the set of logic units to obtain a set of physical devices with determined connection relationships includes:

[0028] Obtain the set of physical positions of the target FPGA chip, and perform the following operations on each logic unit in the set of logic units:

[0029] Map the logic units to the target physical positions in the set of physical positions, where the logic units and the physical positions are in one-to-one correspondence;

[0030] Summarize the target physical positions to obtain a set of physical devices with determined connection relationships corresponding to the set of logic units.

[0031] Optionally, performing a placement stage operation on the set of physical devices to determine the spatial positions of each physical device in the set of physical devices and obtain an optimal placement set includes:

[0032] Construct a placement equation according to the set of physical devices, obtain clock constraints, and group the set of logic units according to the clock constraints to obtain multiple logic unit groups;

[0033] Extract a logic cell group from multiple logic cell groups in sequence, and perform the following operations on each of the extracted logic cell groups:

[0034] Use the layout equation, advanced layout algorithm, and path planning algorithm to perform layout analysis on the logic cell group to obtain a sub-optimal layout, where the advanced layout algorithms include: simulated annealing, genetic algorithm, and particle swarm optimization;

[0035] Perform position constraint on the sub-optimal layout according to the preset positions of key components to obtain an optimal layout;

[0036] Summarize the optimal layouts and determine the spatial positions of each physical device in the physical device set to obtain an optimal layout set corresponding to multiple logic cell groups.

[0037] Optionally, the obtaining of the standard thermal distribution map of the FPGA design chip includes:

[0038] Use the EDA software system to simulate the initial thermal distribution map of the FPGA design chip, and compare the effects of the initial thermal distribution map and the preset thermal distribution map;

[0039] If the initial thermal distribution map does not meet the effect of the preset thermal distribution map, obtain the hot spot area according to the initial thermal distribution map, and adjust the layout and wiring of the hot spot area until the initial thermal distribution map meets the effect of the preset thermal distribution map to obtain the standard thermal distribution map.

[0040] Optionally, the downloading of the design bitstream file to the target FPGA chip to obtain the information on the FPGA device adaptation and the download operation process includes:

[0041] Obtain multiple program download interfaces, where the multiple program download interfaces include: JTAG, USB, and Ethernet;

[0042] Extract the target download interface from the multiple program download interfaces, and set the custom download configuration, where the custom download configuration includes: download speed, selection of the target device, and setting of specific download parameters;

[0043] Obtain the development environment according to the target FPGA chip, the target download interface, and the custom download configuration, and start the download process management, where the download process management includes a process management mechanism;

[0044] Use the process management mechanism to monitor the download process management in real time and provide real-time feedback information, where the real-time feedback information includes: download progress, error detection, and troubleshooting diagnosis;

[0045] Obtain advanced encryption, verification mechanisms, and download function options, where the download function options include: automatic download and batch download;

[0046] Download the design bitstream file to the target FPGA chip according to the development environment, download function options, advanced encryption, and verification mechanism to obtain an FPGA device adapted, and generate download operation process information according to the real-time feedback information.

[0047] Optionally, before downloading the design bitstream file to the target FPGA chip according to the development environment, download function options, advanced encryption, and verification mechanism, the method further includes:

[0048] If an error detection or troubleshooting diagnosis appears in the real-time feedback information, use the EDA software system to provide a solution, and solve the error detection or troubleshooting diagnosis according to the solution until no error detection or troubleshooting diagnosis appears in the real-time feedback information.

[0049] To achieve the above object, the present invention further provides an EDA software system, including:

[0050] A user source code creation module, configured to receive an FPGA design instruction, start a pre-built EDA software system according to the FPGA design instruction, set a project path according to the started EDA software system, and create user source code according to the project path. Among them, the EDA software system includes: an intelligent parser, a download process management, a database, a synthesis process module, and a placement and routing process module;

[0051] A synthesis process start module, configured to start the synthesis process module and obtain a synthesis netlist based on the started synthesis process module and the user source code;

[0052] A placement and routing start module, configured to start the placement and routing process module, perform placement and routing operations on the synthesis netlist using the started placement and routing process module to obtain a placement and routing netlist. Among them, the placement and routing process module includes: an advanced placement algorithm and a path planning algorithm. Obtain a design bitstream file according to the placement and routing netlist. The design bitstream file is a binary file, and the design bitstream file includes: all information required to configure the FPGA. Obtain the target FPGA chip and the information of the target FPGA chip, and query the compatibility result of the information of the target FPGA chip and the design bitstream file in the database. The compatibility result includes: compatible and incompatible;

[0053] A design file download module, configured to, if it is confirmed that the compatibility result of the information of the target FPGA chip and the design bitstream file is compatible, download the design bitstream file to the target FPGA chip to obtain an FPGA device adapted and download operation process information. The download operation process information includes: time, date, device information, and download result. Use a pre-built log file to save the download operation process information to obtain a download operation log, and complete the FPGA design based on the EDA software system based on the adapted FPGA device and the download operation log.

[0054] To solve the above problems, the present invention further provides an electronic device, which includes:

[0055] A memory that stores at least one instruction;

[0056] A processor that executes the instructions stored in the memory to implement the above-mentioned FPGA design method based on the EDA software system.

[0057] To solve the above problems, the present invention further provides a computer-readable storage medium, in which at least one instruction is stored, and the at least one instruction is executed by a processor in an electronic device to implement the above-mentioned FPGA design method based on the EDA software system.

[0058] To solve the problems described in the background art, the present invention receives FPGA design instructions, starts a pre-built EDA software system according to the FPGA design instructions, sets the project path according to the started EDA software system, and creates user source code according to the project path. Among them, the EDA software system includes: an intelligent parser, a download process management, a database, a synthesis process module, and a placement and routing process module. The EDA software system of the present invention integrates multiple functional modules such as an intelligent parser, a download process management, a database, a synthesis process module, and a placement and routing process module, providing a comprehensive design platform to facilitate designers to perform various subsequent design operations, improving design efficiency and quality. The user source code is the basis of FPGA design. Designers can write code according to specific design requirements to achieve specific functions, providing original design materials for subsequent synthesis and placement and routing. Start the synthesis process module, and obtain a synthesis netlist based on the started synthesis process module and the user source code. The synthesis process module of the present invention is a process that can convert high-level hardware description language code into gate-level logic that can be implemented on an FPGA, converting an abstract design description into a specific hardware circuit representation, providing an operable circuit model for subsequent placement and routing. The synthesis netlist is a hardware-level abstract representation of the design function, which contains the connection relationships and logical functions between various logic units in the design, providing accurate circuit information for placement and routing, and helping to optimize the performance and resource utilization of the design. Start the placement and routing process module, and perform placement and routing operations on the synthesis netlist using the started placement and routing process module to obtain a placement and routing netlist. Among them, the placement and routing process module includes: an advanced placement algorithm and a path planning algorithm. The placement and routing process module of the present invention adopts an advanced placement algorithm and a path planning algorithm, which can physically implement the synthesis netlist, reasonably place the logic circuit on the physical resources of the target FPGA chip, and plan the signal routing path to ensure that the design can work properly on the actual FPGA chip. Obtain a design bitstream file according to the placement and routing netlist. Among them, the design bitstream file is a binary file, and the design bitstream file includes: all the information required to configure the FPGA. The present invention configures the FPGA to achieve the functions expected by the designer, which is the key conversion from software description to hardware implementation in FPGA design. Obtain the target FPGA chip and the information of the target FPGA chip, and query the compatibility result between the information of the target FPGA chip and the design bitstream file in the database. Among them, the compatibility result includes: compatible and incompatible. The present invention can discover in advance whether the design bitstream file is compatible with the target FPGA chip by querying the database, avoiding chip damage or program errors caused by incompatibility during the download process, and improving the reliability and stability of the design. If it is confirmed that the compatibility result between the information of the target FPGA chip and the design bitstream file is compatible, then download the design bitstream file to the target FPGA chip to obtain the information of the FPGA device adaptation and the download operation process. Among them,The downloaded operation process information includes: time, date, device information, and download result. By determining the compatibility between the information of the target FPGA chip and the designed bitstream file, the present invention ensures that the design can be correctly implemented on the target FPGA chip, transforms the software design into actual hardware functions, and achieves the ultimate goal of FPGA design. The downloaded operation process information is saved using a pre-built log file to obtain the downloaded operation log. Based on the adapted FPGA device and the downloaded operation log, the FPGA design based on the EDA software system is completed. The present invention records the detailed information of each download operation through the log file, which is convenient for designers to track problems and analyze problems in the design process, and also meets the requirements of auditing and quality control. Therefore, the present invention can improve the design efficiency and optimize the design process. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Figure 1 It is a schematic flowchart of the FPGA design method based on the EDA software system provided by an embodiment of the present invention;

[0060] Figure 2 It is a module diagram of the EDA software system provided by an embodiment of the present invention;

[0061] Figure 3 It is a schematic structural diagram of an electronic device for implementing the FPGA design method based on the EDA software system provided by an embodiment of the present invention.

[0062] DESCRIPTION OF THE REFERENCE NUMERALS:

[0063] 1. Electronic device; 10. Processor; 11. Memory; 12. Bus; 100. EDA software system; 101. User source code creation module; 102. Synthesis process start module; 103. Placement and routing start module; 104. Design file download module.

[0064] The realization, functional features, and advantages of the objectives of the present invention will be further described in conjunction with the embodiments with reference to the drawings. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0065] It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0066] An embodiment of the present application provides an FPGA design method based on an EDA software system. The execution subject of the FPGA design method based on the EDA software system includes, but is not limited to, at least one of electronic devices such as a server, a terminal, etc. that can be configured to execute the method provided in the embodiment of the present application. In other words, the FPGA design method based on the EDA software system can be executed by software or hardware installed on a terminal device or a server device, and the software can be a blockchain platform. The server includes, but is not limited to: a single server, a server cluster, a cloud server, or a cloud server cluster, etc.

[0067] Referring to Figure 1 As shown, it is a schematic flowchart of an FPGA design method based on an EDA software system provided by an embodiment of the present invention. In this embodiment, the FPGA design method based on the EDA software system includes:

[0068] S1. Receive an FPGA design instruction, start a pre-built EDA software system according to the FPGA design instruction, set a project path according to the started EDA software system, and create user source code according to the project path.

[0069] Specifically, the EDA software system includes: an intelligent parser, a download process management, a database, a synthesis process module, and a placement and routing process module.

[0070] It should be explained that the FPGA design instruction is a signal instruction issued by a person to trigger the start of the FPGA design process. The EDA software system refers to a set of tool software specially used to assist in the design of electronic circuits. The EDA software system described in the embodiment of the present invention integrates multiple functional modules, can help designers efficiently complete the entire process from the design to the implementation of the FPGA, and it deeply understands Verilog and SystemVerilog, including all syntax structures and semantic rules of Verilog and SystemVerilog, and can parse complex data structures, coding styles, and design patterns, so as to provide a flexible programming environment for designers.

[0071] Importantly, the steps of setting a project path according to the started EDA software system and creating user source code according to the project path are as follows: Select the path where the project is placed in the file manager of the started EDA software system to obtain the project path. According to the project path, use the file editing function to create a source code file. The user first clicks the file button on the new source file page, then selects Sources in the pop-up options, clicks Create, and then enters the source code file creation interface. After the user enters the module name, the EDA software system will create a corresponding source code file for the user.

[0072] S2. Start the comprehensive process module and obtain the comprehensive netlist based on the started comprehensive process module and the user source code.

[0073] Specifically, the obtaining of the comprehensive netlist based on the started comprehensive process module and the user source code includes:

[0074] Read the user source code based on the started comprehensive process module, and use the intelligent parser to parse the read user source code to obtain source code data. Among them, the intelligent parser includes Verilog and SystemVerilog;

[0075] Perform a syntax check on the source code data to obtain the verified source code data, and perform data initialization on the verified source code data to obtain the initialized source code data;

[0076] Perform a technology mapping operation on the initialized source code data and standardize the structure of the initialized source code data after mapping to obtain the source code with a standard structure. Among them, the technology mapping operation includes DSP, memory mapping, register mapping, LUT mapping, and other device mappings;

[0077] Use the pre-built optimization algorithm to perform an optimization operation on the source code with a standard structure to obtain the initial optimized circuit. Among them, the optimization operation includes circuit optimization and clock optimization. Among them, the optimization algorithm includes constant propagation, dead code elimination, logic simplification, and area and speed trade-off optimization;

[0078] Perform a final check operation on the initial optimized circuit to obtain the final check result. When the final check result of the initial optimized circuit is the preset passing result, confirm the initial optimized circuit as the optimized circuit. Among them, the final check operation includes circuit connection check, drive unit check, hierarchy check, and timing check;

[0079] Generate a comprehensive netlist based on the optimized circuit.

[0080] It should be noted that the synthesis flow module is a module that converts high-level hardware description language code into a gate-level logic process that can be implemented on an FPGA. The synthesis flow module described in the embodiments of the present invention is specifically designed to optimize this conversion process to ensure that the designer's Verilog or SystemVerilog code can be efficiently and accurately mapped to the FPGA hardware. The synthesis flow module includes: a synthesis tool, an intelligent optimization function, a design rule check function, a timing analysis function, and a resource estimation function. The timing analysis function includes: a timing analyzer. The timing analyzer can predict in advance the timing performance of the design in the actual hardware in the synthesis flow module. By analyzing the data path delay and clock domain, the synthesis tool can point out potential timing problems and automatically make adjustments in some cases to meet the timing requirements. In this way, the designer can perform iterative optimization on the design before placement and routing, saving valuable development time.

[0081] Importantly, in the synthesis flow module, the synthesis tool provides a rough estimate of the required FPGA resources, including look-up tables (LUTs), registers, input / output blocks (IOBs), and other dedicated hardware resources (such as DSP blocks and memory), allowing the designer to have a reasonable expectation of the scale and complexity of the design at an early stage and make corresponding design adjustments. To support the development of complex projects and the collaboration of large teams, the synthesis tool provides powerful scripting and automation capabilities. The design team can use scripts to orchestrate the synthesis flow, automatically execute optimization strategies, and integrate custom design checks and rules. These automation functions greatly improve the development efficiency and reduce the possibility of human errors. Considering that multiple design options may need to be tested during the design process of the synthesis flow module, the synthesis tool supports multi-version synthesis and can compare different synthesis results, enabling the designer to explore different design choices, compare their performance and resource consumption, and finally select the optimal solution.

[0082] It can be understood that Verilog and SystemVerilog refer to two of the most widely used hardware description languages. The intelligent parser refers to a device that can recognize and optimize high-level language constructs, such as parameterized modules, generate statements, and complex control flow structures.

[0083] It should be noted that the user source code refers to the code written by the FPGA designer using a hardware description language according to specific design requirements. The source code data refers to the data obtained after the synthesis flow module uses the intelligent parser to parse the read user source code. The verified source code data refers to the data obtained after performing a syntax check on the source code data. The initialized source code data refers to the data obtained after performing a data initialization operation on the verified source code data. The technology mapping operation refers to the operation of mapping the logical description in the initialized source code data to the hardware resources supported by the target FPGA chip.

[0084] It is understandable that an optimization algorithm refers to an algorithm that can reduce the number of required logic units and optimize the timing, thereby achieving a higher operating frequency. The initial optimized circuit refers to the circuit model obtained after performing optimization operations on the standard structure source code using the optimization algorithm. The final inspection result refers to the result obtained after performing the final inspection operation on the initial optimized circuit, including passing and failing. The optimized circuit refers to the final circuit formed after parsing, inspection, technology mapping, and various optimization steps starting from the source code written by the user. The synthesis netlist includes: resource usage distribution, timing performance analysis, and indication of potential problems.

[0085] S3. Start the placement and routing process module, and use the started placement and routing process module to perform placement and routing operations on the synthesis netlist to obtain the placement and routing netlist.

[0086] Specifically, the placement and routing process module includes: high-level placement algorithms and path planning algorithms. The path planning algorithms include: Lee algorithm and Hadlock algorithm.

[0087] It should be explained that the path planning algorithm is used to handle complex routing challenges. It can intelligently optimize the path length and crossing of signals, reduce signal delay and routing congestion, and improve the performance and reliability of the design.

[0088] In detail, the operation of using the started placement and routing process module to perform placement and routing operations on the synthesis netlist to obtain the placement and routing netlist includes:

[0089] Use the started placement and routing process module to read the synthesis netlist and perform parsing to obtain a set of logic units;

[0090] Perform the physical mapping phase on the set of logic units to obtain a set of physical devices with determined connection relationships. Among them, the physical mapping phase includes: device mapping and local connection;

[0091] Perform the placement phase operation on the set of physical devices to determine the spatial positions of each physical device in the set of physical devices, obtain the optimal placement set, and perform device position inspection on each optimal placement set in the optimal placement set to obtain the standard optimal placement set;

[0092] Obtain the standard thermal distribution map of the FPGA design chip;

[0093] Perform the routing phase operation on the standard optimal placement set according to the standard thermal distribution map to obtain the optimal placement and routing set. Among them, the routing phase operation includes: initializing the model, forward routing pathfinding, reverse routing check, netlist connection check, and timing analysis;

[0094] Generate the placement and routing netlist according to the optimal placement and routing set.

[0095] It should be noted that the placement and routing process module refers to the module for mapping the synthesized logic onto the target FPGA chip, including: spatial positioning of components and path planning for connections between different components. The set of logic units refers to the set of logic units obtained after the placement and routing process module reads and parses the synthesized netlist. The set of physical devices refers to the set of physical devices obtained after performing the physical mapping phase on the set of logic units. The placement phase operation is an operation for automatically allocating logic units to physical positions on the FPGA design chip, which is driven by a high-level placement algorithm and takes into account key factors such as the interconnection strength between logic units, timing requirements, and thermal distribution.

[0096] It should be noted that the optimal placement set refers to the set obtained after performing the placement phase operation on the set of physical devices and determining the spatial positions of each physical device in the set of physical devices. The standard optimal placement set refers to the set of standard optimal placements obtained by checking the device positions for each optimal placement in the optimal placement set. The FPGA design chip refers to the chip that configures the FPGA chip through programming. The optimal placement and routing set is the set of the final optimized results of the placement and routing operations, which details the positions of physical devices on the chip and the connection methods between them.

[0097] Specifically, performing the physical mapping phase on the set of logic units to obtain a set of physical devices with determined connection relationships includes:

[0098] Obtaining the set of physical positions of the target FPGA chip, and performing the following operations on each logic unit in the set of logic units:

[0099] Performing device mapping of the logic unit to the target physical position in the set of physical positions, where the logic unit corresponds to the physical position one by one;

[0100] Summarizing the target physical positions to obtain a set of physical devices with determined connection relationships corresponding to the set of logic units.

[0101] It should be noted that the set of physical positions refers to the set of all available physical position information on the target FPGA chip. The target physical position refers to the specific physical position selected from the set of physical positions for each logic unit in the set of logic units during the physical mapping phase of the set of logic units.

[0102] Specifically, performing the placement phase operation on the set of physical devices to determine the spatial positions of each physical device in the set of physical devices and obtain the optimal placement set includes:

[0103] Constructing a placement equation based on the set of physical devices, obtaining clock constraints, and grouping the set of logic units according to the clock constraints to obtain multiple logic unit groups;

[0104] Extract a logic cell group from multiple logic cell groups in sequence, and perform the following operations on each of the extracted logic cell groups:

[0105] Perform layout analysis on the logic cell group using the layout equation, advanced layout algorithms, and path planning algorithms to obtain a sub-optimal layout, where the advanced layout algorithms include: simulated annealing, genetic algorithms, and particle swarm optimization;

[0106] Perform position constraints on the sub-optimal layout according to the preset positions of key components to obtain an optimal layout;

[0107] Summarize the optimal layouts and determine the spatial positions of each physical device in the physical device set to obtain an optimal layout set corresponding to multiple logic cell groups.

[0108] It should be noted that the step of grouping the logic cell set according to the clock constraint to obtain multiple logic cell groups is as follows: Divide the logic cells affected by the same clock constraint into one group to obtain a logic cell group, and summarize the logic cell groups to obtain multiple logic cell groups. The sub-optimal layout refers to the layout obtained during the layout analysis of the logic cell group. The positions of key components are specified in advance.

[0109] Furthermore, the obtaining of the standard thermal distribution map of the FPGA design chip includes:

[0110] Use the EDA software system to simulate the initial thermal distribution map of the FPGA design chip, and compare the effects of the initial thermal distribution map and the preset thermal distribution map;

[0111] If the initial thermal distribution map does not meet the effect of the preset thermal distribution map, obtain the hot spot area according to the initial thermal distribution map, and adjust the layout and wiring of the hot spot area until the initial thermal distribution map meets the effect of the preset thermal distribution map to obtain the standard thermal distribution map.

[0112] It should be noted that the initial thermal distribution map refers to the graph of the temperature distribution of the FPGA design chip obtained by simulating the FPGA design chip using the EDA software system. The thermal distribution map refers to the preset graph used to avoid performance degradation and reliability problems caused by overheating of the FPGA design chip. The standard thermal distribution map refers to the graph obtained by adjusting the hot spot area of the FPGA design chip until the initial thermal distribution map meets the effect of the preset thermal distribution map.

[0113] S4. Obtain the design bitstream file according to the layout and wiring netlist, where the design bitstream file is a binary file and includes all the information required to configure the FPGA.

[0114] It should be noted that the layout and routing netlist refers to a file generated according to the optimal layout and routing set, which records the specific positions of physical devices on the FPGA chip and the connection relationships between them.

[0115] S5. Obtain the target FPGA chip and the information of the target FPGA chip, and query the compatibility result between the information of the target FPGA chip and the design bitstream file in the database, where the compatibility result includes: compatible and incompatible.

[0116] It should be noted that the database includes: multiple FPGA models and configuration specifications, which can ensure the compatibility between the design bitstream file and the target FPGA chip, and avoid device damage or program errors. The step of querying the compatibility result between the information of the target FPGA chip and the design bitstream file in the database is: query the FPGA model and configuration specifications of the target FPGA chip in the database, and determine whether the FPGA model and configuration specifications of the target FPGA chip obtained by querying are compatible with the FPGA chip designed in the design bitstream file.

[0117] S6. If it is confirmed that the compatibility result between the information of the target FPGA chip and the design bitstream file is compatible, then download the design bitstream file to the target FPGA chip to obtain the adapted FPGA device and the download operation process information, where the download operation process information includes: time, date, device information, and download result.

[0118] Specifically, the step of downloading the design bitstream file to the target FPGA chip to obtain the adapted FPGA device and the download operation process information includes:

[0119] Obtain multiple program download interfaces, where the multiple program download interfaces include: JTAG, USB, and Ethernet;

[0120] Extract the target download interface from the multiple program download interfaces, and set the custom download configuration, where the custom download configuration includes: download speed, select the target device, and set specific download parameters;

[0121] Obtain the development environment according to the target FPGA chip, the target download interface, and the custom download configuration, and start the download process management, where the download process management includes a process management mechanism;

[0122] Use the process management mechanism to monitor the download process management in real time and provide real-time feedback information, where the real-time feedback information includes: download progress, error detection, and troubleshooting diagnosis;

[0123] Obtain the advanced encryption, verification mechanism, and download function options, where the download function options include: automatic download and batch download;

[0124] Download the design bitstream file to the target FPGA chip according to the development environment, download function options, advanced encryption, and verification mechanism to obtain an FPGA device adapted to the FPGA, and generate download operation process information according to the real-time feedback information.

[0125] It should be explained that the target download interface refers to a specific interface extracted from multiple program download interfaces for downloading the design bitstream file to the target FPGA chip. The purpose of setting the custom download configuration in the embodiments of the present invention is to provide flexibility, enabling users to adjust the download process according to specific design requirements and resource conditions. The purpose of automatic download is to allow users to preset download tasks and automatically execute the download when the conditions are met. Batch download means being able to download programs to multiple FPGA devices simultaneously, which is particularly useful for large-scale production and testing. Download process management is responsible for securely and accurately transmitting the FPGA configuration bitstream designed by the user and processed through synthesis and placement and routing to the target FPGA chip.

[0126] It should be explained that the purpose of the advanced encryption and verification mechanism is to ensure the security of the design bitstream file during the download process. The FPGA device adapted to the FPGA refers to a device that enables the target FPGA chip to work properly according to the design requirements after successfully downloading the design bitstream file to the target FPGA chip. The purpose of the multiple program download interfaces in the embodiments of the present invention is to adapt to different user requirements and hardware configurations, and users can select the most suitable download method according to the actual hardware settings and personal preferences.

[0127] Importantly, the process management mechanism described in the embodiments of the present invention is used to prompt the user and provide possible solutions to correct errors in a timely manner and ensure the smooth completion of the download process.

[0128] Specifically, before downloading the design bitstream file to the target FPGA chip according to the development environment, download function options, advanced encryption, and verification mechanism, the method further includes:

[0129] If error detection or troubleshooting diagnosis appears in the real-time feedback information, use the EDA software system to provide a solution, and solve the error detection or troubleshooting diagnosis according to the solution until error detection or troubleshooting diagnosis does not appear in the real-time feedback information.

[0130] S7. Use the pre-built log file to save the download operation process information to obtain the download operation log.

[0131] It should be explained that the log file in the embodiments of the present invention is very important for tracking problems, improving the design process, and meeting audit requirements. The download operation log refers to a file used to record the detailed information of the operation process of downloading the design bitstream file to the target FPGA chip.

[0132] S8. Complete the FPGA design based on the EDA software system by adapting the FPGA device and downloading the operation log.

[0133] It should be explained that the EDA software system provides a comprehensive, efficient and secure program download solution. It can not only adapt to a variety of FPGA devices and different download interfaces, but also effectively manage and monitor the entire download process to ensure the correctness and integrity of the design. In addition, functions such as user-defined settings and batch downloading make the EDA software system suitable not only for R & D and test environments, but also for large-scale production environments. Through additional attention to security and reliability, as well as a powerful logging function, it ensures traceability and reliability when transforming the design from concept to actual deployment.

[0134] To solve the problems described in the background art, the present invention receives FPGA design instructions, starts a pre-built EDA software system according to the FPGA design instructions, sets the project path according to the started EDA software system, and creates user source code according to the project path. Among them, the EDA software system includes: an intelligent parser, a download process management, a database, a synthesis process module, and a placement and routing process module. The EDA software system of the present invention integrates multiple functional modules such as an intelligent parser, a download process management, a database, a synthesis process module, and a placement and routing process module, providing a comprehensive design platform to facilitate subsequent various design operations by designers, improving design efficiency and quality. The user source code is the basis of FPGA design. Designers can write code according to specific design requirements to implement specific functions, providing original design materials for subsequent synthesis and placement and routing. Start the synthesis process module, and obtain a synthesis netlist based on the started synthesis process module and the user source code. The synthesis process module of the present invention is a process that can convert high-level hardware description language code into gate-level logic that can be implemented on an FPGA, converting an abstract design description into a specific hardware circuit representation, providing an operable circuit model for subsequent placement and routing. The synthesis netlist is a hardware-level abstract representation of the design function, which contains the connection relationships and logic functions between various logic units in the design, providing accurate circuit information for placement and routing, and helping to optimize the performance and resource utilization of the design. Start the placement and routing process module, and perform placement and routing operations on the synthesis netlist using the started placement and routing process module to obtain a placement and routing netlist. Among them, the placement and routing process module includes: an advanced placement algorithm and a path planning algorithm. The placement and routing process module of the present invention adopts an advanced placement algorithm and a path planning algorithm, which can physically implement the synthesis netlist, reasonably place the logic circuit on the physical resources of the target FPGA chip, and plan the signal routing path to ensure that the design can work properly on the actual FPGA chip. Obtain a design bitstream file according to the placement and routing netlist. Among them, the design bitstream file is a binary file, and the design bitstream file includes: all the information required to configure the FPGA. The present invention configures the FPGA to achieve the functions expected by the designer, which is the key conversion from software description to hardware implementation in FPGA design. Obtain the target FPGA chip and the information of the target FPGA chip, and query the compatibility result between the information of the target FPGA chip and the design bitstream file in the database. Among them, the compatibility result includes: compatible and incompatible. The present invention can discover in advance whether the design bitstream file is compatible with the target FPGA chip by querying the database, avoiding chip damage or program errors caused by incompatibility during the download process, and improving the reliability and stability of the design. If it is confirmed that the compatibility result between the information of the target FPGA chip and the design bitstream file is compatible, then download the design bitstream file to the target FPGA chip to obtain the FPGA device adaptation and download operation process information, whereThe downloaded operation process information includes: time, date, device information, and download result. By determining the compatibility between the information of the target FPGA chip and the design bitstream file, the present invention ensures that the design can be correctly implemented on the target FPGA chip, converts the software design into actual hardware functions, and achieves the ultimate goal of FPGA design. The downloaded operation process information is saved using a pre-built log file to obtain the downloaded operation log. Based on the adapted FPGA device and the downloaded operation log, the FPGA design based on the EDA software system is completed. The present invention records the detailed information of each download operation through the log file, facilitating designers to track problems and analyze problems in the design process, and also meeting the requirements of auditing and quality control. Therefore, the present invention can improve the design efficiency and optimize the design process.

[0135] As Figure 2 shown, it is a module diagram of the EDA software system provided by an embodiment of the present invention.

[0136] The EDA software system 100 described in the present invention can be installed in an electronic device. According to the functions achieved, the EDA software system 100 may include a user source code creation module 101, a synthesis process start module 102, a placement and routing start module 103, and a design file download module 104. The modules described in the present invention may also be referred to as units, which refer to a series of computer program segments that can be executed by the processor of an electronic device and can complete fixed functions, and are stored in the memory of the electronic device;

[0137] The user source code creation module 101 is used to receive FPGA design instructions, start the pre-built EDA software system according to the FPGA design instructions, set the project path according to the started EDA software system, and create user source code according to the project path. Among them, the EDA software system includes: an intelligent parser, a download process management, a database, a synthesis process module, and a placement and routing process module;

[0138] The synthesis process start module 102 is used to start the synthesis process module and obtain a synthesis netlist based on the started synthesis process module and the user source code;

[0139] The placement and routing start module 103 is used to start the placement and routing process module, perform placement and routing operations on the synthesis netlist using the started placement and routing process module to obtain a placement and routing netlist. Among them, the placement and routing process module includes: an advanced placement algorithm and a path planning algorithm. According to the placement and routing netlist, a design bitstream file is obtained. The design bitstream file is a binary file and includes all the information required to configure the FPGA. The target FPGA chip and the information of the target FPGA chip are obtained, and the compatibility result between the information of the target FPGA chip and the design bitstream file is queried in the database. The compatibility result includes: compatible and incompatible;

[0140] The design file download module 104 is configured to download the design bitstream file to the target FPGA chip if it is confirmed that the compatibility result between the information of the target FPGA chip and the design bitstream file is compatible, so as to obtain the information of the adapted FPGA device and the download operation process. The download operation process information includes: time, date, device information, and download result. The download operation process information is saved using a pre-constructed log file to obtain a download operation log, and the FPGA design based on the EDA software system is completed based on the adapted FPGA device and the download operation log.

[0141] Specifically, each module in the EDA software system 100 in the embodiments of the present invention uses the same technical means as the Figure 1 FPGA design method based on the EDA software system described above, and can produce the same technical effects, which will not be elaborated here.

[0142] As Figure 3 shown, it is a schematic structural diagram of an electronic device for implementing the FPGA design method based on the EDA software system provided by an embodiment of the present invention.

[0143] The electronic device 1 may include a processor 10, a memory 11, and a bus 12, and may further include a computer program stored in the memory 11 and executable on the processor 10, such as an FPGA design method program based on the EDA software system.

[0144] Among them, the memory 11 includes at least one type of readable storage medium. The readable storage medium includes flash memory, mobile hard disk, multimedia card, card-type memory (such as SD or DX memory, etc.), magnetic memory, magnetic disk, optical disk, etc. The memory 11 may be an internal storage unit of the electronic device 1 in some embodiments, such as the mobile hard disk of the electronic device 1. The memory 11 may also be an external storage device of the electronic device 1 in other embodiments, such as a plug-in mobile hard disk, a Smart Media Card (SMC), a Secure Digital (SD) card, a Flash Card, etc. equipped on the electronic device 1. Further, the memory 11 further includes an internal storage unit of the electronic device 1 and also includes an external storage device. The memory 11 can not only be used to store application software installed in the electronic device 1 and various types of data, such as the code of the FPGA design method program based on the EDA software system, etc., but also be used to temporarily store data that has been output or will be output.

[0145] In some embodiments, the processor 10 may be composed of an integrated circuit. For example, it may be composed of a single packaged integrated circuit, or may be composed of multiple packaged integrated circuits with the same or different functions, including one or more central processing units (CPUs), microprocessors, digital processing chips, graphics processors, and combinations of various control chips. The processor 10 is the control core (Control Unit) of the electronic device, connecting various components of the entire electronic device through various interfaces and circuits, and by running or executing programs or modules stored in the memory 11 (such as the FPGA design method program based on the EDA software system), and calling the data stored in the memory 11, to execute various functions of the electronic device 1 and process data.

[0146] The bus 12 may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. This bus 12 can be divided into an address bus, a data bus, a control bus, etc. The bus 12 is set to enable connection communication between the memory 11 and at least one processor 10, etc.

[0147] Figure 3 Only the electronic device with components is shown. Those skilled in the art can understand that Figure 3 the shown structure does not constitute a limitation on the electronic device 1, and it may include fewer or more components than shown, or combine certain components, or have a different component layout.

[0148] For example, although not shown, the electronic device 1 may further include a power source (such as a battery) for supplying power to each component. Preferably, the power source can be logically connected to the at least one processor 10 through a power management device, so as to implement functions such as charge management, discharge management, and power consumption management through the power management device. The power source may also include any components such as one or more DC or AC power sources, a recharge device, a power failure detection circuit, a power converter or inverter, and a power status indicator. The electronic device 1 may also include various sensors, a Bluetooth module, a Wi-Fi module, etc., which will not be elaborated here.

[0149] Furthermore, the electronic device 1 may further include a network interface. Optionally, the network interface may include a wired interface and / or a wireless interface (such as a WI-FI interface, a Bluetooth interface, etc.), which is generally used to establish a communication connection between the electronic device 1 and other electronic devices.

[0150] Optionally, the electronic device 1 may further include a user interface, which may be a display, an input unit (such as a keyboard), and optionally, the user interface may also be a standard wired interface or a wireless interface. Optionally, in some embodiments, the display may be an LED display, a liquid crystal display, a touch liquid crystal display, and an OLED (Organic Light-Emitting Diode) toucher, etc. Among them, the display may also be appropriately referred to as a display screen or a display unit, which is used to display the information processed in the electronic device 1 and to display a visual user interface.

[0151] The FPGA design method program stored in the memory 11 of the electronic device 1 is a combination of multiple instructions. When running in the processor 10, it can achieve:

[0152] Receive an FPGA design instruction, start a pre-built EDA software system according to the FPGA design instruction, set a project path according to the started EDA software system, and create user source code according to the project path. Among them, the EDA software system includes: an intelligent parser, a download process management, a database, a synthesis process module, and a placement and routing process module;

[0153] Start the synthesis process module, and obtain a synthesis netlist based on the started synthesis process module and the user source code;

[0154] Start the placement and routing process module, and perform placement and routing operations on the synthesis netlist by using the started placement and routing process module to obtain a placement and routing netlist. Among them, the placement and routing process module includes: an advanced placement algorithm and a path planning algorithm;

[0155] Obtain a design bitstream file according to the placement and routing netlist. Among them, the design bitstream file is a binary file, and the design bitstream file includes: all the information required to configure the FPGA;

[0156] Obtain the target FPGA chip and the information of the target FPGA chip, and query the compatibility result between the information of the target FPGA chip and the design bitstream file in the database. Among them, the compatibility result includes: compatible and incompatible;

[0157] If it is confirmed that the compatibility result between the information of the target FPGA chip and the design bitstream file is compatible, then download the design bitstream file to the target FPGA chip to obtain the FPGA device adaptation and download operation process information. Among them, the download operation process information includes: time, date, device information, and download result;

[0158] Use a pre-built log file to save the information during the download operation, obtain the download operation log, and complete the FPGA design based on the EDA software system by adapting to the FPGA device and the download operation log.

[0159] Specifically, the specific implementation method of the above instructions by the processor 10 can refer to Figures 1 to 3 the description of the relevant steps in the corresponding embodiment, which will not be elaborated here.

[0160] Furthermore, if the modules / units integrated in the electronic device 1 are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. The computer-readable storage medium can be volatile or non-volatile. For example, the computer-readable medium can include: any entity or device capable of carrying the computer program code, recording medium, USB flash drive, mobile hard disk, magnetic disk, optical disc, computer memory, read-only memory (ROM, Read-Only Memory).

[0161] The present invention also provides a computer-readable storage medium. The readable storage medium stores a computer program, and when the computer program is executed by the processor of the electronic device, it can implement:

[0162] Receive the FPGA design instruction, start the pre-built EDA software system according to the FPGA design instruction, set the project path according to the started EDA software system, and create user source code according to the project path. Among them, the EDA software system includes: intelligent parser, download process management, database, synthesis flow module, and placement and routing flow module;

[0163] Start the synthesis flow module, and obtain the synthesis netlist based on the started synthesis flow module and the user source code;

[0164] Start the placement and routing flow module, and perform placement and routing operations on the synthesis netlist using the started placement and routing flow module to obtain the placement and routing netlist. Among them, the placement and routing flow module includes: advanced placement algorithm and path planning algorithm;

[0165] Obtain the design bitstream file according to the placement and routing netlist. The design bitstream file is a binary file, and the design bitstream file includes: all the information required to configure the FPGA;

[0166] Obtain the target FPGA chip and the information of the target FPGA chip, and query the compatibility result between the information of the target FPGA chip and the design bitstream file in the database. The compatibility result includes: compatible and incompatible;

[0167] If it is confirmed that the compatibility result between the information of the target FPGA chip and the design bitstream file is compatible, then download the design bitstream file to the target FPGA chip to obtain the information of the adapted FPGA device and the download operation process, where the download operation process information includes: time, date, device information, and download result;

[0168] Use the pre-constructed log file to save the download operation process information to obtain the download operation log, and complete the FPGA design based on the EDA software system based on the adapted FPGA device and the download operation log.

[0169] In several embodiments provided by the present invention, it should be understood that the disclosed devices, systems, and methods can be implemented in other ways. For example, the system embodiments described above are only illustrative, and there can be other division methods in actual implementation.

[0170] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0171] In addition, in each embodiment of the present invention, the functional modules can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above integrated unit can be implemented in the form of hardware or in the form of a combination of hardware and software functional modules.

[0172] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above exemplary embodiments, and can be implemented in other specific forms without departing from the spirit or basic characteristics of the present invention.

[0173] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. An FPGA design method based on an EDA software system, characterized in that: The method comprises: Receive FPGA design instructions, start a pre-built EDA software system according to the FPGA design instructions, set a project path according to the started EDA software system, and create user source code according to the project path, wherein the EDA software system includes: intelligent parser, download process management, database, comprehensive process module and layout and routing process module; Start the integrated flow module, and obtain the integrated netlist based on the started integrated flow module and the user source code; Starting the layout and routing process module, and using the started layout and routing process module to perform layout and routing operations on the integrated netlist to obtain a layout and routing netlist, wherein the layout and routing process module includes: an advanced layout algorithm and a path planning algorithm; Obtaining a design bitstream file according to the layout and routing netlist, wherein the design bitstream file is a binary file, and the design bitstream file includes: all information required to configure the FPGA; Obtaining information of a target FPGA chip and a target FPGA chip, querying the database for a compatibility result between the information of the target FPGA chip and the design bitstream file, wherein the compatibility result includes: compatible and incompatible; If it is confirmed that the information of the target FPGA chip is compatible with the compatibility result of the design bitstream file, the design bitstream file is downloaded to the target FPGA chip to obtain the adapted FPGA device and the download operation process information, wherein the download operation process information includes: time, date, device information and download result; The pre-built log file is used to save the download operation process information to obtain the download operation log. Based on the adapted FPGA device and the download operation log, the FPGA design based on the EDA software system is completed.

2. The FPGA design method based on the EDA software system according to claim 1, characterized in that: The step of obtaining a comprehensive netlist based on the started comprehensive flow module and user source code includes: Reading the user source code based on the started comprehensive flow module, and parsing the read user source code using the intelligent parser to obtain source code data, wherein the intelligent parser includes: Verilog and SystemVerilog; Performing syntax check on the source code data to obtain verification source code data, and performing data initialization on the verification source code data to obtain initialization source code data; Performing a technology mapping operation on the initialization source code data and standardizing the structure of the mapped initialization source code data to obtain a standard structure source code, wherein the technology mapping operation includes: DSP, storage mapping, register mapping, LUT mapping and other device mappings; Using a pre-built optimization algorithm to perform optimization operations on the standard structure source code to obtain an initial optimized circuit, wherein the optimization operations include: circuit optimization and clock optimization, wherein the optimization algorithm includes: constant propagation, dead code elimination, logic simplification, and area and speed trade-off optimization; Performing a final inspection operation on the initial optimized circuit to obtain a final inspection result, and when the final inspection result of the initial optimized circuit is a preset passing result, confirming the initial optimized circuit as an optimized circuit, wherein the final inspection operation includes: circuit connection inspection, drive unit inspection, hierarchy inspection, and timing inspection; Generate a synthetic netlist based on the optimized circuit.

3. The FPGA design method based on the EDA software system according to claim 1, characterized in that: The method of using the activated layout and routing process module to perform layout and routing operations on the integrated netlist to obtain a layout and routing netlist includes: The integrated netlist is read and parsed using the started placement and routing flow module to obtain a logic unit set; Performing a physical mapping phase on the logical unit set to obtain a physical device set with a determined connection relationship, wherein the physical mapping phase includes: device mapping and local connection; Performing layout phase operations on the physical device set, determining the spatial position of each physical device in the physical device set, obtaining an optimal layout set, and performing device position check on each optimal layout set in the optimal layout set to obtain a standard optimal layout set; Get the standard thermal distribution map of the FPGA design chip; Performing routing phase operations on the standard optimal layout set according to the standard heat distribution map to obtain the optimal layout and routing set, wherein the routing phase operations include: initializing the model, forward routing path finding, reverse routing check, netlist connection check and timing analysis; Generate a place-and-route netlist based on the optimal place-and-route set.

4. The FPGA design method based on the EDA software system as claimed in claim 3, characterized in that: The physical mapping stage is performed on the logical unit set to obtain a physical device set with a determined connection relationship, including: Obtain the physical location set of the target FPGA chip, and perform the following operations on each logic unit in the logic unit set: Mapping the logical unit to a target physical location in the physical location set, wherein the logical unit corresponds to the physical location one by one; The target physical locations are summarized to obtain a set of physical devices with a determined connection relationship corresponding to the logical unit set.

5. The FPGA design method based on the EDA software system as claimed in claim 3, characterized in that: The performing of the layout phase operation on the physical device set, determining the spatial position of each physical device in the physical device set, and obtaining the optimal layout set includes: Constructing a layout equation according to the physical device set, obtaining a clock constraint, and grouping the logic unit set according to the clock constraint to obtain a plurality of logic unit groups; Extract one logical unit group from multiple logical unit groups in turn, and perform the following operations on each of the extracted logical unit groups: Utilizing the layout equation, advanced layout algorithm and path planning algorithm to perform layout analysis on the logic unit group to obtain a suboptimal layout, wherein the advanced layout algorithm includes: simulated annealing, genetic algorithm and particle swarm optimization; According to the preset key component positions, the suboptimal layout is constrained to obtain the optimal layout; The optimal layout is summarized and the spatial position of each physical device in the physical device set is determined to obtain the optimal layout set corresponding to the multiple logic unit groups.

6. The FPGA design method based on the EDA software system as claimed in claim 3, characterized in that: The step of obtaining a standard thermal distribution diagram of the FPGA design chip includes: Use the EDA software system to simulate the initial thermal distribution map of the FPGA design chip, and compare the effects of the initial thermal distribution map with the preset thermal distribution map; If the initial thermal distribution map does not meet the preset thermal distribution map effect, the hot spot area is obtained according to the initial thermal distribution map, and the layout and wiring of the hot spot area are adjusted until the initial thermal distribution map meets the preset thermal distribution map effect to obtain a standard thermal distribution map.

7. The FPGA design method based on the EDA software system according to claim 1, characterized in that: The step of downloading the design bitstream file to the target FPGA chip to obtain the adapted FPGA device and download operation process information includes: Obtain multiple program download interfaces, including JTAG, USB and Ethernet; Extracting a target download interface from multiple program download interfaces and setting a custom download configuration, wherein the custom download configuration includes: download speed, selecting a target device and setting specific download parameters; Obtain the development environment according to the target FPGA chip, the target download interface and the custom download configuration, and start the download process management, wherein the download process management includes the process management mechanism; Use the process management mechanism to monitor the download process in real time and provide real-time feedback information, including download progress, error detection and troubleshooting; Get advanced encryption, authentication mechanisms and download options, including automated and batch downloads; According to the development environment, download function options, advanced encryption and verification mechanisms, the design bitstream file is downloaded to the target FPGA chip to obtain an adapted FPGA device, and download operation process information is generated according to real-time feedback information.

8. The FPGA design method based on the EDA software system as claimed in claim 7, characterized in that: Before downloading the design bitstream file to the target FPGA chip according to the development environment, download function options, advanced encryption and verification mechanism, the method further includes: If it is confirmed that error detection or difficult problem diagnosis appears in the real-time feedback information, the EDA software system is used to provide a solution, and the error detection or difficult problem diagnosis is solved according to the solution until the error detection or difficult problem diagnosis does not appear in the real-time feedback information.

9. An EDA software system, characterized in that: The system comprises: A user source code creation module is used to receive FPGA design instructions, start the pre-built EDA software system according to the FPGA design instructions, set the project path according to the started EDA software system, and create user source code according to the project path, wherein the EDA software system includes: intelligent parser, download process management, database, comprehensive process module and layout and routing process module; A comprehensive process startup module is used to start the comprehensive process module and obtain a comprehensive netlist based on the started comprehensive process module and user source code; A layout and routing startup module is used to start the layout and routing process module, and use the started layout and routing process module to perform layout and routing operations on the integrated netlist to obtain a layout and routing netlist, wherein the layout and routing process module includes: an advanced layout algorithm and a path planning algorithm, and obtains a design bitstream file according to the layout and routing netlist, wherein the design bitstream file is a binary file, and the design bitstream file includes: all information required to configure the FPGA, obtain information of the target FPGA chip and the target FPGA chip, and query the target FPGA chip information in the database for a compatibility result with the design bitstream file, wherein the compatibility result includes: compatible and incompatible; The design file download module is used to download the design bitstream file to the target FPGA chip if it is confirmed that the information of the target FPGA chip is compatible with the compatibility result of the design bitstream file, and obtain the adapted FPGA device and the download operation process information, wherein the download operation process information includes: time, date, device information and download results, and use a pre-built log file to save the download operation process information to obtain the download operation log, and complete the FPGA design based on the EDA software system based on the adapted FPGA device and the download operation log.

Images