Design method of DDR4 memory card for aviation

Abstract

The application discloses a design method of an aviation DDR4 memory card, splits out a memory card from a complex DDR part circuit, fully considers the requirements of DDR on signal integrity and timing during memory card design, and compresses the size of the sub-card as much as possible, designs the part as a typical general circuit, and decouples the processor, so that the memory card can finally be used as a shelf product and be adapted to various application scenes, solves the problems of high design complexity of the DDR circuit, low soldering yield, difficult failure positioning, difficult repair and the like in the application of the aviation product, effectively improves the design and problem troubleshooting efficiency, reduces the product iteration times, and realizes cost reduction and benefit increase.

Description

TECHNICAL FIELD

[0001] The application relates to the field of DDR circuit in avionics circuit, in particular to a design method of an aviation DDR4 memory card. BACKGROUND

[0002] Avionics has engineering characteristics of high reliability requirement, high density and high iteration cost. As the most core circuit in the minimum system of the processor, the DDR uses a high-speed parallel bus with high design difficulty. With the continuous improvement of performance requirements, the selection of DDR is continuously upgraded, the signal rate is higher and higher, the layout and wiring difficulty is higher and higher, the signal integrity design and timing control requirement is more and more strict, and the design of DDR has become a difficulty of the whole circuit board design. Any design mistake of a detail may cause DDR access failure or rate reduction. At present, the mainstream DDR used in the aviation field has been gradually upgraded from DDR3 to DDR4, and the signal rate has been upgraded from 1Gbps to 2Gbps. In order to meet the performance requirements of the product, the number of DDR4 particles of each channel is usually 4, 5 or 9. The address line adopting the flyby topology is prone to signal integrity problems after mounting multiple DDR4 particles. The layout and wiring of DDR4 have the characteristics of strong independence and are only related to the processor. The layout and wiring of this part of circuit should be physically reused in different projects, but due to multiple restrictions of size and circuit board device density, this part of circuit has to be repeatedly adjusted. The soldering yield of high-density circuit is lower than that of ordinary circuit board. After assembly, the stress is more complex than that of ordinary circuit board. The device un-soldering rate caused by the deformation of the printed board is higher. When repairing the un-soldered device, it is more likely to cause the un-soldering of the surrounding devices due to the small distance between the devices. The probability of soldering problem of DDR4 is higher due to the large number of devices and large area occupied. It is difficult to locate the soldering problem chip when the soldering problem occurs.

[0003] Based on the above design difficulties, the application provides a design method of an aviation DDR4 memory card. The method separates the DDR circuit to form a DDR4 memory card which is easy to disassemble. The low-loss, high-reliability and solder-free button is used to realize the interconnection between the DDR4 memory card and the processor. The DDR4 memory card can occupy a small area of the circuit board, and the complex circuit of the DDR part can be decoupled from the whole circuit, which brings benefits in reliability, efficiency and cost, and has a value and application prospect that cannot be ignored. SUMMARY

[0004] The application aims to provide a design method of an aviation DDR4 memory card, which splits the complex DDR part circuit to form a memory card, fully considers the requirements of DDR on signal integrity and timing during the design of the memory card, and tries to compress the size of the sub-card, designs the part as a typical general circuit, decouples with the processor, and finally can be used as a shelf product to adapt to various application scenarios, solves the problems of high design complexity, low soldering yield, difficult failure positioning and repair in the application of aviation products, effectively improves the design and problem troubleshooting efficiency, reduces the product iteration times, and realizes cost reduction and efficiency increase.

[0005] The application aims to provide a design method of an aviation DDR4 memory card, which splits the complex DDR part circuit to form a memory card, fully considers the requirements of DDR on signal integrity and timing during the design of the memory card, and tries to compress the size of the sub-card, designs the part as a typical general circuit, decouples with the processor, and finally can be used as a shelf product to adapt to various application scenarios, solves the problems of high design complexity, low soldering yield, difficult failure positioning and repair in the application of aviation products, effectively improves the design and problem troubleshooting efficiency, reduces the product iteration times, and realizes cost reduction and efficiency increase.

[0006] The application aims to provide a design method of an aviation DDR4 memory card, which splits the complex DDR part circuit to form a memory card, fully considers the requirements of DDR on signal integrity and timing during the design of the memory card, and tries to compress the size of the sub-card, designs the part as a typical general circuit, decouples with the processor, and finally can be used as a shelf product to adapt to various application scenarios, solves the problems of high design complexity, low soldering yield, difficult failure positioning and repair in the application of aviation products, effectively improves the design and problem troubleshooting efficiency, reduces the product iteration times, and realizes cost reduction and efficiency increase.

[0007] The number of layers of the DDR4 memory card is designed as 8, of which 4 layers are used for wiring control, and the remaining 4 layers are used to ensure the power supply, signal backflow and signal shielding performance;

[0008] 5 pieces of 16-bit width DDR4 particles are selected for design to realize 72-bit data width and 8-bit ECC check bit;

[0009] The signal arrangement of the pin connector interconnection signal area adopts 5 columns and 56 rows, with a total of 280 pins;

[0010] When the interconnection signal is defined, the data line is isolated from the data line by a ground pin, and there are not less than three ground pins beside each data signal pin;

[0011] When the interconnection signal is defined, the address and control line are isolated by a ground or power pin, and there are not less than two ground or power pins beside each signal pin;

[0012] The address line is set to 17, and the BG is set to 1;

[0013] Flyby wiring mode is adopted when wiring the clock, address and control line, the main line part and the terminal termination wiring impedance of the wiring are controlled as single-ended 45±5Ω and differential 75±8Ω, and the branch wiring impedance between the DDR particles is controlled as single-ended 50±5Ω and differential 100±10Ω;

[0014] The branch wiring in the Flyby topology is not more than 100 mil long between the DDR particle pins;

[0015] The branch wiring in the Flyby topology is not more than 800 mil long between the terminal termination resistance;

[0016] Clock, address, control signal lines are all equal length control;

[0017] Data lines are grouped and equal length controlled, and each group of data line traces is placed on the same layer, and the length error of the data lines in the group is less than or equal to 5 mils;

[0018] The wiring is ensured to meet the 3W principle.

[0019] Further, the size of the DDR4 memory card is set to be not greater than 33.5*74mm.

[0020] Further, the thickness of the DDR4 memory card is controlled to be 1.6±0.16mm.

[0021] Further, the row pitch and column pitch of each pin are both 1mm.

[0022] Further, the pad of the pin header interconnection signal area adopts a double-sided windowing process.

[0023] Further, the pad of the pin header interconnection signal area adopts a hole-in-disk plus plug hole process.

[0024] Further, five screw holes are opened on the DDR4 memory card, three screw holes are used on one side of the pin header to offset the stress applied to the printed board by the pin header through screws, and two screw holes are used on the other side to reinforce the daughter card.

[0025] The beneficial effects of the present application are as follows:

[0026] The DDR4 memory card designed in the present application can realize DDR4 interconnection with the processor carrier board through the pin header. The complex DDR circuit is stripped out during design to reduce the design difficulty of the processor, improve the design success rate, avoid repeated design of the DDR circuit, shorten the design cycle, and more easily locate the fault as the processor or the DDR fault when the DDR access fails. When repairing, the DDR circuit can be independently removed to reduce the influence domain of local heating during device repair. When the capacity or model of the DDR is changed, the DDR memory card can be directly changed, which reduces the cost and cycle of re-development. The design success rate, reliability, soldering success rate, repair success rate, and fault positioning efficiency of the product are significantly improved, and the project development cycle is shortened and the project cost is saved.

[0027] The DDR4 memory card made by the design method has significant benefits in improving the design success rate, reliability, soldering success rate, repair success rate, and fault positioning efficiency of the product, and can shorten the project development cycle and save project cost. It has an irreplaceable value and application prospect for further improving the reliability and development cycle of China's avionics products. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 is a schematic diagram of the front of a DDR4 memory card implemented by the present application;

[0029] Figure 2 is a schematic diagram of the back of a DDR4 memory card implemented by the present application. DETAILED DESCRIPTION

[0030] The present application will be further described in detail below with reference to the accompanying drawings and examples.

[0031] The design method of a DDR4 memory card for aviation shown in the present example, which realizes DDR4 interconnection through a pin and a processor carrier board.

[0032] The selection of the printed circuit board, the number of layers, the layer structure, and the selection of the device, etc. are consistent with the product characteristics of the related industry and related units, in order to achieve the purpose of simulating engineering practice scheme. When designing the DDR4 memory card, the following steps are followed:

[0033] The number of layers of the DDR4 memory card is designed to be 8 layers, of which 4 layers are used for wiring control, and the remaining 4 layers are used to ensure power supply, signal return flow, and signal shielding performance. The thickness of the DDR4 memory card is controlled to be 1.6±0.16mm, and the thickness of 1.6mm ensures that the printed board can withstand the stress caused by the pin on the basis of meeting the existing 8-layer board processing technology capability.

[0034] 5 pieces of 16-bit wide DDR4 particles are selected for design to realize 72-bit data width, covering the requirements of most processors for DDR4 data width, and having 8-bit ECC check bits to improve the robustness of DDR4 design.

[0035] The signal arrangement of the pin interconnection signal area uses a quantity of 5 columns and 56 rows, a total of 280 pins, which can provide sufficient pins for signal return flow on the premise of meeting the functional requirements of DDR for the number of pins, and the row spacing and column spacing of each pin are both 1mm, to ensure that the length occupied by 56 rows of pins and 5 DDR particles on the printed board is equivalent on the premise of meeting reasonable wiring spacing.

[0036] When defining the interconnection signal, it is ensured that there are ground pins between data lines, and there are not less than three ground pins beside each data signal pin, to play the role of providing a return circuit, impedance control, and crosstalk suppression for the signal.

[0037] When defining the interconnection signal, it is ensured that there are ground or power pins between address and control lines, and there are not less than two ground or power pins beside each signal pin, to play the role of providing a return circuit, impedance control, crosstalk suppression, and power supply for the signal.

[0038] The interconnection signal definition ensures the smoothness of the wiring and the signal integrity. The signal area is defined as follows:

[0039]

[0040]

[0041]

[0042] The address line is set to 17, and the BG is set to 1, so as to realize the maximum addressing capacity of 8GB in the existing size by using 5 pieces of DDR4 particles.

[0043] The Flyby wiring mode is adopted when wiring the clock, address, and control lines. The main line part and the terminal termination wiring impedance of the wiring are controlled to be single-ended 45±5Ω and differential 75±8Ω, and the branch wiring impedance between the DDR particles is controlled to be single-ended 50±5Ω and differential 100±10Ω, so as to realize compensation of the impedance change caused by the capacitive load of the signal.

[0044] In the Flyby topology, the branch wiring to the split length between the pins of the DDR particles does not exceed 100 mil, so as to reduce the impedance mutation caused by the split.

[0045] In the Flyby topology, the wiring length between the branch wiring to the terminal termination resistance does not exceed 800 mil, so as to reduce the influence of the reflection caused by the terminal termination wiring impedance mismatch on the DDR particles.

[0046] The clock, address, and control signal lines are all controlled to be equal in length, so as to ensure that the wiring length error between the processor and each DDR particle is ≤10 mil, so as to meet the DDR read-write access timing.

[0047] The data lines are controlled to be equal in length in groups, and each group of data line wiring is placed on the same layer, and the length error of the data lines in the group is ≤5 mil, so as to meet the DDR read-write access timing.

[0048] The wiring is ensured to meet the 3W principle between signals, so as to reduce the crosstalk between signals. The size of the DDR4 memory card is set to be not greater than 33.5×74mm, and the size of the card is compressed as much as possible under the premise of meeting the reliability of soldering, so that the card can adapt to most application scenarios.

[0049] The pin interconnection signal area pad adopts a double-sided windowing process, so as to keep the DDR4 memory card flexible in assembly and testing.

[0050] The pin interconnection signal area pad adopts a hole-in-disk plus plug hole process, so as to ensure that the signal is reasonably fanned out from the signal interconnection area while the pin contact is well contacted.

[0051] The card has five screw holes for fixing with the module, three screw holes are used on one side of the button to offset the stress applied on the printed board by the button through screws; two screw holes are used on the other side to reinforce the daughter card.

[0052] Referring to Figure 1 Fig. 1 is a front view of a DDR4 memory card according to the design method of the DDR4 memory card for aviation provided by the embodiment, DDR4 particles are arranged on the front, which should be outward in the environment requiring heat dissipation. Fig. 2 is a back view of the DDR4 memory card, which can be outward in the environment without heat dissipation, at this time, the DDR4 particle via hole pad can be used for waveform testing. The memory card can be connected with the processor through the button pressure connection in the interconnection signal area, the interconnection signal area is double-sided windowed, and the pressure connection can be selected on which side according to actual needs. Figure 2

[0053] It can be understood that, for those skilled in the art, equivalent replacements or changes can be made according to the technical solutions and inventive concepts of the present application, and all these changes or replacements shall belong to the protection scope of the claims attached to the present application.​

Claims

1. A design method of an aeronautical DDR4 memory card, which realizes DDR4 interconnection with a processor carrier board through a molex connector, characterized in that It comprises the following steps: The number of layers of the DDR4 memory card is designed to be 8, of which 4 layers are used for wiring control, and the remaining 4 layers are used to ensure power supply, signal backflow and signal shielding performance; 5 pieces of 16-bit wide DDR4 particles are selected for design to realize 72-bit data width and 8-bit ECC check bit; The signal arrangement of the pinout area of the button interconnection signal uses 5 columns and 56 rows, with a total of 280 pins; When defining the interconnection signal, ensure that there is a ground pin between the data lines, and there are not less than three ground pins beside each data signal pin; When defining the interconnection signal, ensure that there is a ground or power pin between the address and control lines, and there are not less than two ground or power pins beside each signal pin; The address line is set to 17, and the BG is set to 1; When wiring the clock, address and control lines, the Flyby wiring method is used, and the main line part and the terminal termination wiring impedance of the wiring are controlled to be single-ended 45±5Ω and differential 75±8Ω, and the branch wiring impedance between the DDR particles is controlled to be single-ended 50±5Ω and differential 100±10Ω; The branch wiring in the Flyby topology does not exceed 100 mil in length between the DDR particle pins; The branch wiring in the Flyby topology does not exceed 800 mil in length between the terminal termination resistor; The clock, address and control signal lines are all controlled to be equal in length. The data lines are grouped and controlled to be equal in length, and each group of data line wiring is placed on the same layer, and the length error of the data lines in the group is ≤5 mil; When wiring, ensure that the distance between signals meets the 3W principle.

2. The design method of a DDR4 memory card for an aircraft according to claim 1, characterized in that It also comprises: the size of the DDR4 memory card is set to be not greater than 33.5×74mm.

3. The design method of a DDR4 memory card for an aircraft according to claim 1, characterized in that It also comprises: the thickness of the DDR4 memory card is controlled to be 1.6±0.16mm.

4. The design method of a DDR4 memory card for an aircraft according to claim 1, characterized in that It also comprises: the row pitch and column pitch of each pin are both 1mm.

5. The design method of a DDR4 memory card for an aircraft according to claim 1, wherein It also comprises: the pinout area of the button interconnection signal area uses a double-sided windowing process.

6. The design method of a DDR4 memory card for an aircraft according to claim 1, wherein It also comprises: the pinout area of the button interconnection signal area uses a hole-in-disk plus plug hole process.

7. The design method of a DDR4 memory card for an aircraft according to claim 1, wherein It also comprises: five screw holes are opened on the DDR4 memory card, three screw holes are used on one side of the button to offset the stress applied to the printed board by the button through screws; and two screw holes are used on the other side to reinforce the daughter card.

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