An intelligent design method for microwave chip circuit architecture

Abstract

The present invention discloses an intelligent design method for microwave chip circuit architecture, comprising the following steps: indicator input, netlist digitization, automatic transistor selection, automatic selection of matching network impedance points, automatic Smith chart matching, automatic determination of the matching network netlist, automatic generation of the netlisted circuit structure, automatic determination of the DC bias network netlist, automatic determination of the overall network netlist, automatic layout conversion, comparison of theoretical and actual indicators, and automatic generation of a circuit diagram. The method of the present invention requires no human intervention throughout the entire process; only the user needs to input indicators to generate the chip layout, thus shortening the design time of microwave chips and effectively applying it to microwave chip circuit design.

Description

Technical Field

[0001] The present invention belongs to the field of microwave chip circuit design, and in particular relates to an intelligent design method for a microwave chip circuit architecture. Background Art

[0002] With the development of data analysis and the gradual transition of artificial intelligence technology from research to application, multidisciplinary integration has become a hot research topic in recent years. Radar systems both domestically and internationally are rapidly moving towards chip integration. Faced with radar and communication systems with diverse frequency bands, reducing chip design time and improving design efficiency have become key research priorities. Summary of the Invention

[0003] The purpose of the present invention is to address the problems of high design threshold, long design time and low design efficiency of existing microwave chips, and to provide an intelligent design method for microwave chip circuit architecture, computer equipment, computer-readable storage medium and computer program product, which can realize the full-process automated design of microwave chips, effectively save chip design time and improve chip design efficiency.

[0004] To achieve the above objectives, one aspect of the present invention provides a method for intelligently designing a microwave chip circuit architecture, comprising:

[0005] Indicator input step, receiving input indicators;

[0006] Netlist digitization step, extracting component connection relationships, component values and component types from the netlist file and forming an array;

[0007] The automatic transistor selection step uses the Monte Carlo tree search method, taking the input indicators as the basis for determining the key nodes of the tree, screening the gate width and gate voltage that meet the indicators, and completing the automatic transistor selection;

[0008] The matching network impedance point automatic selection step uses the interstage DC capacitor as the division point for dividing the cascade circuit into subcircuits, sets the left and right nodes of the capacitor as the starting points of the previous and next subcircuits respectively, and sets the next interstage capacitor or the chip starting port as the end point. Using a breadth-first algorithm, all paths between the two points are searched to form a subcircuit network. The input impedance, output impedance, or minimum noise impedance of the subcircuit network is calculated respectively to complete the automatic selection of the impedance points of the cascade circuit matching network.

[0009] The Smith chart automatic matching step uses the Smith chart graphical method, taking the matching network impedance point as the starting point and end point, and the matching network equal Q line as the boundary condition of the impedance matching path, to complete the path between the starting point and the end point, and realize the automatic determination of the matching network netlist;

[0010] The automatic generation step of the netlist circuit structure determines the DC bias based on the gate voltage and gate width selected in the automatic transistor selection step. By parsing the netlist file of the circuit architecture, networks are added at the nodes of the circuit architecture to generate the circuit structure, and the DC bias network netlist is automatically determined, thus achieving the automatic determination of the overall network netlist.

[0011] In the layout automatic conversion step, the netlist devices are randomly optimized, the random error values are retained, and the randomly optimized netlist is gradient optimized. By comparing the generated error values with the random error values, each device is iterated in turn to achieve the conversion of all ideal devices to actual layout devices;

[0012] Theoretical and actual index comparison step: compare the actual simulation results with the input index. If the difference with the index value does not exceed the tolerance, the process proceeds to the circuit diagram automatic generation step. If the difference with the index value exceeds the tolerance, the process returns to the netlist digitization step.

[0013] The automatic circuit diagram generation step automatically converts the digital netlist into an intuitive graphical circuit diagram.

[0014] Another aspect of the present invention provides a computer device, comprising a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the above method.

[0015] Another aspect of the present invention provides a computer-readable storage medium having a computer program stored thereon, which implements the steps of the above method when executed by a processor.

[0016] Yet another aspect of the present invention provides a computer program product, comprising a computer program, which implements the steps of the above method when executed by a processor.

[0017] According to the above aspects of the present invention, the intelligent design method of microwave chip circuit architecture, computer equipment, computer-readable storage medium and computer program product can realize the full-process automated design of microwave chips, effectively save chip design time and improve chip design efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the present invention, the following briefly introduces the drawings used in the description of the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. Those skilled in the art can also derive other drawings based on these drawings without inventive efforts.

[0019] Figure 1 This is a flow chart of a method for intelligent design of microwave chip circuit architecture according to one embodiment of the present invention;

[0020] Figure 2 It is a structural diagram of a computer device according to one embodiment of the present invention. DETAILED DESCRIPTION

[0021] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0022] An embodiment of the present invention provides an intelligent design method for microwave chip circuit architecture. Targeting microwave low-noise amplifiers, filters, and other chips that are key components of the transceiver system, the method uses data analysis software Python and microwave simulation software ADS to achieve automated chip design. Users only need to input the parameter indicators of interest, and the chip layout can be generated without human intervention in the intermediate process.

[0023] like Figure 1 As shown, the intelligent design method of the microwave chip circuit architecture of the embodiment of the present invention includes the following steps: indicator input, netlist digitization, automatic transistor selection, automatic selection of matching network impedance points, automatic Smith chart matching, automatic generation of netlist circuit structure, automatic determination of DC bias network netlist, automatic determination of overall network netlist, automatic layout conversion, comparison of theoretical and actual indicators, and automatic generation of circuit diagram.

[0024] In the indicator input step, the data analysis software Python is used to receive user input indicators.

[0025] In the netlist digitization step, the input index, component connection relationship, component value and component type are digitized. In one embodiment, the component connection relationship, component value and component type are extracted from the netlist file and formed into an array.

[0026] In the automatic transistor selection step, the Monte Carlo Tree Search (MCTS) method is used to replace the traversal scanning of the transistor gate width and gate voltage to improve the efficiency of transistor selection. Its design idea is to use the input index as the judgment basis of the MCTS key node, which can effectively narrow the range of the set of requirements that meet all indicators and screen out all transistor bias conditions that meet the indicators. Specifically, values are randomly extracted from the limited range of gate width and gate voltage, and combined with the local parameter traversal method, the gain, noise, current and P1dB indicators are used as the criteria for the key nodes of the tree to screen and feedback step by step to complete the automatic selection of transistors. In one embodiment, the gate width array is composed of [2, 4, 6, 8] and the gate voltage array is composed of [25, 50, 75, 100]. The computer randomly extracts values from the two arrays and uses the traversal loop statement to analyze indicators such as gain to complete the screening of gate width and gate voltage values that meet the indicators.

[0027] During the matching network impedance point selection step, the complex cascade circuit is automatically broken down into a collection of simple sub-circuits. The design concept is to use the inter-stage DC capacitor as the partition point for dividing the cascade circuit into sub-circuits. The left and right nodes of the capacitor are set as the starting points of the previous and next sub-circuits, respectively, and the next inter-stage capacitor or chip starting port is set as the end point. Using a breadth-first algorithm, all paths between the two points are searched to form a new sub-circuit network. The input impedance, output impedance, or minimum noise impedance of the sub-circuit network is calculated separately to complete the automatic selection of the impedance points of the cascade circuit matching network.

[0028] In the Smith chart automatic matching step, the Smith chart diagram method is used as a single-layer recursive logical relationship, dual-element matching is used as the recursive termination condition, and the intermediate impedance point in the matching process is used as the recursive return parameter. Its design concept can be summarized as taking the impedance point of the matching network as the starting point and end point, and the matching network equal Q line as the boundary condition of the impedance matching path to complete the path between the starting point and the end point. The path information includes the type of component, component series, parallel form and component value, thereby realizing the automatic determination of the matching network netlist. In one embodiment, the starting point of the matching network is 50 ohms and the end point is 100 ohms. The equal Q line is constructed on the Smith chart. The area within the equal Q line is the area where the matching path is feasible. The matching from the starting point to the end point is completed by using series and parallel capacitors and inductors.

[0029] During the netlist-based circuit structure automatic generation step, a specific network structure is inserted at any node in the existing circuit architecture to implement functions such as noise matching and impedance matching. The design concept is that the object of the automatically generated circuit architecture is a circuit network. From the outside of the network, the original inserted node needs to be split into two nodes; internally, a new set of nodes, new connection relationships, and new device types and values need to be generated. The network to be inserted can be described by the above three factors. Relying on Python data analysis software, key information (such as the insertion node) in the netlist text file is automatically read and written, and the circuit architecture netlist file is parsed to automatically add networks and automatically generate circuit structures. The gate voltage and gate width selected in the automatic transistor selection step determine the DC bias. Using netlist-based circuit structure automatic generation technology, the DC bias network netlist is automatically determined, achieving automatic determination of the overall network netlist.

[0030] In the automatic layout conversion step, ideal devices are automatically converted into actual layout simulation devices. The design concept is divided into two cases: passive or low-noise devices adopt a front-to-back replacement order; power amplifiers adopt a back-to-front replacement order. First, starting with the first replacement device, all devices except the replacement device are prohibited from optimization. A binary search is performed in the inductor and capacitor layout database to determine the initial value. Based on this, a random algorithm is used for optimization, and the optimized error value is retained. Secondly, a temporary netlist file is generated, and the randomly optimized netlist is gradient optimized. The resulting error value is compared with the random optimization error value. If it is better than the former, the temporary netlist file is overwritten with the source netlist file; if it is worse than the former, the temporary netlist file is deleted, and each conversion device is iterated in turn, ultimately achieving the conversion of all ideal devices to actual layout devices.

[0031] In the step of comparing theoretical and actual indicators, the data analysis software Python is used to make judgments by comparing the input indicators with the actual simulation results. If the range of the difference from the indicator value does not exceed the tolerance within the acceptable range, the circuit diagram automatic generation step is entered; if the range of the difference from the indicator value exceeds the tolerance, the step returns to the netlist digitization step and recalculates.

[0032] In the automatic circuit diagram generation step, the calculated digital netlist is automatically converted into an intuitive graphical circuit diagram. The design concept is to use data processing software to analyze the netlist, extract component connection relationships and size information, generate a file format that meets the requirements of EDA software, and automatically convert it into an intuitive circuit diagram. This completes the intelligent design process of microwave chip circuit architecture.

[0033] The intelligent design method for microwave chip circuit architecture of the embodiment of the present invention is applicable to the design of microwave active and passive chips. The design method does not require human participation throughout the process. The user only needs to input indicators to obtain the chip layout, which shortens the design time of the microwave chip and can be effectively applied in the design of microwave chip circuits.

[0034] The embodiment of the present invention further provides a computer device, which may be a server, and its internal structure diagram may be as shown in FIG. Figure 2 As shown. The computer device includes a processor, a memory and a network interface connected via a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and computer program in the non-volatile storage medium. The database of the computer device is used to store operating parameter data of each framework. The network interface of the computer device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, the steps of the method of the embodiment of the present invention are implemented.

[0035] Those skilled in the art will understand that Figure 2 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0036] An embodiment of the present invention further provides a computer-readable storage medium having a computer program stored thereon, which implements the steps of the method of the embodiment of the present invention when the computer program is executed by a processor.

[0037] An embodiment of the present invention further provides a computer program product, comprising a computer program, which implements the steps of the method of the embodiment of the present invention when executed by a processor.

[0038] The above description is merely illustrative of certain exemplary embodiments of the present invention. It goes without saying that those skilled in the art will be able to modify the described embodiments in various ways without departing from the spirit and scope of the present invention. Therefore, the above drawings and description are illustrative in nature and should not be construed as limiting the scope of protection of the claims.

Claims

1. A method for intelligent design of microwave chip circuit architecture, characterized in that: include: Indicator input step, receiving input indicators; Netlist digitization step, extracting component connection relationships, component values and component types from the netlist file and forming an array; The automatic transistor selection step uses the Monte Carlo tree search method, taking the input indicators as the basis for determining the key nodes of the tree, screening the gate width and gate voltage that meet the indicators, and completing the automatic transistor selection; The matching network impedance point automatic selection step uses the interstage DC capacitor as the division point for dividing the cascade circuit into subcircuits, sets the left and right nodes of the capacitor as the starting points of the previous and next subcircuits respectively, and sets the next interstage capacitor or the chip starting port as the end point. Using a breadth-first algorithm, all paths between the two points are searched to form a subcircuit network. The input impedance, output impedance, or minimum noise impedance of the subcircuit network is calculated to complete the automatic selection of the impedance points of the cascade circuit matching network. The Smith chart automatic matching step uses the Smith chart graphical method, taking the matching network impedance point as the starting point and end point, and the matching network equal Q line as the boundary condition of the impedance matching path, to complete the path between the starting point and the end point, and realize the automatic determination of the matching network netlist; The automatic generation step of the netlist circuit structure determines the DC bias based on the gate voltage and gate width selected in the automatic transistor selection step. By parsing the netlist file of the circuit architecture, networks are added at the nodes of the circuit architecture to generate the circuit structure, and the DC bias network netlist is automatically determined, thus achieving the automatic determination of the overall network netlist. In the layout automatic conversion step, the netlist devices are randomly optimized, the random error values are retained, and the randomly optimized netlist is gradient optimized. By comparing the generated error values with the random error values, each device is iterated in turn to achieve the conversion of all ideal devices to actual layout devices; Theoretical and actual index comparison step: compare the actual simulation results with the input index. If the difference with the index value does not exceed the tolerance, the process proceeds to the circuit diagram automatic generation step. If the difference with the index value exceeds the tolerance, the process returns to the netlist digitization step. The automatic circuit diagram generation step automatically converts the digital netlist into an intuitive graphical circuit diagram.

2. The method according to claim 1, wherein In the automatic transistor selection step, values are randomly extracted from the limited range of gate width and gate voltage, and a local parameter traversal method is adopted to use the input indicators as the criteria of the tree key nodes for step-by-step screening and cyclic feedback to complete the automatic transistor selection.

3. The method according to claim 1 or 2, wherein: In the automatic layout conversion step, the initial value of the netlist device is determined by the dichotomy method, and the random algorithm is used for optimization. The optimized random error value is retained, and a temporary netlist file is generated. The randomly optimized netlist is gradient optimized, and the generated error value is compared with the random error value. If it is better than the random error value, the temporary netlist file is overwritten with the source netlist file; if it is worse than the random error value, the temporary netlist file is deleted, and each device is iterated in turn to realize the conversion of all ideal devices into actual layout devices.

4. A computer device comprising a memory, a processor, and a computer program stored in the memory, characterized in that: The processor executes the computer program to implement the steps of the method according to any one of claims 1 to 3.

5. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 3 are implemented.

6. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 3 are implemented.

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