Time delay determination method and device, electronic equipment and storage medium

Abstract

The embodiment of the invention provides a time delay determination method and device, electronic equipment and a storage medium. According to the scheme, the method comprises the following steps: determining a to-be-processed first line channel and a to-be-processed second line channel in the quantum computing measurement and control system; under the condition that the first line channel and the second line channel establish a link through the first quantum bit, obtaining a relative time delay between corresponding signal transmission durations of the first line channel and the second line channel; searching a first time delay of the first line channel and a second time delay of the second line channel at the current moment; and updating the first time delay and / or the second time delay based on the first time delay, the second time delay and the relative time delay. Through the technical scheme provided by the embodiment of the invention, the time delay of signal transmission between each pulse modulation line channel and each magnetic flux modulation line channel in the quantum computing measurement and control system is determined, so that the quantum state regulation and control signal and the quantum bit frequency regulation and control signal can be transmitted to the quantum bit at the same time; and the accuracy of quantum calculation is improved.

Description

Technical Field

[0001] The present application relates to the field of quantum computing technology, and in particular to a method, device, electronic device and storage medium for determining a time delay. Background Art

[0002] Quantum computing is a computational model that uses the basic properties of quantum mechanics to solve problems. It is achieved by building a quantum physics hardware system that can be precisely operated and running quantum computing software to implement quantum algorithms, solve computational problems, and apply quantum computing to specific problems or fields.

[0003] During quantum computing, the quantum computing measurement and control system (such as the integrated measurement and control machine) transmits the quantum state modulation signal to the interface of the pulse modulation line (i.e., XY line) corresponding to the quantum bit through the pulse modulation line channel, and transmits the quantum bit frequency control signal to the interface of the flux modulation line (i.e., Z line) corresponding to the same quantum bit through the flux modulation line channel. The quantum bit performs quantum computing based on the received quantum state control signal and quantum bit frequency control signal. Summary of the invention

[0004] The purpose of the embodiments of the present invention is to provide a method, device, electronic device and storage medium for determining the delay of signal transmission between each pulse modulation line channel and each flux modulation line channel in a quantum computing measurement and control system, thereby ensuring that the quantum state control signal and the quantum bit frequency control signal can be transmitted to the quantum bit at the same time, thereby improving the accuracy of quantum computing. The specific technical solution is as follows:

[0005] The present invention provides a method for determining a delay, the method comprising:

[0006] Determine a first line channel to be processed and a second line channel to be processed in a quantum computing measurement and control system, wherein the first line channel is used to transmit a quantum state control signal, and the second line channel is used to transmit a quantum bit frequency control signal;

[0007] When the first line channel and the second line channel are linked via the first quantum bit, a relative delay between corresponding signal transmission times of the first line channel and the second line channel is obtained;

[0008] Finding a first delay of the first line channel and a second delay of the second line channel at the current moment; wherein the first delay and the second delay are preset delays, or delays updated before the current moment;

[0009] The first delay and / or the second delay are updated based on the first delay, the second delay and the relative delay.

[0010] The embodiment of the present application further provides a delay determination device, the device comprising:

[0011] A first determination module is used to determine a first line channel to be processed and a second line channel to be processed in a quantum computing measurement and control system, wherein the first line channel is used to transmit a quantum state control signal, and the second line channel is used to transmit a quantum bit frequency control signal;

[0012] An acquisition module, configured to acquire a relative delay between corresponding signal transmission durations of the first line channel and the second line channel when the first line channel and the second line channel are linked via a first quantum bit;

[0013] A first search module, configured to search for a first delay of the first line channel and a second delay of the second line channel at a current moment; wherein the first delay and the second delay are preset delays, or delays updated before the current moment;

[0014] A first updating module is configured to update the first delay and / or the second delay based on the first delay, the second delay and the relative delay.

[0015] The embodiment of the present application also provides an electronic device, including a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus;

[0016] Memory, used to store computer programs;

[0017] The processor is used to implement any of the above-mentioned delay determination method steps when executing the program stored in the memory.

[0018] An embodiment of the present application further provides a computer-readable storage medium, characterized in that a computer program is stored in the computer-readable storage medium, and when the computer program is executed by a processor, any of the above-mentioned delay determination method steps is implemented.

[0019] An embodiment of the present invention further provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute any of the delay determination methods described above.

[0020] An embodiment of the present application also provides a quantum computing measurement and control system to implement any of the above-mentioned delay determination methods.

[0021] Beneficial effects of the embodiments of the present invention:

[0022] The technical solution provided by the embodiment of the present invention determines the first line channel to be processed and the second line channel to be processed in the quantum computing measurement and control system. Then, according to the first delay of the first line channel at the current moment, the second delay of the second line channel at the current moment, and the relative delay between the corresponding signal transmission times of the first line channel and the second line channel, the first delay and / or the second delay can be updated to realize the determination of the signal transmission delay between any pulse modulation line channel and each flux modulation line channel in the quantum computing measurement and control system.

[0023] Since the first delay and / or the second delay is updated based on the relative delay between the first line channel and the second line channel, the updated first delay and / or the updated second delay matches the relative delay, effectively ensuring the accuracy of the updated first delay and / or the updated second delay, thereby ensuring that the quantum state control signal and the quantum bit frequency control signal transmitted respectively through the first line channel and the second line channel can be transmitted to the same quantum bit at the same time, thereby improving the accuracy of quantum computing.

[0024] In addition, when the above-mentioned first delay or second delay is a delay updated before the current moment, that is, the first delay and the second delay have been updated before the current moment according to the relative delay between the first line channel or the second line channel and other line channels, then the first delay and / or the second delay is updated according to the relative delay between the first line channel and the second line channel, which can effectively establish the correlation between the delays of each line channel, so that the delays between each line channel finally determined are correlated with each other, effectively improving the accuracy and correlation of the determined delays, and once the line channel is replaced, the signal can be directly transmitted according to the determined delay without re-determining the delay, thereby improving the applicability of the determined delay.

[0025] Of course, it is not necessary to achieve all of the advantages described above at the same time to implement any product or method of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0027] Figure 1 A schematic diagram of a first flow chart of a delay determination method provided in an embodiment of the present application;

[0028] Figure 2A second flow chart of the delay determination method provided in an embodiment of the present application;

[0029] Figure 3 A third flow chart of the delay determination method provided in an embodiment of the present application;

[0030] Figure 4 A fourth flow chart of the delay determination method provided in an embodiment of the present application;

[0031] Figure 5 A fifth flow chart of the delay determination method provided in the embodiment of the present application;

[0032] Figure 6 A sixth flow chart of the delay determination method provided in an embodiment of the present application;

[0033] Figure 7 A seventh flow chart of the delay determination method provided in the embodiment of the present application;

[0034] Figure 8 An eighth flow chart of the delay determination method provided in an embodiment of the present application;

[0035] Fig. 9 A ninth flow chart of the delay determination method provided in an embodiment of the present application;

[0036] Fig.10 A tenth flow chart of the delay determination method provided in the embodiment of the present application;

[0037] Fig.11 A schematic diagram of an eleventh flow chart of a delay determination method provided in an embodiment of the present application;

[0038] Fig.12 A twelfth flow chart of the delay determination method provided in an embodiment of the present application;

[0039] Fig.13 A schematic diagram of the structure of a delay determination device provided in an embodiment of the present application;

[0040] Fig.14 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0041] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0042] In the related technology, since the quantum state modulation signal and the quantum bit frequency control signal are transmitted to the quantum bit on the quantum chip through the pulse modulation line channel and the flux modulation line channel respectively, it is necessary to perform different processing on the quantum state modulation signal and the quantum bit frequency control signal respectively, such as noise reduction, coupling and other processing. As a result, if the quantum computing measurement and control system sends the quantum state modulation signal and the quantum bit frequency control signal at the same time, the quantum bit cannot receive the quantum state modulation signal and the quantum bit frequency control signal at the same time, which affects the quantum bit's quantum computing process.

[0043] In the related technology, for the XY line interface and Z line interface corresponding to each quantum bit, the relative delay between the corresponding signals of the two interfaces is determined, so as to ensure that the XY line interface and the Z line interface can receive signals at the same time, providing guarantee for the quantum computing process.

[0044] However, since the determined delay is the delay of signal transmission corresponding to the XY line interface and Z line interface corresponding to each quantum bit, the delay is only related to the XY line interface and Z line interface corresponding to each quantum bit, and has no association with other quantum bits. In addition, since the delay is only bound to the XY line interface and Z line interface on the quantum bit, once the line channel connected by the XY line interface and the Z line interface changes, that is, when the line is switched, it is necessary to redetermine the delay between the XY line interface and the Z line interface on the quantum bit.

[0045] In order to solve the problems in the related art, the present application embodiment provides a method for determining a delay. Figure 1 As shown, Figure 1 A first flow chart of a delay determination method provided in an embodiment of the present application is provided. The method can be applied to any electronic device, and the method includes the following steps.

[0046] Step S101, determining a first line channel to be processed and a second line channel to be processed in a quantum computing measurement and control system, wherein the first line channel is used to transmit a quantum state control signal, and the second line channel is used to transmit a quantum bit frequency control signal.

[0047] Step S102, when the first line channel and the second line channel are linked through the first quantum bit, the relative delay between the corresponding signal transmission time of the first line channel and the second line channel is obtained.

[0048] Step S103, searching for a first delay of the first line channel and a second delay of the second line channel at the current moment; wherein the first delay and the second delay are preset delays, or delays updated before the current moment.

[0049] Step S104: updating the first delay and / or the second delay based on the first delay, the second delay and the relative delay.

[0050] In an embodiment of the present application, the above-mentioned quantum computing measurement and control system may include devices such as an arbitrary waveform generator and a DC source. Devices such as arbitrary waveform generators and DC sources may include multiple line channels for signal transmission. For the pulse modulation line channel for transmitting quantum state control signals (i.e., the third line channel hereinafter) and the flux modulation line channel for transmitting quantum bit frequency control signals (i.e., the fourth line channel hereinafter), the third line channel and the fourth line channel can establish a link through the quantum bits on the quantum chip, that is, the third line channel is connected to the interface of the XY line corresponding to the quantum bit, and the fourth line channel is connected to the interface of the Z line corresponding to the quantum bit.

[0051] In the embodiment of the present application, the quantum computing measurement and control system may include a plurality of third circuit channels and a plurality of fourth circuit channels. Here, the number of the third circuit channels and the fourth circuit channels in the quantum computing measurement and control system is not specifically limited.

[0052] pass Figure 1 The method shown, after determining the first line channel to be processed and the second line channel to be processed in the quantum computing measurement and control system, can update the first delay and / or the second delay according to the first delay of the first line channel at the current moment, the second delay of the second line channel at the current moment, and the relative delay between the signal transmission times corresponding to the first line channel and the second line channel, thereby realizing the determination of the signal transmission delay between any pulse modulation line channel and each flux modulation line channel in the quantum computing measurement and control system.

[0053] Since the first delay and / or the second delay is updated based on the relative delay between the first line channel and the second line channel, the updated first delay and / or the updated second delay matches the relative delay, effectively ensuring the accuracy of the updated first delay and / or the updated second delay, thereby ensuring that the quantum state control signal and the quantum bit frequency control signal transmitted respectively through the first line channel and the second line channel can be transmitted to the same quantum bit at the same time, thereby improving the accuracy of quantum computing. In addition, when the above-mentioned first delay or second delay is a delay updated before the current moment, that is, the first delay and the second delay have been updated before the current moment according to the relative delay between the first line channel or the second line channel and other line channels, then the first delay and / or the second delay is updated according to the relative delay between the first line channel and the second line channel, which can effectively establish the correlation between the delays of each line channel, so that the delays between each line channel finally determined are correlated with each other, effectively improving the accuracy and correlation of the determined delays, and once the line channel is replaced, the signal can be directly transmitted according to the determined delay without re-determining the delay, thereby improving the applicability of the determined delay.

[0054] The embodiments of the present application are described below through specific examples.

[0055] With respect to the above step S101, that is, determining a first line channel to be processed and a second line channel to be processed in the quantum computing measurement and control system, the first line channel is used to transmit a quantum state control signal, and the second line channel is used to transmit a quantum bit frequency control signal.

[0056] In an embodiment of the present application, for multiple third line channels and multiple fourth line channels included in the quantum computing measurement and control system, the electronic device can obtain any one of the third line channels as the first line channel to be processed, and obtain any one of the fourth line channels as the second line channel to be processed.

[0057] In an optional embodiment, in order to avoid the situation where the determined first line channel and the second line channel remain unchanged, the electronic device pre-stores a table or character string indicating whether each third line channel and each fourth line channel have ever established a link through a quantum bit (i.e., the second quantum bit below).

[0058] For ease of understanding, the following is explained in a table form, that is, the first list as an example. The value of each cell in the first list is used to indicate whether the third line channel and the fourth line channel corresponding to the cell have ever established a link through the second quantum bit. The first list can be shown in Table 1.

[0059] Table 1

[0060] XY / Z Z1 Z2 Z3 … XY1 0 / 1 0 / 1 0 / 1 … XY2 0 / 1 0 / 1 0 / 1 … XY3 0 / 1 0 / 1 0 / 1 … … … … … …

[0061] In the above Table 1, each row corresponds to a third line channel in the quantum computing measurement and control system, and each column corresponds to a fourth line channel in the quantum computing measurement and control system. Each cell in Table 1 has a corresponding third line channel, fourth line channel and value.

[0062] In an optional embodiment, the value corresponding to each cell in Table 1 may be a first value, such as 0 in Table 1, or a second value, such as 1 in Table 1. When the value corresponding to a cell is 0, it means that before the current moment, the third line channel and the fourth line channel corresponding to the cell have not established a link through the second quantum bit. When the value corresponding to a cell is 1, it means that before the current moment, the third line channel and the fourth line channel corresponding to the cell have established a link through the second quantum bit.

[0063] In an optional embodiment, the initialization value of each cell in the above Table 1 can be the above first value. The above first value and the second value can be any value. In the embodiment of the present application, only the above first value is 0 and the second value is 1 as an example for illustration, which does not serve any limiting role.

[0064] In an optional embodiment, the electronic device may also represent the above Table 1 in the form of a string. For ease of understanding, the example in which the values ​​corresponding to the cells in Table 1 are all the above first values ​​is used for illustration. The above Table 1 may be represented as

[0065] In the embodiment of the present application, the representation of the first list and the character string is not specifically limited. For ease of understanding, the following description is only based on the first list as an example, which does not serve any limiting role.

[0066] In an optional embodiment, when determining the first line channel and the second line channel, as follows Figure 2 As shown, Figure 2 A second flow chart of the delay determination method provided in the embodiment of the present application. Figure 2 In the method shown, the above step S101 is refined into the following steps, namely step S1011.

[0067] Step S1011, according to the third line channel, the fourth line channel and the value corresponding to each cell in the first list, the third line channel and the fourth line channel corresponding to the target cell are determined as the first line channel to be processed and the second line channel to be processed.

[0068] The numerical value corresponding to the above-mentioned target cell is a first numerical value, and the first numerical value indicates that before the current moment, the third line channel and the fourth line channel corresponding to the cell have not established a link through the third quantum bit.

[0069] In this step, the electronic device can traverse each cell in the first list in a pre-set traversal order, such as in a row-by-row traversal order or a column-by-column traversal order. During the traversal process, if a cell with a value equal to the first value is found, the cell is determined as a target cell. At this time, the electronic device can determine the third line channel and the fourth line channel corresponding to the target cell as the first line channel to be processed and the second line channel to be processed. That is, the third line channel corresponding to the target cell is determined as the first line channel to be processed, and the fourth line channel corresponding to the target cell is determined as the second line channel to be processed.

[0070] For ease of understanding, the first table shown in Table 2 is used as an example for explanation.

[0071] Table 2

[0072] XY / Z Z1 Z2 Z3 Z4 XY1 1 0 0 0 XY2 0 0 0 0 XY3 1 1 1 0 XY4 0 0 0 1

[0073] According to Table 2, the above quantum computing measurement and control system includes 4 third line channels, namely XY1-XY4, and 4 fourth line channels, namely Z1-Z4.

[0074] The electronic device can traverse the cells in Table 2 in a row-by-row order. When the electronic device traverses the cells corresponding to XY1 and Z1, since the value corresponding to the cell is 1, that is, the second value, not the first value. At this time, the electronic device can traverse the next cell, that is, the cell corresponding to XY1 and Z2. Since the value corresponding to the cell is 0, that is, the first value, at this time, the electronic device can determine the cell as the target cell.

[0075] After determining the cells corresponding to XY1 and Z2 as target cells, the electronic device can determine the third line channel corresponding to the target cell as the first line channel to be processed, that is, the first line channel is the line channel corresponding to XY1, and determine the fourth line channel corresponding to the target cell as the second line channel to be processed, that is, the second line channel is the line channel corresponding to the above-mentioned Z2.

[0076] In the above embodiment, only the first list is used as an example to illustrate the determination of the first line channel and the second line channel. In addition, the electronic device can also determine the first line channel and the second line channel based on the line channel and the value corresponding to the above character string. For details, refer to the method shown in the above step S1011, which will not be described in detail here.

[0077] Through the above step S1011, the electronic device can determine the third line channel and the fourth line channel corresponding to the target cell with the first value as the first line channel to be processed and the second line channel to be processed according to the value corresponding to each cell in the first list. This effectively avoids the electronic device determining the third line channel and the fourth line channel that have been linked through the third quantum bit as the above-mentioned first line channel and the second line channel, reduces the duplication of the determined first line channel and the second line channel, and improves the efficiency of the corresponding delay between each line channel.

[0078] With respect to the above step S102, that is, when the first line channel and the second line channel establish a link through the first quantum bit, the relative delay between the corresponding signal transmission durations of the first line channel and the second line channel is obtained.

[0079] In this step, after the first line channel and the second line channel establish a link through a quantum bit (recorded as the first quantum bit) on the quantum chip, the electronic device can obtain the signal transmission duration of the first line channel transmitting the quantum state control signal, and the time delay (recorded as the relative delay) between the signal transmission duration of the second line channel transmitting the quantum bit frequency control signal.

[0080] In an optional embodiment, the relative delay may be the time length required to compensate the first line channel relative to the second line channel, or the time length required to compensate the second line channel relative to the first line channel. In this case, the relative delay is a positive number.

[0081] In another optional embodiment, the relative delay may be the time required to compensate or delay the first line channel relative to the second line channel, or the time required to compensate or delay the second line channel relative to the first line channel. In this case, the relative delay may be a positive number or a negative number.

[0082] In the embodiment of the present application, the above relative delay is not specifically limited.

[0083] In an optional embodiment, for the above relative delay, after the first line channel and the second line channel establish a link through the above first quantum bit, the electronic device can obtain the signal transmission time (recorded as the first transmission time) of the quantum state control signal transmitted to the first quantum bit through the first line channel, and obtain the signal transmission time (recorded as the second transmission time) of the quantum bit frequency control signal transmitted to the first quantum bit through the second line channel. The electronic device can calculate the time difference between the first transmission time and the second transmission time as the relative delay.

[0084] In an optional embodiment, the relative delay can reflect the size relationship between the first transmission duration and the second transmission duration. For example, if the relative delay is the first transmission duration minus the second transmission duration, when the relative delay is a positive number, the electronic device can determine that the first transmission duration is greater than the second transmission duration, that is, the speed at which the first line channel transmits the quantum state control signal is slower than the speed at which the second line channel transmits the quantum bit frequency control signal; when the relative delay is a negative number, the electronic device can determine that the first transmission duration is less than the second transmission duration, that is, the speed at which the first line channel transmits the quantum state control signal is faster than the speed at which the second line channel transmits the quantum bit frequency control signal; when the relative delay is 0, the electronic device can determine that the first transmission duration is equal to the second transmission duration, that is, the speed at which the first line channel transmits the quantum state control signal is the same as the speed at which the second line channel transmits the quantum bit frequency control signal.

[0085] In an optional embodiment, for the above relative delay, after the first line channel and the second line channel establish a link through the first quantum bit, the relative duration between the transmission durations of the corresponding signals of the first line channel and the second line channel can be obtained by performing an XYZtiming experiment on the first quantum bit. At this time, the electronic device can obtain the relative duration.

[0086] By transmitting a π pulse on the first line channel, if the frequency of the first quantum bit is the operating frequency of the quantum bit, this π pulse can excite the quantum bit to the |1> state. Therefore, by transmitting a square wave of a certain amplitude on the second line channel, the frequency of the quantum bit can be changed, thereby affecting the effect of the π pulse on the excitation of the quantum bit to the |1> state. When the square wave overlaps with the π pulse, the probability of the quantum bit being excited to the |1> state will change suddenly. Therefore, in the above-mentioned XYZtiming experiment, by continuously changing the sending time of the square wave relative to the π pulse, the time when the square wave and the center of the π pulse are completely aligned can be accurately determined, that is, the time when the |1> state is minimum can be measured. At this time, the electronic device can determine the relative delay between the corresponding signal transmission time of the first line channel and the second line channel.

[0087] In the embodiment of the present application, the method for obtaining the relative duration between the signal transmission durations corresponding to the first line channel and the second line channel is not specifically limited.

[0088] With respect to the above step S103, the first delay of the first line channel and the second delay of the second line channel at the current moment are found; wherein the first delay and the second delay are preset delays, or delays updated before the current moment.

[0089] In an optional embodiment, the electronic device pre-stores the correspondence relationship between the third line channel and the time delay (recorded as the first correspondence relationship), and the correspondence relationship between the fourth line channel and the time delay (recorded as the second correspondence relationship).

[0090] In an optional embodiment, the first correspondence relationship and the second correspondence relationship may be expressed in the form of a table or a character string, etc. Here, the expression method of the first correspondence relationship and the second correspondence relationship is not specifically limited.

[0091] For ease of understanding, the first correspondence relationship and the second correspondence relationship are described in the form of a table. The first correspondence relationship may be shown in Table 3, and the second correspondence relationship may be shown in Table 4.

[0092] Table 3

[0093] Line Channel XY1 XY2 XY3 … Latency 0 0 0 …

[0094] Table 4

[0095] Line Channel Z1 Z2 Z3 … Latency 0 0 0 …

[0096] In the above Table 3 and Table 4, each third line channel and each fourth line channel has a corresponding delay. The delay corresponding to each line channel in the above Table 3 and Table 4 is a preset delay, that is, 0 in the above Table 3 and Table 4. When the delay corresponding to any line channel is updated, the delay corresponding to the line channel in the above Table 3 or Table 4 is recorded as the updated delay. Here, the preset delay of 0 is used as an example for explanation only, and it does not serve any limiting role.

[0097] In the embodiment of the present application, the delay corresponding to each line channel in the second list and the third list can be expressed as: the waiting time corresponding to the line channel when transmitting the corresponding quantum state control signal or the quantum bit frequency control signal. The difference between the delays corresponding to any two line channels is the time difference between the two line channels when transmitting the corresponding quantum state control signal or the quantum bit frequency control signal.

[0098] The delay update in Table 3 and Table 4 above can be based on the relative delay update between any group of the third line channel and the fourth line channel, or can be updated based on the delay update amount corresponding to other line channels associated with itself. The delay update process can be seen in the description below and will not be described in detail here.

[0099] In an optional embodiment, when searching for the first delay and the second delay, as Figure 3 As shown, Figure 3 A third flow chart of the delay determination method provided in the embodiment of the present application. Figure 3In the method shown, the above step S103 is refined into the following steps, namely step S1031-step S1032.

[0100] Step S1031: according to the first corresponding relationship between the line channel and the delay in the second list, searching for the delay corresponding to the first line channel as the first delay.

[0101] In this step, the second list may reflect the first correspondence between each third line channel and the delay. After determining the first line channel, the electronic device may determine the delay corresponding to the first line channel in the first list as the first delay according to the first correspondence between the third line channel and the delay in the first list. The first delay may be the preset delay, or may be the delay updated before the current moment, that is, the delay updated according to the relative delay between the first line channel and the other fourth line channels, or the delay updated according to the corresponding delay update amount of other line channels associated with the first line channel.

[0102] Step S1032: according to the second corresponding relationship between the line channel and the delay in the third list, find the delay corresponding to the second line channel as the second delay.

[0103] In this step, the third list may reflect the second correspondence between each fourth line channel and the delay. After determining the second line channel, the electronic device may determine the delay corresponding to the second line channel in the second list as the second delay according to the second correspondence between the fourth line channel and the delay in the second list. The second delay may be the preset delay, or may be the delay updated before the current moment, that is, the delay updated according to the relative delay between the second line channel and other third line channels, or the delay updated according to the corresponding delay update amount of other line channels associated with the second line channel.

[0104] exist Figure 3 In the illustrated embodiment, only the first correspondence and the second correspondence in the form of a table are taken as an example to illustrate the search for the first delay and the second delay. When the first correspondence and the second correspondence are in other forms, such as the above-mentioned string, etc., the method shown in the above-mentioned steps S1031-S1032 can be referred to for searching the first delay and the second delay, and no specific description is given here.

[0105] In the above Figure 3 In the illustrated embodiment, the above step S1031 may be executed before step S1032, may be executed after step S1032, or may be executed simultaneously with step S1032. Here, the execution order of the above step S1031 and step S1032 is not specifically limited.

[0106] Through the above steps S1031 and S1032, the electronic device can record the above first corresponding relationship through the first list and the above second corresponding relationship through the second list, which effectively improves the convenience and accuracy of obtaining the above first delay and second delay.

[0107] In the above embodiment, the first correspondence relationship and the second correspondence relationship are recorded using the second list and the third list respectively. In addition, the first correspondence relationship and the second correspondence relationship may also be recorded in the same list.

[0108] In the above Figure 1 In the method shown, the above step S102 is performed before step S103. In addition, the above step S102 can also be performed after step S103, or performed simultaneously with step S103. Here, the execution order of the above step S102 and step S103 is not specifically limited.

[0109] With respect to the above step S104, the first delay and / or the second delay is updated based on the first delay, the second delay and the relative delay.

[0110] In this step, after obtaining the above relative delay, the first delay and the second delay, the electronic device can choose to update the first delay, or choose to update the second delay, or choose to update the first delay and the second delay at the same time according to the relative delay, the first delay and the second delay. For the above-mentioned updating method of the first delay and / or the second delay, please refer to the description below, which will not be repeated here.

[0111] In an optional embodiment, in the above Figure 3 In the illustrated embodiment, the above step S104 can be refined into the following steps, namely step S1041.

[0112] Step S1041: based on the first delay, the second delay and the relative delay, update the first delay in the second list, and / or update the second delay in the third list.

[0113] In this step, when the electronic device updates the delay according to the first delay, the second delay and the relative delay, it may update the first delay in the second list and / or update the second delay in the third list.

[0114] In an optional embodiment, when updating the above-mentioned first time delay, the electronic device may update the first time delay in the second list.

[0115] In another optional embodiment, when updating the second time delay, the electronic device may update the second time delay in the third list.

[0116] In another optional embodiment, when the first delay and the second delay are updated simultaneously, the electronic device may update the first delay in the second list and update the second delay in the third list respectively.

[0117] Through the above-mentioned step S1041, when the electronic device updates the above-mentioned first delay and / or second delay, it directly updates the first delay in the above-mentioned second list and / or the second delay in the third list, so as to facilitate the subsequent transmission of quantum state control signals and quantum bit frequency control signals to quantum bits directly according to the delays in the second list and the third list, thereby providing guarantee for the quantum computing process.

[0118] In an optional embodiment, according to the above Figure 1 The method shown in the figure, the embodiment of the present application also provides a method for determining the delay. Figure 4 As shown, Figure 4 A fourth flow chart of the delay determination method provided in the embodiment of the present application. Figure 4 In the method shown, the above step S104 is refined into the following steps, namely step S1042.

[0119] Step S1042: According to the first delay, the second delay and the relative delay, the first delay is updated to the eighth delay, and the second delay is updated to the ninth delay, and the difference between the eighth delay and the ninth delay matches the relative delay.

[0120] In this step, the electronic device can update the first delay and the second delay at the same time according to the first delay, the second delay and the relative delay, so that the difference between the updated first delay (recorded as the eighth delay) and the updated second delay (recorded as the ninth delay) matches the above relative delay.

[0121] The matching of the difference between the eighth delay and the ninth delay and the relative delay can be expressed as the same magnitude of the difference, and the same or opposite signs. For ease of understanding, taking the relative delay as the difference between the second transmission duration and the first transmission duration as an example, at this time, the numerical value of the difference between the eighth delay and the ninth delay is the same as the numerical value of the relative delay, and the sign of the difference is opposite to the sign of the relative delay, that is, when the relative delay is positive, the difference is negative, and when the relative delay is negative, the difference is positive. Here, the matching of the difference between the eighth delay and the ninth delay and the relative delay is not specifically limited.

[0122] In the embodiment of the present application, the update of the first delay and the delay in the above step S1042 can be expressed as an increase in the first delay and the second delay, or as a decrease in the first delay and the second delay, or as an increase in one delay (such as the first delay) and a decrease in the other delay (such as the second delay). Here, the adjustment method of the above first delay and the second delay is not specifically limited.

[0123] Through the above-mentioned step S1042, the electronic device can update the first delay and the second delay based on the above-mentioned relative delay, so that the difference between the updated first delay and the updated second delay matches the relative delay, so that the first line channel and the second line channel can simultaneously transmit the quantum state control signal and the quantum bit frequency control signal to the quantum bit, thereby ensuring the accuracy of quantum computing.

[0124] In an optional embodiment, according to the above Figure 1 The method shown in the figure, the embodiment of the present application also provides a method for determining the delay. Figure 5 As shown, Figure 5 A fifth flow chart of the delay determination method provided in the embodiment of the present application. Figure 5 In the method shown, the above step S104 is refined into the following steps, namely step S1043-step S1044.

[0125] Step S1043: when the relative delay indicates that the signal transmission time length of the first line channel is greater than the signal transmission time length of the second line channel, the second delay is updated to a sixth delay according to the first delay and the relative delay, and the difference between the first delay and the sixth delay is the relative delay.

[0126] In this step, when the relative delay indicates that the first transmission duration is greater than the second transmission duration, if the relative delay is a positive number, the electronic device can determine that the speed at which the first line channel transmits the quantum state control signal is slower than the speed at which the second line channel transmits the quantum bit frequency control signal. At this time, for the line channel with faster transmission, that is, the second line channel, the electronic device can update the delay of the second line channel. That is, the electronic device can update the second delay according to the first delay and the relative delay to obtain the sixth delay.

[0127] The difference between the first delay and the sixth delay is the relative delay, that is, the sixth delay is the difference between the first delay and the relative delay.

[0128] Step S1044: when the relative delay indicates that the signal transmission duration of the first line channel is less than the signal transmission duration of the second line channel, the first delay is updated to the seventh delay according to the second delay and the relative delay, and the difference between the second delay and the seventh delay is the relative delay.

[0129] In this step, when the relative delay indicates that the first transmission duration is less than the second transmission duration, such as when the relative delay is a negative number, the electronic device can determine that the speed at which the first line channel transmits the quantum state control signal is faster than the speed at which the second line channel transmits the quantum bit frequency control signal. At this time, for the faster transmission signal line channel, that is, the first line channel, the electronic device can update the delay of the first line channel. That is, the electronic device can update the first delay according to the second delay and the relative delay to obtain the seventh delay.

[0130] The difference between the second delay and the seventh delay is the relative delay, that is, the seventh delay is the difference between the second delay and the relative delay.

[0131] In the embodiment of the present application, the above step S1043 and step S1044 are steps respectively performed by the electronic device when the first transmission duration is different from the second transmission duration. Here, the execution of the above step S1043 and step S1044 is not specifically limited.

[0132] Through the above steps S1043-S1044, when the above-mentioned first delay or the second delay is updated based on the relative delay, the electronic device updates the delay of the line channel with a faster signal transmission speed according to the delay of the line channel with a slower signal transmission speed among the first line channel and the second line channel and the above-mentioned relative delay, thereby realizing the update of the above-mentioned first delay or the second delay, and ensuring that the updated first delay and the second delay match the relative delay.

[0133] In addition, when the delay is updated based on the relative delay, the electronic device only updates one of the first delay or the second delay, which reduces the operational difficulty of the delay update and reduces the number of operations corresponding to the relative global update.

[0134] In the above Figure 5 In the method shown, only the delay of a line channel with a faster signal transmission speed is adjusted based on the relative delay as an example. In addition, the electronic device can also adjust the delay of a line channel with a slower signal transmission speed based on the relative delay. For details, please refer to the steps shown in the above steps S1043-S1044, which will not be described in detail here.

[0135] In an optional embodiment, when the first delay is greater than the second delay, according to the Figure 1 The method shown in the figure, the embodiment of the present application also provides a method for determining the delay. Figure 6 As shown, Figure 6 The sixth flow chart of the delay determination method provided in the embodiment of the present application is as follows. Figure 6In the method shown above, the above-mentioned step S104 is refined into the following steps, namely step S1045 - step S1046.

[0136] Step S1045, when the first difference is less than the relative delay, update the first delay to the first sum value.

[0137] The above-mentioned first difference is the difference between the first delay and the second delay, and the first sum value is the sum of the second delay and the relative delay.

[0138] Step S1046, when the first difference is greater than the relative delay, update the second delay to the second difference.

[0139] The above-mentioned second difference is the difference between the first delay and the relative delay.

[0140] For ease of understanding, take the first delay as t XY , the second delay as t Z , and the relative delay as t as an example for illustration.

[0141] Since t XY is greater than t Z , therefore, the first difference t1 must be greater than 0, that is, t1 = t XY -t Z > 0. The electronic device can compare the above-mentioned first difference t1 with the above-mentioned relative delay t.

[0142] When the first difference t1 is less than the relative delay t, the electronic device can update the first delay t XY , that is, the updated t' XY = t Z + t. t Z + t is the above-mentioned first sum value. At this time, since t XY -t Z < t, therefore, t XY < t + t Z , that is, the updated t' XY is increased relative to t XY before the update. Correspondingly, the delay update amount Δ corresponding to the first delay = t' XY -t XY = t Z + t - t XY .

[0143] When the first difference t1 is greater than the relative delay t, the electronic device can update the second delay t Z , that is, the updated t' Z = t XY - t. t XY - t is the above-mentioned second difference. At this time, since t XY -t Z>t, therefore, t XY -t>t Z , that is, the updated t′ Z Relative to the t before update Z Correspondingly, the delay update amount corresponding to the second delay Δ=t′ Z -t Z =t XY -tt Z .

[0144] In an optional embodiment, when the first difference is the same as the relative delay, the electronic device may match the first delay and the second delay corresponding to the current moment with the relative delay. At this time, the electronic device may not perform any processing, that is, not update the first delay and the second delay.

[0145] The above steps S1045 and S1046 are steps respectively executed by the electronic device when the comparison result between the first difference and the relative delay is different. Here, the execution of the above steps S1045 and S1046 is not specifically limited.

[0146] In an embodiment of the present application, when the first delay is greater than the second delay, through the above-mentioned steps S1045-S1046, the electronic device can update the first delay or the second delay by adding an operation on the basis of the first delay or the second delay, so that the updated first delay or the second delay will not have a negative delay, thereby reducing the risk of abnormal data.

[0147] In addition, when the delay is updated based on the relative delay, the electronic device only updates one of the first delay or the second delay, which reduces the operational difficulty of the delay update and reduces the number of operations corresponding to the relative global update.

[0148] In an optional embodiment, when the second delay is greater than the first delay, according to the above Figure 1 The method shown in the figure, the embodiment of the present application also provides a method for determining the delay. Figure 7 As shown, Figure 7 The seventh flow chart of the delay determination method provided in the embodiment of the present application is as follows. Figure 7 In the method shown, the above step S104 is refined into the following steps, namely step S1047-step S1048.

[0149] Step S1047: When the third difference is smaller than the relative delay, the second delay is updated to a second sum value.

[0150] The third difference is the difference between the second delay and the first delay, and the second sum is the sum of the first delay and the relative delay.

[0151] Step S1048: When the third difference is greater than the relative time delay, update the first time delay to the fourth difference.

[0152] The above-mentioned fourth difference is the difference between the second time delay and the relative time delay.

[0153] For ease of understanding, still take the first time delay as t XY , the second time delay as t Z , and the relative time delay as t as an example for illustration.

[0154] Since t XY is less than t Z , therefore, the third difference t3 must be greater than 0, that is, t3 = t Z -t XY > 0. The electronic device can compare the above-mentioned third difference t3 with the above-mentioned relative time delay t.

[0155] When the third difference t3 is less than the relative time delay t, the electronic device can update the second time delay t Z , that is, the updated t' Z = t XY + t. t XY + t is the above-mentioned second sum. At this time, since t Z -t XY < t, therefore, t Z < t + t XY , that is, the updated t' Z is increased relative to t Z before the update. Correspondingly, the time delay update amount Δ corresponding to the second time delay = t' Z -t Z = t + t XY -t Z .

[0156] When the third difference t3 is greater than the relative time delay t, the electronic device can update the first time delay t XY , that is, the updated t' XY = t Z -t. t Z -t is the above-mentioned fourth difference. At this time, since t Z -t XY > t, therefore, t Z -t > t xY , that is, the updated t' xY is increased relative to t XY before the update. Correspondingly, the time delay update amount Δ corresponding to the first time delay = t' XY -t XY = t Z -t - t XY .

[0157] In an optional embodiment, when the third difference is the same as the relative delay, the electronic device may match the first delay and the second delay corresponding to the current moment with the relative delay. At this time, the electronic device may not perform any processing, that is, not update the first delay and the second delay.

[0158] The above steps S1047 and S1048 are steps respectively executed by the electronic device when the comparison result between the third difference and the relative delay is different. Here, the execution of the above steps S1047 and S1048 is not specifically limited.

[0159] In an embodiment of the present application, when the first delay is less than the second delay, through the above-mentioned steps S1047-S1048, the electronic device can update the first delay or the second delay by adding an operation on the basis of the first delay or the second delay, so that the updated first delay or the second delay will not have a negative delay, thereby reducing the risk of abnormal data.

[0160] In addition, when the delay is updated based on the relative delay, the electronic device only updates one of the first delay or the second delay, which reduces the operational difficulty of the delay update and reduces the number of operations corresponding to the relative global update.

[0161] In an optional embodiment, when the first delay is the same as the second delay, that is, the t XY and t Z When the first delay and the second delay are the same, the electronic device can update the first delay or the second delay by referring to the method shown in the above step S1045 or step S1047, or the electronic device can update the first delay and the second delay at the same time. Here, the method of updating the delay when the first delay and the second delay are the same is not specifically limited.

[0162] In an optional embodiment, according to the above Figure 2 The method shown in the figure, the embodiment of the present application also provides a method for determining the delay. Figure 8 As shown, Figure 8 The eighth flow chart of the delay determination method provided in the embodiment of the present application is as follows. Figure 8 The following step is added to the method shown, namely step S105.

[0163] Step S105, updating the value corresponding to the target cell to a second value, wherein the second value indicates that the third line channel and the fourth line channel corresponding to the cell before the current moment are linked through the third quantum bit.

[0164] In this step, after the electronic device updates the first delay and / or the second delay, the electronic device may update the value corresponding to the first cell in the first list to a second value, such as 1 in Table 2. The second value may indicate that the third line channel and the fourth line channel corresponding to the cell have established a link through the third quantum bit before the current moment.

[0165] For ease of understanding, the above Table 2 is still used as an example for explanation. After the cells corresponding to XY1 and Z2 are determined as target cells and the delays corresponding to XY1 and / or Z2 are updated, the electronic device can update the values ​​of the cells corresponding to XY1 and Z2 in the above Table 2 to 1, and obtain Table 5.

[0166] Table 5

[0167] XY / Z Z1 Z2 Z3 Z4 XY1 1 1 0 0 XY2 0 0 0 0 XY3 1 1 1 0 XY4 0 0 0 1

[0168] In an embodiment of the present application, after the delay of the third line channel and / or the fourth line channel corresponding to the target cell is updated, by updating the numerical value corresponding to the target cell to the second numerical value, it is convenient for subsequent electronic devices to redetermine the new first line channel and second line channel based on the first list, thereby realizing the determination and update of the delay of all line channels.

[0169] In an optional embodiment, according to the above Figure 8 The method shown in the figure, the embodiment of the present application also provides a method for determining the delay. Fig. 9 As shown, Fig. 9 The ninth flow chart of the delay determination method provided in the embodiment of the present application. Fig. 9 The following steps are added to the method shown, namely step S106 - step S107.

[0170] Step S106: based on the first list, searching for all fifth line channels associated with the updated line channels, where the updated line channels are the first line channels for delay update and / or the second line channels for delay update.

[0171] In an optional embodiment, when searching for all fifth line channels associated with the update line channel, the electronic device may first search for the line channels directly associated with the update line channel (recorded as the ninth line channel) based on the first list, and then for each ninth line channel, search for a line channel directly associated with the ninth line channel and not repeated, as a line channel indirectly associated with the update line channel (recorded as the tenth line channel), and so on, search for a line channel directly associated with each tenth line channel and not repeated, until there are no directly associated and non-repeated line channels for each line channel, thereby obtaining all third line channels associated with the update line channel.

[0172] The direct association between the two line channels can be expressed as follows: in the first list, the values ​​of the cells corresponding to the same line channel of the two line channels are the second values.

[0173] For ease of understanding, taking the delay updated by the electronic device based on the relative delay as the second delay as an example, combined with the above Table 5 as an example, the search process of the fifth line channel is explained.

[0174] After the electronic device updates the value of the target cell corresponding to XY1 and Z2 to 1, since the second delay is updated, the electronic device can determine the second line channel corresponding to the second delay as the updated line channel. For Z2, according to Table 5, since the values ​​of the cells corresponding to XY1 and Z1, the cells corresponding to XY3 and Z1, and the cells corresponding to XY3 and Z3 are all the above-mentioned second values, the electronic device can determine that Z1, Z3, XY1, and XY3 are all directly associated with Z2. That is, Z1, Z3, XY1, and XY3 are all the fifth line channels directly associated with Z2.

[0175] For each line channel among Z1, Z3, XY1 and XY3, the electronic device can further search for line channels associated with the line channel. For example, for Z1, the value of the cell corresponding to XY1 and Z1 is 1, and the value of the cell corresponding to XY3 and Z1 is 1, but XY3 is already the fifth line channel, so there is no directly associated and non-repeating line channel for Z1. Similarly, there is no directly associated and non-repeating line channel for Z3, XY1 and XY3. At this point, the electronic device can determine that the line channels associated with Z2 include Z1, Z3, XY1 and XY3.

[0176] In the embodiment of the present application, the number of fifth line channels associated with the update line channel is not specifically limited.

[0177] Step S107: updating the third delay of each fifth line channel at the current moment according to the delay update amount corresponding to the updated line channel.

[0178] In this step, for each fifth line channel, the electronic device can search the delay of the fifth line channel at the current moment in the second list or the third list. The electronic device can synchronously update the delay of the fifth line channel at the current moment according to the delay update amount corresponding to the update line channel.

[0179] The updating method of the third delay is the same as the updating method of the delay of the line channel.

[0180] For ease of understanding, the delay update amount corresponding to the updated line channel is the above Δ, and the delay of the fifth line channel at the current moment is t7 as an example for explanation.

[0181] If the update method of the delay corresponding to the above-mentioned updated line channel is to increase Δ, the electronic device can determine that the updated delay of the fifth line channel is t7+Δ; if the update method of the delay corresponding to the above-mentioned updated line channel is to reduce Δ, the electronic device can determine that the updated delay of the fifth line channel is t7-Δ.

[0182] In an embodiment of the present application, after the electronic device updates the delay of the above-mentioned update line channel, it synchronously updates the delay corresponding to the associated fifth line channel according to the delay of the update line channel, so that the delay difference between the fifth line channel and the update line channel remains unchanged, thereby ensuring that the delay between the update line channel and the fifth line channel matches the relative delay between the two, thereby ensuring that the signal can be transmitted to different quantum bits on the quantum chip at the same time, thereby improving the accuracy of quantum computing.

[0183] In an optional embodiment, according to the above Figure 8 The method shown in the figure, the embodiment of the present application also provides a method for determining the delay. Fig.10 As shown, Fig.10 The tenth flow chart of the delay determination method provided in the embodiment of the present application is as follows. Fig.10 The following step is added to the method shown, namely step S108.

[0184] Step S108, if it is determined that the target cell exists in the first list, return to the step of determining the third line channel and the fourth line channel corresponding to the target cell as the first line channel to be processed and the second line channel to be processed, until the target cell does not exist in the first list.

[0185] In this step, after updating the value of the above-mentioned target cell to the above-mentioned second value, the electronic device can continue to traverse the above-mentioned first list. When traversing to a cell with a value of the above-mentioned first value, the electronic device can determine that the cell is the above-mentioned target cell, and return to execute the above-mentioned step S1011 to determine the third line channel and the fourth line channel corresponding to the target cell as the first line channel to be processed and the second line channel to be processed, until there is no target cell in the first list.

[0186] Through the above step S108, after the electronic device updates the delay of the third line channel and / or the fourth line channel corresponding to each target cell, it continues to update the delay of the third line channel and / or the fourth line channel corresponding to other target cells in the first list until the value of each cell in the first list is the above second value. At this time, the electronic device can determine the delay corresponding to each third line channel and each fourth line channel, and the delay corresponding to any third line channel and fourth line channel matches the relative delay corresponding to the two, thereby improving the accuracy of the determined delay.

[0187] In an optional embodiment, according to the above Figure 1 The method shown in the embodiment of the present application also provides a method for determining a delay, such as Fig.11 As shown, Fig.11 The eleventh flow chart of the delay determination method provided in the embodiment of the present application includes the following steps.

[0188] Step S1101, determining a first line channel to be processed and a second line channel to be processed in a quantum computing measurement and control system, wherein the first line channel is used to transmit a quantum state control signal, and the second line channel is used to transmit a quantum bit frequency control signal.

[0189] Step S1102, when the first line channel and the second line channel are linked through the first quantum bit, the relative delay between the corresponding signal transmission time of the first line channel and the second line channel is obtained.

[0190] Step S1103, searching for a first delay of a first line channel and a second delay of a second line channel at the current moment; wherein the first delay and the second delay are preset delays, or delays updated before the current moment.

[0191] Step S1104: update the first delay and / or the second delay based on the first delay, the second delay and the relative delay.

[0192] The above steps S1101 to S1104 are the same as the above steps S101 to S104.

[0193] Step S1105, determining the minimum delay according to the fifth delay corresponding to each sixth line channel at the current moment, the sixth line channel being the third line channel with a delay updated before the current moment, or the sixth line channel being the fourth line channel with a delay updated before the current moment.

[0194] In an optional embodiment, for the above second list, the electronic device can determine all third line channels that have been updated with delays before the current moment, and record them as sixth line channels. The electronic device can obtain the fifth delay corresponding to each sixth line channel at the current moment from the second list, and select the minimum delay therefrom (recorded as the first minimum delay).

[0195] In another optional embodiment, for the third list above, the electronic device may determine all fourth line channels that have been updated with delays before the current moment, recorded as sixth line channels. The electronic device may obtain the fifth delay corresponding to each sixth line channel at the current moment from the third list, and select the minimum delay therefrom (recorded as the second minimum delay).

[0196] Step S1106: If the minimum delay is not equal to the third value, then for each sixth line channel, the fifth delay of the sixth line channel is updated to the difference between the fifth delay corresponding to the sixth line channel and the minimum delay.

[0197] In an optional embodiment, for the above-mentioned first minimum delay, the electronic device may compare the first minimum delay with the third value. If the first minimum delay is not equal to the third value, then for each sixth line channel, the electronic device may update the fifth delay corresponding to the sixth line channel in the first list to the difference between the fifth delay and the first minimum delay.

[0198] In another optional embodiment, for the second minimum delay, the electronic device may compare the second minimum delay with the third value. If the second minimum delay is not equal to the third value, then for each sixth line channel, the electronic device may update the fifth delay corresponding to the sixth line channel in the second list to the difference between the fifth delay and the second minimum delay.

[0199] In an optional embodiment, the third value may be 0. When the first minimum delay is equal to the third value, the electronic device may not perform any processing. Alternatively, when the second minimum delay is equal to the third value, the electronic device may not perform any processing.

[0200] Through the above steps S1105-S1106, the electronic device can reset the minimum delay value in the above-mentioned first list and the second list to zero, effectively reducing the data size of each delay in the first list and the second list, making it convenient for subsequent electronic devices to transmit the above-mentioned quantum state control signal and quantum bit frequency control signal according to the delay in the first list and the second list.

[0201] In the above Fig.11In the method shown, only the above-mentioned minimum delay, that is, the above-mentioned first minimum delay and the second minimum delay are positive numbers, is used as an example for explanation. In addition, when the above-mentioned first minimum delay and the second minimum delay are negative numbers, the electronic device can add the absolute value of the first minimum delay or the second minimum delay to the fourth delay of each sixth line channel at the current moment to achieve the above-mentioned zeroing.

[0202] In an optional embodiment, according to the above Figure 1 The method shown in the figure, the embodiment of the present application also provides a method for determining the delay. Fig.12 As shown, Fig.12 The twelfth flow chart of the delay determination method provided in the embodiment of the present application includes the following steps.

[0203] Step S1201, determine a first line channel to be processed and a second line channel to be processed in a quantum computing measurement and control system, where the first line channel is used to transmit a quantum state control signal, and the second line channel is used to transmit a quantum bit frequency control signal.

[0204] Step S1202, when the first line channel and the second line channel are linked through the first quantum bit, the relative delay between the corresponding signal transmission times of the first line channel and the second line channel is obtained.

[0205] Step S1203, searching for a first delay of a first line channel and a second delay of a second line channel at the current moment; wherein the first delay and the second delay are preset delays, or delays updated before the current moment.

[0206] Step S1204: Update the first delay and / or the second delay based on the first delay, the second delay and the relative delay.

[0207] The above steps S1201 to S1204 are the same as the above steps S101 to S104.

[0208] Step S1205, when the first line channel and the second line channel establish a link through the second quantum bit, if an enable signal for the second quantum bit is received, the third delay of the first line channel at the current moment and the fourth delay of the second line channel at the current moment are found.

[0209] In this step, when the first line channel and the second line channel establish a link through the second quantum bit, the user can trigger an enable signal for the second quantum bit. At this time, the electronic device will receive the enable signal. After receiving the enable signal, the electronic device can search the second list for the delay corresponding to the first line channel at the current moment (recorded as the third delay), and search the third list for the delay corresponding to the second line channel at the current moment (recorded as the fourth delay).

[0210] In the embodiment of the present application, the first qubit, the second qubit and the third qubit may be any qubit on the quantum chip. The first qubit, the second qubit and the third qubit may be the same or different.

[0211] Step S1206: According to the time difference between the third delay and the fourth delay, the quantum state control signal and the quantum bit frequency control signal are transmitted to the second quantum bit using the first line channel and the second line channel respectively.

[0212] In this step, after finding the above-mentioned third delay and fourth delay, the electronic device can transmit a quantum state control signal to the second quantum bit through the first line channel and transmit a quantum bit frequency control signal to the second quantum bit through the second line channel according to the time difference between the third delay and the fourth delay.

[0213] For ease of understanding, the third delay is 10 nanoseconds (ns) and the fourth delay is 20ns. The time difference between the fourth delay and the third delay is 10ns. After the electronic device transmits the quantum state control signal to the second quantum bit through the first line channel, after 10ns, the electronic device can transmit the quantum bit frequency control signal to the second quantum bit through the second line channel. Under this condition, the second quantum bit will receive both the quantum state control signal and the quantum bit frequency control signal at the same time.

[0214] Through the above steps S1205-S1206, after the line channels for transmitting the quantum state control signal and the quantum bit frequency control signal are connected to the quantum bit, signal transmission is performed according to the time delay corresponding to each line channel in the above second list and the third list, so that the quantum state control signal and the quantum bit frequency control signal can reach the quantum bit at the same time, avoiding the influence of the time delay of different line channels on the quantum computing process, and improving the quantum computing efficiency.

[0215] In the above Fig.12In the illustrated embodiment, only the second quantum bit links the first line channel and the second line channel as an example to illustrate the transmission of the signal required for the second quantum bit quantum computing process. After the delay of each line channel in the second list and the third list is determined, the electronic device can perform signal transmission based on the delay in the second list and the third list to implement the quantum computing process of each quantum bit.

[0216] Based on the same inventive concept, according to the delay determination method provided in the above embodiment of the present application, the embodiment of the present application also provides a delay determination device. Fig.13 As shown, Fig.13 A schematic diagram of a structure of a delay determination device provided in an embodiment of the present application. The device includes the following modules.

[0217] A first determination module 1301 is used to determine a first line channel to be processed and a second line channel to be processed in a quantum computing measurement and control system, where the first line channel is used to transmit a quantum state control signal, and the second line channel is used to transmit a quantum bit frequency control signal;

[0218] An acquisition module 1302 is used to acquire a relative delay between corresponding signal transmission durations of the first line channel and the second line channel when the first line channel and the second line channel are linked via the first quantum bit;

[0219] A first search module 1303 is used to search for a first delay of a first line channel and a second delay of a second line channel at a current moment; wherein the first delay and the second delay are preset delays, or delays updated before the current moment;

[0220] The first updating module 1304 is configured to update the first delay and / or the second delay based on the first delay, the second delay and the relative delay.

[0221] Optionally, the delay determination device may further include:

[0222] A second search module is used to search for the third delay of the first line channel at the current moment and the fourth delay of the second line channel at the current moment if an enable signal for the second qubit is received when the first line channel and the second line channel establish a link through the second qubit;

[0223] The transmission module is used to transmit the quantum state control signal and the quantum bit frequency control signal to the second quantum bit using the first line channel and the second line channel respectively according to the time difference between the third delay and the fourth delay.

[0224] Optionally, the first determining module 1301 may be specifically configured to determine the third line channel and the fourth line channel corresponding to the target cell as the first line channel to be processed and the second line channel to be processed according to the third line channel, the fourth line channel and the value corresponding to each cell in the first list;

[0225] Among them, the numerical value corresponding to the target cell is the first numerical value, and the first numerical value indicates that before the current moment, the third line channel and the fourth line channel corresponding to the cell have not established a link through the third quantum bit.

[0226] Optionally, the delay determination device may further include:

[0227] The second updating module is used to update the numerical value corresponding to the target cell to a second numerical value after updating the first delay and / or the second delay based on the first delay, the second delay and the relative delay, and the second numerical value indicates that the third line channel and the fourth line channel corresponding to the cell before the current moment are linked through the third quantum bit.

[0228] Optionally, the delay determination device may further include:

[0229] A third search module is used to search all fifth line channels associated with the update line channels based on the first list after updating the value corresponding to the target cell to the second value, where the update line channels are the first line channels of the delay update and / or the second line channels of the delay update;

[0230] The third updating module is used to update the delay of each fifth line channel at the current moment according to the delay update amount corresponding to the updated line channel.

[0231] Optionally, the delay determination device may further include:

[0232] A calling module is used to, after updating the numerical value corresponding to the target cell to the second numerical value, if it is determined that the target cell exists in the first list, return to call the first determination module to execute the step of determining the third line channel and the fourth line channel corresponding to the target cell as the first line channel to be processed and the second line channel to be processed, until the target cell does not exist in the first list.

[0233] Optionally, the delay determination device may further include:

[0234] A second determination module is used to determine the minimum delay according to the fifth delay corresponding to each sixth line channel at the current moment, where the sixth line channel is the third line channel with a delay updated before the current moment, or the sixth line channel is the fourth line channel with a delay updated before the current moment;

[0235] The fourth updating module is configured to update, for each sixth line channel, the fifth delay of the sixth line channel to the difference between the fifth delay corresponding to the sixth line channel and the minimum delay if the minimum delay is not equal to the third value.

[0236] Optionally, the first updating module 1304 may be specifically configured to update the first delay to a first sum value when the first difference is less than the relative delay if the first delay is greater than the second delay;

[0237] When the first difference is greater than the relative delay, updating the second delay to the second difference;

[0238] The first difference is the difference between the first delay and the second delay, the first sum is the sum of the second delay and the relative delay, and the second difference is the difference between the first delay and the relative delay.

[0239] Optionally, the first updating module 1304 may be specifically configured to update the second delay to a second sum value when the third difference is less than the relative delay if the second delay is greater than the first delay;

[0240] When the third difference is greater than the relative delay, updating the first delay to a fourth difference;

[0241] The third difference is the difference between the second delay and the first delay, the second sum is the sum of the first delay and the relative delay, and the fourth difference is the difference between the second delay and the relative delay.

[0242] Optionally, the first updating module 1304 may be specifically configured to update the second delay to a sixth delay according to the first delay and the relative delay when the relative delay indicates that the signal transmission duration of the first line channel is greater than the signal transmission duration of the second line channel, and the difference between the first delay and the sixth delay is the relative delay;

[0243] When the relative delay indicates that the signal transmission duration of the first line channel is less than the signal transmission duration of the second line channel, the first delay is updated to the seventh delay according to the second delay and the relative delay, and the difference between the second delay and the seventh delay is the relative delay.

[0244] Optionally, the first updating module 1304 may be specifically configured to update the first delay to an eighth delay and the second delay to a ninth delay according to the first delay, the second delay and the relative delay, and the difference between the eighth delay and the ninth delay matches the relative delay.

[0245] Optionally, the first search module 1303 may be specifically configured to search for a delay corresponding to the first line channel as the first delay according to a first corresponding relationship between the line channel and the delay in the second list;

[0246] According to the second corresponding relationship between the line channel and the delay in the third list, searching for the delay corresponding to the second line channel as the second delay;

[0247] The first updating module 1304 may be specifically configured to update the first delay in the second list and / or update the second delay in the third list based on the first delay, the second delay and the relative delay.

[0248] Through the device provided in the embodiment of the present application, after determining the first line channel to be processed and the second line channel to be processed in the quantum computing measurement and control system, the first delay and / or the second delay can be updated according to the first delay of the first line channel at the current moment, the second delay of the second line channel at the current moment, and the relative delay between the corresponding signal transmission times of the first line channel and the second line channel, so as to realize the determination of the signal transmission delay between any pulse modulation line channel and each flux modulation line channel in the quantum computing measurement and control system.

[0249] Since the first delay and / or the second delay is updated based on the relative delay between the first line channel and the second line channel, the updated first delay and / or the updated second delay matches the relative delay, effectively ensuring the accuracy of the updated first delay and / or the updated second delay, thereby ensuring that the quantum state control signal and the quantum bit frequency control signal transmitted respectively through the first line channel and the second line channel can be transmitted to the same quantum bit at the same time, thereby improving the accuracy of quantum computing.

[0250] In addition, when the above-mentioned first delay or second delay is a delay updated before the current moment, that is, the first delay and the second delay have been updated before the current moment according to the relative delay between the first line channel or the second line channel and other line channels, then the first delay and / or the second delay is updated according to the relative delay between the first line channel and the second line channel, which can effectively establish the correlation between the delays of each line channel, so that the delays between each line channel finally determined are correlated with each other, effectively improving the accuracy and correlation of the determined delays, and once the line channel is replaced, the signal can be directly transmitted according to the determined delay without re-determining the delay, thereby improving the applicability of the determined delay.

[0251] Based on the same inventive concept, according to the delay determination method provided in the above-mentioned embodiment of the present application, the embodiment of the present application also provides an electronic device, such as Fig.14 As shown, it includes a processor 1401, a communication interface 1402, a memory 1403 and a communication bus 1404, wherein the processor 1401, the communication interface 1402, and the memory 1403 communicate with each other through the communication bus 1404.

[0252] Memory 1403, used for storing computer programs;

[0253] The processor 1401 is used to implement the following steps when executing the program stored in the memory 1403:

[0254] Determine a first line channel to be processed and a second line channel to be processed in a quantum computing measurement and control system, the first line channel is used to transmit a quantum state control signal, and the second line channel is used to transmit a quantum bit frequency control signal;

[0255] When the first line channel and the second line channel are linked through the first quantum bit, a relative delay between the transmission times of the corresponding signals of the first line channel and the second line channel is obtained;

[0256] Finding a first delay of a first line channel and a second delay of a second line channel at the current moment; wherein the first delay and the second delay are preset delays, or delays updated before the current moment;

[0257] Based on the first delay, the second delay and the relative delay, the first delay and / or the second delay is updated.

[0258] After determining the first line channel to be processed and the second line channel to be processed in the quantum computing measurement and control system through the electronic device provided in the embodiment of the present application, the first delay and / or the second delay can be updated according to the first delay of the first line channel at the current moment, the second delay of the second line channel at the current moment, and the relative delay between the corresponding signal transmission times of the first line channel and the second line channel, so as to determine the signal transmission delay between any pulse modulation line channel and each flux modulation line channel in the quantum computing measurement and control system.

[0259] Since the first delay and / or the second delay is updated based on the relative delay between the first line channel and the second line channel, the updated first delay and / or the updated second delay matches the relative delay, effectively ensuring the accuracy of the updated first delay and / or the updated second delay, thereby ensuring that the quantum state control signal and the quantum bit frequency control signal transmitted respectively through the first line channel and the second line channel can be transmitted to the same quantum bit at the same time, thereby improving the accuracy of quantum computing.

[0260] In addition, when the above-mentioned first delay or second delay is a delay updated before the current moment, that is, the first delay and the second delay have been updated before the current moment according to the relative delay between the first line channel or the second line channel and other line channels, then the first delay and / or the second delay is updated according to the relative delay between the first line channel and the second line channel, which can effectively establish the correlation between the delays of each line channel, so that the delays between each line channel finally determined are correlated with each other, effectively improving the accuracy and correlation of the determined delays, and once the line channel is replaced, the signal can be directly transmitted according to the determined delay without re-determining the delay, thereby improving the applicability of the determined delay.

[0261] Furthermore, compared with the method of binding to the signal receiving interface of the quantum bit in the related art, the delay in the embodiment of the present application is bound to the line channel of the signal transmission. Therefore, when a line change occurs, since the delays between the line channels are globally correlated, that is, the delay between the line channel for transmitting the quantum state control signal and the line channel for transmitting the quantum bit frequency control signal after the line change is also accurate, this avoids the need to re-determine the delay when changing the line in the related art, and improves the effectiveness and applicability of the determined delay.

[0262] The communication bus mentioned in the above electronic device can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0263] The communication interface is used for communication between the above electronic device and other devices.

[0264] The memory may include a random access memory (RAM) or a non-volatile memory (NVM), such as at least one disk memory. Optionally, the memory may also be at least one storage device located away from the aforementioned processor.

[0265] The above-mentioned processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0266] Based on the same inventive concept, according to the delay determination method provided in the above-mentioned embodiments of the present application, the embodiments of the present application also provide a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the steps of any of the above-mentioned delay determination methods are implemented.

[0267] Based on the same inventive concept, according to the delay determination method provided in the above-mentioned embodiments of the present application, the embodiments of the present application also provide a computer program product containing instructions, which, when executed on a computer, enables the computer to execute any delay determination method in the above-mentioned embodiments.

[0268] Based on the same inventive concept, according to the delay determination method provided in the above-mentioned embodiments of the present application, the embodiments of the present application also provide a quantum computing measurement and control system to implement any of the above-mentioned delay determination methods.

[0269] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented by software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present invention is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state hard disk Solid State Disk (SSD)), etc.

[0270] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0271] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for embodiments such as devices, electronic devices, computer-readable storage media, computer program products, and quantum computing and control systems, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.

[0272] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A method for determining a delay, characterized in that: The method comprises: Determine a first line channel to be processed and a second line channel to be processed in a quantum computing measurement and control system, wherein the first line channel is used to transmit a quantum state control signal, and the second line channel is used to transmit a quantum bit frequency control signal; When the first line channel and the second line channel are linked via the first quantum bit, a relative delay between corresponding signal transmission times of the first line channel and the second line channel is obtained; Finding a first delay of the first line channel and a second delay of the second line channel at the current moment; wherein the first delay and the second delay are preset delays, or delays updated before the current moment; The first delay and / or the second delay are updated based on the first delay, the second delay and the relative delay.

2. The method according to claim 1, characterized in that The method further comprises: When the first line channel and the second line channel establish a link through the second quantum bit, if an enable signal for the second quantum bit is received, then find the third delay of the first line channel at the current moment and the fourth delay of the second line channel at the current moment; According to the time difference between the third delay and the fourth delay, the quantum state control signal and the quantum bit frequency control signal are transmitted to the second quantum bit by using the first line channel and the second line channel respectively.

3. The method according to claim 1, characterized in that The step of determining a first circuit channel to be processed and a second circuit channel to be processed in the quantum computing measurement and control system comprises: According to the third line channel, the fourth line channel and the value corresponding to each cell in the first list, the third line channel and the fourth line channel corresponding to the target cell are determined as the first line channel to be processed and the second line channel to be processed; Among them, the numerical value corresponding to the target cell is a first numerical value, and the first numerical value indicates that before the current moment, the third line channel and the fourth line channel corresponding to the cell have not established a link through the third quantum bit.

4. The method according to claim 3, characterized in that After updating the first delay and / or the second delay based on the first delay, the second delay and the relative delay, the method further includes: The numerical value corresponding to the target cell is updated to a second numerical value, wherein the second numerical value indicates that the third line channel and the fourth line channel corresponding to the cell before the current moment are linked through the third quantum bit.

5. The method according to claim 4, characterized in that: After updating the value corresponding to the target cell to the second value, the method further includes: Based on the first list, searching for all fifth line channels associated with the update line channels, where the update line channels are the first line channels for delay update and / or the second line channels for delay update; According to the delay update amount corresponding to the updated line channel, the delay of each fifth line channel at the current moment is updated.

6. The method according to claim 4, characterized in that After updating the value corresponding to the target cell to the second value, the method further includes: If it is determined that the target cell exists in the first list, the step of determining the third line channel and the fourth line channel corresponding to the target cell as the first line channel to be processed and the second line channel to be processed is returned to execution until the target cell does not exist in the first list.

7. The method according to claim 6, characterized in that The method further comprises: Determine the minimum delay according to the fifth delay corresponding to each sixth line channel at the current moment, the sixth line channel being the third line channel with the delay updated before the current moment, or the sixth line channel being the fourth line channel with the delay updated before the current moment; If the minimum delay is not equal to the third value, then for each sixth line channel, the fifth delay of the sixth line channel is updated to the difference between the fifth delay corresponding to the sixth line channel and the minimum delay.

8. The method according to claim 1, characterized in that If the first delay is greater than the second delay, the step of updating the first delay and / or the second delay based on the first delay, the second delay and the relative delay includes: When the first difference is less than the relative delay, updating the first delay to a first sum value; When the first difference is greater than the relative delay, updating the second delay to a second difference; The first difference is the difference between the first delay and the second delay, the first sum is the sum of the second delay and the relative delay, and the second difference is the difference between the first delay and the relative delay.

9. The method according to claim 1, characterized in that: If the second delay is greater than the first delay, the step of updating the first delay and / or the second delay based on the first delay, the second delay and the relative delay includes: When the third difference is less than the relative delay, updating the second delay to a second sum value; When the third difference is greater than the relative delay, updating the first delay to a fourth difference; The third difference is the difference between the second delay and the first delay, the second sum is the sum of the first delay and the relative delay, and the fourth difference is the difference between the second delay and the relative delay.

10. The method according to claim 1, characterized in that The step of updating the first delay and / or the second delay based on the first delay, the second delay and the relative delay comprises: When the relative delay indicates that the signal transmission time length of the first line channel is greater than the signal transmission time length of the second line channel, the second delay is updated to a sixth delay according to the first delay and the relative delay, and the difference between the first delay and the sixth delay is the relative delay; When the relative delay indicates that the signal transmission duration of the first line channel is less than the signal transmission duration of the second line channel, the first delay is updated to a seventh delay according to the second delay and the relative delay, and the difference between the second delay and the seventh delay is the relative delay.

11. The method according to claim 1, characterized in that: The step of updating the first delay and / or the second delay based on the first delay, the second delay and the relative delay comprises: According to the first delay, the second delay and the relative delay, the first delay is updated to an eighth delay, and the second delay is updated to a ninth delay, and a difference between the eighth delay and the ninth delay matches the relative delay.

12. The method according to claim 1, characterized in that The step of finding the first delay of the first line channel and the second delay of the second line channel at the current moment includes: According to the first corresponding relationship between the line channel and the delay in the second list, searching for the delay corresponding to the first line channel as the first delay; According to the second corresponding relationship between the line channel and the delay in the third list, searching for the delay corresponding to the second line channel as the second delay; The step of updating the first delay and / or the second delay based on the first delay, the second delay and the relative delay comprises: Based on the first delay, the second delay and the relative delay, the first delay in the second list is updated, and / or the second delay in the third list is updated.

13. A delay determination device, characterized in that: The device comprises: A first determination module is used to determine a first line channel to be processed and a second line channel to be processed in a quantum computing measurement and control system, wherein the first line channel is used to transmit a quantum state control signal, and the second line channel is used to transmit a quantum bit frequency control signal; An acquisition module, configured to acquire a relative delay between corresponding signal transmission durations of the first line channel and the second line channel when the first line channel and the second line channel are linked via a first quantum bit; A first search module, configured to search for a first delay of the first line channel and a second delay of the second line channel at a current moment; wherein the first delay and the second delay are preset delays, or delays updated before the current moment; A first updating module is configured to update the first delay and / or the second delay based on the first delay, the second delay and the relative delay.

14. An electronic device, characterized in that: It includes a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other through the communication bus; Memory, used to store computer programs; A processor, for implementing the method steps described in any one of claims 1-12 when executing a program stored in a memory.

15. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method steps described in any one of claims 1 to 12 are implemented.

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