Time prediction method and semiconductor process equipment

Abstract

The invention discloses a time prediction method and semiconductor process equipment. The method comprises the following steps: obtaining the total residual processing time of each wafer in a scheduling task in a current real-time state; acquiring necessary idle time of each processing module in the scheduling task in the current real-time state; and according to the residual processing total time of each wafer and the necessary idle time of each processing module, obtaining the processing completion time of all wafers in the scheduling task in the current real-time state. In the process of predicting the processing completion time, all wafers in the scheduling task are traversed, the remaining processing total time of each wafer is considered, and the necessary idle time of all processing modules in the current real-time state is considered at the same time. Accurate prediction of the processing completion time of all wafers in the whole scheduling task under a certain processing state (namely the current real-time state) is realized.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular, relates to a time prediction method and semiconductor process equipment. Background Art

[0002] Semiconductor processing is one of the most advanced and complex manufacturing industries today. In order to adapt to the complexity and precision requirements of semiconductor processing, semiconductor process equipment is often composed of a combination of multiple modules. The prediction of the time to complete processing (i.e., the remaining completion time) of semiconductor process equipment scheduling can not only serve as an important basis for the scheduling action planning of the semiconductor process equipment itself, but also the predicted index value can be provided as an important system parameter to the users of semiconductor process equipment as a reference for decision-making. It can also be used as a key indicator for factory-level task management, task issuance, and material transmission planning in semiconductor processing plants. It is an important basis for the intelligent scheduling of single semiconductor process equipment and the entire semiconductor processing plant.

[0003] Related technology, commonly used methods for predicting the time to complete a process are mainly to estimate the time to complete a process before the process starts, and it is difficult to accurately predict the time to dynamically complete a process under a specific state. Summary of the invention

[0004] The purpose of the embodiments of the present application is to provide a time prediction method and semiconductor process equipment to solve the problem in the related art that it is difficult to accurately predict the time for dynamic completion of processing under specific conditions.

[0005] To achieve the above objectives, the present application embodiment adopts the following technical solutions: In a first aspect, an embodiment of the present application provides a time prediction method for predicting the completion time of a scheduled task of semiconductor processing during semiconductor processing, including: obtaining the total remaining processing time of each wafer in the scheduled task under the current real-time state; obtaining the necessary idle time of each processing module in the scheduled task under the current real-time state; and obtaining the completion time of all wafers in the scheduled task under the current real-time state based on the total remaining processing time of each wafer and the necessary idle time of each processing module.

[0006] In a second aspect, an embodiment of the present application provides a semiconductor process equipment, comprising: a controller and multiple processing modules, wherein the controller is arranged in a host computer and / or a slave computer of the semiconductor process equipment, and the controller comprises at least one processor and at least one memory, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the steps of the time prediction method described in the embodiment of the first aspect of the present application are implemented.

[0007] At least one of the above technical solutions adopted in the embodiments of the present application can achieve the following beneficial effects: When predicting the time to complete processing in real time, the embodiment of the present application obtains the total remaining processing time of each wafer in the scheduling task under the current real-time state and the necessary idle time of each processing module in the scheduling task under the current real-time state, and obtains the time to complete processing of all wafers in the scheduling task under the current real-time state based on the total remaining processing time of each wafer and the necessary idle time of each processing module. In the process of predicting the time to complete processing, the embodiment of the present application traverses all wafers in the scheduling task, takes into account the total remaining processing time of each wafer, and takes into account the necessary idle time of all processing modules in the current real-time state, thereby achieving an accurate prediction of the time to complete processing of all wafers in the entire scheduling task under a certain processing state (i.e., the current real-time state). BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings: Figure 1 A schematic diagram of the structure of a semiconductor process equipment provided for one embodiment of the present application; Figure 2 A schematic flow chart of a time prediction method provided for one embodiment of the present application; Figure 3 A schematic diagram of various time meanings in wafer processing provided for one embodiment of the present application. DETAILED DESCRIPTION

[0009] In order to make the purpose, technical solution and advantages of the present application clearer, the technical solution of the present application will be clearly and completely described below in combination with the specific embodiments of the present application and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.

[0010] The terms "first", "second", etc. in this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here. In addition, the "and / or" in this application represents at least one of the connected objects, and the character " / " generally represents that the front and back associated objects are in an "or" relationship. It should be noted that the data involved in this application are all obtained on the premise of obtaining user authorization.

[0011] To clearly illustrate the time prediction method and semiconductor process equipment of the present application, the following is combined with Figure 1 The application scenario of the time prediction method of the embodiment of the present application is described. The semiconductor process equipment of the embodiment of the present application is often composed of a combination of multiple processing modules, such as a cluster device commonly used for wafer processing, whose processing modules generally include a processing module (chamber 11, calibration position 12 and cooling position 13), a manipulator (atmospheric manipulator 14 and vacuum manipulator 15), a loading port 16 and a vacuum lock 17, etc. Figure 1 As shown. Figure 1 It can be seen that the semiconductor process equipment is composed of multiple cascades (atmospheric cascade, vacuum cascade 1 and vacuum cascade 2) with the robot as the core. Each cascade includes multiple processing modules. The processing modules include the following types: 1) Load Port (LP) 16: mainly used to connect to a wafer cassette storing wafers, supporting the atmospheric robot 14 to take wafers to be processed and put back processed wafers.

[0012] 2) Process Module (PM): a module used to perform processing, calibration, cooling and other operations, including a chamber (CH) 11, an aligner (AL) 12 and a cooling position (CL) 13.

[0013] 3) Load Lock (LL) 17: It is used to connect the atmospheric side module and the vacuum side module, store wafers, and realize part of the processing process, so as to realize the flow of wafers between the atmospheric side and the vacuum side. The inside of the load lock can be kept in the atmospheric state or evacuated into a vacuum state by an air pump.

[0014] 4) Transfer Robot (TR): A transfer unit used to transfer wafers between processing modules, including an air transfer robot (ATR) 14 and a vacuum transfer robot (VTR) 15. The vacuum transfer robot VTR15 transfers wafers between the vacuum side LL17 and the processing module, and the air transfer robot ATR14 transfers wafers between the atmosphere side LP16, the processing module and LL17.

[0015] The technical solutions provided by various embodiments of the present application are described in detail below in conjunction with the accompanying drawings.

[0016] Figure 2 A schematic diagram of a time prediction method provided by an embodiment of the present application. Figure 2As shown, the time prediction method of the embodiment of the present application is used to predict the completion time of the scheduling task of semiconductor processing during the semiconductor processing process, and may specifically include the following steps: S201, obtaining the total remaining processing time of each wafer in the scheduling task in the current real-time state.

[0017] In the embodiment of the present application, the execution subject of the time prediction method of the embodiment of the present application is a controller, and the controller can be set in the upper computer and / or the lower computer of the semiconductor process equipment.

[0018] The current real-time state refers to any processing state or any real-time scheduling state of semiconductor process equipment. The time corresponding to this state is the current time point of the system. T .

[0019] The scheduling task includes multiple wafers, each of which corresponds to a processing path. The processing path of the wafer includes multiple consecutive processing steps, and each processing step contains only one processing action (which can be one of the four types of actions: wafer pick-up, wafer movement, wafer placement, and process action). The connection relationship between the four types of actions is as follows: Figure 3 As shown in the figure, the processing time of each type of processing action is pre-defined by the processing path of each wafer. When a processing step has multiple processing actions, it means that the processing step can select any one of the actions (no multiple actions will be selected).

[0020] 1) Wafer removal: The robot takes the wafer from the loading port LP, processing module PM or the slot in the vacuum lock LL and puts it on the robot.

[0021] 2) Wafer placement: The robot places the wafer on it into the slot in the load port LP, process module PM or vacuum lock LL.

[0022] 3) Moving action: The process of moving the wafer from one position to another on the robot.

[0023] 4) Process action: The process in which the wafer completes processing operations such as etching, deposition, cleaning, calibration and cooling according to the planned time in the processing module PM or vacuum lock LL.

[0024] Among them, only the two actions of taking and placing the wafer will cause the position of the wafer to change. The moving action only occurs when the wafer is on the robot arm, and the process action only occurs when the wafer is in the processing module or vacuum lock. The loading port is generally only responsible for storing wafers that have not yet started processing or have been processed, and is not used to execute process actions.

[0025] In the scheduling of semiconductor process equipment, the time to complete the processing of the scheduled task mainly depends on the total remaining processing time of each wafer. It is also affected by the necessary idle time of the processing module in the scheduled task (time that cannot be fully utilized, specifically refers to when a certain processing module meets the processing conditions of a certain processing step, the wafer to be processed needs to wait for a period of time before reaching the processing module for processing due to the long previous process time. During this period, the processing module can only be in an idle state) and the number of slots of the processing module in the scheduled task (determines the maximum number of wafers that can be processed simultaneously).

[0026] Among them, Figure 3 As shown in the figure, the total remaining processing time of the wafer consists of two parts: the remaining processing time of the current step and the time spent on the remaining steps of the completion. Under a certain real-time scheduling state, the relationship between the remaining processing time of the current step, the time spent on the remaining steps of the completion, and the time spent on the remaining steps of the intermediate process is as follows: Figure 3 The meaning of each time part is as follows: 1) Remaining processing time of the current step: that is, in a certain real-time state, the processing action of the current processing step of the wafer, minus the completed part, the remaining processing time required.

[0027] 2) Time spent on the remaining steps to complete the process: that is, under a certain real-time state, for the current processing step of the wafer, the sum of the processing action times of all processing steps from the next processing step (including the next processing step) to the completion step (including the completion step).

[0028] 3) Total remaining processing time of wafer: that is, in a certain real-time state, the remaining processing time of the wafer in the current step and the total processing time of all subsequent processing steps until completion. It is the sum of the previous two times: the remaining processing time of the current step and the remaining processing time of the completion step.

[0029] 4) Time consumed by the remaining steps: that is, for a certain processing step, the sum of the processing action time of all processing steps from the next processing step (including the next processing step) to a certain intermediate step (including the intermediate step). Among them, the intermediate step is the subsequent step of the above processing step and is not a completed step.

[0030] based on Figure 3It can be seen that the remaining total processing time of each wafer can be obtained through the following steps: obtain the remaining step consumption time for completion of the current processing step corresponding to the wafer in the current real-time state; obtain the remaining processing time of the current step in the current processing step of the wafer in the current real-time state; obtain the sum of the remaining step consumption time for completion of the current processing step corresponding to the wafer and the remaining processing time of the current step in the current processing step of the wafer to obtain the remaining total processing time of the wafer.

[0031] Specifically, assuming the wafer processing path s Mid-processing steps p The remaining steps of the completion process take time L s,p , wafer processing path s Processing steps p Wafer w The remaining processing time of the current step is I s,p,w The sum of the two can be used to obtain the wafer processing path in the current real-time state. s Processing steps p Wafer w The remaining processing time X s,p,w , as shown below: X s,p,w = I s,p,w + L s,p Among them, the time consumed to complete the remaining steps of the current processing step corresponding to the wafer in the current real-time state can be obtained through the following steps: obtain the sum of the processing action times in all subsequent processing steps corresponding to the current processing step of the wafer in the current real-time state, and obtain the time consumed to complete the remaining steps of the current processing step corresponding to the wafer.

[0032] Specifically, for the wafer processing path s Mid-processing steps p The time taken to complete the remaining steps is p The sum of the processing action times of all processing steps from the start of the next processing step (including the next processing step) to the completion step (including the completion step).

[0033] Assume that in a certain wafer processing path s Next, the processing steps p The subsequent shortest processing path is pp 1 p 2 … p k … pf ,in p f For the finishing step, processing step p The corresponding remaining steps of the completion process take time L s,p The processing steps in the shortest processing path p All subsequent processing steps time d ( p k )( k =1,…, f ), as shown below:

[0034] Among them, the remaining processing time of the wafer in the current processing step in the current real-time state can be obtained through the following steps: if the time that the wafer has been processed in the current processing step in the current real-time state exceeds the time the wafer is planned to be processed in the current processing step, then the remaining processing time of the wafer in the current processing step in the current processing step is determined to be zero; if the time that the wafer has been processed in the current processing step in the current real-time state does not exceed the time the wafer is planned to be processed in the current processing step, then the remaining processing time of the wafer in the current processing step in the current processing step is determined to be the difference between the time the wafer is planned to be processed in the current processing step and the time the wafer has been processed in the current processing step.

[0035] Specifically, the remaining processing time of the wafer in the current step is the time the wafer is planned to be processed in the current step minus the time the wafer has been processed in the current step. The time the wafer has been processed in the current step is the current time point of the system. T Subtract the start time of the wafer current step g s,p,w ,Right now Tg s,p,w .

[0036] In the current real-time state, assuming a wafer processing path s Wafer w In the current processing step p The processing start time is g s,p,w , the system current time point is T , wafer w In the current processing step p The planned processing time is d(s , p , w) .

[0037] If the wafer w In the current processing step pProcessing time Tg s,p,w Larger than wafer w In the current processing step p Planned processing time d(s , p , w) ,Right now Tg s,p,w > d(s , p , w) , then it means wafer w Processing has been completed and the wafer is confirmed w In the current processing step p The remaining processing time of the current step I s,p,w is 0, that is I s,p,w =0.

[0038] If the wafer w In the current processing step p Processing time Tg s,p,w Equal to or smaller than wafer w In the current processing step p Planned processing time d(s , p , w) ,Right now Tg s,p,w ≤ d(s , p , w) , then it means wafer w Not processed yet, confirm the wafer w In the current processing step p The remaining processing time of the current step I s,p,w For wafer w In the current processing step p Planned processing time d(s , p , w) With wafer w In the current processing step p Processing time Tg s,p,w The difference between I s,p,w = d(s, p , w)- ( T- g s,p,w ).

[0039] Combining the above two situations, the wafer w In the current processing step p The remaining processing time of the current step I s,p,w It can be obtained by the following formula: I s,p,w = max {0, d(s , p , w)- ( Tg s,p,w )} S202, obtaining the necessary idle time of each processing module in the scheduling task under the current real-time state.

[0040] In an embodiment of the present application, the necessary idle time of each processing module in the current real-time state can be obtained through the following steps: if the usage time point of the earliest use of the action of the processing module in the current real-time state is equal to or less than the earliest available time point of the processing module, the necessary idle time of the processing module is determined to be zero, and the usage time point of the earliest use of the action of the processing module is the minimum value of the predicted trigger time points of all actions that need to use the processing module; if the usage time point of the earliest use of the action of the processing module in the current real-time state is greater than the earliest available time point of the processing module, the necessary idle time of the processing module is determined to be the difference between the usage time point of the earliest use of the action of the processing module and the earliest available time point of the processing module.

[0041] The predicted triggering time point of an action is when all preceding actions of the action are completed and the processing module required by the action is available, the action can be triggered. This time point is the predicted triggering time point of the action.

[0042] Assuming the use of processing module r The set of all actions of A r , in the current real-time state, A r Medium Action α The predicted trigger time point is PT s,α,r , processing module r The earliest available time point is IS r . | If the processing module is used first r The time point of using the action my { PT s,α,r | α ∈ A r}Equal to or less than the processing module r The earliest available time point IS r ,Right now my { PT s,α,r | α ∈ A r}≤ IS r , it means that the processing module is used at the earliest r The time point of using the action, processing module r Not yet available or just available, so determine the processing module r Necessary free time G r ( M,R ) is 0, that is, G r ( M,R )=0.

[0043] If the processing module is used first r The time point of using the action my { PT s,α,r | α ∈ A r} is greater than the processing module r The earliest available time point IS r ,Right now my { PT s,α,r | α ∈ A r}> IS r , then it means the processing module r After it is in the available state, it takes some time before it can be used, so determine the processing module r Necessary free time G r ( M,R ) is the earliest used processing module r The time point of using the action my { PT s,α,r | α ∈ A r} and processing module r The earliest available time point ISr The difference my { PT s,α,r | α ∈ A r}- IS r , that is, G r ( M,R )= my { PT s,α,r | α ∈ A r}- IS r .

[0044] Combining the above two situations, the processing module r Necessary free time G r ( M,R ) can be obtained by the following formula: G r ( M,R )= max (0, my { PT s,α,r | α ∈ A r}- IS r ) Among them, the predicted trigger time point of the action that requires the use of the processing module is obtained through the following steps: the maximum value of the earliest trigger time point of the action that requires the use of the processing module and the earliest available time point of the processing module is determined as the predicted trigger time point of the action that requires the use of the processing module.

[0045] Specifically, due to the action α Prediction trigger time point PT s,α,r For the action α All preceding actions of α Processing modules to be occupied r Available, this action α It can be triggered, and the time point at this time is the action α Prediction trigger time point PT s,α,r , therefore, the action α Prediction trigger time point PT s,α,r On the one hand, it needs to be later than the time when the previous action is completed (that is, the earliest trigger time point EP s,α ), on the other hand, needs to be later than the action αProcessing modules to be occupied r The earliest available time point IS r , i.e. action α Prediction trigger time point PT s,α,r To use the processing module r Action α The earliest trigger time EP s,α and processing modules r The earliest available time point IS r The maximum value in the action α Prediction trigger time point PT s,α,r It can be obtained by the following formula: PT s,α,r = max ( EP s,α , IS r ) Among them, the earliest available time point of the processing module in the current real-time state is obtained through the following steps: if the processing module is not fully occupied by wafers in the current real-time state, the earliest available time point of the processing module is determined to be the current time point of the system; if the processing module is fully occupied by wafers in the current real-time state, the earliest available time point of the processing module is determined to be the minimum value of the earliest trigger time point of the action of all wafers currently occupying the processing module to subsequently leave the processing module.

[0046] Specifically, the earliest available time point of the processing module in the current real-time state can be obtained according to two situations: the processing module is fully occupied by the wafers and the processing module is not fully occupied by the wafers.

[0047] 1) In the current real-time state, if the processing module r If the wafer is not fully occupied, the processing module is determined r The earliest available time point IS r is the current time point T of the system, that is IS r =T.

[0048] 2) In the current real-time state, if the processing module r If all wafers are occupied, determine the processing module r The earliest available time point IS r Processing module for current occupancy r All wafers subsequently leave the processing module r The minimum value of the earliest triggering time point of the action.

[0049] Assume occupancy processing module r The set of all wafers is O r , w For collection O r A wafer in w The corresponding wafer path is s ( w ), the corresponding subsequent actions are α ( w ), wafer w Subsequent departure processing module r The earliest triggering time point of the action is EP s(w),α(w) , processing module r The earliest available time point IS r It can be obtained by the following formula: IS r = my { EP s(w),α(w) | w ∈ O r} In the above formula, my { EP s(w),α(w) | w ∈ O r} represents the earliest exit processing module r The departure time of the wafer, which leaves the post-processing module r becomes available, so the departure time is also the processing module r The earliest available time. For example, if a chamber (a processing module) is occupied by multiple wafers, each wafer occupies a slot in the chamber, and the subsequent action of each wafer is to take the wafer out of the chamber, then the earliest available time of the chamber is the departure time of the wafer that leaves the chamber earliest.

[0050] Among them, the earliest triggering time point of the action that requires the use of the processing module in the current real-time state is obtained through the following steps: in the current real-time state, if there is a wafer in the previous processing step of the action, the earliest triggering time point of the action is determined to be the sum of the current time point of the system and the minimum value of the remaining processing time of the current step of all wafers in the previous processing step of the action; if there is no wafer in the previous processing step of the action in the current real-time state, the earliest triggering time point of the action is determined to be the sum of the current time point of the system and the shortest time for all wafers in the previous processing step to reach the previous processing step of the action and complete processing in the previous processing step.

[0051] Among them, the time when all wafers in the previous step arrive at the previous processing step and complete processing in the previous processing step can be obtained by the following steps: obtain the earliest time when all wafers in the intermediate processing step leave the intermediate processing step and the sum of the time consumed by the remaining steps from the intermediate processing step to the previous processing step, and obtain the time when all wafers in the previous step arrive at the previous processing step and complete processing in the previous processing step. The intermediate processing step is the processing step subsequent to the current processing step except the previous processing step.

[0052] Specifically, the earliest triggering time point of the action that requires the use of the processing module in the current real-time state can be obtained according to two situations: a wafer exists in the previous processing step of the action and a wafer does not exist in the previous processing step of the action.

[0053] 1) In the current real-time state, if the wafer processing path s An action in α If there is a wafer in the previous processing step, then determine the action α The earliest trigger time point is the current system time point T + action α The minimum remaining processing time of the current step for all wafers in the previous processing step.

[0054] Assume machining path s Medium Action α The previous processing step is q ( α ), q ( α ) is the wafer set W s,q(α) , then determine the processing path s Medium Action α The earliest trigger time EP s,α The current system time point T + action α The previous processing step q ( α ) is the minimum value of the remaining processing time of the current step for all wafers my { I s,q,w | w ∈ W s,q(α)}, that is, the processing path s Medium Action α The earliest trigger time EP s,α It can be obtained by the following formula: EP s,α (M,R)= T+ my { I s,q,w | w ∈ W s,q(α)} In the above formula, T + my { I s,q,w | w ∈ W s,q(α)} represents that all the next steps can reach the action α Wafer arrival action of the corresponding step α The earliest time point of the step, which is the action α The earliest trigger time point, the earliest arriving action α Wafer arrival action of the corresponding step α Action after the step α It starts executing (i.e. triggered).

[0055] 2) In the current real-time state, if the wafer processing path s An action in α If the wafer does not exist in the previous processing step, the action is determined α The earliest trigger time point is the current system time point T + all possible arrival actions α The wafer from the previous processing step arrives at this step (i.e., action α The previous processing step) and in this step (i.e. action α The shortest time to complete processing (the previous processing step).

[0056] Assume machining path s Medium Action α The previous processing step is q ( α ), wafer processing path s Can reach the action α The previous processing step q ( α ) and there are other processing steps for the wafer o The collection is Q s,α , other processing steps o The wafer set in W s,o ,step o To Action α The previous processing step q ( α ) The remaining steps in the process take time L s,(o,q(α)) , then determine the processing path sMedium Action α The earliest trigger time EP s,α The current system time point T + all possible arrival actions α The wafer from the previous processing step arrives at this step (i.e., action α The previous processing step) and in this step (i.e. action α The shortest time to complete the processing my { my ( I s,o,w | w ∈ W s,o )+ L s,(o,q(α)) |o∈ Q s,α}, that is, the processing path s Medium Action α The earliest trigger time EP s,α It can be obtained by the following formula: EP s,α = T + my { my ( I s,o,w | w ∈ W s,o )+ L s,(o,q(α)) |o∈ Q s,α} In the above formula, my ( I s,o,w | w ∈ W s,o ) is in the processing step o All wafers leave the processing step o The earliest time, L s,(o,q(α)) Indicates the processing steps o To processing step q ( α ) takes time to complete, then my { my ( I s,o,w | w ∈ W s,o )+ L s,(o,q(α)) |o∈ Q s,α} for all arrival stepsq ( α ) wafers arrive q ( α ) and in q ( α )The shortest time to complete the processing, T + my { my ( I s,o,w | w ∈ W s,o )+ L s,(o,q(α)) |o∈ Q s,α} means the wafer has completed the arrival action α The earliest time point of the step, the earliest arriving action α Wafer arrival action of the corresponding step α Action after the step α It starts executing (i.e. triggered).

[0057] Among them, the time consumed by the remaining steps from the intermediate processing step to the previous processing step is obtained by the following steps: the sum of the processing action time from the start of the next processing step of the intermediate processing step to the previous processing step is obtained, and the time consumed by the remaining steps from the intermediate processing step to the previous processing step is obtained.

[0058] Specifically, for a processing step in a processing path p and its subsequent intermediate steps o combination( p,o ), the remaining steps take time from the processing step p The next processing step (including the next processing step) starts from the intermediate step o The sum of the processing action times of all processing steps between the processing step and the intermediate step (including the intermediate step).

[0059] Assume that in a certain wafer processing path s Next, from the processing steps p Begin to reach the intermediate step o The shortest processing path is pp 1 p 2 … p k … p o , then from the processing steps p To the intermediate step o The remaining steps in the process take time L s,(p,o) The processing steps in the shortest pathp (excluding processing steps p ) and intermediate steps o Processing time of all steps d ( p k )( k =1,…, o ), as shown below:

[0060] Correspondingly, assuming that in a certain wafer processing path s Next, from the processing steps o Start to reach the processing step q ( α ) is the shortest processing path p o p o+1 p o+2 … p m … p q(α) ,but L s,(o,q(α)) It can be obtained by the following formula:

[0061] S203, obtaining the processing completion time of all wafers in the scheduling task in the current real-time state according to the remaining total processing time of each wafer and the necessary idle time of each processing module.

[0062] In an embodiment of the present application, the time for completing processing of all wafers in a scheduling task can be obtained by the following steps: based on the total remaining processing time of each wafer, the sum of the total remaining processing time of all wafers is obtained; based on the necessary idle time of each processing module and the number of times each processing module is subsequently used by wafers, the sum of the necessary idle time of all processing modules in the scheduling task is obtained; based on the sum of the total remaining processing time of all wafers and the sum of the necessary idle time of all processing modules, the time for completing processing of all wafers is obtained.

[0063] Among them, the time for completing the processing of all wafers is obtained according to the sum of the total remaining processing time of all wafers and the sum of the necessary idle time of all processing modules, which can specifically include the following steps: the time for completing the processing of all wafers is obtained according to the sum of the total remaining processing time of all wafers, the sum of the necessary idle time of all processing modules and the total number of slots of all processing modules.

[0064] Specifically, assume that the set of all wafers in the scheduling task is W ,for W A wafer inw , and its corresponding processing path is s ( w ), the step is p ( w ), wafer w The remaining total processing time is X s(w),p(w),w , then the total remaining processing time of all wafers is EX is the sum of the remaining processing time of all wafers, as shown in the following formula:

[0065] Assume that the set of all processing modules in the scheduling task is ψ ,for ψ A processing module in r , which is subsequently used by the wafer for the number of times in the current real-time state φ r The necessary free time is G r , then the sum of the necessary idle time of all processing modules from the current state to the final completion of processing EG The necessary idle time of each processing module is the sum of the product of the number of times the processing module is subsequently used by the wafer, as shown in the following formula:

[0066] Among them, the number of times the processing module is subsequently used by the wafer mainly depends on the current real-time state, the processing path, and the total number of wafers corresponding to each processing path. Assume that the set of all processing paths is S , where the processing path s Middle processing module r The number of times the wafer is used is N s,r , processing path s The corresponding number of wafers is M s , processing module r The number of times used is θ r , then the processing module r Subsequent wafer usage times φ r For this processing module r The total number of times the wafer is planned to be used N s,r M s Subtract the current number of times used θ r , i.e. processing module r Subsequent wafer usage times φ r It can be obtained by the following formula:

[0067] Time to complete processing of all wafers H , the total remaining processing time of all wafers can be obtained by EX The sum of the necessary idle time of all processing modules in the scheduled task EG The sum of the values ​​is divided by the total number of slots of all processing modules in the scheduled task| ψ | (assuming that multiple slots execute all processing tasks concurrently) is obtained as shown in the following formula:

[0068] In summary, the time prediction method of the embodiment of the present application, when predicting the time to complete processing in real time, obtains the total remaining processing time of each wafer in the scheduling task under the current real-time state and the necessary idle time of each processing module in the scheduling task under the current real-time state, and obtains the time to complete processing of all wafers in the scheduling task under the current real-time state based on the total remaining processing time of each wafer and the necessary idle time of each processing module. In the process of predicting the time to complete processing, the embodiment of the present application traverses all wafers in the scheduling task, takes into account the total remaining processing time of each wafer, and takes into account the necessary idle time of all processing modules in the current real-time state, thereby realizing the accurate prediction of the time to complete processing of all wafers in the entire scheduling task under a certain processing state (i.e., the current real-time state).

[0069] The present application also provides a semiconductor process equipment. Figure 1 As shown, the semiconductor process equipment includes: a controller ( Figure 1 The semiconductor process equipment is shown in Figure 1 and Figure 2 (not shown), and multiple processing modules, the processing modules include a processing module (a chamber 11, a calibration position 12 and a cooling position 13), a robot (an atmospheric robot 14 and a vacuum robot 15), a loading port 16 and a vacuum lock 17, etc. The controller is arranged in the upper computer and / or the lower computer of the semiconductor process equipment, the controller includes at least one processor and at least one memory, a computer program is stored in the memory, and when the computer program is executed by the processor, the steps of any of the above-mentioned time prediction method embodiments are implemented.

[0070] The semiconductor process equipment of the embodiment of the present application, when predicting the time to complete processing in real time, obtains the total remaining processing time of each wafer in the scheduling task in the current real-time state and the necessary idle time of each processing module in the scheduling task in the current real-time state, and obtains the time to complete processing of all wafers in the scheduling task in the current real-time state based on the total remaining processing time of each wafer and the necessary idle time of each processing module. In the process of predicting the time to complete processing, the embodiment of the present application traverses all wafers in the scheduling task, takes into account the total remaining processing time of each wafer, and takes into account the necessary idle time of all processing modules in the current real-time state, thereby realizing the accurate prediction of the time to complete processing of all wafers in the entire scheduling task under a certain processing state (i.e., the current real-time state).

[0071] An embodiment of the present application also proposes a readable storage medium, on which one or more computer programs are stored. The one or more computer programs include instructions. When the program or instructions are executed by a processor in a semiconductor process equipment including multiple application programs, the processor in the semiconductor process equipment can execute the various processes of the above-mentioned time prediction method embodiment, and is specifically used to execute the steps of any of the above-mentioned time prediction method embodiments.

[0072] The readable storage medium of the embodiment of the present application obtains the total remaining processing time of each wafer in the scheduling task in the current real-time state and the necessary idle time of each processing module in the scheduling task in the current real-time state when predicting the time to complete the processing in real time, and obtains the time to complete the processing of all wafers in the scheduling task in the current real-time state based on the total remaining processing time of each wafer and the necessary idle time of each processing module. In the process of predicting the time to complete the processing, the embodiment of the present application traverses all wafers in the scheduling task, takes into account the total remaining processing time of each wafer, and takes into account the necessary idle time of all processing modules in the current real-time state, thereby realizing the accurate prediction of the time to complete the processing of all wafers in the entire scheduling task under a certain processing state (i.e., the current real-time state).

[0073] The systems, devices, modules or units described in the above embodiments may be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, the computer may be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0074] For the convenience of description, the above device is described in various units according to their functions. Of course, when implementing the present application, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0075] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0076] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0077] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0078] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0079] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0080] Memory may include non-permanent storage in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. Memory is an example of a computer-readable medium.

[0081] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined in this article, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0082] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0083] The present application may be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. The present application may also be practiced in distributed computing environments where tasks are performed by remote processing devices connected through a communication network. In a distributed computing environment, program modules may be located in local and remote computer storage media, including storage devices.

[0084] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0085] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included within the scope of the claims of the present application.

Claims

1. A time prediction method for predicting the completion time of a scheduling task of a semiconductor processing during a semiconductor processing process, characterized in that: include: Obtaining the total remaining processing time of each wafer in the scheduling task in the current real-time state; Obtaining the necessary idle time of each processing module in the scheduling task under the current real-time state; According to the remaining total processing time of each wafer and the necessary idle time of each processing module, the completion time of processing of all wafers in the scheduling task in the current real-time state is obtained.

2. The method according to claim 1, characterized in that The obtaining of the total remaining processing time of each wafer in the scheduling task in the current real-time state includes: Obtaining the time consumed for the remaining steps of the current processing step corresponding to the wafer in the current real-time state; Obtaining the remaining processing time of the wafer in the current processing step in the current real-time state; The sum of the completion remaining step consuming time of the current processing step corresponding to the wafer and the current step remaining processing time of the wafer in the current processing step is obtained to obtain the remaining total processing time of the wafer.

3. The method according to claim 2, characterized in that The obtaining of the remaining steps of the current processing step corresponding to the wafer in the current real-time state takes time to complete, including: The sum of the processing action times in all subsequent processing steps corresponding to the current processing step of the wafer in the current real-time state is obtained, and the completion remaining step consumption time of the current processing step corresponding to the wafer is obtained.

4. The method according to claim 2, characterized in that: The obtaining of the remaining processing time of the wafer in the current processing step in the current real-time state includes: If the time that the wafer has been processed in the current processing step in the current real-time state exceeds the time that the wafer is planned to be processed in the current processing step, then determining that the remaining processing time of the wafer in the current processing step is zero; If in the current real-time state, the time that the wafer has been processed in the current processing step does not exceed the time that the wafer is planned to be processed in the current processing step, then the remaining processing time of the wafer in the current processing step is determined to be the difference between the time that the wafer is planned to be processed in the current processing step and the time that the wafer has been processed in the current processing step.

5. The method according to claim 1, characterized in that The obtaining of the necessary idle time of each processing module in the scheduling task under the current real-time state includes: If the earliest usage time point of the action that uses the processing module in the current real-time state is equal to or less than the earliest available time point of the processing module, the necessary idle time of the processing module is determined to be zero, and the earliest usage time point of the action that uses the processing module is the minimum value of the predicted trigger time points of all actions that need to use the processing module; If the earliest usage time point of the action that uses the processing module in the current real-time state is greater than the earliest available time point of the processing module, the necessary idle time of the processing module is determined as the difference between the earliest usage time point of the action that uses the processing module and the earliest available time point of the processing module.

6. The method according to claim 5, characterized in that The predicted triggering time point of the action requiring the use of the processing module is obtained by the following steps: The maximum value of the earliest trigger time point of the action requiring the use of the processing module and the earliest available time point of the processing module is determined as the predicted trigger time point of the action requiring the use of the processing module.

7. The method according to claim 5, characterized in that The earliest available time point of the processing module in the current real-time state is obtained by the following steps: If the processing module is not fully occupied by wafers in the current real-time state, the earliest available time point of the processing module is determined to be the current time point of the system; If the processing module has been fully occupied by wafers in the current real-time state, the earliest available time point of the processing module is determined to be the minimum value of the earliest trigger time points of the actions of all wafers currently occupying the processing module to subsequently leave the processing module.

8. The method according to claim 6, characterized in that The earliest triggering time point of the action that needs to use the processing module in the current real-time state is obtained by the following steps: If there is a wafer in the processing step before the action in the current real-time state, the earliest triggering time point of the action is determined to be the sum of the minimum value of the remaining processing time of the current step of all wafers in the processing step before the action; If there is no wafer in the previous processing step of the action under the current real-time state, the earliest triggering time point of the action is determined as the sum of the current time point of the system and the shortest time for all wafers in the previous processing step of the action to reach the previous processing step of the action and complete processing in the previous processing step of the action.

9. The method according to claim 8, characterized in that The time when all wafers in the previous step of the action arrive at the previous processing step of the action and complete processing in the previous processing step of the action is obtained by the following steps: The earliest time when all wafers in the intermediate processing step leave the intermediate processing step and the sum of the time consumed in the remaining steps from the intermediate processing step to the previous processing step of the action is obtained, and the time when all wafers in the previous step of the action arrive at the previous processing step of the action and complete processing in the previous processing step of the action is obtained. The intermediate processing step is the processing step subsequent to the current processing step except the previous processing step of the action.

10. The method according to claim 9, characterized in that The remaining step time from the intermediate processing step to the previous processing step of the action is obtained by the following steps: The sum of the processing action time from the start of the next processing step of the intermediate processing step to the previous processing step of the action is obtained, and the remaining step consumption time from the intermediate processing step to the previous processing step of the action is obtained.

11. The method according to claim 1, characterized in that: The step of obtaining the processing completion time of all wafers in the scheduling task in the current real-time state according to the remaining total processing time of each wafer and the necessary idle time of each processing module includes: According to the remaining total processing time of each wafer, obtaining the sum of the remaining total processing time of all the wafers; Obtaining the sum of necessary idle times of all processing modules in the scheduling task according to necessary idle time of each processing module and the number of times each processing module is subsequently used by the wafer; The time for completing the processing of all the wafers is obtained according to the sum of the total remaining processing time of all the wafers and the sum of the necessary idle time of all the processing modules.

12. The method according to claim 11, characterized in that The step of obtaining the processing completion time of all the wafers according to the sum of the remaining processing total time of all the wafers and the sum of the necessary idle time of all the processing modules comprises: The time for completing the processing of all the wafers is obtained according to the sum of the total remaining processing time of all the wafers, the sum of the necessary idle time of all the processing modules and the total number of slots of all the processing modules.

13. A semiconductor process equipment, characterized in that: include: A controller and multiple processing modules, wherein the controller is arranged in the upper computer and / or the lower computer of the semiconductor process equipment, the controller includes at least one processor and at least one memory, the memory stores a computer program, and when the computer program is executed by the processor, the steps of the method as described in any one of claims 1 to 12 are implemented.

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