Output amplifier circuit, display driver, and display device

Abstract

The purpose of the present invention is to provide an output amplifier circuit capable of suppressing display unevenness, a display driver including the output amplifier circuit, and a display device. The present invention is provided with: first to nth amplifiers that receive first to nth input voltages and generate first to nth output voltages obtained by amplification; first to Kth bias circuits provided corresponding to each of first to Kth amplifier groups obtained by dividing the first to nth amplifiers into K groups, each of the first to Kth bias circuits generating a bias voltage for setting a current value of an operation current of the amplifier; first to K-th wirings that supply the bias voltages generated in the first to K-th bias circuits to the first to K-th amplifier groups, respectively; and a switching circuit that, in the on state, connects one of the first to Kth wirings to another wiring different from the one wiring.

Description

Technical Field

[0001] The present invention relates to an output amplifier circuit including a plurality of amplifiers, a display driver including the output amplifier circuit, and a display device. Background Art

[0002] A display driver that drives a display panel such as a liquid crystal display panel or an organic electroluminescence (EL) panel includes a plurality of output amplifiers that amplify grayscale voltages corresponding to brightness levels represented by image signals and supply the amplified grayscale voltages to source lines of the display panel.

[0003] In addition, with the recent trend of larger screens and higher definition of display panels, the output amplifier is expected to have a shorter rise or fall time of the output voltage, i.e., a higher slew rate. In addition, the output amplifier, such as an operational amplifier, can increase the slew rate by increasing the operating current flowing through its differential stage, but this will increase the power consumption accordingly.

[0004] Therefore, it is considered to control the magnitude of the operating current flowing through the differential stage of the output amplifier by bias voltage from the outside of the output amplifier so that the magnitude of the operating current becomes larger in the first half of a data period and smaller in the second half. For example, a bias circuit for generating a bias voltage is provided in the center of a semiconductor integrated circuit (IC) chip as a display driver, and the bias voltage is supplied from the bias circuit to the output amplifiers arranged along the long side direction of the semiconductor IC chip through a bias line.

[0005] However, due to large impedance caused by the resistance of the bias line or the gate capacitance of the transistor included in each output amplifier, there is a concern that the timing of changing the bias voltage may greatly deviate between the chip center and the chip end, thereby causing display unevenness.

[0006] Therefore, as a method of shortening the timing difference between the bias voltage changes in the chip center and the chip ends, a display driver has been proposed that groups output amplifiers and provides a sub-bias circuit for generating a bias voltage for each group (see, for example, Patent Document 1).

[0007] In the display driver disclosed in Patent Document 1, output amplifiers are divided into groups, and a sub-bias circuit for generating a bias voltage is provided for each group.

[0008] [Prior art literature]

[0009] [Patent Document]

[0010] [Patent Document 1] Japanese Patent Application Publication No. 2019-95545 Summary of the invention

[0011] [Problems to be solved by the invention]

[0012] In the display driver disclosed in Patent Document 1, if the bias voltage generated in each sub-bias circuit varies due to manufacturing variations or the like, this may cause characteristics of output amplifiers to vary between groups, thereby causing display unevenness.

[0013] Therefore, an object of the present invention is to provide an output amplifier circuit capable of suppressing display unevenness, a display driver including the output amplifier circuit, and a display device.

[0014] [Technical means to solve the problem]

[0015] The output amplifier circuit of the present invention includes: first to n-th amplifiers, which receive first to n-th (n is an integer greater than or equal to 2) input voltages in each data period of a predetermined cycle and generate first to n-th output voltages respectively obtained by amplification; first to K-th bias circuits, which are provided corresponding to each of the first to K-th amplifier groups obtained by dividing the first to n-th amplifiers into K (K is an integer greater than or equal to 2) groups, and each generate a bias voltage for setting the current value of the operating current of the amplifier; first to K-th wirings, which are independent of each other and supply the bias voltage generated in each of the first to K-th bias circuits to the first to K-th amplifier groups; and a switch circuit, which connects one of the first to K-th wirings to another wiring different from the first wiring when in an on state.

[0016] The display driver of the present invention includes: a grayscale voltage generating circuit, which generates first to nth grayscale voltages (n is an integer greater than or equal to 2) having voltage values ​​corresponding to the brightness level of each pixel based on an image signal; first to nth amplifiers, which receive the first to nth grayscale voltages and supply first to nth output voltages obtained by amplifying each of the first to nth grayscale voltages to first to nth data lines of a display panel; first to kth bias circuits, which are provided corresponding to each of first to kth amplifier groups obtained by dividing the first to nth amplifiers into k (k is an integer greater than or equal to 2) groups, and each of which generates a bias voltage for setting the current value of the operating current of the amplifier; first to kth wirings, which are independent of each other and supply the bias voltages generated in each of the first to kth bias circuits to the first to kth amplifier groups; and a switch circuit, which, when in an on state, connects one of the first to kth wirings to another wiring different from the first wiring.

[0017] The display device of the present invention comprises: a display panel having first to nth data lines (n is an integer greater than or equal to 2) extending in the horizontal direction of a display screen; a grayscale voltage generating circuit generating first to nth grayscale voltages having voltage values ​​corresponding to the brightness level of each pixel based on an image signal; first to nth amplifiers receiving the first to nth grayscale voltages and supplying first to nth output voltages obtained by amplifying the first to nth grayscale voltages to the first to nth data lines of the display panel; and first to kth bias circuits corresponding to the first to nth bias circuits. A first amplifier group to a K-th amplifier group are provided for each of the first amplifier group to the K-th amplifier group obtained by dividing the first amplifier group to the n-th amplifier group into K (K is an integer greater than 2) groups, each generating a bias voltage for setting the current value of the operating current of the amplifier; a first wiring to a K-th wiring are independent of each other and supply the bias voltage generated in each of the first bias circuit to the K-th bias circuit to the first amplifier group to the K-th amplifier group respectively; and a switch circuit, when in a conducting state, connects one of the first wiring to the K-th wiring to another wiring different from the first wiring.

[0018] [Effects of the Invention]

[0019] In the present invention, first to K-th bias circuits are provided, the first to K-th bias circuits correspond to the first to K-th amplifier groups obtained by dividing the first to n-th amplifiers into K groups, and each generates a bias voltage for setting the current value of the operating current of the amplifier, and the first to n-th amplifiers receive the first to n-th input voltages in each data period of a predetermined cycle and generate the first to n-th output voltages obtained by amplification. Furthermore, a switch circuit is provided, and when the bias voltages generated by the first to K-th bias circuits are supplied to the first to K-th amplifier groups via the first to K-th wirings, the switch circuit connects one of the first to K-th wirings to another wiring different from the first wiring.

[0020] Therefore, even if the bias voltages generated in the first to Kth bias circuits vary, the difference in voltage values ​​between the bias voltages generated in the bias circuits disappears just before the end of each data period, thereby reducing display unevenness in the display screen. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 1 is a block diagram showing a configuration of an output amplifier circuit 100_1 as a first embodiment of the output amplifier circuit of the present invention.

[0022] Figure 2 This is a circuit diagram showing the internal structure of amplifier AP1 selected from amplifiers AP1 to APn.

[0023] Figure 3 3 is a circuit diagram showing the internal structure of each of sub-bias circuits SB1 to SB3.

[0024] Figure 4 1 is a timing chart showing an example of the internal operation of the output amplifier circuit 100_1.

[0025] Figure 5 1 is a timing chart showing another example of the internal operation of the output amplifier circuit 100_1.

[0026] Figure 6 1 is a block diagram showing a configuration of an output amplifier circuit 100_2 as a second embodiment of the output amplifier circuit of the present invention.

[0027] Figure 7 100_1 or 100_2 is a block diagram showing a configuration of a display device having a display driver including the output amplifier circuit 100_1 or the output amplifier circuit 100_2.

[0028] [Explanation of Symbols]

[0029] 13: Data Driver

[0030] 133: Output

[0031] 200: Display device

[0032] AP1~APn:Amplifier

[0033] CM_1: Current mirror circuit

[0034] CN_1: Control unit

[0035] MB_1: Main bias circuit

[0036] SB1~SB3: Sub bias circuit DETAILED DESCRIPTION

[0037] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0038] [Example 1]

[0039] Figure 1 1 is a block diagram showing a configuration of an output amplifier circuit 100_1 as a first embodiment of the output amplifier circuit of the present invention.

[0040] In addition, the output amplifier circuit 100_1 is, for example, arranged in a display driver that drives a display panel, and receives n (n is an integer greater than 2) input voltages V1 to Vn as grayscale voltages corresponding to the brightness level represented by the image signal, and outputs each amplified voltage to the display panel as an output voltage G1 to Gn for driving the display panel.

[0041] The output amplifier circuit 100_1 is formed in a semiconductor IC chip, and includes a main bias circuit MB_1, sub bias circuits SB1 to SB3, a control unit CN_1, and an output amplifier unit OBLK_1.

[0042] The main bias circuit MB_1 includes a current mirror circuit CM_1 and a reference current source IG_1 .

[0043] The reference current source IG_1 generates a reference current Io having a predetermined constant current value.

[0044] The current mirror circuit CM_1 generates three bias control currents I1 to I3, each of which is a copy of the reference current Io. The current mirror circuit CM_1 supplies the bias control current I1 to the sub-bias circuit SB1 via the wiring BL1, supplies the bias control current I2 to the sub-bias circuit SB2 via the wiring BL2, and supplies the bias control current I3 to the sub-bias circuit SB3 via the wiring BL3.

[0045] The control unit CN_1 receives a clock signal CLK which is a clock signal of a predetermined period, and supplies a bias control signal PWRC which specifies a voltage value of a bias voltage to the sub-bias circuits SB1 to SB3 at the timing of the clock signal CLK. Furthermore, the control unit CN_1 supplies a switch control signal SWC which sets a switch to an on state or an off state to the output amplifier unit OBLK_1.

[0046] The output amplifier unit OBLK_1 includes amplifiers AP1 to APn, a switch circuit SW12 , and a switch circuit SW23 .

[0047] The amplifiers AP1 to APn receive input voltages V1 to Vn in each data period of a predetermined cycle separated by the rising edge (or falling edge) of the clock signal CLK. The amplifiers AP1 to APn generate n voltages obtained by amplifying the input voltages V1 to Vn individually as output voltages G1 to Gn, and output them through output terminals T1 to Tn of the semiconductor IC chip. The amplifiers AP1 to APn each include, for example, operational amplifiers of the same structure. In addition, for example, in order to suppress the influence of noise caused by the simultaneous operation of the amplifiers AP1 to APn, the start timing of the data period is set to be gradually shifted for each predetermined amplifier among the amplifiers AP1 to APn.

[0048] The amplifiers AP1 to APn set the operating current flowing through their differential stages and current mirror stages by the bias voltages VB1N to VB3N and the bias voltages VB1P to VB3P supplied from the sub-bias circuits SB1 to SB3. Thus, the amplifiers AP1 to APn each adjust their output slew rate based on the bias voltage group (VB1N to VB3N, VB1P to VB3P).

[0049] In addition, amplifiers AP1 to APn are grouped into a first group including amplifiers AP1 to APr (r is an integer less than n), a second group including amplifiers AP(r+1) to APg (g is an integer greater than r and less than n), and a third group including amplifiers AP(g+1) to APn.

[0050] At this time, the amplifiers AP1 to APr belonging to the first group receive the bias voltages VB1N to VB3N and the bias voltages VB1P to VB3P generated in the sub-bias circuit SB1 via the first wiring group L1 including six wirings. The amplifiers AP(r+1) to APg belonging to the second group receive the bias voltages VB1N to VB3N and the bias voltages VB1P to VB3P generated in the sub-bias circuit SB2 via the second wiring group L2 including six wirings. The amplifiers AP(g+1) to APn belonging to the third group receive the bias voltages VB1N to VB3N and the bias voltages VB1P to VB3P generated in the sub-bias circuit SB3 via the third wiring group L3 including six wirings.

[0051] The switch circuit SW12 includes six switch elements. When in the on state, the six switch elements electrically connect the first wiring group L1 and the second wiring group L2 to each other by supplying the same bias voltage. On the other hand, when in the off state, the connection between the first wiring group L1 and the second wiring group L2 is disconnected.

[0052] The switch circuit SW23 includes six switch elements. When in the on state, the six switch elements electrically connect the second wiring group L2 and the third wiring group L3 to each other by supplying the same bias voltage. On the other hand, when in the off state, the connection between the second wiring group L2 and the third wiring group L3 is disconnected.

[0053] The switch circuit SW12 and the switch circuit SW23 are set to the on state or the off state according to the switch control signal SWC supplied from the control unit CN_1.

[0054] Sub-bias circuits SB1 to SB3 have the same internal structure, and are provided in association with the first to third groups into which amplifiers AP1 to APn are divided into three groups, as described above.

[0055] The sub-bias circuit SB1 receives the bias control current I1 sent from the main bias circuit MB_1 via the wiring BL1. The sub-bias circuit SB1 generates bias voltages VB1N to VB3N and bias voltages VB1P to VB3P having voltage values ​​corresponding to the current value of the bias control current I1, and supplies them to the amplifiers AP1 to APr belonging to the first group via the first wiring group L1.

[0056] The sub-bias circuit SB2 receives the bias control current I2 sent from the main bias circuit MB_1 via the wiring BL2. The sub-bias circuit SB2 generates bias voltages VB1N to VB3N and bias voltages VB1P to VB3P having voltage values ​​corresponding to the current value of the bias control current I2, and supplies them to each of the amplifiers AP(r+1) to APg belonging to the second group via the second wiring group L2.

[0057] The sub-bias circuit SB3 receives the bias control current I3 sent from the main bias circuit MB_1 via the wiring BL3. The sub-bias circuit SB3 generates bias voltages VB1N to VB3N and bias voltages VB1P to VB3P having voltage values ​​corresponding to the current value of the bias control current I3, and supplies them to each of the amplifiers AP(g+1) to APn belonging to the third group via the third wiring group L3.

[0058] In addition, the sub-bias circuits SB1 to SB3 have a function of adjusting the voltage values ​​of the bias voltages (VB1N to VB3N, VB1P to VB3P) according to the bias control signal PWRC.

[0059] The following, Figure 1 The detailed structures of the amplifier AP1 to the amplifier APn and the sub-bias circuit SB1 to the sub-bias circuit SB3 shown in FIG.

[0060] Figure 2 This is a circuit diagram showing the internal structure of amplifier AP1 by selecting amplifier AP1 from among amplifiers AP1 to amplifiers APn.

[0061] Amplifier AP1 has: a differential stage, including P-channel transistors U2 to U4 and N-channel transistors J2 to J4; an output stage, including P-channel transistor U11 and N-channel transistor J11; a common-source and common-gate current mirror circuit 30 and a common-source and common-gate current mirror circuit 40; and a floating current source 50 and a floating current source 60.

[0062] The power supply voltage VDD is applied to the source of the transistor U2 of the differential stage, and the bias voltage VB1P is supplied to the gate. The transistor U2 generates an operating current Iu1 having a current value corresponding to the bias voltage VB1P, and supplies it to the respective sources of the transistor U3 and the transistor U4. The transistor U3 receives the input voltage V1 at its gate. The transistor U4 receives the output of the amplifier AP1, that is, the output voltage G1, at its gate. The transistor U3 and the transistor U4 generate a current NCM1 and a current NCM2 by dividing the operating current Iu1 supplied from the transistor U2 into two currents at a voltage ratio of the input voltage V1 to the output voltage G1. The transistor U3 and the transistor U4 supply the current NCM1 and the current NCM2 to the node n3 and the node n4 of the common source and common gate current mirror circuit 40 via their respective drains. That is, the transistor U3 supplies the current NCM2 corresponding to the voltage value of the input voltage V1 to the node n4 of the common source and common gate current mirror circuit 40. The transistor U4 supplies a current NCM1 corresponding to the voltage value of the output voltage G1 to a node n3 of the cascode current mirror circuit 40 .

[0063] A ground voltage VSS is applied to the source of the transistor J2 of the differential stage, and a bias voltage VB1N is supplied to the gate. The drain of the transistor J2 is connected to the source of each of the transistors J3 and J4. The transistor J2 generates an operating current Ij1 having a current value corresponding to the bias voltage VB1N, and extracts it from the sources of the transistors J3 and J4. The transistor J3 receives the input voltage V1 at its gate. The transistor J4 receives the output voltage G1 at its gate. The transistor J3 and the transistor J4 generate a current as the current PCM1 and the current PCM2, which is a current obtained by dividing the operating current Ij1 into two at a voltage ratio of the input voltage V1 received by each gate and the output voltage G1. The transistor J3 extracts the current PCM2 corresponding to the input voltage V1 from the node n2 of the common source and common gate current mirror circuit 30, and supplies it to the drain of the transistor J2. The transistor J4 extracts a current PCM1 corresponding to the output voltage G1 from the node n1 of the cascode current mirror circuit 30 , and supplies the current PCM1 to the drain of the transistor J2 .

[0064] In addition, in the differential stage, the current value of the operating current Iu1 is adjusted by the bias voltage VB1P, and further, the current value of the operating current Ij1 is adjusted by the bias voltage VB1N. Thus, for example, the lower the voltage value of the bias voltage VB1P, the larger the current is supplied to the node n3 and the node n4 of the cascode current mirror circuit 40. Moreover, the higher the voltage value of the bias voltage VB1N, the larger the current is extracted from the node n1 and the node n2 of the cascode current mirror circuit 30.

[0065] The cascode current mirror circuit 30 includes P-channel transistors U5 to U8, and the cascode current mirror circuit 40 includes N-channel transistors J7 to J10. Furthermore, the floating current source 50 includes a P-channel transistor U9 and an N-channel transistor J5, and the floating current source 60 includes a P-channel transistor U10 and an N-channel transistor J6.

[0066] The power supply voltage VDD is applied to the source of each transistor U5 and transistor U6 of the common source and common gate current mirror circuit 30, and the gates of each transistor U5 and transistor U6 are connected to each other. The drain of transistor U5 is connected to the source of transistor U7 via node n1. The drain of transistor U6 is connected to the source of transistor U8 via node n2. The gates of transistor U7 and transistor U8 are both applied with bias voltage VB2P. The drain of transistor U7 is connected to the gates of transistor U5 and transistor U6, the source of transistor U9 of floating current source 50, and the drain of transistor J5 via node n5.

[0067] The drain of transistor U8 is connected to the source of transistor U10 of floating current source 60 and the drain of transistor J6 via node n6, which is a driving node on the high potential side. Bias voltage VB3P is applied to the gates of transistors U9 and U10, respectively, and bias voltage VB3N is applied to the gates of transistors J5 and J6, respectively. The drain of transistor U9 and the source of transistor J5 are connected to the drain of transistor J7 of cascode current mirror circuit 40 via node n7. The drain of transistor U10 and the source of transistor J6 are connected to the drain of transistor J8 of cascode current mirror circuit 40 via node n8, which is a driving node on the low potential side.

[0068] A bias voltage VB2N is applied to each gate of the transistor J7 and the transistor J8. The source of the transistor J7 is connected to the drain of the transistor J9 via the node n3. The source of the transistor J8 is connected to the drain of the transistor J10 via the node n4. A ground voltage VSS is applied to each source of the transistor J9 and the transistor J10, and each gate of the transistor J9 and the transistor J10 is connected to the drain of the transistor J7.

[0069] In the common-source common-gate current mirror circuit 30, the common-source common-gate current mirror circuit 40, the floating current source 50, and the floating current source 60, the action current Iu2 supplied from the differential stage and having a current value corresponding to the difference between the current PCM1 and the current PCM2 flows to the node n6, and the action current Ij2 supplied from the differential stage and having a current value corresponding to the difference between the current NCM1 and the current NCM2 flows to the node n8.

[0070] Thus, in the cascode current mirror circuit 30, the cascode current mirror circuit 40, the floating current source 50, and the floating current source 60, the operation current Iu2 corresponding to the difference between the current PCM1 and the current PCM2 is supplied to the node n6 or extracted from the node n6, thereby generating an output drive voltage PG on the high potential side at the node n6. The output drive voltage PG is supplied to the gate of the transistor U11 of the output stage. Moreover, in the cascode current mirror circuit 30, the cascode current mirror circuit 40, the floating current source 50, and the floating current source 60, the operation current Ij2 corresponding to the difference between the current NCM1 and the current NCM2 is supplied to the node n8 or extracted from the node n8, thereby generating an output drive voltage NG on the low potential side at the node n8. The output drive voltage NG is supplied to the gate of the transistor J11 of the output stage.

[0071] The power supply voltage VDD0 is applied to the source of the transistor U11 of the output stage, and a current corresponding to the output drive voltage PG received at its gate is generated and supplied to the output node nZ, thereby increasing the voltage of the output node nZ. The ground voltage VSS0 is applied to the source of the transistor J11, and a current corresponding to the output drive voltage NG received at its gate is drawn from the output node nZ, thereby decreasing the voltage of the output node nZ.

[0072] The transistors U11 and J11 operate to generate an output voltage G1 at the output node nZ and output it through the output terminal. The output voltage G1 is fed back to the gates of the high potential side transistors U4 and J4 of the differential stage.

[0073] In addition, according to Figure 2 The structure of the amplifier AP1 shown in the figure adjusts the current values ​​of the operating current Iu2 and the operating current Ij2 flowing to the node n6 and the node n8 which are the driving nodes driving the transistor U11 and the transistor J11 of the output stage by the magnitude of the bias voltage VB1N to the bias voltage VB3N and the bias voltage VB1P to the bias voltage VB3P. As a result, the magnitude of the current sent to the output node nZ and the magnitude of the current drawn from the output node nZ are changed, and the slew rate of the amplifier AP1 can be adjusted.

[0074] Figure 3 This is a circuit diagram showing the internal structure of the sub-bias circuit SB1 selected from the sub-bias circuits SB1 to SB3.

[0075] Sub-bias circuit SB1 includes a voltage adjustment unit VCN including P-channel metal-oxide-semiconductor (MOS) transistors Q1 to Q5 and switch circuits SW1 to SW3 , P-channel MOS transistors 6 to Q12 , and N-channel MOS transistors R1 to R10 .

[0076] The transistor R1 receives the bias control current I1 supplied from the main bias circuit MB_1 via the wiring BL1 at its drain. The drain and gate of the transistor R1 are connected to the gate of the transistor R2, and the ground voltage VSS is applied to the source of each of the transistors R1 and R2. The drain of the transistor R2 is connected to the voltage adjustment unit VCN via the node w2.

[0077] With the above configuration, the transistor R2 generates a current I1a corresponding to the bias control current I1 and causes the current to flow to the node w2.

[0078] The gates of transistors Q1 and Q2 of voltage regulator VCN are connected to node w2. Power supply voltage VDD is applied to the sources of transistors Q1 and Q2. The drain of transistor Q2 is connected to the drain and gate of transistor R3 via node w3. Ground voltage VSS is applied to the source of transistor R3.

[0079] With the above configuration, the transistor Q2 outputs the current I1b corresponding to the current I1a to the node w3, thereby generating the reference bias voltage VQ at the node w3.

[0080] The power supply voltage VDD is applied to the source of each of the transistors Q3 to Q5 of the voltage adjustment unit VCN, and the drain of each of the transistors Q3 to Q5 is connected to the node w3 .

[0081] The switch circuit SW1 is set to a state in which the power supply voltage VDD is supplied to the gate of the transistor Q3 (referred to as an off state) or a state in which the node w2 is connected to the gate of the transistor Q3 (referred to as an on state) according to the bias control signal PWRC. The switch circuit SW2 is set to a state in which the power supply voltage VDD is supplied to the gate of the transistor Q4 (referred to as an off state) or a state in which the node w2 is connected to the gate of the transistor Q4 (referred to as an on state) according to the bias control signal PWRC. The switch circuit SW3 is set to a state in which the power supply voltage VDD is supplied to the gate of the transistor Q5 (referred to as an off state) or a state in which the node w2 is connected to the gate of the transistor Q5 (referred to as an on state) according to the bias control signal PWRC.

[0082] The transistor Q3 is turned on only when the switch circuit SW1 is turned on, and sends the current Ic corresponding to the current I1a to the node w3. The transistor Q4 is turned on only when the switch circuit SW2 is turned on, and sends the current Ic corresponding to the current I1a to the node w3. The transistor Q5 is turned on only when the switch circuit SW3 is turned on, and sends the current Ic corresponding to the current I1a to the node w3.

[0083] With the above configuration, the voltage adjustment unit VCN sends a composite current It to the node w3, wherein the composite current It is a composite current I1b corresponding to the bias control current I1 and a current Ic sent from the transistors Q3 to Q5 set to the on state according to the bias control signal PWRC. The voltage value of the reference bias voltage VQ generated by sending the composite current It to the node w3 can be adjusted.

[0084] For example, when the voltage regulator VCN receives the bias control signal PWRC indicating zero as the number of transistors set to the on state among the transistors Q3 to Q5 , the combined current It flowing through the node w3 becomes the current I1b.

[0085] Furthermore, when the voltage regulator VCN receives the bias control signal PWRC indicating "2" as the number of transistors to be turned on among the transistors Q3 to Q5, for example, only the transistor Q3 and the transistor Q4 among the transistors Q3 to Q5 are turned on. Thus, the composite current It becomes a current (I1b+2·Ic) obtained by adding the current I1b to the current Ic sent out from the transistors Q3 and Q4, respectively.

[0086] Right now, Figure 3 The voltage adjustment unit VCN shown adjusts the voltage value of the reference bias voltage VQ in four stages according to the bias control signal PWRC.

[0087] exist Figure 3 In the embodiment, the gates of transistors R4 to R7 are connected to the gate of transistor R3 and node w3, and the ground voltage VSS is applied to the sources of transistors R4 to R7. The drain of transistor R4 is connected to the gate and drain of transistor Q6 via node w4. The drain of transistor R5 is connected to the gate and drain of transistor Q7 via node w5. The drain of transistor R6 is connected to the gate and drain of transistor Q8 via node w6. The power supply voltage VDD is applied to the sources of transistors Q6 to Q8.

[0088] The drain of transistor R7 is connected to the drain of transistor Q9 and the gates of transistors Q9 to Q12. A power supply voltage VDD is applied to the sources of transistors Q9 to Q12. The drain of transistor Q10 is connected to the gate and drain of transistor R8 via node w7. The drain of transistor Q11 is connected to the gate and drain of transistor R9 via node w8. The drain of transistor Q12 is connected to the gate and drain of transistor R9 via node w9. A ground voltage VSS is applied to the sources of transistors R8 to R10.

[0089] In the circuit including the transistor R4 and the transistor Q6, the transistor R4 allows a current corresponding to the reference bias voltage VQ supplied to its gate to flow to the node w4. Thus, the voltage generated at the node w4 is supplied to the amplifiers AP1 to APr as the bias voltage VB1P.

[0090] In the circuit including transistor R5 and transistor Q7, transistor R5 allows a current corresponding to reference bias voltage VQ supplied to its gate to flow to node w5. Thus, a voltage generated at node w5 is supplied to amplifiers AP1 to APr as bias voltage VB2P.

[0091] In the circuit including transistor R6 and transistor Q8, transistor R6 allows a current corresponding to reference bias voltage VQ supplied to its gate to flow to node w6. Thus, a voltage generated at node w6 is supplied to amplifiers AP1 to APr as bias voltage VB3P.

[0092] In addition, a current corresponding to the reference bias voltage VQ supplied to the gate of the transistor R7 flows through the transistor Q9. Thus, a current corresponding to the reference bias voltage VQ is sent from the drains of the transistors Q10 to Q12 to the nodes w7 to w9, respectively.

[0093] At this time, a current corresponding to the reference bias voltage VQ is sent to the node w7 through the transistor Q10, and a voltage generated at the node w7 is supplied to the amplifier AP1 to the amplifier APr as a bias voltage VB1N. Furthermore, a current corresponding to the reference bias voltage VQ is sent to the node w8 through the transistor Q11, and a voltage generated at the node w8 is supplied to the amplifier AP1 to the amplifier APr as a bias voltage VB2N. Furthermore, a current corresponding to the reference bias voltage VQ is sent to the node w9 through the transistor Q12, and a voltage generated at the node w9 is supplied to the amplifier AP1 to the amplifier APr as a bias voltage VB3N.

[0094] As described above, the sub-bias circuit SB1 generates bias voltages VB1N to VB3N and bias voltages VB1P to VB3P by performing current-voltage conversion processing on the bias control current I1. Furthermore, the sub-bias circuit SB1 adjusts the voltage values ​​of the bias voltages VB1N to VB3N and the bias voltages VB1P to VB3P of the six systems according to the bias control signal PWRC.

[0095] In addition, the sub-bias circuit SB2 and the sub-bias circuit SB3 also adopt the same Figure 3 The structure shown is the same as the structure, and thus, like the auxiliary bias circuit SB1, bias voltages VB1N~bias voltage VB3N and bias voltages VB1P~bias voltage VB3P are generated based on the bias control currents I2 and I3 received respectively, and the voltage value of each bias voltage is adjusted based on the bias control signal PWRC.

[0096] Next, the internal operation of the output amplifier circuit 100_1 will be described in detail.

[0097] Figure 4 1 is a timing chart showing an example of the internal operation (CLK, PWRC, SWC, VBx, V1, G1) of the output amplifier circuit 100_1. Figure 4 In FIG. 8 , VBx collectively represents bias voltages VB1N to VB3N and bias voltages VB1P to VB3P generated in sub-bias circuits SB1 to SB3 , respectively.

[0098] Starting from the time point t0 of the rising edge of the clock signal CLK, throughout the predetermined first period PE1, the control unit CN_1 generates a bias control signal PWRC of logic level 1 that specifies a predetermined first voltage value that makes the amplifier slew rate high as the voltage value of the bias voltage, and supplies it to the sub-bias circuits SB1 to SB3. Figure 4 In the first period PE1 shown, the sub-bias circuits SB1 to SB3 supply the bias voltage group VBx (VB1N to VB3N, VB1P to VB3P) having the high voltage value Vbxb to the amplifier groups belonging to the respective groups according to the bias control signal PWRC.

[0099] Furthermore, throughout the second period PE2 from the time point t1 after the first period PE1 until the time point t2 of the rising edge of the next clock signal CLK, the control unit CN_1 supplies the bias control signal PWRC of logic level 0 to the sub-bias circuits SB1 to SB3, which specifies the second voltage value that reduces the slew rate of the amplifier as the voltage value of the bias voltage. Figure 4 In the second period PE2 shown, the sub-bias circuits SB1 to SB3 supply the bias voltage group VBx (VB1N to VB3N, VB1P to VB3P) having the low voltage value Vbxa lower than the high voltage value Vbxb to the amplifier groups belonging to their respective groups according to the bias control signal PWRC.

[0100] Through the series of actions, such as Figure 4 As shown, starting from the time point t0 of the rising edge of the clock signal CLK, throughout the first period PE1, the action current flowing through each amplifier AP is larger than the action current flowing through each amplifier AP in the second period PE2 subsequent to the first period PE1.

[0101] Therefore, a high-speed response output voltage (for example Figure 4 In the rising or falling interval of the output voltage G1 shown in FIG. 1 , the slew rate of the amplifier AP becomes higher, so the rising or falling time of the output voltage output from the amplifier AP also becomes shorter.

[0102] On the other hand, in the second period PE2 starting from the end time point t1 of the first period PE1 to the time point t2 of the rising edge of the next clock signal CLK, the operating current flowing through each amplifier AP is smaller than the operating current flowing through each amplifier AP in the first period PE1.

[0103] As a result, in the voltage value constant section (PE2) of the output voltage in which a high-speed response is not required, the power consumed by the amplifier AP is reduced.

[0104] As described above, in the output amplifier circuit 100_1, the bias voltage that determines the operating current in each of the amplifiers AP1 to APn is adjusted according to the bias control signal PWRC, thereby controlling (changing) the slew rate of each amplifier, thereby achieving both high-speed response and low power consumption.

[0105] Furthermore, in the output amplifier circuit 100_1, as Figure 4 As shown, the control unit CN_1 sets the switch circuit SW12 and the switch circuit SW23 to the on state during a predetermined period (ts to t2) in the second half of the second period PE2 in each data period.

[0106] Thus, even when the bias voltage group (VB1N to VB3N and VB1P to VB3P) is supplied to the amplifiers AP1 to APn individually for each of the first to third groups obtained by dividing the amplifiers AP1 to APn into three groups, the voltage difference between the bias voltages of the groups can be reduced. Therefore, even if the voltage values ​​of the bias voltage group (VB1N to VB3N and VB1P to VB3P) vary between the sub-bias circuits SB1 to SB3, the difference in the voltage value disappears just before the end of each data period, thereby reducing display unevenness in the display screen.

[0107] In addition, when using switch elements having an on-resistance higher than a predetermined value as the six switch elements included in each of the switch circuits SW12 and SW23, the control unit CN_1 may set the switch circuits SW12 and SW23 to an on state throughout the first period PE1 and the second period PE2. In addition, in the above case, six high resistance elements may be used instead of the six switch elements included in each of the switch circuits SW12 and SW23.

[0108] Figure 5 1 is a timing chart showing another example of the internal operation (CLK, PWRC, SWC, VBx, V1, G1) of the output amplifier circuit 100_1.

[0109] exist Figure 5 In the operation shown, in each data period, at a time point tP a predetermined time before the head time point t0 of the data period, the control unit CN_1 switches the bias control signal PWRC from the state of logic level 0 for reducing the slew rate of the amplifier to the state of logic level 1 for increasing the slew rate of the amplifier. In addition, the on-off switching timing of the switch circuit SW12 and the switch circuit SW23 based on the switch control signal SWC is consistent with the Figure 4 Same as shown.

[0110] according to Figure 5 The operation shown can restore the output voltage to the desired voltage value even if the output voltage of each amplifier slightly changes due to external noise (such as coupling noise caused by changes in gate voltage) during the second period PE2 when the bias voltage is low.

[0111] Furthermore, in each data period, each amplifier is set to a high slew rate state by the bias control signal PWRC from immediately before the start of the data period, so that each amplifier operates at a high slew rate without causing a delay with respect to a change in output voltage immediately after the start of a data period. Thus, the influence of a response delay from the start of the adjustment process of changing the slew rate of the amplifier in accordance with the bias control signal PWRC until the bias voltage actually changes can be eliminated.

[0112] [Example 2]

[0113] Figure 6 1 is a block diagram showing a configuration of an output amplifier circuit 100_2 as a second embodiment of the output amplifier circuit of the present invention.

[0114] The output amplifier circuit 100_2 adopts sub-bias circuits SB1a to SB3a to replace sub-bias circuits SB1 to SB3, adopts current mirror circuit CM_2 to replace current mirror circuit CM_1, and newly sets a common bias voltage generating circuit VG. In addition to the above aspects, the other structures (IG_1, CN_1, OBLK_1) are the same as those of the output amplifier circuit 100_2. Figure 1 Same as shown.

[0115] The current mirror circuit CM_2 supplies the bias control current I1 obtained by copying the reference current Io generated by the reference current source IG_1 to the sub-bias circuit SB1a, supplies the bias control current I2 obtained by copying the reference current Io to the sub-bias circuit SB2a, and supplies the bias control current I3 obtained by copying the reference current Io to the sub-bias circuit SB3a.

[0116] Furthermore, the current mirror circuit CM_2 supplies the bias control current I_C obtained by replicating the reference current Io to the common bias voltage generating circuit VG.

[0117] The common bias voltage generating circuit VG generates bias voltages VB2N, VB3N, VB2P, and VB3P that have little influence on the slew rate of the amplifier by performing current-voltage conversion on the bias control current I_C, and supplies the bias voltages to all amplifiers AP1 to APn.

[0118] Sub bias circuit SB1a generates bias voltage VB1N and bias voltage VB1P which have a large influence on the slew rate of the amplifier by performing current-voltage conversion on bias control current I1, and supplies the generated bias voltages to amplifiers AP1 to APr belonging to the first group.

[0119] Sub bias circuit SB2a generates bias voltage VB1N and bias voltage VB1P which have a large influence on the slew rate of the amplifier by performing current-voltage conversion on bias control current I2, and supplies them to amplifiers AP(r+1) to APg belonging to the second group.

[0120] Sub bias circuit SB3a generates bias voltage VB1N and bias voltage VB1P which have a large influence on the slew rate of the amplifier by performing current-voltage conversion on bias control current I3, and supplies them to amplifiers AP(g+1) to APn belonging to the third group.

[0121] As described above, in the output amplifier circuit 100_2, bias voltage VB1N and bias voltage VB1P having a large influence on the slew rate of the amplifier are generated in each of the sub-bias circuits SB1a to SB3a among the six bias voltage groups, and the other bias voltage groups (VB2N, VB3N, VB2P, VB3P) are generated in the common bias voltage generating circuit VG as common to all amplifiers.

[0122] Therefore, the sub-bias circuits SB1a to SB3a are respectively Figure 3 In the structure shown, the transistor group involved in the generation of bias voltage VB2N, bias voltage VB3N, bias voltage VB2P, and bias voltage VB3P is omitted. This can reduce the number of elements constituting the sub-bias circuit and achieve area saving.

[0123] [Example 3]

[0124] Figure 7 2 is a block diagram showing a configuration of a display device 200 having a display driver including an output amplifier circuit according to the present invention.

[0125] like Figure 7 As shown, the display device 200 includes a drive control unit 10 , a scan driver 120 , a data driver 13 , and a display panel 20 .

[0126] The display panel 20 includes, for example, an organic EL panel or a liquid crystal display panel. In the display panel 20, horizontal scanning lines S1 to Sm (m is an integer greater than or equal to 2) extending in the horizontal direction of the two-dimensional screen and data lines D1 to Dn (n is an integer greater than or equal to 2) extending in the vertical direction of the two-dimensional screen are formed. Display units are formed in the regions (regions surrounded by dotted lines) of the intersections of the horizontal scanning lines and the data lines.

[0127] In addition, the horizontal scanning lines S1 to Sm are connected to the scanning driver 120 , and the data lines D1 to Dn are connected to the data driver 13 .

[0128] The drive control unit 10 receives the image signal VD, detects a horizontal synchronization signal from the image signal VD, and supplies it to the scan driver 120. Furthermore, the drive control unit 10 generates an image data signal PD based on the image signal VD, and supplies it to the data driver 13. The image data signal PD includes, for example, a column of pixel data pieces representing the brightness level of a pixel with eight-bit brightness grayscale, and various control signals such as a clock signal and a data import signal.

[0129] The scan driver 120 sequentially applies a horizontal scan pulse to each of the horizontal scan lines S1 to Sm of the display panel 20 at a timing signal synchronized with a horizontal synchronization signal supplied from the drive control section 10 .

[0130] The data driver 13 is formed on, for example, a semiconductor integrated circuit (IC) chip, and includes a data importing section 131 , a grayscale voltage generating section 132 , and an output section 133 .

[0131] The data importing section 131 imports pixel data pieces for an amount corresponding to one horizontal scan line, that is, every n pixel data pieces, according to the data importing signal included in the image data signal PD. The data importing section 131 sets the imported n pixel data pieces as pixel data P1 to pixel data Pn, and supplies these pixel data P1 to pixel data Pn to the grayscale voltage generating section 132 at the timing of, for example, the rising edge of the clock signal CLK. In addition, the clock signal CLK is a signal generated in the data driver 13 based on the clock signal included in the image data signal PD.

[0132] The grayscale voltage generating section 132 converts the pixel data P1 to the pixel data Pn supplied from the data introducing section 131 into grayscale voltages V1 to Vn having voltage values ​​corresponding to the respective luminance levels, and supplies the converted grayscale voltages to the output section 133 .

[0133] The output unit 133 includes the output amplifier circuit 100_1 or the output amplifier circuit 100_2, receives the grayscale voltage V1 to the grayscale voltage Vn as the input voltage V1 to the input voltage Vn, and supplies the output voltage G1 to the output voltage Gn respectively amplified by the amplifier AP1 to the amplifier APn to the data line D1 to the data line Dn of the display panel 20.

[0134] In the above embodiment, the output amplifier circuit 100_1 or the output amplifier circuit 100_2 is used as the output section 133 of the data driver 13 , but the output amplifier circuit may be used as a circuit included in the drive control section 10 that outputs the timing signal.

[0135] Moreover, in Figure 1 or Figure 6In the output amplifier circuit 100_1 or the output amplifier circuit 100_2 shown in the figure, three sub-bias circuits (SB1 to SB3 or SB1a to SB3a) are provided for one main bias circuit MB_1, and the number of sub-bias circuits may be more than two. Furthermore, the main bias circuit MB_1 may be eliminated and a current mirror circuit may be provided in each sub-bias circuit, and the current mirror circuit may generate a bias control current obtained by replicating the reference current Io.

[0136] Moreover, in Figure 1 or Figure 6 In the output amplifier circuit 100_1 or the output amplifier circuit 100_2 shown in the figure, each sub-bias circuit generates six bias voltages (VB1N to VB3N, VB1P to VB3P), but it is sufficient to generate at least one bias voltage.

[0137] In summary, the output amplifier circuit of the present invention only needs to include the following first to nth amplifiers (n is an integer greater than 2), first to Kth bias circuits (K is an integer greater than 2), first to Kth wirings, and a switch circuit.

[0138] The first to n-th amplifiers (AP1 to APn) receive the first to n-th input voltages (V1 to Vn) in each data period of a predetermined cycle and generate the first to n-th output voltages (G1 to Gn) obtained by amplifying them. The first to K-th bias circuits (e.g., SB1 to SB3) are provided corresponding to each of the first to K-th amplifier groups obtained by dividing the first to n-th amplifiers into K (e.g., 3) groups, and each generates a bias voltage for setting the current value of the operating current of the amplifier. The first to K-th wirings (e.g., L1 to L3) are wirings that are independent of each other and supply the bias voltages generated in each of the first to K-th bias circuits to the first to K-th amplifier groups. When the switch circuits (SW12, SW23) are in the on state, one of the first to K-th wirings is connected to another wiring that is different from the one wiring.

Claims

1. An output amplifier circuit, characterized in that include: The first to n-th amplifiers receive first to n-th (n is an integer greater than or equal to 2) input voltages in each data period of a predetermined cycle and generate first to n-th output voltages respectively obtained by amplification; First to K-th bias circuits are provided corresponding to first to K-th amplifier groups obtained by dividing the first to n-th amplifiers into K (K is an integer greater than or equal to 2) groups, and each generates a bias voltage for setting a current value of an operating current of the amplifier; First to K-th wirings are independent of each other and supply the bias voltages generated in the first to K-th bias circuits to the first to K-th amplifier groups, respectively; as well as The switch circuit connects one of the first to K-th wirings to another wiring different from the one wiring when in an on state.

2. The output amplifier circuit according to claim 1, characterized in that comprising a control unit, the control unit setting the switch circuit to an on state or an off state, Each of the data periods includes a first period immediately after the start of the data period and a second period subsequent to the first period, and the control unit sets the switch circuit to an on state at least throughout the second period.

3. The output amplifier circuit according to claim 2, characterized in that: The control unit disconnects the one wiring from the other wiring by setting the switch circuit to an OFF state during the first period.

4. The output amplifier circuit according to claim 2, characterized in that: The on-resistance of the switch circuit itself is higher than a specified value, The control unit sets the switch circuit to an on state throughout the data period.

5. The output amplifier circuit according to claim 1, wherein: The data period is set so that the start timing of the data period is shifted for each predetermined number of amplifiers among the first to n-th amplifiers.

6. The output amplifier circuit according to any one of claims 1 to 5, characterized in that: The first to Kth bias circuits include a voltage adjustment unit that receives a bias control signal that specifies a voltage value of the bias voltage and adjusts the voltage value of each bias voltage to the voltage value specified by the bias control signal.

7. The output amplifier circuit according to claim 6, characterized in that A common bias voltage generating circuit is included, which generates a bias voltage having a fixed voltage value different from the bias voltage and supplies the bias voltage to the first to n-th amplifiers.

8. A display driver, characterized in that include: a grayscale voltage generating circuit for generating first to nth grayscale voltages (n is an integer greater than or equal to 2) each having a voltage value corresponding to a brightness level of each pixel based on an image signal; The first to nth amplifiers receive the first to nth grayscale voltages and supply the amplified first to nth output voltages to the first to nth data lines of the display panel; First to K-th bias circuits are provided corresponding to first to K-th amplifier groups obtained by dividing the first to n-th amplifiers into K (K is an integer greater than or equal to 2) groups, and each generates a bias voltage for setting a current value of an operating current of the amplifier; First to K-th wirings are independent of each other and supply the bias voltages generated in the first to K-th bias circuits to the first to K-th amplifier groups, respectively; as well as The switch circuit connects one of the first to K-th wirings to another wiring different from the one wiring when in an on state.

9. A display device, characterized in that include: The display panel has first to nth data lines (n is an integer greater than or equal to 2) extending in the horizontal direction of the display screen; A grayscale voltage generating circuit that generates first to nth grayscale voltages each having a voltage value corresponding to a brightness level of each pixel based on an image signal; first to n-th amplifiers, receiving the first to n-th grayscale voltages and supplying first to n-th output voltages obtained by respectively amplifying the first to n-th output voltages to the first to n-th data lines of the display panel; First to K-th bias circuits are provided corresponding to first to K-th amplifier groups obtained by dividing the first to n-th amplifiers into K (K is an integer greater than or equal to 2) groups, and each generates a bias voltage for setting a current value of an operating current of the amplifier; First to K-th wirings are independent of each other and supply the bias voltages generated in the first to K-th bias circuits to the first to K-th amplifier groups, respectively; as well as The switch circuit connects one of the first to K-th wirings to another wiring different from the one wiring when in an on state.

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