Driving method and device of display panel and display device

Abstract

The invention discloses a driving method and device of a display panel and a display device, and belongs to the technical field of display. In the display panel, different clock signals are accessed to a first scanning circuit and a second scanning circuit, and a partition enable signal is also accessed to the second scanning circuit; the voltages of the clock signals and the partition enable signals are provided by the same power supply; the first scanning circuit is used for providing a first scanning signal for each pixel circuit, and the second scanning circuit is used for controlling the frequency of a second scanning signal provided for each pixel circuit according to a partition enable signal; the driving method of the display panel comprises the following steps: controlling voltage jump edges in all clock signals accessed by a first scanning circuit and voltage jump edges with the same voltage jump direction in all clock signals accessed by a second scanning circuit under the condition that the display panel displays in at least two display partitions with different refresh frequencies, and the time is not overlapped. According to the invention, the problem of cross grains during partition multi-frequency display of the display panel can be solved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel driving method and device, and a display device. Background Art

[0002] With the development of display technology, partition multi-frequency technology is gradually gaining attention. Dividing a screen into different areas and matching different refresh rates according to the displayed content can achieve fine scene control while reducing power consumption. However, in related technologies, the display panel has horizontal stripes when displaying in partition multi-frequency. Summary of the invention

[0003] The present invention provides a display panel driving method and device, and a display device, so as to solve the problem of horizontal stripes when the display panel performs partition multi-frequency display.

[0004] In a first aspect, an embodiment of the present invention provides a method for driving a display panel, wherein the display panel comprises: a first scanning circuit, a second scanning circuit and a plurality of pixel circuits; the first scanning circuit and the second scanning circuit are connected to different clock signals, and the second scanning circuit is also connected to a partition enable signal; the voltages of the clock signals and the partition enable signal are provided by the same power supply; the first scanning circuit is used to provide a first scanning signal to each pixel circuit, and the second scanning circuit is used to control the frequency of a second scanning signal provided to each pixel circuit according to the partition enable signal;

[0005] The driving method of the display panel includes:

[0006] When the display panel displays in at least two display partitions with different refresh frequencies, the voltage jump edges in all clock signals connected to the first scanning circuit are controlled to not overlap in time with the voltage jump edges with the same voltage jump direction in all clock signals connected to the second scanning circuit.

[0007] Optionally, each of the clock signals is a pulse signal in which the first voltage and the second voltage appear alternately; the second scanning circuit is connected to at least one of the partition enable signals;

[0008] The driving method of the display panel further includes:

[0009] In the case where the display panel needs to display in at least two display partitions with different refresh frequencies, at least part of the partition enable signals are controlled to be signals in which the first voltage and the second voltage appear alternately, so that the frequencies of the second scanning signals received by at least two of the display partitions are different; wherein the refresh frequency of any of the display partitions is the frequency of the second scanning signal received by the display partition; the first voltages of the clock signals and the partition enable signals are provided by the same power supply, and the second voltages of the clock signals and the partition enable signals are provided by the same power supply;

[0010] Preferably, the display panel further comprises a plurality of light-emitting devices arranged in an array, and each of the pixel circuits is connected to each of the light-emitting devices in a one-to-one correspondence; the second scanning circuit comprises a plurality of second shift registers connected in cascade, each of the second shift registers is connected to a corresponding partition enable signal, and one of the second shift registers provides the second scanning signal to each of the pixel circuits connected to at least one row of the light-emitting devices;

[0011] For any pixel circuit, in the gate initialization phase and the data writing phase of any display frame, the second shift register controls the voltage of the second scanning signal output to be equal to the voltage of the connected partition enable signal.

[0012] Optionally, the driving method of the display panel also includes: controlling at least part of the voltage transition edges in at least part of the clock signal connected to the first scanning circuit to overlap in time with at least part of the voltage transition edges in the opposite direction of the voltage transition of at least part of the clock signal connected to the second scanning circuit.

[0013] Optionally, controlling at least part of the voltage transition edges in at least part of the clock signal connected to the first scanning circuit to overlap in time with at least part of the voltage transition edges in opposite directions of the voltage transitions in at least part of the clock signal connected to the second scanning circuit comprises:

[0014] Controlling at least part of the voltage rising edge of at least one clock signal connected to the first scanning circuit to overlap in time with at least part of the voltage falling edge of at least one clock signal connected to the second scanning circuit;

[0015] or,

[0016] Controlling at least part of the voltage falling edge of at least one clock signal connected to the first scanning circuit to overlap in time with at least part of the voltage rising edge of at least one clock signal connected to the second scanning circuit;

[0017] Preferably, the frequencies and pulse widths of all clock signals connected to the first scanning circuit and the second scanning circuit are the same.

[0018] Optionally, the driving method of the display panel also includes: controlling the voltage transition edges in all clock signals connected to the first scanning circuit to be non-overlapping in time with the voltage transition edges in the opposite directions of the voltage transitions in all clock signals connected to the second scanning circuit.

[0019] Optionally, the pixel circuit includes: a driving transistor, a threshold compensation transistor and a first initialization transistor; the threshold compensation transistor is connected between the gate and the second electrode of the driving transistor, and the first initialization transistor is connected to the second electrode of the driving transistor;

[0020] The first scanning circuit is used to provide the first scanning signal to the gate of each of the first initialization transistors, and the second scanning circuit is used to provide the second scanning signal to the gate of each of the threshold compensation transistors;

[0021] Preferably, the threshold compensation transistor and the first initialization transistor have the same channel type;

[0022] Preferably, the first scanning circuit is further connected to a first start signal, and the first scanning circuit is used to generate each first scanning signal according to the first start signal and the connected clock signal; the second scanning circuit is further connected to a second start signal, and the second scanning circuit is used to generate each second scanning signal according to the second start signal, the partition enable signal and the connected clock signal; the first start signal and the second start signal have the same frequency and different pulse widths;

[0023] The driving method of the display panel further includes:

[0024] Controlling the pulse width of the first start signal to be smaller than the pulse width of the second start signal; and controlling each pulse of the second start signal to temporally overlap each pulse of the first start signal;

[0025] Preferably, the pixel circuit further includes a data writing transistor, the data writing transistor is connected to the first electrode of the driving transistor; the display panel further includes a third scanning circuit, the third scanning circuit is connected to a third starting signal, and the third scanning circuit is used to provide a third scanning signal to the gate of the data writing transistor in each pixel circuit according to the third starting signal; wherein the frequency of the third starting signal is the same as that of the first starting signal;

[0026] The driving method of the display panel further includes:

[0027] Control the pulse width of the third start signal to be one line time; control the starting time of the first pulse of the third start signal to be later than or at the same time as the ending time of the first pulse of the first start signal; and control each pulse of the second start signal to temporally cover each pulse of the first start signal and each pulse of the third start signal;

[0028] Preferably, the first scanning circuit is connected to the two clock signals; the pulse start time of the first start signal overlaps with a voltage transition edge of one of the clock signals connected to the first scanning circuit in time;

[0029] The second scanning circuit is connected to the two clock signals; the pulse start time of the second start signal overlaps in time with a voltage transition edge of one of the clock signals connected to the second scanning circuit.

[0030] Optionally, the pulse width of the first start signal is: L1∈[2H, 10H], where L1 is the pulse width of the first start signal and H is the line time.

[0031] Optionally, the display panel further includes a plurality of light-emitting devices arranged in an array, and each of the pixel circuits is connected to each of the light-emitting devices in a one-to-one correspondence; each of the pixel circuits connected to each of the light-emitting devices in every k rows is connected to the same second scanning signal; k is a positive integer;

[0032] The pulse width of the second start signal satisfies: L2≥k*(L1+H); wherein L2 is the pulse width of the second start signal;

[0033] Preferably, L2≥18H;

[0034] Preferably, k=2, L1=2H, L2=18H.

[0035] In a second aspect, an embodiment of the present invention further provides a driving device for a display panel, comprising:

[0036] A time phase control module is used to control the voltage jump edges in all clock signals connected to the first scanning circuit when the display panel displays in at least two display partitions with different refresh frequencies, so that the voltage jump edges with the same voltage jump direction in all clock signals connected to the second scanning circuit do not overlap in time.

[0037] In a third aspect, an embodiment of the present invention further provides a display device, including: a display panel and a driving chip, wherein the driving chip is used to execute the display panel driving method provided by any embodiment of the present invention.

[0038] In the driving method of the display panel provided by the embodiment of the present invention, by controlling the voltage jump edges in all the clock signals connected to the first scanning circuit, and the voltage jump edges in the same voltage jump direction in all the clock signals connected to the second scanning circuit, they are not overlapped in time, which can effectively disperse the load on the power supply used to provide voltage to the clock signal and the partition enable signal, and avoid the load mutation causing obvious jitter in the voltage output of the power supply. In this way, the voltage jitter of the partition enable signal can be effectively reduced. In the partition multi-frequency display mode, the partition enable signal itself needs to perform a voltage jump corresponding to the boundary position of the adjacent display partitions. By reducing the voltage jitter on the partition enable signal, the voltage jitter of the second scanning signal can be reduced, thereby reducing the impact on the on-off state of the transistor connected to the second scanning signal in the pixel circuit, reducing the voltage fluctuation of the gate of the driving transistor in the pixel circuit, and effectively improving the horizontal stripe problem during the partition multi-frequency display.

[0039] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0041] Figure 1 is a schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0042] Figure 2 It is a timing relationship diagram of each clock signal in the related art;

[0043] Figure 3 is a timing relationship diagram of various clock signals provided by an embodiment of the present invention;

[0044] Figure 4 is another timing relationship diagram of various clock signals provided by an embodiment of the present invention;

[0045] Figure 5 is another timing relationship diagram of various clock signals provided by an embodiment of the present invention;

[0046] Figure 6 is a schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0047] Figure 7is a schematic structural diagram of a second shift register provided by an embodiment of the present invention;

[0048] Figure 8 is a structural schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0049] Fig. 9 is a driving timing diagram of a pixel circuit provided by an embodiment of the present invention;

[0050] Fig.10 is a driving timing diagram of a display panel provided by an embodiment of the present invention;

[0051] Fig.11 is a structural schematic diagram of a second scanning circuit provided by an embodiment of the present invention;

[0052] Fig.12 is a driving timing diagram of another display panel provided by an embodiment of the present invention;

[0053] Fig.13 is a driving timing diagram of another pixel circuit provided by an embodiment of the present invention;

[0054] Fig.14 It is a structural schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0055] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0056] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0057] An embodiment of the present invention provides a method for driving a display panel. By adjusting the time phase of clock signals connected to different scanning circuits, the horizontal stripe problem in a partitioned multi-frequency display mode can be effectively improved. The method can be executed by a driving device of the display panel. The driving device of the display panel can be implemented in the form of hardware and / or software. The driving device of the display panel can be configured in a driving chip of the display device.

[0058] The structure and driving process of the display panel are first briefly described below. Figure 1 is a schematic diagram of the structure of a display panel provided by an embodiment of the present invention. Figure 1 , the display panel includes: a first scanning circuit 11, a second scanning circuit 12 and a plurality of pixel circuits 20. The first scanning circuit 11 and the second scanning circuit 12 are connected to different clock signals, for example, the first scanning circuit 11 is connected to the first clock signal CK1 and the second clock signal CK2, and the second scanning circuit 12 is connected to the third clock signal CK3 and the fourth clock signal CK4; the second scanning circuit 12 is also connected to the partition enable signal VFE. The display panel also includes a plurality of light-emitting devices arranged in an array, and each pixel circuit 20 is connected to each light-emitting device in a one-to-one correspondence. Figure 1 For example, the pixel circuits 20 may be arranged in an array in the display area AA of the display panel 100 , and the first scanning circuit 11 and the second scanning circuit 12 are both disposed in the non-display area NAA of the display panel 100 .

[0059] The first scanning circuit 11 and the second scanning circuit 12 are both connected to each pixel circuit 20, and for the same pixel circuit 20, the first scanning circuit 11 and the second scanning circuit 12 are connected to different signal terminals of the pixel circuit 20. The first scanning circuit 11 is used to provide a first scanning signal S1 to each pixel circuit 20, and the second scanning circuit 12 is used to control the frequency of the second scanning signal S2 provided to each pixel circuit 20 according to the partition enable signal VFE, thereby controlling the position and refresh frequency of each display partition in the display panel 100. Specifically, the first scanning circuit 11 can access a first start signal with a pulse of a certain frequency, and according to the control of the first clock signal CK1 and the second clock signal CK2, the pulse of the first start signal is shifted step by step and output, so as to obtain the first scanning signal S1 with the same frequency as the first start signal at each stage. The second scanning circuit 12 can be connected to a second start signal with a pulse of a certain frequency (for example, the same frequency as the first start signal), and control the step-by-step shift transmission of the pulse of the second start signal according to the third clock signal CK3 and the fourth clock signal CK4, so as to obtain the level transmission signals of each level with the same frequency as the second start signal, and control the voltage of the output second scanning signal S2 of each level according to the partition enable signal VFE, so that the number of pulses of the second scanning signal S2 of any level is less than or equal to the number of pulses in the level transmission signal of the same level, so that the frequency of the second scanning signal S2 of the level is less than or equal to the frequency of the level transmission signal of the same level. Among them, the second scanning signal S2 is used to control whether the driving stage related to the gate voltage of the driving transistor in the pixel circuit is carried out, for example, it is used to control whether the gate initialization stage and the data writing stage are carried out; the frequency of the second scanning signal S2 received by the pixel circuit 20 in the same display partition is the refresh frequency of the display partition. The scanning signal is usually provided to each pixel circuit 20 through a scanning line extending along the row direction X. Each pixel circuit 20 in the same row is connected to the first scanning signal S1 of the same level and the second scanning signal S2 of the same level. The scanning stage of the pixel circuit 20 is performed row by row. Therefore, by controlling the frequency of the second scanning signal S2 of each level, a partitioned multi-frequency display along the column direction Y can be achieved; the row direction X is perpendicular to the column direction Y. Among them, the frequency of any scanning signal refers to: the frequency of the conduction pulse in the scanning signal, and the conduction pulse is a pulse that controls the conduction of the transistor connected to the scanning signal in the pixel circuit 20.

[0060] The voltages of each clock signal and the partition enable signal VFE are provided by the same power supply. Specifically, each clock signal is a signal in which a first voltage and a second voltage appear alternately; in the partition multi-frequency display mode, the partition enable signal VFE is also a signal in which a first voltage and a second voltage appear alternately; the first voltage of each clock signal and the first voltage of the partition enable signal VFE are provided by, for example, the same first power supply, and the second voltage of each clock signal and the second voltage of the partition enable signal VFE are provided by, for example, the same second power supply.

[0061] The driving method of the display panel includes: when the display panel displays in at least two display partitions with different refresh frequencies, controlling the voltage jump edges in all clock signals connected to the first scanning circuit so that the voltage jump edges with the same voltage jump direction in all clock signals connected to the second scanning circuit do not overlap in time.

[0062] The situation where the display panel performs display in at least two display partitions with different refresh frequencies is the situation where the display panel performs display in the partition multi-frequency display mode.

[0063] The same voltage jump direction of the two voltage jump edges means that both voltage jump edges are voltage rising edges or both are voltage falling edges. Then, the control step is specifically: control the voltage rising edges in all clock signals connected to the first scanning circuit to be staggered in time with the voltage rising edges in all clock signals connected to the second scanning circuit; and control the voltage falling edges in all clock signals connected to the first scanning circuit to be staggered in time with the voltage falling edges in all clock signals connected to the second scanning circuit.

[0064] Since the voltages of the clock signals and the partition enable signal VFE are provided by the same power supply, the first scanning circuit 11 and the second scanning circuit 12 are both loads carried by the power supply. When the load fluctuates greatly, the voltage output by the power supply will fluctuate. For example, the voltage fluctuation of the first power supply output will cause the first voltage of the partition enable signal VFE to fluctuate, and the voltage fluctuation of the second power supply output will cause the second voltage of the partition enable signal VFE to fluctuate. As for the second scanning circuit 12, when it outputs the second scanning signal S2 of each level, the voltage of the connected partition enable signal VFE is output as the second scanning signal S2 corresponding to the period when the level transfer signal of the same level outputs the conduction pulse. For example, the first voltage is the on-voltage of the transistor in the pixel circuit 20 connected to the second scanning signal S2, and the second voltage is the cut-off voltage of the transistor. Exemplarily, the level transfer signal is a high-frequency signal having an on-pulse in each display frame; then, corresponding to the time period in which the level transfer signal of the same level outputs an on-pulse in any display frame, if the partition enable signal VFE is the first voltage, the second scanning signal S2 has an on-pulse in the display frame, and the pixel circuit 20 connected to the second scanning signal S2 performs data refresh in the display frame; if the partition enable signal VFE is the second voltage, the second scanning signal S2 does not have an on-pulse in the display frame, and the pixel circuit 20 connected to the second scanning signal S2 maintains data in the display frame without refreshing data. In summary, the voltage of the partition enable signal VFE determines the on-off state of the transistor connected to the second scan signal S2 in the pixel circuit 20. When the first voltage on the partition enable signal VFE fluctuates, it will affect the conduction degree of the transistor connected to the second scan signal S2, thereby affecting the data writing degree of the gate of the driving transistor in the pixel circuit 20; when the second voltage on the partition enable signal VFE fluctuates, it will affect the off degree of the transistor connected to the second scan signal S2, thereby affecting the leakage degree of the gate of the driving transistor in the pixel circuit 20; the above-mentioned influences will cause the gate voltage of the driving transistor to deviate from the expected value, resulting in fluctuations in the driving current output by the driving transistor, thereby causing fluctuations in the brightness of the light-emitting device. Since the second scan signal S2 is provided row by row, when the voltage on the partition enable signal VFE fluctuates, the driving current output by a whole row of pixel circuits will fluctuate, resulting in fluctuations in the brightness of a whole row of light-emitting devices, which is manifested as a horizontal stripe problem.

[0065] Each clock signal is used to control the on and off of multiple transistors in the corresponding scanning circuit, and the load carried by each clock signal serves as an important load of the power supply. Figure 2In the related art, at least part of the voltage rising edge (or voltage falling edge) of each clock signal connected to the first scanning circuit 11 has a voltage rising edge (or voltage falling edge) occurring simultaneously with it in each clock signal connected to the second scanning circuit 12, which makes the load fluctuation of the first power supply and the second power supply relatively large. Specifically, the pulses of the first clock signal CK1 and the second clock signal CK2 connected to the first scanning circuit 11 appear alternately; the pulses of the third clock signal CK3 and the fourth clock signal CK4 connected to the second scanning circuit 11 appear alternately. Taking the first voltage as a high voltage and the second voltage as a low voltage as an example, see Figure 2 The short dashed line in the figure indicates that the voltage rising edge of the first clock signal CK1 and the voltage rising edge of the fourth scanning signal CK4 occur simultaneously, and the voltage rising edge of the second clock signal CK2 and the voltage rising edge of the third scanning signal CK3 occur simultaneously, which will cause the load of the first power supply to increase suddenly and the load of the second power supply to decrease suddenly, thereby causing the first voltage and the second voltage to fluctuate. Figure 2 The dotted dashed line in the figure shows that the voltage falling edge of the first clock signal CK1 and the voltage falling edge of the fourth scanning signal CK4 occur simultaneously, and the voltage falling edge of the second clock signal CK2 and the voltage falling edge of the third scanning signal CK3 occur simultaneously, which will cause the load of the first power supply to drop suddenly and the load of the second power supply to increase suddenly, which will also cause the first voltage and the second voltage to fluctuate. In the partition multi-frequency display mode, the partition enable signal VFE itself will jump between the first voltage and the second voltage, which will cause the load fluctuations on the two power supplies. Combined with the voltage jumps in the same direction at the same time due to different clock signals, the voltage fluctuation of the partition enable signal VFE will be more obvious, and the horizontal stripe problem will be more likely to occur.

[0066] In this embodiment, see Figure 3 ,like Figure 3 As shown in the middle and short dashed lines, the voltage rising edge of the first clock signal CK1 and the voltage rising edge of the fourth scanning signal CK4 are staggered in time, and the voltage rising edge of the second clock signal CK2 and the voltage rising edge of the third scanning signal CK3 are staggered in time, so that the load of the first power supply increases in stages and the load of the second power supply decreases in stages, thereby distributing the loads of the two power supplies. And, as Figure 3As shown in the dotted line position, the voltage falling edge of the first clock signal CK1 and the voltage falling edge of the fourth scanning signal CK4 are staggered in time, and the voltage falling edge of the second clock signal CK2 and the voltage falling edge of the third scanning signal CK3 are staggered in time, so that the load of the first power supply can be reduced in stages and the load of the second power supply can be increased in stages, so as to achieve the dispersion of the loads of the two power supplies. This arrangement makes the loads carried by the clock signal as the main load dispersed in time, which can reduce the jitter of the output voltage of the two power supplies. In particular, corresponding to the display partition boundary position, the partition enable signal VFE itself jumps between the first voltage and the second voltage, which will cause the power supply output voltage to fluctuate and easily cause boundary horizontal stripe problems; but since the load carried by the clock signal is heavier than the load carried by the partition enable signal VFE, compared with the jitter of the power supply output voltage increased by the load fluctuation carried by the partition enable signal VFE, the improvement effect of reducing the jitter of the power supply output voltage obtained by dispersing the load carried by the clock signal in time is more obvious. Therefore, the jitter of the power supply output voltage can still be reduced as a whole, thereby reducing the voltage jitter of the partition enable signal VFE, and then reducing the voltage jitter of the second scanning signal S2 connected to the pixel circuit 20 at the partition boundary position, which can effectively improve the horizontal stripe problem at the partition boundary.

[0067] In the driving method of the display panel provided by the embodiment of the present invention, by controlling the voltage jump edges in all the clock signals connected to the first scanning circuit, and the voltage jump edges in the same voltage jump direction in all the clock signals connected to the second scanning circuit, they are not overlapped in time, which can effectively disperse the load on the power supply used to provide voltage to the clock signal and the partition enable signal, and avoid the load mutation causing obvious jitter in the voltage output of the power supply. In this way, the voltage jitter of the partition enable signal can be effectively reduced. In the partition multi-frequency display mode, the partition enable signal itself needs to perform a voltage jump corresponding to the boundary position of the adjacent display partitions. By reducing the voltage jitter on the partition enable signal, the voltage jitter of the second scanning signal can be reduced, thereby reducing the impact on the on-off state of the transistor connected to the second scanning signal in the pixel circuit, reducing the voltage fluctuation of the gate of the driving transistor in the pixel circuit, and effectively improving the horizontal stripe problem during the partition multi-frequency display.

[0068] On the basis of the above-mentioned embodiments, optionally, for each voltage transition edge in each clock signal connected to the first scanning circuit and each voltage transition edge in the opposite direction of the voltage transition in each clock signal connected to the second scanning circuit, different time alignment relationships can be adopted, which are explained respectively below.

[0069] In one embodiment, optionally, the driving method of the display panel also includes: controlling the voltage transition edges in all clock signals connected to the first scanning circuit to be non-overlapping in time with the voltage transition edges in opposite directions of the voltage transitions in all clock signals connected to the second scanning circuit.

[0070] Among them, the voltage jump directions of the two voltage jump edges are opposite, which means that one of the two voltage jump edges is a voltage rising edge, and the other is a voltage falling edge. Then, the control step is specifically: control the voltage rising edges in all clock signals connected to the first scanning circuit and the voltage falling edges in all clock signals connected to the second scanning circuit to be staggered in time; and control the voltage falling edges in all clock signals connected to the first scanning circuit and the voltage rising edges in all clock signals connected to the second scanning circuit to be staggered in time. In this way, all the voltage jump edges in all clock signals connected to the first scanning circuit and all the voltage jump edges in all clock signals connected to the second scanning circuit do not overlap in time. Exemplarily, the timing relationship diagram of each clock signal obtained by the control of this embodiment can be seen in Figure 3 All voltage transition edges in the first clock signal CK1, the second clock signal CK2, the third clock signal CK3 and the fourth clock signal CK4 do not overlap in time and all occur in time division. This embodiment is configured in this way to disperse the load of the power supply to the greatest extent and avoid voltage fluctuations of the power supply output.

[0071] In another embodiment, optionally, the driving method of the display panel also includes: controlling at least part of the voltage jump edges in at least part of the clock signal connected to the first scanning circuit to overlap in time with at least part of the voltage jump edges in the opposite direction of the voltage jump directions in at least part of the clock signal connected to the second scanning circuit.

[0072] In this way, at least part of the voltage jump edges in the clock signal connected to the first scanning circuit can be found in the clock signal connected to the second scanning circuit. The voltage jump edges that occur simultaneously and have the opposite voltage jump direction can balance the load on the power supply and further avoid voltage jitter of the power supply output. For example, if the voltage rising edge in the clock signal connected to the first scanning circuit and the voltage falling edge in the clock signal connected to the second scanning circuit occur simultaneously, then for the clock signal connected to the first scanning circuit, the load on the first power supply increases and the load on the second power supply decreases, while for the clock signal connected to the second scanning circuit, the load on the first power supply decreases and the load on the second power supply increases. The effects of the two on the loads of the two power supplies can offset each other, and the loads of the two power supplies increase and decrease, so that the loads of the first power supply and the second power supply are dynamically balanced, thereby effectively avoiding voltage jitter of the power supply output.

[0073] Exemplarily, the above-mentioned control of at least part of the voltage transition edges in at least part of the clock signal connected to the first scanning circuit and at least part of the voltage transition edges in the opposite direction of the voltage transition in at least part of the clock signal connected to the second scanning circuit overlaps in time, which may specifically include: controlling at least part of the voltage rising edge in at least one clock signal connected to the first scanning circuit to overlap in time with at least part of the voltage falling edge in at least one clock signal connected to the second scanning circuit. Figure 4 As shown, the voltage rising edge of the first clock signal CK1 and the voltage falling edge of the third clock signal CK3 occur simultaneously, and the voltage rising edge of the second clock signal CK2 and the voltage falling edge of the fourth clock signal CK4 occur simultaneously.

[0074] Alternatively, the above-mentioned control of at least part of the voltage transition edges in at least part of the clock signal connected to the first scanning circuit and at least part of the voltage transition edges in the opposite direction of the voltage transition in at least part of the clock signal connected to the second scanning circuit overlaps in time, which may specifically include: controlling at least part of the voltage falling edges in at least one clock signal connected to the first scanning circuit to overlap in time with at least part of the voltage rising edges in at least one clock signal connected to the second scanning circuit. For example Figure 5 As shown, the voltage falling edge of the first clock signal CK1 and the voltage rising edge of the third clock signal CK3 occur simultaneously, and the voltage falling edge of the second clock signal CK2 and the voltage rising edge of the fourth clock signal CK4 occur simultaneously.

[0075] Based on the above embodiments, optionally, the frequencies and pulse widths of all clock signals connected to the first scanning circuit and the second scanning circuit are the same. Figure 4 When the voltage rising edge of at least one of the first clock signal CK1 and the second clock signal CK2 is controlled to occur simultaneously with the voltage falling edge of at least one of the third clock signal CK3 and the fourth clock signal CK4, the voltage falling edge of at least one of the first clock signal CK1 and the second clock signal CK2 does not overlap with the voltage rising edge of at least one of the third clock signal CK3 and the fourth clock signal CK4 in time. Figure 5 When the voltage falling edge of at least one of the first clock signal CK1 and the second clock signal CK2 is controlled to occur simultaneously with the voltage rising edge of at least one of the third clock signal CK3 and the fourth clock signal CK4, the voltage rising edge of at least one of the first clock signal CK1 and the second clock signal CK2 does not overlap in time with the voltage falling edge of at least one of the third clock signal CK3 and the fourth clock signal CK4.

[0076] Based on the above embodiments, optionally, the second scanning circuit may be connected to at least one partition enable signal. In other words, at least one partition enable signal line may be provided in the display panel to provide the partition enable signals required by the second scanning circuit.

[0077] The driving method of the display panel further includes: when the display panel needs to display in at least two display partitions with different refresh frequencies, controlling at least part of the partition enable signal to be a signal that alternates between a first voltage and a second voltage, so that the frequencies of the second scanning signals received by at least two display partitions are different. The refresh frequency of any display partition is the frequency of the second scanning signal received by the display partition. That is, by controlling the voltage change process of the partition enable signal, the partition multi-frequency display of the display panel can be achieved.

[0078] The specific structure of the display panel and the specific implementation of the partitioned multi-frequency display are described below, but are not intended to limit the present invention.

[0079] Figure 6 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention. Figure 6 , each pixel circuit 20 can be connected one by one to each light emitting device (not shown in the figure) arranged in an array in the display area AA; Figure 6 Exemplarily, each pixel circuit 20 is also arranged in an array in the display area. The first scanning circuit 11 may include a plurality of first shift registers 110 connected in cascade, the input end of the first-stage first shift register 110 is connected to the first start signal SIN1, and the output end of each stage of the first shift register 110 is connected to the input end of the next stage of the first shift register 110; the first clock end and the second clock end of each stage of the first shift register 110 are alternately connected to the first clock signal CK1 and the second clock signal CK2; each stage of the first shift register 110 outputs a first scanning signal S1, and each stage of the first scanning signal S1 is a step-by-step shift output of the first start signal SIN1. Exemplarily, one first shift register 110 provides a first scanning signal S1 to each pixel circuit 20 connected to a row of light-emitting devices.

[0080] The second scanning circuit 12 may include a plurality of second shift registers 120 connected in cascade, the input end of the first stage second shift register 120 is connected to the second start signal SIN2, the first output end of each stage second shift register 120 is connected to the input end of the next stage second shift register 120, and the stage transfer signal Carry is provided to the input end of the next stage second shift register 120; each stage transfer signal Carry is a stage-by-stage shift output of the second start signal SIN2; the first clock end and the second clock end of each stage second shift register 120 are alternately connected to the third clock signal CK3 and the fourth clock signal CK4; each second shift register 120 is connected to the corresponding partition enable signal VFE, and the second output end of each stage second shift register 120 outputs a stage second scanning signal S2, and the partition enable signal VFE is used to control the voltage of the second scanning signal S2. Exemplarily, a second shift register 120 shifts at least one row ( Figure 6 The second scanning signal S2 is provided to each pixel circuit 20 connected during the light emission period (two rows in the figure).

[0081] For any pixel circuit 20 , in the gate initialization phase and the data writing phase of any display frame, the second shift register 120 controls the voltage of the output second scanning signal S2 to be equal to the voltage of the connected partition enable signal VFE.

[0082] Specifically, the structure of the second shift register 120 can be seen in Figure 7, the second shift register 120 may include a voltage control module 31, a level transmission output module 32 and a scan output module 33. Among them, the voltage control module 31 is used to control the voltage of the first node N1 and the second node N2 according to the third clock signal CK3, the fourth clock signal CK4 and the input signal IN; the input signal IN is the second start signal SIN2 or the level transmission signal Carry output by the second shift register 120 of the previous stage; the voltage control module 31 may have any structure in the relevant technology, which will not be described in detail here. The level transmission output module 32 may include a ninth transistor M9 and a tenth transistor M10, the ninth transistor M9 is used to control whether the first voltage VGH is output as the level transmission signal Carry according to the voltage of the first node N1, and the tenth transistor M10 is used to control whether the second voltage VGL is output as the level transmission signal Carry according to the voltage of the second node N2; the level transmission output module 32 may also include a capacitor C2 for storing the voltage of the first node N1. The scan output module 33 may include an eleventh transistor M11 and a twelfth transistor M12, wherein the eleventh transistor M11 is used to control whether the partition enable signal VFE is output as the second scan signal S2 according to the voltage of the first node N1, and the twelfth transistor M12 is used to control whether the second voltage VGL is output as the second scan signal S2 according to the voltage of the second node N2. The difference between the level transmission output module 32 and the scan output module 33 is that the level transmission output module 32 is directly connected to the first voltage, and when the ninth transistor M9 is turned on, the voltage of the level transmission signal Carry is equal to the first voltage VGH; the scan output module 33 is connected to the partition enable signal VFE, and when the eleventh transistor M11 is turned on, the voltage of the second scan signal S2 is equal to the voltage of the partition enable signal VFE. Since the voltage of the partition enable signal VFE is adjustable, it can be the first voltage VGH or the second voltage VGL, so that the frequency of the second scan signal S2 is adjustable.

[0083] Figure 8 is a schematic diagram of a pixel circuit provided by an embodiment of the present invention. Figure 8 , the pixel circuit 20 includes: a driving transistor M1, a threshold compensation transistor M3 and a first initialization transistor M4; the threshold compensation transistor M3 is connected between the gate and the second electrode of the driving transistor M1, and the first initialization transistor M4 is connected to the second electrode of the driving transistor M1. The first scanning circuit is used to provide a first scanning signal S1 to the gate of each first initialization transistor M4, and the second scanning circuit is used to provide a second scanning signal S2 to the gate of each threshold compensation transistor M3. Among them, the channel type of the threshold compensation transistor M3 and the first initialization transistor M4 is the same, for example, both are N-type transistors. The first voltage is, for example, the on-voltage of the threshold compensation transistor M3, specifically a high voltage, and the second voltage is, for example, the off-voltage of the threshold compensation transistor M3, specifically a low voltage.

[0084] And, the pixel circuit may also include: a data writing transistor M2, a first light-emitting control transistor M5, a second light-emitting control transistor M6, a second initialization transistor M7, a third initialization transistor M8 and a storage capacitor Cst. Among them, the first light-emitting control transistor M5, the driving transistor M1, the second light-emitting control transistor M6 and the light-emitting device OLED are connected in series in sequence, for example, they are connected in series between the first power line and the second power line, the first power line is used to provide the first power signal VDD, and the second power line is used to provide the second power signal VSS; the gate of the first light-emitting control transistor M5 and the gate of the second light-emitting control transistor M6 are both connected to the light-emitting control signal EM. The data writing transistor M2 is connected to the first electrode of the driving transistor M1, and is connected to the third scanning signal S3 and the data voltage Vdata. The first initialization transistor M4 is also connected to the first initialization voltage Vrefn1. The second initialization transistor M8 is connected to the second electrode of the driving transistor M1, and is connected to the second initialization voltage Vrefp and the fourth scanning signal S4. The third initialization transistor M7 is connected to the anode of the light-emitting device OLED, and is connected to the third initialization voltage Vrefn2 and the fourth scanning signal S4. The storage capacitor Cst is connected to the gate of the driving transistor M1 and connected to the first power supply signal VDD. Except for the threshold compensation transistor M3 and the first initialization transistor M4, other transistors in the pixel circuit 20 can be P-type transistors, the third scanning signal S3 and the fourth scanning signal S4 can be provided by the third scanning circuit, the light-emitting control signal EM can be provided by the light-emitting control circuit, and the power supply of the clock signal connected to the third scanning circuit and the light-emitting control circuit is different from the power supply of the clock signal connected to the first scanning circuit and the second scanning circuit, that is, the working process of the third scanning circuit and the light-emitting control circuit does not affect the voltage on the partition enable signal VFE.

[0085] The driving timing of the pixel circuit 20 can be found in Fig. 9 , combined with Figure 8 and Fig. 9 , the driving process of the pixel circuit 20 may include:

[0086] In the gate initialization stage T11, the first scanning signal S1 and the second scanning signal S2 are both high voltages, the threshold compensation transistor M3 and the first initialization transistor M4 are both turned on, and the first initialization voltage Vrefn1 is transmitted to the gate of the driving transistor M1 through the threshold compensation transistor M3 and the first initialization transistor M4, thereby initializing the gate of the driving transistor M1.

[0087] In the data writing stage T12, the second scanning signal S2 is a high voltage, the third scanning signal S3 is a low voltage, the threshold compensation transistor M3 and the data writing transistor M2 are both turned on, and the data voltage Vdata is transmitted to the gate of the driving transistor M1 through the data writing transistor M2, the driving transistor M1 and the threshold compensation transistor M3 to charge the storage capacitor Cst.

[0088] In the anode initialization stage T13, the fourth scanning signal S4 is a low voltage, and the second initialization transistor M8 and the third initialization transistor M7 are both turned on; the second initialization voltage Vrefp is transmitted to the second electrode of the driving transistor M1 through the second initialization transistor M8 to initialize the second electrode of the driving transistor M1; the third initialization voltage Vrefn2 is transmitted to the anode of the light-emitting device OLED through the third initialization transistor M7 to initialize the anode of the light-emitting device OLED.

[0089] In the light emitting stage T14, the light emitting control signal EM is at a low voltage, the first light emitting control transistor M5 and the second light emitting control transistor M6 are both turned on; the driving transistor M1 generates a driving current according to the voltage of its gate to drive the light emitting device OLED to emit light.

[0090] It can be understood that the driving process of the above pixel circuit 20 is the driving process in the refresh frame. In the hold frame, the second scanning signal S2 maintains a low voltage, the threshold compensation transistor M3 remains off, the gate initialization phase T11 and the data writing phase T12 are not performed, and the gate voltage of the driving transistor M1 is maintained by the storage capacitor Cst. Therefore, by adjusting the voltage of the partition enable signal VFE, partition multi-frequency display can be achieved.

[0091] For details, see Fig.10 , with the display panel as Figure 1 The three upper, middle and lower partitions shown include the first display partition A1, the second display partition A2 and the third display partition A3 as an example, and the second scanning circuit 12 is connected to a partition enable signal VFE as an example, Fig.10 In the figure, the shaded filling indicates that the display partition performs data refresh, and the blank filling indicates that the display partition performs data retention. In the scanning phase of any display partition in any display frame F, when the partition enable signal VFE maintains the first voltage (here is a high voltage), each second scanning signal S2 connected to the corresponding display partition includes a conduction pulse, and the display frame is a refresh frame for each pixel circuit 20 in the display partition; when the partition enable signal VFE maintains the second voltage (here is a low voltage), each second scanning signal S2 connected to the corresponding display partition does not include a conduction pulse in the display frame, and the display frame is a retention frame for each pixel circuit 20 in the display partition.

[0092] like Fig.10In the driving timing shown, the refresh frequency of the first display partition A1 is equal to the refresh frequency of the third display partition A3, and both are lower than the refresh frequency of the second display partition A2. The display process of the display panel may include multiple display cycles CYCLE, and each display cycle CYCLE may include: display frames from a full refresh frame to the next full refresh frame; the full refresh frame is a refresh frame for the pixel circuit 20 of each display partition.

[0093] On the basis of the above embodiments, optionally, the second scanning circuit 12 can be connected to multiple partition enable signals to make the control of partition multi-frequency more flexible. Fig.11 The second scanning circuit 12 may include a plurality of sequentially connected driving groups 121, each driving group 121 includes a plurality of sequentially connected second shift registers 120; the display panel further includes a plurality of partition enable signal lines, respectively used to transmit a plurality of partition enable signals; Fig.11 Four partition enable signal lines are exemplarily given, which are used to transmit the first partition enable signal VFE1, the second partition enable signal VFE2, the third partition enable signal VFE3 and the fourth partition enable signal VFE4 respectively. Among them, each partition enable signal line is alternately connected to each driving group 121, and each second shift register 120 in the same driving group 121 is connected to the same partition enable signal line.

[0094] Then, for the full refresh frame, each partition enable signal maintains the first voltage; Fig.10 In the display frame shown in F2, each partition enable signal maintains the second voltage; Fig.10 In the display frame shown in F3, each partition enable signal is a first voltage and a second voltage that appear alternately. Fig.12 , illustratively, the first display partition A1 receives the second scanning signals output by the first four driving groups (respectively 121-1, 121-2, 121-3 and 121-4), the second display partition A2 receives the second scanning signals output by the fifth to eighth driving groups (respectively 121-5, 121-6, 121-7 and 121-8), and the third display partition A3 receives the second scanning signals output by the ninth to twelfth driving groups (respectively 121-9, 121-10, 121-11 and 121-12). Then, for example Fig.10In the display frame shown in F3, the first partition enable signal VFE1 is the second voltage in the output stage of the first driving group 121-1, so that the first driving group 121-1 does not output the conduction pulse of the second scanning signal in the display frame, the first voltage in the output stage of the fifth driving group 121-5, so that the fifth driving group 121-5 outputs the conduction pulse of the second scanning signal in the display frame, and the first voltage in the output stage of the ninth driving group 121-9, so that the ninth driving group 121-9 does not output the conduction pulse of the second scanning signal in the display frame; in the output stage of other driving groups, the first partition enable signal VFE1 can maintain the voltage, for example, maintain the voltage in the output stage of the previous driving group. Similarly, the second partition enable signal VFE2 is the second voltage in the output stage of the second driving group 121-2, the first voltage in the output stage of the sixth driving group 121-6, the first voltage in the output stage of the tenth driving group 121-10, and the voltage is maintained in the output stage of other driving groups. The third partition enable signal VFE3 is the second voltage in the output stage of the third driving group 121-3, the first voltage in the output stage of the seventh driving group 121-7, the first voltage in the output stage of the eleventh driving group 121-11, and the voltage is maintained in the output stages of the other driving groups. The fourth partition enable signal VFE4 is the second voltage in the output stage of the fourth driving group 121-4, the first voltage in the output stage of the eighth driving group 121-8, the first voltage in the output stage of the twelfth driving group 121-12, and the voltage is maintained in the output stages of the other driving groups.

[0095] Exemplarily, each driving group 121 includes eight levels of second shift registers 120, and each level of second shift registers 120 provides the same second scanning signal S2 to two rows of pixel circuits 20. Then, each partition enable signal line is equivalent to driving 16 rows of pixel circuits 20, and 64 rows of pixel circuits 20 are used as a cycle. The output of the partition enable signal directly acts on the gate of the threshold compensation transistor M3. If the power supply of the partition enable signal fluctuates, the gate voltage acting on the threshold compensation transistor M3 will jitter, thereby affecting the stability of the charging state of the storage capacitor Cst, resulting in the appearance of horizontal stripes. The driving method of the display panel provided in an embodiment of the present invention can effectively weaken the ripple jitter of the power supply output voltage of the partition enable signal by dispersing the changes in the load carried by the clock signal and reducing the coupling effect caused by the load jump, thereby improving the 16 rows of equally spaced horizontal stripes caused by the sudden change of the load.

[0096] Based on the above implementations, optionally, see Figure 6, the first scanning circuit 11 is also connected to the first start signal SIN1, and the first scanning circuit 11 is used to generate each first scanning signal S1 according to the first start signal SIN1 and the connected clock signal; the second scanning circuit 12 is also connected to the second start signal SIN2, and the second scanning circuit 12 is used to generate each second scanning signal S2 according to the second start signal SIN2, the partition enable signal VFE and the connected clock signal; the first start signal SIN1 and the second start signal SIN2 have the same frequency and different pulse widths. Figure 3 , the driving method of the display panel also includes: controlling the pulse width L1 of the first start signal SIN1 to be smaller than the pulse width L2 of the second start signal SIN2; and controlling each pulse of the second start signal SIN2 to temporally cover each pulse of the first start signal SIN1. The pulses mentioned here are all on pulses, which are first voltage pulses (high voltage pulses) here. This arrangement allows the first scan signal S1 and the second scan signal S2 to have Fig. 9 The corresponding relationship shown.

[0097] On the basis of the above-mentioned embodiments, optionally, the display panel 100 further includes a third scanning circuit, the third scanning circuit is connected to a third start signal, and the third scanning circuit is used to provide a third scanning signal S3 to the gate of the data writing transistor M2 in each pixel circuit 10 according to the third start signal. The third start signal has the same frequency as the first start signal SIN1. The driving method of the display panel also includes: controlling the pulse width of the third start signal to be one line time; controlling the starting time of the first pulse of the third start signal to be later than or at the same time as the ending time of the first pulse of the first start signal; and controlling each pulse of the second start signal to temporally cover each pulse of the first start signal and each pulse of the third start signal. This arrangement allows the first scanning signal S1, the second scanning signal S2, and the third scanning signal S3 to have in each refresh frame. Fig. 9 The corresponding relationship shown is that the pulse of the second scanning signal S2 contains the pulse of the first scanning signal S1 and the pulse of the third scanning signal S3 that occur successively. It can be understood that the line time is equal to 1 / reference refresh frequency / equivalent number of sub-pixel rows. The reference refresh frequency is the highest refresh frequency that each display partition of the display panel can support, and the equivalent number of sub-pixel rows can be obtained according to the resolution of the display panel.

[0098] Based on the above implementations, optionally, see Figure 3-5 , the first scanning circuit is connected to two clock signals. The pulse start time of the first start signal SIN1 overlaps with a voltage transition edge of one of the clock signals connected to the first scanning circuit; for example, the pulse start time of the first start signal SIN1 overlaps with a voltage falling edge of the first clock signal CK1.

[0099] The second scanning circuit is connected to two clock signals. The pulse start time of the second start signal SIN2 overlaps with a voltage transition edge of one of the clock signals connected to the second scanning circuit. For example, the pulse start time of the second start signal SIN2 overlaps with a voltage falling edge of the third clock signal CK3.

[0100] Then, when adjusting the corresponding timing of the clock signal, the start signal must also be adjusted in timing with the clock signal to ensure that the timing relationship between the start signal and the corresponding clock signal remains unchanged. Figure 2 In the related art, there is a dead time t1 between the voltage rising edge of the second clock signal CK2 and the voltage falling edge adjacent to the voltage rising edge in the first clock signal CK1, for example, 1.9 us. In one embodiment, when the clock signal is adjusted to Figure 5 When the timing relationship is shown, the first clock signal CK1, the second clock signal CK2 and the first start signal SIN1 can be shifted forward by a dead time t1, that is, by 1.9us. The above offset method is only used as an example and is not intended to limit the present invention. In practical applications, the optimal shift amount can be selected for optimization according to the performance of different screens and driver chips.

[0101] On the basis of the above-mentioned embodiments, optionally, considering the working characteristics of the first initialization transistor M4 and the threshold compensation transistor M3, the pulse widths of the first start signal SIN1 and the second start signal SIN2 can be appropriately adjusted, that is, the pulse widths of the first scan signal S1 and the second scan signal S2 are adjusted to reduce the characteristic differences between the first initialization transistor M4 and the threshold compensation transistor M3 at different refresh frequencies, and reduce the brightness differences between different display partitions.

[0102] First, the characteristics of the transistor are briefly described below by taking the threshold compensation transistor M3 as an N-type transistor as an example: when the partition multi-frequency function is turned on, the different display partitions will have different brightness due to the different characteristic offsets of the threshold compensation transistor M3 at different refresh rates. Specifically, at a high refresh rate, such as 120Hz, the transistor is in a positive bias (PBS) / negative bias (NBS) cycle state; at a low refresh rate, such as 1Hz, the transistor is in a long-term NBS state. In the PBS state, the gate of the transistor has a positive voltage of about 6V, causing the electrons in the film to be attracted close to the interface between the active layer and the gate insulating layer, thereby being captured by the defects at the interface, causing the transfer characteristic curve of the device to move toward the positive value of Vgs (gate-source voltage difference). In the NBS state, the holes in the film are attracted close to the interface and captured by the defects at the interface, causing the device characteristics to drift toward the negative value of Vgs.

[0103] Among them, under high refresh frequency, the threshold compensation transistor M3 is turned on for a long time, and the PBS effect causes the voltage stress (stress) level of the high refresh frequency display partition to be higher than that of the low refresh frequency display partition, resulting in a positive bias in the threshold voltage Vth of the threshold compensation transistor M3, which weakens the degree of coupling of the gate of the threshold compensation transistor M3 from high voltage to low voltage to the gate of the driving transistor M1, resulting in a darker display partition at high refresh frequency. On the other hand, under low refresh frequency, the threshold compensation transistor M3 is turned off for a long time and is in the NBS effect, resulting in a higher stress level of the low refresh frequency display partition than that of the high refresh frequency display partition, resulting in a negative bias in the threshold voltage Vth of the threshold compensation transistor M3, which weakens the degree of coupling of the gate of the threshold compensation transistor M3 from low voltage to high voltage to the gate of the driving transistor M1, resulting in a brighter display partition at low refresh frequency.

[0104] In order to optimize the difference in characteristic offset of the threshold compensation transistor M3 in display partitions with different refresh frequencies, the timing corresponding to the first initialization transistor M4 / threshold compensation transistor M3 can be adjusted to reduce the high-level pulse width of the first start signal SIN1 / second start signal SIN2, thereby reducing the PBS time of the transistor in the high refresh frequency display partition as a whole, thereby reducing the threshold voltage offset caused by the PBS / NBS difference, resulting in the brightness difference problem of different display partitions under multi-frequency refresh of the partitions.

[0105] Specifically, the pulse width of the first start signal SIN1 is: L1∈[2H, 10H], where L1 is the pulse width of the first start signal, and H is the line time.

[0106] The display panel also includes a plurality of light-emitting devices arranged in an array, and each pixel circuit is connected to each light-emitting device in a one-to-one correspondence; each pixel circuit connected to each k-row light-emitting device is connected to the same second scanning signal; k is a positive integer; the pulse width of the second start signal SIN2 satisfies: L2 ≥ k * (L1 + H), so as to meet the driving timing requirements of the k-row gate initialization phase and the data writing phase. Wherein, L2 is the pulse width of the second start signal. Exemplarily, in the case where a set of driving groups includes eight second shift registers and drives 16 rows of pixel circuits, L2 ≥ 18H can be set to avoid the appearance of periodic horizontal stripes across the entire screen.

[0107] Specifically, k = 2, L1 = 10H, L2 = 22H can be set, then the waveform correspondence of each scanning signal in the refresh frame can be seen in Fig. 9 More preferably, L1=2H, L2=18H can be set, then the waveform correspondence of each scanning signal in the refresh frame can be seen in Fig.13By reducing the pulse width of the two start signals, the PBS difference between the threshold compensation transistor M3 and the first initialization transistor M4 at high refresh frequency and low refresh frequency can be effectively reduced, thereby alleviating the problem of distinguishing brightness differences between different display partitions under multi-frequency refresh.

[0108] The embodiment of the present invention further provides a driving device for a display panel, which is used to execute the driving method for a display panel provided by any embodiment of the present invention, and has corresponding beneficial effects. The driving device for the display panel includes: a time phase control module. The time phase control module is used to control the voltage jump edges in all clock signals connected to the first scanning circuit and the voltage jump edges in the same voltage jump direction in all clock signals connected to the second scanning circuit to not overlap in time when the display panel displays at least two display partitions with different refresh frequencies.

[0109] On the basis of the above-mentioned embodiments, optionally, the driving device of the display panel further includes: a partition multi-frequency control module, which is used to control at least part of the partition enable signals to be signals in which the first voltage and the second voltage alternately appear when the display panel needs to display in at least two display partitions with different refresh frequencies, so that the frequencies of the second scanning signals received by at least two display partitions are different; wherein the refresh frequency of any display partition is the frequency of the second scanning signal received by the display partition; the first voltage of each clock signal and each partition enable signal is provided by the same power supply, and the second voltage of each clock signal and each partition enable signal is provided by the same power supply.

[0110] Based on the above embodiments, optionally, the time phase control module is also used to: control at least part of the voltage jump edges in at least part of the clock signal connected to the first scanning circuit, and at least part of the voltage jump edges in the opposite direction of the voltage jump in at least part of the clock signal connected to the second scanning circuit, so that they overlap in time.

[0111] Based on the above embodiments, optionally, the time phase control module is specifically used to: control at least part of the voltage rising edge of at least one clock signal connected to the first scanning circuit to overlap in time with at least part of the voltage falling edge of at least one clock signal connected to the second scanning circuit; or, control at least part of the voltage falling edge of at least one clock signal connected to the first scanning circuit to overlap in time with at least part of the voltage rising edge of at least one clock signal connected to the second scanning circuit.

[0112] Based on the above embodiments, optionally, the time phase control module is also used to: control the voltage transition edges in all clock signals connected to the first scanning circuit, so that the voltage transition edges in the opposite direction of the voltage transition in all clock signals connected to the second scanning circuit do not overlap in time.

[0113] Based on the above embodiments, optionally, the driving device of the display panel also includes: a pulse width control module, which is used to control the pulse width of the first start signal to be smaller than the pulse width of the second start signal; and control each pulse of the second start signal to temporally cover each pulse of the first start signal.

[0114] Based on the above embodiments, optionally, the pulse width control module is also used to: control the pulse width of the third start signal to be one line time; control the start time of the first pulse of the third start signal to be later than or simultaneous with the end time of the first pulse of the first start signal; and control each pulse of the second start signal to temporally overlap each pulse of the first start signal and each pulse of the third start signal.

[0115] An embodiment of the present invention further provides a display device, which can apply the display panel driving method provided by any embodiment of the present invention to drive the display panel, and has corresponding beneficial effects. Fig.14 is a schematic diagram of the structure of a display device provided by an embodiment of the present invention. Fig.14 The display device includes: a display panel 100 and a driving chip 200, wherein the driving chip 200 is used to execute the driving method of the display panel. Exemplarily, the driving device of the display panel provided in any embodiment of the present invention can be integrated into the driving chip 200.

[0116] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0117] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for driving a display panel, characterized in that: The display panel comprises: a first scanning circuit, a second scanning circuit and a plurality of pixel circuits; the first scanning circuit and the second scanning circuit are connected to different clock signals, and the second scanning circuit is also connected to a partition enable signal; the voltages of the clock signals and the partition enable signal are provided by the same power supply; the first scanning circuit is used to provide a first scanning signal to each pixel circuit, and the second scanning circuit is used to control the frequency of a second scanning signal provided to each pixel circuit according to the partition enable signal; The driving method of the display panel includes: When the display panel displays in at least two display partitions with different refresh frequencies, the voltage jump edges in all clock signals connected to the first scanning circuit are controlled to not overlap in time with the voltage jump edges with the same voltage jump direction in all clock signals connected to the second scanning circuit.

2. The method for driving a display panel according to claim 1, wherein: Each of the clock signals is a pulse signal in which the first voltage and the second voltage appear alternately; The second scanning circuit is connected to at least one of the partition enable signals; The display panel driving method further includes: In the case where the display panel needs to display in at least two display partitions with different refresh frequencies, at least part of the partition enable signals are controlled to be signals in which the first voltage and the second voltage appear alternately, so that the frequencies of the second scanning signals received by at least two of the display partitions are different; wherein the refresh frequency of any of the display partitions is the frequency of the second scanning signal received by the display partition; the first voltages of the clock signals and the partition enable signals are provided by the same power supply, and the second voltages of the clock signals and the partition enable signals are provided by the same power supply; Preferably, the display panel further comprises a plurality of light-emitting devices arranged in an array, and each of the pixel circuits is connected to each of the light-emitting devices in a one-to-one correspondence; the second scanning circuit comprises a plurality of second shift registers connected in cascade, each of the second shift registers is connected to a corresponding partition enable signal, and one of the second shift registers provides the second scanning signal to each of the pixel circuits connected to at least one row of the light-emitting devices; For any pixel circuit, in the gate initialization phase and the data writing phase of any display frame, the second shift register controls the voltage of the second scanning signal output to be equal to the voltage of the connected partition enable signal.

3. The method for driving a display panel according to claim 1 or 2, characterized in that: Also includes: Control at least part of the voltage transition edges in at least part of the clock signal connected to the first scanning circuit to overlap in time with at least part of the voltage transition edges in the opposite direction of the voltage transition in at least part of the clock signal connected to the second scanning circuit.

4. The method for driving a display panel according to claim 3, wherein: Controlling at least part of the voltage transition edges in at least part of the clock signal connected to the first scanning circuit to overlap in time with at least part of the voltage transition edges in the opposite direction of the voltage transition of at least part of the clock signal connected to the second scanning circuit, including: Controlling at least part of the voltage rising edge of at least one clock signal connected to the first scanning circuit to overlap in time with at least part of the voltage falling edge of at least one clock signal connected to the second scanning circuit; or, Controlling at least part of the voltage falling edge of at least one clock signal connected to the first scanning circuit to overlap in time with at least part of the voltage rising edge of at least one clock signal connected to the second scanning circuit; Preferably, the frequencies and pulse widths of all clock signals connected to the first scanning circuit and the second scanning circuit are the same.

5. The method for driving a display panel according to claim 1 or 2, characterized in that: Also includes: The voltage transition edges in all the clock signals connected to the first scanning circuit are controlled to not overlap in time with the voltage transition edges in the opposite direction of the voltage transition in all the clock signals connected to the second scanning circuit.

6. The method for driving a display panel according to claim 1 or 2, characterized in that: The pixel circuit comprises: a driving transistor, a threshold compensation transistor and a first initialization transistor; the threshold compensation transistor is connected between the gate electrode and the second electrode of the driving transistor, and the first initialization transistor is connected to the second electrode of the driving transistor; The first scanning circuit is used to provide the first scanning signal to the gate of each of the first initialization transistors, and the second scanning circuit is used to provide the second scanning signal to the gate of each of the threshold compensation transistors; Preferably, the threshold compensation transistor and the first initialization transistor have the same channel type; Preferably, the first scanning circuit is further connected to a first start signal, and the first scanning circuit is used to generate each first scanning signal according to the first start signal and the connected clock signal; the second scanning circuit is further connected to a second start signal, and the second scanning circuit is used to generate each second scanning signal according to the second start signal, the partition enable signal and the connected clock signal; the first start signal and the second start signal have the same frequency and different pulse widths; The display panel driving method further includes: Controlling the pulse width of the first start signal to be smaller than the pulse width of the second start signal; and controlling each pulse of the second start signal to temporally cover each pulse of the first start signal; Preferably, the pixel circuit further includes a data writing transistor, the data writing transistor is connected to the first electrode of the driving transistor; the display panel further includes a third scanning circuit, the third scanning circuit is connected to a third starting signal, and the third scanning circuit is used to provide a third scanning signal to the gate of the data writing transistor in each pixel circuit according to the third starting signal; wherein the frequency of the third starting signal is the same as that of the first starting signal; The display panel driving method further includes: Control the pulse width of the third start signal to be one line time; control the starting time of the first pulse of the third start signal to be later than or at the same time as the ending time of the first pulse of the first start signal; and control each pulse of the second start signal to temporally cover each pulse of the first start signal and each pulse of the third start signal; Preferably, the first scanning circuit is connected to the two clock signals; the pulse start time of the first start signal overlaps with a voltage transition edge of one of the clock signals connected to the first scanning circuit in time; The second scanning circuit is connected to the two clock signals; the pulse start time of the second start signal overlaps in time with a voltage transition edge of one of the clock signals connected to the second scanning circuit.

7. The method for driving a display panel according to claim 6, wherein: The pulse width of the first start signal is: L1∈[2H, 10H], where L1 is the pulse width of the first start signal and H is the line time.

8. The method for driving a display panel according to claim 7, wherein: The display panel further includes a plurality of light emitting devices arranged in an array, each of the pixel circuits is connected to each of the light emitting devices in a one-to-one correspondence; each of the pixel circuits connected to each of the light emitting devices in every k rows is connected to the same second scanning signal; k is a positive integer; The pulse width of the second start signal satisfies: L2≥k*(L1+H); wherein L2 is the pulse width of the second start signal; Preferably, L2≥18H; Preferably, k=2, L1=2H, L2=18H.

9. A driving device for a display panel, characterized in that: include: A time phase control module is used to control the voltage jump edges in all clock signals connected to the first scanning circuit when the display panel displays in at least two display partitions with different refresh frequencies, so that the voltage jump edges with the same voltage jump direction in all clock signals connected to the second scanning circuit do not overlap in time.

10. A display device, characterized in that: include: A display panel and a driving chip, wherein the driving chip is used to execute the display panel driving method described in any one of claims 1 to 8.

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