Display device

Abstract

A display device may include: a display panel including a display area in which a plurality of pixels are disposed and a non-display area disposed around the display area; and a gate driver configured to receive a start signal and a clock signal and supply a gate signal to the display panel, in which each of the plurality of pixels may include at least one first transistor and at least one second transistor, the gate driver may include at least one first transistor and at least one second transistor having a characteristic different from a characteristic of the at least one first transistor, where the gate driver may include at least one third transistor and at least one fourth transistor having a characteristic different from a characteristic of the at least one third transistor.

Description

Technical Field

[0001] The present disclosure relates to a display device, for example, and more particularly to a display device having improved stability and reliability of a gate signal output from a gate driver. Background Art

[0002] The display device uses gate lines, data lines and several power lines to drive pixels. The display device may include several driver circuits, for example, a gate driver to drive the gate lines, a data driver to drive the data lines and a power supply to drive the multiple power lines.

[0003] The gate driver can supply a gate signal to the gate line at a set timing, and can control the operation timing of the pixel connected to the gate line. The gate driver may include several circuit elements for outputting the gate signal. These circuit elements included in the gate driver may deteriorate as the operation time increases, especially when the gate driver operates for a long time in an environment with high temperature or high humidity. The degradation of these circuit elements included in the gate driver may cause the output of the gate signal to be abnormal.

[0004] Therefore, a solution is needed to improve the stability and reliability of the gate signal output from the gate driver.The description of the related art should not be considered as prior art merely because it is mentioned in or related to this section.

[0005] The description of related art should not be considered as prior art just because it is mentioned in this section or is related to this section. The description of related art includes information describing one or more aspects of the subject technology. The description in this section does not limit the present invention. Summary of the invention

[0006] One or more aspects of the present disclosure are to provide a display device in which degradation of circuit elements included in a gate driver is reduced, thereby improving stability and reliability of a gate signal output from the gate driver.

[0007] The aspects according to the present disclosure are not limited to the aspects mentioned above. Other aspects, objects and advantages according to the present disclosure that are not mentioned can be understood based on the following description, and can be more clearly understood based on the embodiments according to the present disclosure. In addition, it will be easily understood that the means shown in the claims and their combinations can be used to achieve the aspects, objects and advantages according to the present disclosure.

[0008] In order to achieve one or more of the above aspects, a display device according to one or more exemplary embodiments of the present disclosure may include: a display panel including a display area in which a plurality of pixels are arranged and a non-display area arranged around the display area; and a gate driver configured to receive a start signal and a clock signal and supply a gate signal to the display panel, wherein each of the plurality of pixels includes at least one first transistor and at least one second transistor, the at least one second transistor having characteristics different from those of the at least one first transistor, and wherein the gate driver includes at least one third transistor and at least one fourth transistor, the at least one fourth transistor having characteristics different from those of the at least one third transistor.

[0009] In a display device according to one or more exemplary embodiments of the present disclosure, the gate driver having an oxide semiconductor layer susceptible to degradation caused by threshold voltage shift can be repeatedly turned on and off, thereby preventing screen defects that may occur in a high temperature and high humidity environment and ensuring its stable operation.

[0010] The effects of the present disclosure are not limited to the effects mentioned above, and those skilled in the art will clearly understand other unmentioned effects from the following description. In addition to the above effects, while describing the specific details for performing the present disclosure, the specific effects of the present disclosure are described together.

[0011] Other features, advantages and aspects of the present disclosure are set forth in part in the description below, and some will become apparent from the present disclosure, or may be learned by practicing the inventive concepts provided herein. Other features, advantages and aspects of the present disclosure may be realized and achieved by the description provided in the present disclosure, or the description derived therefrom, its claims and the accompanying drawings. All of these features, advantages and aspects are included in this specification, belong to the scope of the present disclosure, and are protected by the appended claims. Nothing in this section shall be construed as a limitation on these claims. More aspects and advantages will be discussed below in conjunction with the embodiments of the present disclosure.

[0012] It should be understood that the above description and the following description of the present disclosure are exemplary, and are intended to provide further explanation of the present disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings are intended to provide further understanding of the present disclosure, and are incorporated in and constitute a part of the present disclosure. The accompanying drawings illustrate various aspects and embodiments of the present disclosure, and together with the description, are used to explain the principles and examples of the present disclosure.

[0014] Figure 1 is a block diagram schematically illustrating a display device according to an exemplary embodiment of the present disclosure.

[0015] Figure 2 is a cross-sectional view illustrating a stack structure of a display device according to an exemplary embodiment of the present disclosure.

[0016] Figure 3 is a diagram of a pixel circuit in a display device according to an exemplary embodiment of the present disclosure.

[0017] Figure 4 It shows that Figure 3 0 is an example of a diagram of scan signals and light emission control signals applied in a refresh period and a hold period in a pixel circuit shown in .

[0018] Figure 5 is a diagram of a configuration of a gate driver in a display device according to an exemplary embodiment of the present disclosure.

[0019] Fig. 6A is a diagram showing a configuration of a shift register of a gate driver according to an exemplary embodiment of the present disclosure, and Figure 6B Shows Fig. 6A An example of a driver circuit for a shift register in FIG.

[0020] Fig. 7A is a diagram showing a configuration of a shift register of another gate driver according to an exemplary embodiment of the present disclosure, Figure 7B Shows Fig. 7A An example of a shift register driver circuit in which Figure 7C Yes Figure 7B An example of an operation waveform diagram of a driver circuit is shown in FIG.

[0021] Fig. 8A An example of a driver circuit of a shift register of another gate driver according to an exemplary embodiment of the present disclosure is shown, and Figure 8B Yes Fig. 8A An example of an operating waveform diagram of a driver circuit is shown.

[0022] Throughout the drawings and detailed description, unless otherwise specified, the same drawing reference numerals should be understood to refer to the same elements, features, and structures. The sizes, lengths, and thicknesses of layers, regions, and elements and their descriptions may be exaggerated for clarity, illustration, and / or convenience. DETAILED DESCRIPTION

[0023] The advantages and features of the present disclosure and the methods for achieving the advantages and features will become apparent with reference to the embodiments described in detail below in conjunction with the accompanying drawings. However, the present disclosure is not limited to the embodiments disclosed below, but may be implemented in various different forms. Therefore, these embodiments are set forth only to complete the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art to which the present disclosure belongs, and the present disclosure is limited only by the scope of the claims.

[0024] For the sake of simplicity and clarity of illustration, the elements in the figures are not necessarily drawn to scale. The same reference numerals in different figures represent the same or similar elements and thus perform similar functions. In addition, for the sake of simplicity of description, the description and details of known steps and elements are omitted. In addition, many specific details are set forth in the detailed description of the present disclosure below to provide a thorough understanding of the present invention. However, it should be understood that the present disclosure can be practiced without these specific details. In other cases, known methods, processes, components and circuits are not described in detail to avoid unnecessary ambiguity in various aspects of the present disclosure. Examples of various embodiments are further illustrated and described below. It will be understood that the description herein is not intended to limit the claims to the specific embodiments described. On the contrary, it is intended to cover alternatives, modifications and equivalents that may be included in the essence and scope of the present disclosure defined by the appended claims.

[0025] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for illustrating the embodiments of the present disclosure are merely illustrative, and the embodiments of the present disclosure are not limited thereto.

[0026] The terms used herein are only to achieve the purpose of describing specific embodiments, and are not intended to limit the present disclosure. As used herein, the singular forms of "one" and "a" are intended to include plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the words "include", "comprise", "have" and "contain" when used in this specification specify the existence of stated features, integers, operations, elements and / or parts, but do not exclude the existence or addition of one or more other features, integers, operations, elements, parts and / or parts thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated enumeration items. The expression of "at least one of..." can modify the entire element enumeration when modifying the enumeration of elements, and may not modify the individual elements in the enumeration. When explaining numerical values, there may be errors or tolerances, even if this is not clearly described.

[0027] In addition, it should be understood that when a first element or layer is referred to as being present "on" a second element or layer, the first element may be directly disposed on the second element, or may be indirectly disposed on the second element, in which case a third element or layer is disposed between the first and second elements or layers. It should be understood that when an element or layer is referred to as being "connected to" or "coupled to" another element or layer, the element or layer may be directly located on, directly connected to, or directly coupled to, the other element or layer, or one or more intervening elements or layers may be present. In addition, it should be understood that when an element or layer is referred to as being "between" two elements or layers, only the element or layer may be located between the two elements or layers, or one or more intervening elements or layers may also be present.

[0028] In addition, as used herein, when a layer, film, region, plate, etc. is disposed "on" or "on top of" another layer, film, region, plate, etc., the former may directly contact the latter or another layer, film, region, plate, etc. may be disposed between the former and the latter. As used herein, when a layer, film, region, plate, etc. is disposed directly "on" or "on top of" another layer, film, region, plate, etc., the former directly contacts the latter, and another layer, film, region, plate, etc. is not disposed between the former and the latter. In addition, as used herein, when a layer, film, region, plate, etc. is disposed "below" or "under" another layer, film, region, plate, etc., the former may directly contact the latter or another layer, film, region, plate, etc. may be disposed between the former and the latter. As used herein, when a layer, film, region, plate, etc. is disposed directly "below" or "under" another layer, film, region, plate, etc., the former directly contacts the latter, and another layer, film, region, plate, etc. is not disposed between the former and the latter.

[0029] In descriptions of a temporal relationship, for example, the temporal sequence between two events, such as "after", "following", "before", etc., another event may occur between the two events, unless it is specified as "directly after", "directly following" or "directly before".

[0030] When a particular embodiment can be implemented in different ways, the functions or operations specified in a particular block may occur in a different order than the order specified in the flow chart. For example, two consecutive blocks may actually be executed substantially simultaneously, or two blocks may be executed in reverse order, depending on the functions or operations involved.

[0031] It should be understood that although the words "first", "second", "third" and the like may be used herein to describe various elements, components, transistors, nodes, regions, layers and / or cycles, these elements, components, transistors, nodes, regions, layers and / or cycles should not be limited by these words. These words are only used to distinguish one element, component, transistor, node, region, layer or cycle from another element, component, region, layer or cycle. Thus, the first element, component, transistor, node, region, layer or cycle described below may be referred to as a second element, component, transistor, node, region, layer or cycle without departing from the essence and scope of the present disclosure.

[0032] The features of various embodiments of the present disclosure may be partially or completely combined with each other, and may be technically related to each other or may interoperate with each other. The embodiments may be implemented independently of each other, and may be implemented together in an associated relationship.

[0033] When interpreting numerical values, the values ​​are interpreted as including a certain error range unless expressly stated otherwise.

[0034] Unless otherwise defined, all terms (including technical terms) used herein have the same meaning as commonly understood by ordinary technicians in the field to which the principles of the present invention belong. It will also be understood that terms, such as those defined in general dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless explicitly defined in this article.

[0035] As used herein, "embodiment," "example," "aspect," etc. should not be construed as implying that any aspect or design described is superior or advantageous over other aspects or designs.

[0036] Additionally, the term "or" means an inclusive or rather than an exclusive or. That is, unless specified otherwise, or clear from the context, the phrase "x employs a or b" means any of the natural inclusive permutations.

[0037] The terms used in the following description are selected to be general and common in the relevant technical field. However, there may be other terms other than the above terms according to the development and / or change of technology, convention, preference of technicians, etc. Therefore, the terms used in the following description should not be understood as limiting the technical creativity, but should be understood as terminology examples for illustrating the embodiments.

[0038] In addition, in specific cases, the terms may be arbitrarily selected by the applicant, in which case their detailed meanings will be described in the corresponding description period. Therefore, the terms used in the following description should not be simply understood based on the names of the terms, but based on the meanings of the terms and the content of the entire detailed description section.

[0039] In the description of a signal flow, for example, when a signal is transmitted from node A to node B, a case where the signal is transmitted from node A to node B via another node may be included unless the phrase “immediately transmitted” or “directly transmitted” is used.

[0040] Hereinafter, a display device according to some embodiments will be described.

[0041] Figure 1 is a block diagram schematically illustrating a display device according to an exemplary embodiment of the present disclosure.

[0042] refer to Figure 1 The display device 10 includes a display panel 100 having a plurality of pixels P, a controller 200, a gate driver 300 for supplying a gate signal to each of the plurality of pixels P, a data driver 400 for supplying a data signal to each of the plurality of pixels P, and a power supply 500 for supplying power required for operation to each of the plurality of pixels P.

[0043] The display panel 100 includes a display area (AA, see Figure 2 ) and the non-display area (NA, see Figure 2 ). The gate driver 300 and the data driver 400 are disposed in the non-display area NA.

[0044] In the display panel 100, a plurality of gate lines GL and a plurality of data lines DL intersect each other, and each of the plurality of pixels P is connected to the gate line GL and the data line DL. Specifically, one pixel P receives a gate signal from a gate driver 300 via the gate line GL, receives a data signal from a data driver 400 via the data line DL, and receives a high potential driving voltage EVDD and a low potential driving voltage EVSS from a power source 500 via a driving power line PL.

[0045] In this regard, the gate line GL supplies a scan signal SC and a light emission control signal EM to the pixel, and the data line DL supplies a data voltage Vdata to the pixel. In addition, according to various embodiments, the gate line GL may include a plurality of scan lines SCL supplying the scan signal SC, and a light emission control signal line EML supplying the light emission control signal EM. In addition, the plurality of pixels P may additionally include at least one power line VL and may receive a bias voltage Vobs and initialization voltages Vini and Var via the at least one power line VL.

[0046] In addition, if Figure 2 As shown in FIG. 1 , each pixel P includes a light emitting element EL and a pixel circuit that controls the operation of the light emitting element EL. In this regard, the light emitting element EL is composed of an anode electrode 171 , a cathode electrode 173 , and a light emitting layer 172 located between the anode electrode 171 and the cathode electrode 173 .

[0047] The pixel circuit includes a plurality of switching elements, a driving element, and a capacitor. In this regard, each of the switching element and the driving element may be embodied as a thin film transistor. In the pixel circuit, the driving element controls the amount of current supplied to the light emitting element EL based on the data voltage to adjust the amount of light emitted from the light emitting element EL. In addition, the plurality of switching elements receive a scanning signal SC supplied via a plurality of scanning lines SCL and a light emitting control signal EM supplied via a light emitting control line EML, and operate the pixel circuit based on the scanning signal SC and the light emitting control signal EM.

[0048] The display panel 100 may be embodied as a non-transmissive display panel or a transmissive display panel. The transmissive display panel may be applied to a transparent display device, wherein an image is displayed on a screen and actual objects in the background are visible to a viewer in front of the display device. The display panel 100 may be manufactured as a flexible display panel. The flexible display panel may be embodied as an OLED panel using a plastic substrate.

[0049] The pixel P may include a red pixel, a green pixel, and a blue pixel to emit light of corresponding colors. The pixel P may further include a white pixel. Each of the pixels P includes a pixel circuit.

[0050] The touch sensor may be provided on the display panel 100. A separate touch sensor may be used to sense the touch input, or the touch input may be sensed by the pixel P. The touch sensor may be provided on the screen of the display panel as an on-cell type or an add-on type, or may be embodied as an in-cell type touch sensor built into the display panel 100.

[0051] The controller 200 processes the image data RGB from an external source (e.g., a host system) to adapt it to the size and resolution of the display panel 100, and supplies the processed image data to the data driver 400. The controller 200 generates a gate control signal GCS and a data control signal DCS based on synchronization signals (e.g., a clock signal CLK, a data enable signal DE, a horizontal synchronization signal Hsync, and a vertical synchronization signal Vsync input from an external source), and supplies the generated gate control signal GCS and data control signal DCS to the gate driver 300 and the data driver 400, respectively, thereby controlling the gate driver 300 and the data driver 400.

[0052] The controller 200 may be configured to be coupled to a processor, such as a microprocessor, a mobile processor, an application processor, etc., depending on the type of device in which the controller is installed.

[0053] The host system may be any of a television (TV) system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a mobile device, a wearable device, and a vehicle system.

[0054] The controller 200 multiplies the input frame rate by i, and controls the operation timing of each of the gate driver 300 and the data driver 400 using frame rate=input frame rate×i (i is a positive integer greater than 0) Hz. The input frame rate is 60 Hz in the National Television Standards Committee (NTSC) scheme and 50 Hz in the Phase Alternation Line (PAL) scheme.

[0055] The controller 200 generates a signal that causes the pixel to operate at various refresh rates. That is, the controller 200 generates an operation-related signal so that the pixel can operate in a variable refresh rate (VRR) mode, or its refresh rate can be switched between a first refresh rate and a second refresh rate. For example, the controller 200 can simply change the rate of the clock signal, can generate a synchronization signal to generate a horizontal blank or a vertical blank, or can operate the gate driver 300 in a masking manner so that the pixel P can operate at various refresh rates.

[0056] The controller 200 generates a gate control signal GSC for controlling the operation timing of the gate driver 300 and a data control signal DSC for controlling the operation timing of the data driver 400 based on the timing signals Vsync, Hsync, and DE received from the host system. The controller 200 controls the operation timings of the gate driver 300 and the data driver 400 so that the gate driver 300 and the data driver 400 are synchronized with each other.

[0057] The level shifter (not shown) converts the voltage level of the gate control signal GSC output from the controller 200 into gate low voltages VGL, VEL and gate high voltages VGH, VEH, which are in turn supplied to the gate driver 300 via the driving power line PL. The level shifter converts the low level voltage of the gate control signal GSC into the gate low voltage VGL, and converts the high level voltage of the gate control signal GSC into the gate high voltage VGH. The gate control signal GSC includes a start pulse and a shift clock.

[0058] The gate driver 300 supplies the scan signal SC to the gate line GL according to the gate control signal GCS supplied from the controller 200. The gate driver 300 may be disposed on one or each of two opposite sides of the display panel 100 in a GIP (gate in panel) manner.

[0059] The gate driver 300 sequentially outputs gate signals to the plurality of gate lines GL under the control of the controller 200. The gate driver 300 may shift the gate signals using a shift register and sequentially supply the shifted gate signals to the gate lines GL.

[0060] In an organic light-emitting display device, a gate signal may include a scan signal SC and a light-emitting control signal EM. The scan signal SC includes a scan pulse swinging between a gate-on voltage VGL and a gate-off voltage VGH. The light-emitting control signal may include a light-emitting control signal pulse swinging between a gate-on voltage VEL and a gate-off voltage VEH.

[0061] The scan pulse is synchronized with the data voltage Vdata to select pixels of one line where data is to be written. The light emission control signal defines the light emission time of each pixel.

[0062] The gate driver 300 may include a light emission control driver 310 and at least one scan driver 320 .

[0063] The light emission control driver 310 outputs a light emission control signal pulse in response to a start pulse and a shift clock received from the controller 200 , and sequentially shifts the light emission control signal pulse according to the shift clock.

[0064] Each of the at least one scan driver 320 outputs a scan pulse in response to a start pulse and a shift clock received from the controller 200, and shifts the scan pulse according to the shift clock timing.

[0065] The data driver 400 converts the image data RGB into the data voltage Vdata according to the data control signal DCS supplied from the controller 200 , and supplies the converted data voltage Vdata to the pixels P through the data lines DL.

[0066] exist Figure 1 , it is shown that one data driver 400 is provided to one side of the display panel 100. However, the number and position of the data driver 400 are not limited thereto.

[0067] That is, the data driver 400 may be embodied as a plurality of integrated circuits (ICs), which may be provided on one side of the display panel 100 and may be separately arranged along the one side.

[0068] The power supply 500 uses a DC-DC converter to generate direct current (DC) power required for operating the pixel array of the display panel 100 and the display panel driving circuit including the gate driver 300 and the data driver 400. The DC-DC converter may include a charge pump, a voltage regulator, a buck converter, a boost converter, etc. The power supply 500 receives a DC input voltage applied by a host system (not shown) and generates a DC voltage, for example, a gate-on voltage VGL and VEL, a gate-off voltage VGH and VEH, a high potential driving voltage EVDD, a low potential driving voltage EVSS, etc. The gate-on voltage VGL and VEL and the gate-off voltage VGH and VEH are supplied to a level shifter (not shown) and the gate driver 300. Each of the high potential driving voltage EVDD and the low potential driving voltage EVSS is commonly supplied to the pixel.

[0069] In addition, reference Figure 1 , at least one optical area OA1 and OA2 may be disposed in the display area AA.

[0070] The at least one optical area OA1 and OA2 may be positioned to overlap with at least one optical electronic device, for example, the optical electronic device may be a capture device such as a camera (image sensor) and a detection sensor such as a proximity sensor and a brightness sensor.

[0071] For the operation of the optical electronic device, the at least one optical area OA1 and OA2 may have a light-transmitting structure and thus may have a transmittance equal to or greater than a predefined value. In other words, the number of pixels P per unit area in the at least one optical area OA1 and OA2 may be smaller than the number of pixels P per unit area in the general area of ​​the display area AA except for the at least one optical area OA1 and OA2. That is, the resolution of the at least one optical area OA1 and OA2 may be lower than the resolution of the general area of ​​the display area AA.

[0072] The light transmission structure of the at least one optical area OA1 and OA2 may be formed by patterning the cathode electrode in the area where the pixel P is not provided. At this time, a portion of the cathode electrode to be patterned may be removed by laser. Alternatively, the cathode electrode may be selectively formed by using a material such as a cathode deposition preventing layer so as to pattern it.

[0073] Alternatively, the light-transmitting structure of the at least one optical area OA1 and OA2 may be formed by separately forming the light-emitting element EL and the pixel circuit in the pixel P. In other words, the light-emitting element EL of the pixel P may be positioned on the at least one optical area OA1 and OA2, and a plurality of transistors TFT constituting the pixel circuit may be disposed around the at least one optical area OA1 and OA2, and the light-emitting element EL and the pixel circuit may be electrically connected to each other via a transparent metal layer.

[0074] Figure 2 is a cross-sectional view illustrating a stack structure of a display device according to an exemplary embodiment of the present disclosure.

[0075] refer to Figure 2 , the display panel 100 includes a display area AA where the pixels P are located and a non-display area NA surrounding the display area AA. The gate driver 300 and the data driver 400 are disposed in the non-display area NA.

[0076] The display panel 100 according to an exemplary embodiment of the present disclosure includes a substrate 101 , thin film transistors TFT1 and TFT2 , a bank layer 165 , a light emitting element EL, an encapsulation layer 180 , a touch layer 190 , a touch protection film 197 , a dam DAM, and a pad 198 .

[0077] The thin film transistor TFT1 may be disposed on the substrate 101. The thin film transistor TFT1 drives the light emitting element EL of the display area AA.

[0078] The substrate 101 supports various components of the display panel 100. The substrate 101 may be made of a transparent insulating material such as glass or plastic. When the substrate 101 is made of plastic, the substrate may be referred to as a plastic film or a plastic substrate. For example, the substrate 101 may have a film form including one of a polyimide-based polymer, a polyester-based polymer, a silicone-based polymer, an acrylic-based polymer, a polyolefin-based polymer, and a copolymer thereof. However, the embodiments of the present disclosure are not limited thereto.

[0079] The thin film transistor TFT1 may include a semiconductor layer 115, a gate electrode 125, and a source electrode / drain electrode 140. The thin film transistor TFT1 is a driving transistor ( Figure 4T1 in ). The semiconductor layer 115 may be composed of polycrystalline silicon (p-Si). In this case, a predetermined region thereof may be doped with impurities. In addition, the semiconductor layer 115 may be made of amorphous silicon (a-Si) or various organic semiconductor materials (e.g., pentacene). The semiconductor layer 115 may be made of an oxide. The embodiments of the present disclosure are not limited by the material constituting the semiconductor layer 115. The semiconductor layer 115 may be an active layer. However, the embodiments of the present disclosure are not limited thereto.

[0080] The gate electrode 125 may be disposed on the top of the semiconductor layer 115. The gate electrode 125 may be made of various conductive materials, for example, magnesium (Mg), aluminum (Al), nickel (Ni), chromium (Cr), molybdenum (Mo), tungsten (W), gold (Au), or alloys thereof, etc. However, the embodiments of the present disclosure are not limited thereto.

[0081] The gate insulating layer may be disposed between the semiconductor layer 115 and the gate electrode 125. The gate insulating layer may be a layer that insulates the semiconductor layer 115 and the gate electrode 125 from each other, and may be made of an insulating material. For example, the gate insulating layer may be composed of a single layer or a double layer, and the single layer or the double layer may be made of silicon oxide (SiOx) or silicon nitride (SiNx). However, the embodiments of the present disclosure are not limited thereto.

[0082] The source electrode / drain electrode 140 may be electrically connected to the semiconductor layer 115 and spaced apart from each other. The source electrode / drain electrode 140 may be disposed on the insulating layer. Each of the source electrode / drain electrode 140 may be made of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), or an alloy thereof. However, the embodiments of the present disclosure are not limited thereto.

[0083] The capacitor Cst may be disposed on the substrate 101. The capacitor Cst may include a first gate electrode 142 and a second gate electrode 144. The gate insulating layer 124 may be disposed between the first gate electrode 142 and the second gate electrode 144. At least one of the first gate electrode 142 and the second gate electrode 144 may be connected to an electrode of the thin film transistor TFT1. The capacitor Cst may be connected to the thin film transistor TFT1 via a connection electrode 157.

[0084] Another thin film transistor TFT2 may be disposed on the substrate 101. The thin film transistor TFT2 may include a semiconductor layer 116, a gate electrode 126, and a source electrode / drain electrode 112. The thin film transistor TFT2 may be one of the first to seventh transistors T1 to T7 ( Figure 4 The gate insulating layer 122 may be disposed between the semiconductor layer 116 and the gate electrode 126 .

[0085] An interlayer insulating layer 128 may be provided between the thin film transistor TFT1 and the capacitor Cst or between the thin film transistor TFT1 and another thin film transistor TFT2 .

[0086] For the sake of illustration, among various thin film transistors that may be included in the display device 10, only the thin film transistor TFT1 and the thin film transistor TFT2 are shown. However, other thin film transistors may be included in the display panel 100. In addition, an example in which the thin film transistors have a coplanar structure is described. However, the thin film transistors may be implemented to have other structures, for example, a staggered structure. The present disclosure is not limited thereto.

[0087] The thin film transistor TFT1 may receive a high potential driving voltage EVDD in response to a data voltage Vdata supplied to the gate electrode 125 of the thin film transistor TFT1 to control the amount of current supplied to the light emitting element EL, thereby adjusting the amount of light emitted from the light emitting element EL. The thin film transistor TFT1 may supply a constant current based on the voltage charged in the capacitor Cst, thereby maintaining the light emission of the light emitting element EL until the data voltage Vdata of the next frame is supplied thereto. The high potential supply line may extend in parallel with the data line.

[0088] The thin film transistor TFT1 may include a semiconductor layer 115 disposed on the interlayer insulating layer 128 , a gate electrode 125 overlapping the semiconductor layer 115 with the second insulating layer 120 interposed therebetween, and a source / drain electrode 140 formed on the third insulating layer 135 and contacting the semiconductor layer 115 .

[0089] The semiconductor layer 115 may serve as a region for forming a channel during the operation of the thin film transistor TFT1. The semiconductor layer 115 may be made of an oxide semiconductor, or may be made of various organic semiconductors such as amorphous silicon (a-Si), polycrystalline silicon (poly-Si) or pentacene. The present disclosure is not limited thereto. The semiconductor layer 115 may be formed on the interlayer insulating layer 128. The semiconductor layer 115 may include a channel region, a source region, and a drain region. The channel region may overlap with the gate electrode 125, and the second insulating layer 120 is interposed therebetween. The channel region may be formed between the source electrode / drain electrode 140. The source region may be electrically connected to the source electrode 140 via a contact hole extending through the second insulating layer 120 and the third insulating layer 135. The drain region may be electrically connected to the drain electrode 140 via a contact hole extending through the second insulating layer 120 and the third insulating layer 135.

[0090] The buffer layer 105 and the first insulating layer 110 may be disposed between the semiconductor layer 116 and the substrate 101. The buffer layer 105 may delay the intrusion of moisture or oxygen into the substrate 101. The first insulating layer 110 may protect the semiconductor layer 116 and may block various types of defects introduced from the substrate 101.

[0091] The uppermost layer of the buffer layer 105 in contact with the first insulating layer 110 may be made of a material having an etching characteristic different from that of each of the remaining layers of the buffer layer 105, the first insulating layer 110, the second insulating layer 120, and the third insulating layer 135. The uppermost layer of the buffer layer 105 in contact with the first insulating layer 110 may be made of silicon nitride (SiN x ) and silicon oxide (SiO x ). Each of the remaining layers of the buffer layer 105, the first insulating layer 110, the second insulating layer 120, and the third insulating layer 135 may be made of silicon nitride (SiN x ) and silicon oxide (SiO x ) is made of the other one of the above. For example, the uppermost layer of the buffer layer 105 in contact with the first insulating layer 110 may be made of silicon nitride (SiN x ), and each of the remaining layers of the buffer layer 105, the first insulating layer 110, the second insulating layer 120, and the third insulating layer 135 may be made of silicon oxide (SiO x The present disclosure is not limited thereto.

[0092] The gate electrode 125 may be formed on the second insulating layer 120 and may overlap the channel region of the semiconductor layer 115 with the second insulating layer 120 interposed therebetween. The gate electrode 125 may be made of a first conductive material and may be embodied as a single layer or multiple layers, the single layer or multiple layers being composed of magnesium (Mg), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or an alloy thereof. The present disclosure is not limited thereto.

[0093] The source electrode 140 may be connected to the exposed source region of the semiconductor layer 115 via a contact hole extending through the second insulating layer 120 and the third insulating layer 135. The drain electrode 140 may be opposite to the source electrode 140 and may be connected to the exposed drain region of the semiconductor layer 115 via a contact hole extending through the second insulating layer 120 and the third insulating layer 135. Each of the source electrode / drain electrode 140 may be made of a second conductive material and may be embodied as a single layer or multiple layers made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or an alloy thereof. The present disclosure is not limited thereto.

[0094] The connection electrode 155 may be disposed between the first intermediate layer 150 and the second intermediate layer 160. The connection electrode 155 may be connected to the drain electrode 140 via a connection electrode contact hole 156 extending through the protective film 145 and the first intermediate layer 150. The connection electrode 155 may be made of a material having a low resistivity that is equal to or similar to that of the drain electrode 140. The present disclosure is not limited thereto.

[0095] The reference voltage line VrefL may be a sub-power line branched from the reference voltage bus of the at least one power line VL, and may be disposed in the same layer as the layer of the source / drain electrode 140 of the thin film transistor TFT2. The embodiments of the present disclosure are not limited thereto, and the reference voltage line VrefL may be disposed on the interlayer insulating layer 128 or the second insulating layer 120.

[0096] The light emitting element EL including the light emitting layer 172 may be disposed on the second intermediate layer 160 and the bank layer 165. The light emitting element 170 may include an anode electrode 171, at least one light emitting layer 172 formed on the anode electrode 171, and a cathode electrode 173 formed on the light emitting layer 172.

[0097] The anode electrode 171 may be electrically connected to an exposed portion of the connection electrode 155 disposed on the first intermediate layer 150 and facing the second intermediate layer 160 via a contact hole extending through the second intermediate layer 160 .

[0098] The anode electrode 171 of each pixel is not covered by the bank layer 165. The bank layer 165 may be made of an opaque material (e.g., black) to prevent light interference between adjacent pixels. In this case, the bank layer 165 may include a light shielding material including at least one of a pigment, organic black, and carbon black. The present disclosure is not limited thereto.

[0099] At least one light-emitting layer 172 may be formed on a portion of the anode electrode 171 corresponding to the light-emitting region defined by the bank layer 165. The at least one light-emitting layer 172 may include a hole transport layer, a hole injection layer, a hole blocking layer, a light-emitting layer 172, an electron injection layer, an electron blocking layer, and an electron transport layer located on the anode electrode 171. The stacking order of the hole transport layer, the hole injection layer, the hole blocking layer, the light-emitting layer 172, the electron injection layer, the electron blocking layer, and the electron transport layer may be based on the light emission direction. In addition, the light-emitting layer 172 may include a first and a second light-emitting stack, which face each other, while the charge generation layer is interposed therebetween. In this case, the light-emitting layer 172 of one of the first and second light-emitting stacks may generate blue light, while the light-emitting layer 172 of the other of the first and second light-emitting stacks may generate yellow-green light, so that white light may be generated from the combination of the first and second light-emitting stacks. The white light generated from the combination of the first and second light-emitting stacks may be incident on a color filter located above or below the light-emitting layer 172, so that a color image may be realized. In another example, each light emitting layer 172 can generate each color light corresponding to each pixel without a separate color filter, so that a color image can be rendered. For example, the light emitting layer 172 of a red (R) pixel emits red light, the light emitting layer 172 of a green (G) pixel emits green light, and the light emitting layer 172 of a blue (B) pixel emits blue light.

[0100] The cathode electrode 173 may be formed to face the anode electrode 171 with the light emitting layer 172 disposed therebetween, and may receive a high potential driving voltage EVDD.

[0101] The encapsulation layer 180 can prevent external moisture or oxygen from penetrating into the light-emitting element EL that is susceptible to damage from external moisture or oxygen. To this end, the encapsulation layer 180 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. The present disclosure is not limited thereto. In the present disclosure, the structure of the encapsulation layer 180 in which the first encapsulation layer 181, the second encapsulation layer 182, and the third encapsulation layer 183 are sequentially stacked is described by way of example.

[0102] The first encapsulation layer 181 is formed on the substrate 101 on which the cathode electrode 173 has been formed. The third encapsulation layer 183 is formed on the substrate 101 on which the second encapsulation layer 182 has been formed. The third encapsulation layer 183 and the first encapsulation layer 181 may surround the top surface, the bottom surface, and the side surfaces of the second encapsulation layer 182. The first encapsulation layer 181 and the third encapsulation layer 183 may prevent external moisture or oxygen from penetrating into the light emitting element EL or minimize the penetration. Each of the first encapsulation layer 181 and the third encapsulation layer 183 may be made of an inorganic insulating material that can be deposited at low temperature, for example, the inorganic insulating material may be silicon nitride (SiN x), silicon oxide (SiO x ), silicon oxynitride (SiON) or aluminum oxide (Al2O3). Each of the first encapsulation layer 181 and the third encapsulation layer 183 is deposited in a low temperature atmosphere. Thus, during the deposition process of the first encapsulation layer 181 and the third encapsulation layer 183, the light emitting element EL that is susceptible to damage by a high temperature atmosphere can be prevented from being damaged.

[0103] The second encapsulation layer 182 acts as an impact absorbing layer, thereby releasing the stress between the layers caused by the bending of the display device 10, and can flatten the steps between the layers. The second encapsulation layer 182 can be made of a non-photosensitive organic insulating material (e.g., acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, polyethylene or silicon oxycarbide (SiOCN)) or a photosensitive organic insulating material (e.g., optical acrylic resin). The present disclosure is not limited to this. When the second encapsulation layer 182 is formed by an inkjet method, a dam DAM can be set to prevent the second encapsulation layer 182 in a liquid state from diffusing to the edge of the substrate 101. The dam DAM can be closer to the edge of the substrate 101 than the second encapsulation layer 182. The dam DAM can prevent the second encapsulation layer 182 in a liquid state from diffusing to the pad area where the outermost conductive pad set on the substrate 101 is set.

[0104] The dam DAM is designed to prevent diffusion of the second encapsulation layer 182. However, when the second encapsulation layer 182 overflows over the dam DAM during the process, the second encapsulation layer 182 as an organic layer may be exposed to the outside, so that moisture, etc. may invade the light emitting element. Therefore, in order to prevent this invasion, at least ten dams DAM may be stacked.

[0105] The bank DAM may be disposed on an interlayer insulating layer disposed on the third insulating layer 135 in the non-display area NA. However, embodiments of the present disclosure are not limited thereto, and the interlayer insulating layer may be the third insulating layer 135 .

[0106] In addition, the dam DAM, the first intermediate layer 150 and the second intermediate layer 160 may be formed simultaneously. The first intermediate layer 150 and the lower layer of the dam DAM may be formed simultaneously. The second intermediate layer 160 and the upper layer of the dam DAM may be formed simultaneously. Thus, the dam DAM may have a double-layer structure.

[0107] Accordingly, the dam DAM may be made of the same material as each of the first intermediate layer 150 and the second intermediate layer 160. However, embodiments of the present disclosure are not limited thereto.

[0108] The bank DAM may overlap the low potential driving power line VSS. For example, the low potential driving power line VSS may be formed in a layer below the bank DAM in the non-display area NA.

[0109] The low potential driving power line VSS and the gate driver 300 in the form of a gate in panel (GIP) may surround the periphery of the display panel. The low potential driving power line VSS may be located at an outward position of the gate driver 300. In addition, the low potential driving power line VSS may be connected to the anode electrode 171 so as to apply a common voltage thereto. The gate driver 300 is simply shown in a plan view and a cross-sectional view. However, the gate driver 300 may be configured with a thin film transistor TFT having the same structure as the thin film transistor TFT of the display area AA.

[0110] The low potential driving power line VSS is arranged at an outward position of the gate driver 300. The low potential driving power line VSS is arranged at an outward position of the gate driver 300 and surrounds the display area AA. The low potential driving power line VSS can be made of the same material as each of the source electrode / drain electrode 140 of the thin film transistor TFT. The present disclosure is not limited thereto. For example, the low potential driving power line VSS can be made of the same material as the gate electrode 125.

[0111] In addition, a low potential driving power line VSS may be electrically connected to the anode electrode 171. The low potential driving power line VSS may supply a low potential driving voltage EVSS to a plurality of pixels in the display area AA.

[0112] The low potential driving power line VSS may be disposed on the third insulating layer 135. Alternatively, the low potential driving power line VSS may be disposed on a layer of the source / drain electrodes 140 or the gate electrode 125 of the thin film transistor TFT1. However, the embodiments of the present disclosure are not limited thereto.

[0113] The at least one power line VL may be disposed between the gate driver 300 and the display area AA. The at least one power line VL may be disposed in the same layer as the layer of the source electrode / drain electrode 140 of the thin film transistor TFT1. However, the embodiments of the present disclosure are not limited thereto. The at least one power line VL is shown in a simple manner in the cross-sectional view. However, the initialization voltage bus ViniL and the reference voltage bus VrefL may be arranged side by side and may be disposed in the same layer. Alternatively, the initialization voltage bus ViniL and the reference voltage bus VrefL may be disposed in different layers in an overlapping or non-overlapping manner. The initialization voltage bus ViniL may supply a second initialization voltage Vini to a plurality of pixels in the display area AA. The reference voltage bus VrefL may supply a reference voltage Vref to a plurality of pixels in the display area AA. The at least one power line VL is illustrated as being disposed between the gate driver 300 and the display area AA. However, the embodiments of the present disclosure are not limited thereto.

[0114] The touch layer 190 may be disposed on the encapsulation layer 180. In the touch layer 190, a touch buffer film 191 may be located between the touch sensor metal (including the touch electrode connection lines 192 and 194 and the touch electrodes 195 and 196) and the cathode electrode 173 of the light emitting element EL.

[0115] The touch buffer film 191 can prevent chemical substances (developer, etchant, etc.) used in the manufacturing process of the touch sensor metal provided on the touch buffer film 191 or moisture from the outside from intruding into the light emitting layer 172 including organic materials. Accordingly, the touch buffer layer 191 can prevent damage to the light emitting layer 172 that is susceptible to damage by chemical substances or moisture.

[0116] The touch buffer film 191 may be made of an organic insulating material, which may be formed at a low temperature lower than or equal to a certain temperature (100 degrees Celsius) to prevent damage to the light emitting layer 172 including an organic material susceptible to high temperature damage, and the organic insulating material has a low dielectric constant of 1 to 3. For example, the touch buffer layer 191 may be made of an acrylic-based material, an epoxy-based material, or a siloxane-based material. The touch buffer film 191 made of an organic insulating material and having a planarization property may prevent the encapsulation layer 180 from being damaged due to bending of the organic light emitting display device and the touch sensor metal formed on the touch buffer film 191 from being broken.

[0117] According to a mutual capacitance-based touch sensor structure, the touch electrodes 195 and 196 may be disposed on the touch buffer layer 191 and the touch electrodes 195 and 196 may be disposed to intersect each other.

[0118] The touch electrode connection lines 192 and 194 electrically connect the touch electrodes 195 and 196 to each other. The touch electrode connection lines 192 and 194 and the touch electrodes 195 and 196 may be located on different layers with the touch insulating film 193 interposed therebetween.

[0119] The touch electrode connection lines 192 and 194 may overlap the bank layer 165 , thereby preventing an aperture ratio from being reduced.

[0120] In one example, a portion of the touch electrode connection line 192 may extend along the upper and side surfaces of the encapsulation layer 180 and the upper and side surfaces of the dam DAM, and then may be electrically connected to a touch driver circuit (not shown) via a pad 198. Thus, the touch electrodes 195 and 196 may be electrically connected to the touch driver circuit.

[0121] This portion of the touch electrode connection line 192 may receive a touch drive signal from a touch driver circuit and transmit it to the touch electrodes 195 and 196 , and may receive a touch sensing signal from the touch electrodes 195 and 196 and transmit it to the touch driver circuit.

[0122] The touch protection film 197 may be disposed on the touch electrodes 195 and 196. In the drawings, it is shown that the touch protection film 197 is disposed only on the touch electrodes 195 and 196. However, the embodiments of the present disclosure are not limited thereto. The touch protection film 197 may extend to the inner end or the outer end of the dam DAM, and thus may also be disposed on the touch electrode connection line 192.

[0123] In addition, a color filter (not shown) may be further disposed on the encapsulation layer 180 , and the color filter may be located on the touch layer 190 or between the encapsulation layer 180 and the touch layer 190 .

[0124] Figure 3 is a diagram of a pixel circuit in a display device according to an exemplary embodiment of the present disclosure.

[0125] Figure 3 Only an example of a pixel circuit is shown for illustration. The structure of the pixel circuit is not particularly limited as long as its structure can apply a light emitting control signal EM(n) to the pixel to control the light emitting element EL. For example, the pixel circuit may include a switching thin film transistor connected to an additional scanning signal and a switching thin film transistor to which an additional initialization voltage is applied. The connection relationship of the switching element or the connection position of the capacitor may vary. In the following, for ease of explanation, a pixel circuit having Figure 3 A display device with a pixel circuit structure.

[0126] refer to Figure 3 , each of the plurality of pixels P may include a pixel circuit including a driving transistor DT and a light emitting element EL connected to the pixel circuit.

[0127] The pixel circuit may control a driving current flowing through the light emitting element EL to drive the light emitting element EL. The pixel circuit may include a driving transistor DT, first to seventh transistors T1 to T7, and a capacitor Cst. Each of the transistors DT and T1 to T7 may include a first electrode, a second electrode, and a gate electrode. One of the first electrode and the second electrode may be a source electrode, and the other of the first electrode and the second electrode may be a drain electrode.

[0128] Each of the transistors DT and T1 to T7 may be a P-type thin film transistor or an N-type thin film transistor. Figure 3In the embodiment of the present invention, the first transistor T1 and the seventh transistor T7 are embodied as N-type thin film transistors, and the remaining transistors DT and T2 to T6 are embodied as P-type thin film transistors. However, the embodiments of the present disclosure are not limited thereto. According to the embodiment, each of all or some of the transistors DT and T1 to T7 may be a P-type thin film transistor or an N-type thin film transistor. In addition, the N-type thin film transistor may be embodied as an oxide thin film transistor. The P-type thin film transistor may be embodied as a polysilicon thin film transistor.

[0129] Hereinafter, an example in which the first transistor T1 and the seventh transistor T7 are embodied as N-type thin film transistors and the remaining transistors DT and T2 to T6 are embodied as P-type thin film transistors will be described. Therefore, each of the first transistor T1 and the seventh transistor T7 can be turned on when a high voltage is applied. Each of the remaining transistors DT and T2 to T6 can be turned on when a low voltage is applied.

[0130] According to one example, the first transistor T1 constituting the pixel circuit may function as a compensation transistor, the second transistor T2 may function as a data supply transistor, each of the third and fourth transistors T3 and T4 may function as a light emitting control transistor, the fifth transistor T5 may function as a bias transistor, and each of the sixth and seventh transistors T6 and T7 may function as an initialization transistor.

[0131] The light emitting element EL may include an anode electrode and a cathode electrode. The anode electrode of the light emitting element EL may be connected to the fifth node N5, and the cathode electrode thereof may be connected to the low potential driving voltage EVSS.

[0132] The driving transistor DT may include a first electrode connected to the second node N2, a second electrode connected to the third node N3, and a gate electrode connected to the first node N1. The driving transistor DT may provide a driving current Id to the light emitting element EL based on a voltage of the first node N1 or a data voltage stored in the capacitor Cst as will be described below.

[0133] The first transistor T1 may include a first electrode connected to the first node N1, a second electrode connected to the third node N3, and a gate electrode receiving the first scan signal SC1(n). The first transistor T1 may be turned on in response to the first scan signal SC1(n) to establish a diode connection between the first node N1 and the third node N3, thereby sampling the threshold voltage Vth of the driving transistor DT. This first transistor T1 may be a compensation transistor.

[0134] The capacitor Cst may be connected to the first node N1 and the fourth node N4 and disposed therebetween. The capacitor Cst may store or maintain the high potential driving voltage EVDD supplied thereto.

[0135] The second transistor T2 may include a first electrode connected to the data line DL or receiving the data voltage Vdata, a second electrode connected to the second node N2, and a gate electrode receiving the second scan signal SC2(n). The second transistor T2 may be turned on in response to the second scan signal SC2(n) so that the data voltage Vdata may be transmitted to the second node N2. This second transistor T2 may be a data supply transistor.

[0136] The third transistor T3 and the fourth transistor T4 (or the first and second light emission control transistors) may be connected to and disposed between the high potential driving voltage EVDD and the light emitting element EL, and may establish a current path through which the driving current Id generated by the driving transistor DT flows.

[0137] The third transistor T3 may include a first electrode connected to the fourth node N4 to receive the high potential driving voltage EVDD, a second electrode connected to the second node N2, and a gate electrode receiving the light emitting control signal EM(n).

[0138] The fourth transistor T4 may include a first electrode connected to the third node N3, a second electrode connected to the fifth node N5 (or the anode electrode of the light emitting element EL), and a gate electrode receiving the light emitting control signal EM(n).

[0139] Each of the third and fourth transistors T3 and T4 may be turned on in response to the light emission control signal EM(n). In this case, the driving current Id may be provided to the light emitting element EL so that the light emitting element EL may emit light at a brightness level corresponding to the driving current Id.

[0140] The fifth transistor T5 may include a first electrode receiving the bias voltage Vobs, a second electrode connected to the second node N2, and a gate electrode receiving the third scan signal SC3(n). This fifth transistor T5 may be a bias transistor.

[0141] The sixth transistor T6 may include a first electrode receiving the first initialization voltage Var, a second electrode connected to the fifth node N5, and a gate electrode receiving the third scan signal SC3(n).

[0142] The sixth transistor T6 can be turned on in response to the third scan signal SC3(n) before the light emitting element EL emits light (or after the light emitting element EL emits light), so that the anode electrode (or pixel electrode) of the light emitting element EL can be initialized based on the first initialization voltage Var.

[0143] The light emitting element EL may have a parasitic capacitor generated between the anode electrode and the cathode electrode. Therefore, while the light emitting element EL emits light, the parasitic capacitor is charged so that the anode electrode of the light emitting element EL may have a specific voltage. Accordingly, the amount of charge accumulated in the light emitting element EL may be initialized by applying a first initialization voltage Var to the anode electrode of the light emitting element EL via the sixth transistor T6.

[0144] In the present disclosure, the fifth transistor T5 and the sixth transistor T6 are configured so that the gate electrodes of the fifth transistor T5 and the sixth transistor T6 receive the third scan signal SC3(n) in common. However, the embodiments of the present disclosure are not limited thereto, and the fifth transistor T5 and the sixth transistor T6 are configured so that the gate electrodes of the fifth transistor T5 and the sixth transistor T6 receive separate scan signals and thus operate independently.

[0145] The seventh transistor T7 may include a first electrode receiving the second initialization voltage Vini, a second electrode connected to the first node N1, and a gate electrode receiving the fourth scan signal SC4(n).

[0146] The seventh transistor T7 can be turned on in response to the fourth scan signal SC4 (n), so that the gate electrode of the driving transistor DT can be initialized using the second initialization voltage Vini. Due to the high potential driving voltage EVDD stored in the capacitor Cst, unnecessary charges can be retained in the gate electrode of the driving transistor DT. Therefore, the amount of residual charge can be initialized by applying the second initialization voltage Vini to the gate electrode of the driving transistor DT via the seventh transistor T7.

[0147] Figure 4 It shows that Figure 3 0 is an example of a diagram of scan signals and light emission control signals applied in a refresh period and a hold period in a pixel circuit shown in .

[0148] The display device according to the exemplary embodiment of the present disclosure can operate as a VRR mode display device. In the VRR mode, the display device operates at a constant frequency. When high-speed operation is required, the refresh rate of the update data voltage Vdata is increased. Therefore, the pixel operates at an increased refresh rate. When low power consumption or low-speed operation is required, the refresh rate is reduced so that the pixel operates at a reduced refresh rate.

[0149] Each of the plurality of pixels P may operate based on a combination of a refresh frame and a hold frame. In other words, when the device operates at a high speed (e.g., 120 Hz) or a normal speed (e.g., 60 Hz), only the refresh cycle may be repeated. However, when the device operates at a low speed (e.g., 1 Hz or 10 Hz), the refresh cycle and the hold cycle may be arranged in an alternating manner.

[0150] In the refresh frame, a new data voltage Vdata is charged, and thus the new data voltage Vdata is applied to the driving transistor DT. In the hold frame, the data voltage Vdata of the previous frame is held. In this regard, the hold frame can be referred to as a skip cycle in the sense that the process of applying the new data voltage Vdata to the driving transistor DT is omitted in the hold frame.

[0151] Each of the plurality of pixels P can initialize the voltage charged or remaining in the pixel circuit during the refresh frame. Specifically, each of the plurality of pixels P can remove the influence of the data voltage Vdata and the high potential driving voltage EVDD stored in the previous frame during the refresh frame. Therefore, each of the plurality of pixels P can display an image corresponding to the new data voltage Vdata in the hold frame.

[0152] In the holding frame, each of the plurality of pixels P may supply a driving current corresponding to the data voltage Vdata to the light emitting element EL to display an image, and may maintain the on state of the light emitting element EL.

[0153] refer to Figure 4 , the refresh frame may include at least one bias period Tobs1 and Tobs2, an initialization period Ti, a sampling period Ts, and a light emitting period Te. However, this is only an example, and the embodiments of the present disclosure are not necessarily limited to this order.

[0154] At least one bias period Tobs1 and Tobs2 refers to a period for performing an on-bias stress (OBS) operation (applying a bias voltage Vobs). In the at least one bias period, the light emitting control signal EM(n) is at a high voltage, and the third and fourth transistors T3 and T4 are turned off. The first scan signal SC1(n) and the fourth scan signal SC4(n) are at a low voltage, and the first transistor T1 and the seventh transistor T7 are turned off. The second scan signal SC2 is at a high voltage and the second transistor T2 is turned off.

[0155] In the at least one bias period Tobs1 and Tobs2, the third scan signal SC3(n) having a low voltage is input so that the fifth transistor T5 and the sixth transistor T6 are turned on. As the fifth transistor T5 is turned on, the bias voltage Vobs is applied to the first electrode of the driving transistor DT connected to the second node N2.

[0156] In this regard, the bias voltage Vobs is supplied to the second node N2 as the source electrode of the driving transistor DT. Therefore, in the light emission period, the charging time or charging delay of the voltage of the fifth node N5 as the anode electrode of the light emitting element EL can be shortened. The driving transistor DT is maintained in a strong saturation state.

[0157] In this regard, the magnitude of the drain-source current Id flowing through the driving transistor DT can be reduced, and the stress of the driving transistor DT can be reduced under the positive bias stress condition, thereby solving the charging delay of the voltage of the third node N3. In other words, the hysteresis of the driving transistor DT can be alleviated by performing a turn-on bias stress operation on the driving transistor DT before sampling the threshold voltage Vth of the driving transistor DT.

[0158] refer to Figure 4 , the pixel circuit can be operated so that the initialization period Ti is included in the refresh frame. The initialization period Ti refers to a period in which the voltage of the gate electrode of the driving transistor DT is initialized.

[0159] In the initialization period Ti, each of the first to fourth scan signals SC1(n) to SC4(n) and the light emitting control signal EM(n) is at a high voltage, and the first transistor T1 and the seventh transistor T7 are turned on. The second to sixth transistors T2, T3, T4, T5, and T6 are turned off. Since the first transistor T1 and the seventh transistor T7 are turned on, the gate electrode and the second electrode of the driving transistor DT connected to the first node N1 are initialized with the second initialization voltage Vini.

[0160] refer to Figure 4 , the pixel circuit can be operated so that the sampling period Ts is included in the refresh frame. The sampling period refers to the period for sampling the threshold voltage Vth of the driving transistor DT.

[0161] In the sampling period Ts, each of the first scan signal SC1(n), the third scan signal SC3(n) and the light emitting control signal EM(n) is at a high voltage, and the second scan signals SC2_O(n) to SC2_E(n) and the fourth scan signal SC4(n) having a low voltage are input. Therefore, the third to seventh transistors T3, T4, T5, T6 and T7 are turned off, the first transistor T1 is maintained in the on state, and the second transistor T2 is turned on. That is, the second transistor T2 is turned on, so that the data voltage Vdatat is applied to the driving transistor DT, and thus a diode connection between the first node N1 and the third node N3 is established, so that the threshold voltage Vth of the driving transistor DT can be sampled.

[0162] refer to Figure 4 , the pixel circuit can operate so that the light emitting period Te is included in the refresh frame. The light emitting period Te refers to a period in which the sampling threshold voltage Vth of the driving transistor DT is canceled and the light emitting element EL emits light under the driving current corresponding to the sampling data voltage Vdata.

[0163] In the light emitting period Te, the light emitting control signal EM(n) is at a low voltage and the third transistor T3 and the fourth transistor T4 are turned on.

[0164] Since the third transistor T3 is turned on, the high potential driving voltage EVDD connected to the fourth node N4 can be applied to the first electrode of the driving transistor DT connected to the second node N2 via the third transistor T3. The driving current Id supplied from the driving transistor DT to the light emitting element EL via the fourth transistor T4 can depend on the data voltage Vdata regardless of the value of the threshold voltage Vth of the driving transistor DT. Therefore, the threshold voltage Vth of the driving transistor DT is compensated.

[0165] refer to Figure 4 , the operations of the pixel circuit and the light emitting element in the hold frame will be described.

[0166] The hold frame may include at least one bias period Tobs3 and Tobs4 and a light emitting period Te'. Description of the same operations performed by the pixel circuit in the hold frame as those performed in the refresh frame will be omitted.

[0167] As described above, in the refresh frame, a new data voltage Vdata is charged, so that the new data voltage Vdata is applied to the gate electrode of the driving transistor DT. However, in the hold frame, the data voltage Vdata of the refresh frame is held. Therefore, unlike the refresh frame, the hold frame does not require an initialization period Ti and a sampling period Ts.

[0168] refer to Figure 4 , the difference between the driving signal in the refresh frame described above and the driving signal in the hold frame is about the second scan signal SC2(n) and the fourth scan signal SC4(n). In the hold frame, the initialization period Ti and the sampling period Ts are unnecessary. Thus, unlike the refresh frame, in the hold frame, the second scan signals SC2_O(n) to SC2_E(n) are always at a high voltage, and the fourth scan signal SC4(n) is always at a low voltage. That is, the second transistor T2 and the seventh transistor T7 are always turned off.

[0169] Figure 5 is a diagram of a configuration of a gate driver in a display device according to an embodiment.

[0170] refer to Figure 5, the gate driver 300 includes a light emission control driver 310 and a scan driver 320. The scan driver 320 may include first to fourth scan drivers 321, 322, 333, and 334. In addition, the second scan driver 322 may be composed of an odd-numbered second scan driver 322_O and an even-numbered second scan driver 322_E. In other words, each of the stages STG(1) to STG(n) of the shift register may include each of the first scan signal generators 321(1) to 321(n), each of the second scan signal generators 322_O(1) to SC2_O(n) and 322_E(1) to SC2_E(n), each of the third scan signal generators 323(1) to 323(n), each of the fourth scan signal generators 324(1) to 324(n), and each of the light emission control signal generators 310(1) to 310(n).

[0171] The gate driver 300 may include shift registers symmetrically disposed on opposite sides of the display area AA, respectively. The second scan drivers 322_O and 322_E, the fourth scan driver 324, and the light emission control driver 310 may be disposed in a side region around the display area AA. The first scan driver 321, the second scan drivers 322_O and 322_E, and the third scan driver 323 may be disposed in the other side region around the display area AA. However, the embodiments of the present disclosure are not limited thereto, and according to an embodiment, at least one of the second scan drivers 322_O and 322_E, the fourth scan driver 324, and the light emission control driver 310 may be disposed in the other side region around the display area AA, and at least one of the first scan driver 321, the second scan drivers 322_O and 322_E, and the third scan driver 323 may be disposed in a side region around the display area AA.

[0172] In a side area of ​​the display area AA, the second scan drivers 322_O and 322_E may be disposed adjacent to the display area AA, the fourth scan driver 324 may be disposed in the outermost area, and the light emission control driver 310 may be disposed between the second scan drivers 322_O and 322_E and the fourth scan driver 324.

[0173] Alternatively, according to an embodiment, the light emission control driver 310 may be disposed in the outermost region.

[0174] In addition, in the other side area around the display area AA, the second scan drivers 322_O and 322_E can be set adjacent to the display area AA, the first scan driver 321 can be set to the outermost area, and the third scan driver 323 can be set between the second scan drivers 322_O and 322_E and the first scan driver 321.

[0175] Alternatively, according to an embodiment, the third scan driver 323 may be disposed in the outermost region.

[0176] In addition, the second scan drivers 322_O and 322_E may be divided into an odd-numbered scan driver 322_O and an even-numbered scan driver 322_E. The odd-numbered scan driver 322_O may be respectively arranged on opposite sides of the display area AA. The even-numbered scan driver 322_E may be respectively arranged on opposite sides of the display area AA. When the second scan driver operates so that the odd-numbered scan driver 322_O and the even-numbered scan driver 322_E work separately, sufficient time required for sampling the data voltage Vdata may be ensured. In addition, the odd-numbered scan driver 322_O is respectively arranged on opposite sides of the display area AA, and the even-numbered scan driver 322_E is respectively arranged on opposite sides of the display area AA, thereby reducing the difference between the sampling times of the data voltage Vdata in the pixel. Accordingly, as the second scan drivers 322_O and 322_E work, sufficient sampling time may be ensured, and the difference between its sampling times in the pixel may be shortened when sampling the data voltage Vdata, thereby improving the image quality of the display panel.

[0177] Each of the light emission control driver 310 and the first to fourth scan drivers 321 to 324 operates in response to receiving each of a start signal and a clock signal applied thereto via each of a plurality of start signal lines VSTL and a plurality of clock signal lines CLKL.

[0178] In this regard, the clock signals may have different phases, and the clock signals applied to the same gate driver may be applied via adjacent clock signal lines CLKL, respectively. In other words, in response to receiving a start signal and a clock signal, each of the light emitting control driver 310 and the first to fourth scanning drivers 321 to 324 may output a gate signal to the pixel circuit. The clock signal includes a first clock signal and a second clock signal. The first clock signal and the second clock signal are applied thereto via adjacent clock signal lines CLKL, respectively, and the adjacent clock signal lines CLKL may form a pair.

[0179] refer to Figure 5, power lines VL such as the bias voltage bus VobsL, the first initialization voltage bus VarL, and the second initialization voltage bus ViniL may be disposed in the link area LA between the gate driver 300 and the display area AA. The power lines VL may be disposed adjacent to the display area in the following order: the bias voltage bus VobsL, the second initialization voltage bus ViniL, and the first initialization voltage bus VarL. However, the arrangement order is not limited thereto and may vary according to design.

[0180] The power line VL may supply the bias voltage Vobs, the first initialization voltage Var, and the second initialization voltage Vini as a direct current voltage DC from the power supply 500 to the pixel circuit via a power link line VLL branched from the bias voltage bus VobsL, the first initialization voltage bus VarL, and the second initialization voltage bus ViniL, respectively.

[0181] In the drawings, it is shown that the power lines VL are arranged symmetrically on opposite sides of the display area AA. However, the embodiments of the present disclosure are not limited thereto, and the power lines VL may be located only on the left or right side of the display area AA. Alternatively, the power lines may be located only on the upper side or the lower side of the display area AA.

[0182] The power line VL and the source or drain electrode 140 may be made of the same material and may be disposed in the same layer. The power line VL and the connection electrode 155 may be made of the same material and may be disposed in the same layer.

[0183] At least a portion of the power link line VLL and the gate electrodes 125 and 126 may be made of the same material and may be disposed in the same layer. Alternatively, at least a portion of the power link line VLL and the touch electrodes 194, 195, and 196 may be made of the same material and may be disposed in the same layer. Alternatively, at least a portion of the power link line VLL and the semiconductor layers 115 and 116 may be made of the same material and may be disposed in the same layer. In addition, at least a portion of the power link line VLL and a shielding metal layer not shown in the drawings may be made of the same material and may be disposed in the same layer.

[0184] Fig. 6A is a diagram showing a configuration of a shift register of a gate driver according to an exemplary embodiment of the present disclosure, and Figure 6B yes Fig. 6A An example of a driver circuit for a shift register in FIG.

[0185] refer to Fig. 6AThe light emitting control signal generators 310(1) to 310(n) of the light emitting control driver 310 may receive a light emitting control start signal EVST, a first light emitting control clock signal ECLK1, and a second light emitting control clock signal ECLK2, and may output light emitting control signals EM(1) to EM(n) via a plurality of light emitting control lines EML.

[0186] The first scan signal generators 321(1) to 321(n) of the first scan driver 321 may receive the first start signal SC1_VST, the (1-1)th clock signal SC1_GCLK1, and the (1-2)th clock signal SC1_GCLK2, and may output a plurality of first scan signals SC1(1) to SC1(n) via a plurality of first scan lines SCL1.

[0187] The fourth scan signal generators 324(1) to 324(n) of the fourth scan driver 324 may receive the fourth start signal SC4_VST, the (4-1)th clock signal SC4_GCLK1, and the (4-2)th clock signal SC4_GCLK2, and may output a plurality of fourth scan signals SC4(1) to SC4(n) via a plurality of fourth scan lines SCL4.

[0188] The shift register structure of each of the first scan driver 321 and the fourth scan driver 324 may be the same as the shift register structure of the light emission control driver 310 .

[0189] The clock signal lines CLKL corresponding to the light emission control signal generators 310(1) to 310(n) may be alternately connected to the odd-numbered stages and the even-numbered stages so that each of the light emission control signal generators 310(1) to 310(n) may receive only one clock signal. Fig. 6A As shown in , the first light emitting control clock signal ECLK1 may be applied to odd-numbered stages, and the second light emitting control clock signal ECLK2 may be applied to even-numbered stages.

[0190] As in the light emitting control driver 310, the clock signal line CLKL corresponding to the scan signal generator of each of the first scan driver 321 and the fourth scan driver 324 can be alternately connected to the odd-numbered stages and the even-numbered stages, so that each of the scan signal generators of each of the first scan driver 321, the third scan driver 323 and the fourth scan driver 324 receives only one clock signal.

[0191] The gate signal output from each of the signal generators of each of the light emission control driver 310, the first scan driver 321, and the fourth scan driver 324 may be affected by the start signal instead of the clock signal. Thus, only one clock signal may be applied thereto.

[0192] In addition, the light emitting control driver 310, the first scan driver 321, and the fourth scan driver 324 may be arranged on the left or right side of the display area AA, and may supply gate signals to a plurality of pixels P connected thereto via one gate line GL. This scheme may be a single-feed scheme. However, the embodiments of the present disclosure are not limited thereto. The light emitting control driver 310, the first scan driver 321, the third scan driver 323, and the fourth scan driver 324 may be arranged on opposite sides of the display area AA in a symmetrical structure, and may supply the same signal to one gate line GL. This scheme may be a dual-feed scheme.

[0193] In addition, the same gate signal output from each of the light emission control driver 310, the first scan driver 321, the third scan driver 323, and the fourth scan driver 324 may be applied to two pixel rows arranged in the display area AA. This scheme may be a two-row sharing structure.

[0194] In addition, it is shown that the clock signal line CLKL for applying the first and second emission control clock signals ECLK1 and ECLK2 is disposed at an outward position of the start signal line VSTL to apply the emission control start signal EVST. However, the embodiments of the present disclosure are not limited thereto.

[0195] Figure 6B 1 and 2. The driver circuit of the light emission control driver 310 is shown. The configuration thereof may be applied to the driver circuit of each of the first scan driver 321 or the fourth scan driver 324.

[0196] refer to Figure 6B The driver circuit of the light emitting control driver 310 may include a (1-1)th gate transistor T11, a (1-2)th gate transistor T12, a (1-3)th gate transistor T13, a (1-4)th gate transistor T14, a (1-5)th gate transistor T15, a (1-6)th gate transistor T16, a first transmission transistor TA, a first capacitor CQ1, a second capacitor CQB1 and a third capacitor CC1.

[0197] The (1-1)th gate transistor T11 can pull up the output terminal in response to the signal of the Q1 node, and the (1-2)th gate transistor T12 can pull down the output terminal in response to the signal of the QB1 node. The (1-3)th gate transistor T13 provides the start signal EVST or the output signal EM[n-1] of the previous stage to the Q12 node in response to the clock signal ECLK. The (1-4)th gate transistor T14 transmits the high potential voltage VEH to the Q11 node in response to the start signal EVST or the output signal EM[n-1] of the previous stage. The (1-5)th gate transistor T15 provides the clock signal ECLK to the QB node in response to the voltage of the Q11 node. The (1-6)th gate transistor T16 transmits the high potential voltage VEH to the QB node in response to the voltage of the Q12 node.

[0198] The first transfer transistor TA transfers the charge of Q12 to the Q1 node in response to the low potential voltage VEL. The first transfer transistor TA can be connected to the Q12 node and the Q1 node and arranged therebetween, and acts as a buffer to prevent the voltage applied to the Q1 node from changing suddenly. The first transfer transistor TA electrically connects the Q1 node and the Q12 node to each other continuously. Therefore, the voltage of the Q12 node can be maintained equal to the voltage of the Q1 node.

[0199] The first capacitor CQ1 may be coupled to the Q1 node and the output and disposed therebetween. The second capacitor CQB1 may be coupled to the QB1 node and the high potential voltage VEH and disposed therebetween. The third capacitor CC1 may be coupled to the clock signal ECLK and the drain electrode of the transistor T14 and disposed therebetween, and may be coupled to the clock signal ECLK and the gate electrode of the transistor T15 and disposed therebetween.

[0200] The first capacitor CQ1 and the second capacitor CQB1 may operate as bootstrap capacitors, and the third capacitor CC1 may operate as a stabilizing capacitor.

[0201] In addition, the third capacitor CC1 may be designed to have a larger capacity than the first capacitor CQ1 or the second capacitor CQB1. In other words, the third capacitor CC1 may occupy an area larger than that of the first capacitor CQ1 or the second capacitor CQB1.

[0202] Fig. 7A is a diagram showing a configuration of a shift register of another gate driver according to an exemplary embodiment of the present disclosure, and Figure 7B yes Fig. 7A An example of a driver circuit for a shift register in FIG. Figure 7C Yes Figure 7B An example of an operating waveform diagram of a driver circuit is shown.

[0203] refer to Fig. 7A The second scan signal generators 322(1) to 322(n) of the second scan driver 322 can receive the second start signal SC2_VST, the (2-1)th clock signal SC2_GCLK1 and the (2-2)th clock signal SC2_GCLK2 and can output a plurality of second scan signals SC2(1) to SC2(n) via a plurality of second scan lines SCL2.

[0204] The clock signal lines CLKL corresponding to the second scan signal generators 322(1) to 322(n) may be connected to the respective stages, respectively, so that each of the second scan signal generators 322(1) to 322(n) receives two clock signals. Fig. 7A As shown in , the second scan signal generator 322 (n) may be composed of an odd-numbered second scan driver 322_O and an even-numbered second scan driver 322_E. The odd-numbered (2-1)th clock signal SC2_O_GCLK1 and the odd-numbered (2-2)th clock signal SC2_O_GCLK2 may be applied to each odd-numbered second scan driver 322_O disposed in the odd-numbered stage. The even-numbered (2-1)th clock signal SC2_E_GCLK1 and the even-numbered (2-2)th clock signal SC2_E_GCLK2 may be applied to each even-numbered second scan driver 322_E disposed in the even-numbered stage. In other words, a plurality of clock signal lines CLKL may be alternately connected to the odd-numbered stage and the even-numbered stage.

[0205] The gate signal outputted by each of the scan signal generators of the second scan driver 322 may be affected by the clock signal instead of the start signal. Thus, at least two clock signals may be applied thereto.

[0206] In addition, the second scan driver 322 can be symmetrically arranged on opposite sides of the display area AA, and can supply the same signal to one gate line GL. This scheme can be a dual-feed scheme. However, the embodiments of the present disclosure are not limited thereto. The second scan driver 322 can be arranged on the left or right side of the display area AA, and can supply gate signals to a plurality of pixels P connected thereto via one gate line GL. This scheme can be a single-feed scheme.

[0207] In addition, the same gate signal output from the second scan driver 322 may be supplied to one pixel row arranged in the display area AA. This configuration may be a single row sharing structure.

[0208] In addition, it is shown that the clock signal line CLKL to which the even-numbered (2-1) clock signal SC2_E_GCLK1 and the even-numbered (2-2) clock signal SC2_E_GCLK2 are applied is arranged at an outward position of the clock signal line CLKL to which the odd-numbered (2-1) clock signal SC2_O_GCLK1 and the odd-numbered (2-2) clock signal SC2_O_GCLK2 are applied. However, the embodiments of the present disclosure are not limited thereto.

[0209] Hereinafter, for the convenience of description, the odd-numbered second scan driver 322_O and the even-numbered second scan driver 322_E are not distinguished, but are collectively referred to as one second scan driver 322. The clock signals respectively input to the odd-numbered second scan driver 322_O and the even-numbered second scan driver 322_E are not distinguished, but are collectively referred to as one clock signal. The start signals respectively input to the odd-numbered second scan driver 322_O and the even-numbered second scan driver 322_E are not distinguished, but are collectively referred to as one start signal.

[0210] refer to Figure 7B , the driver circuit of the second scan driver 322 may include a plurality of gate transistors T21, T22, T23, T24, T25, T26, T27, and TB and at least one capacitor CQ2, CQB2, and CC2.

[0211] The driver circuit of the second scan driver 322 may include a fourth capacitor CQ2 electrically connected to the Q2 node and the output terminal of the gate signal and disposed therebetween, and a fifth capacitor CQB2 electrically connected to the QB2 node and the input terminal of the second gate driving voltage VGH2 and disposed therebetween.

[0212] The fourth capacitor CQ2 and the fifth capacitor CQB2 may operate as bootstrap capacitors.

[0213] In addition, the driver circuit of the second scan driver 322 may include a sixth capacitor CC2 electrically connected to the Q21 node and the input terminal of the (2-1)th clock signal SC2_GCLK1 and disposed therebetween.

[0214] The capacity of the sixth capacitor CC2 may be set to a capacity such that the sixth capacitor can stably control the voltage level of the Q21 node. Thus, the sixth capacitor may operate as a stabilizing capacitor.

[0215] The capacity of the sixth capacitor CC2 may be the same as or different from the capacity of the fourth capacitor CQ2 or the fifth capacitor CQB2. In other words, the sixth capacitor CC2 may be designed to have a larger capacity than the capacity of the fourth capacitor CQ2 or the fifth capacitor CQB2, and may occupy an area larger than the area occupied by the fourth capacitor CQ2 or the fifth capacitor CQB2.

[0216] The input terminal of the (2-1)th clock signal SC2_GCLK1 may refer to the input terminal of the (2-1)th clock signal SC2_GCLK1 electrically connected to the gate node of the (2-4)th gate transistor T24. Alternatively, the input terminal of the (2-1)th clock signal SC2_GCLK1 may refer to the input terminal of the (2-1)th clock signal SC2_GCLK1 electrically connected to the gate node of the (2-1)th gate transistor T21.

[0217] A line supplying the (2-1)th clock signal SC2_GCLK1 to the (2-4)th gate transistor T24 and a line supplying the (2-1)th clock signal SC2_GCLK1 to the (2-6)th transistor T26 may be the same as or different from each other.

[0218] refer to Figure 7C , the driver circuit of the second scan driver 322 can operate so that during period ①, the (2-1)th clock signal SC2_GCLK1 is at a high level, and the (2-2)th clock signal SC2_GCLK2 is at a low level, and the second start signal SC2_VST is at a low level.

[0219] Since the (2-1)th clock signal SC2_GCLK1 is at a high level, the (2-4)th gate transistor T24 is turned off. Since the (2-2)th clock signal SC2_GCLK2 is at a low level, the (2-3)th gate transistor T23 and the (2-7)th gate transistor T27 may be turned on. Since the (2-3)th gate transistor T23 is turned on and the (2-4)th gate transistor T24 is turned off, the low-level second start signal SC2_VST may be supplied to the Q21 node. Since the second transfer transistor TB remains in the on state, the Q2 node may be turned on like Figure 2Since the Q21 node is at a low level, the (2-6)th gate transistor T26 can be turned on. Since the (2-6)th gate transistor T26 is turned on, the low-level (2-2)th clock signal SC2_GCLK2 can be supplied to the QB2 node. In addition, since the (2-7)th gate transistor T27 is turned on, the low-level second gate low voltage VGL2 can be supplied to the QB2 node. Since both the Q2 node and the QB2 node are at a low level, both the (2-1)th gate transistor T21 and the (2-2)th gate transistor T22 can be turned on.

[0220] Accordingly, the (2-1)th clock signal SC2_GCLK1 can be output via the (2-1)th gate transistor T21, and the second gate high voltage VGH2 can be output via the (2-2)th gate transistor T22. Since both the (2-1)th clock signal SC2_GCLK1 and the second gate high voltage VGH2 are at a high level, a high-level scan signal can be output.

[0221] During period ②, the (2-1)th clock signal SC2_GCLK1 may be at a low level, the (2-2)th clock signal SC2_GCLK2 may be at a high level, and the second start signal SC2_VST may be at a high level.

[0222] Since the (2-1)th clock signal SC2_GCLK1 is at a low level, the (2-4)th gate transistor T24 can be turned on. Since the (2-2)th clock signal SC2_GCLK2 is at a high level, the (2-3)th gate transistor T23 and the (2-7)th gate transistor T27 can be turned off. Since the (2-3)th gate transistor T23 is turned off, the second start signal SC2_VST may not be supplied to the Q21 node and the Q21 node may remain at a low level. Since the Q21 node remains at a low level, the (2-6)th gate transistor T26 may remain in a conducting state. Since the (2-6)th gate transistor T26 remains in a conducting state, the high-level (2-2)th clock signal SC2_GCLK2 may be supplied to the QB2 node. Since the (2-7)th gate transistor T27 is turned off, the second gate low voltage VGL2 may not be supplied to the QB2 node, the Q21 node and the Q2 node may be maintained at a low level, and the QB2 node may be maintained at a high level. In addition, since the sixth transistor CC2 is provided between the Q21 node and the input terminal of the (2-1)th clock signal SC2_GCLK1, the Q21 node may be stably maintained at a low level.

[0223] During period ②, since the (2-1)th clock signal SC2_GCLK1 at a low level is input, the low level of the Q21 node can be stably maintained, wherein a capacitance is generated between the Q21 node and the input terminal of the (2-1)th clock signal SC2_GCLK1. The low level of the Q21 node can be stably maintained, so that the conduction state of the (2-6)th gate transistor T26 is maintained, and the refresh of the QB2 node can be stably performed.

[0224] Since the QB2 node is at a high level, the (2-5)th gate transistor T25 and the (2-2)th gate transistor T22 can be turned off. Since the Q2 node is at a low level, the (2-1)th gate transistor T21 can be turned on. Since the (2-1)th gate transistor T21 is turned on, the (2-1)th clock signal SC2_GCLK1 can be output via the output terminal of the scan signal. Since the (2-1)th clock signal SC2_GCLK1 is at a low level, the (2-1)th clock signal SC2_GCLK1 is output via the output terminal of the scan signal, so that the level of the Q2 node can become lower. Since the second transfer transistor TB is located between the Q2 node and the Q21 node, the voltage level of the Q2 node and the voltage level of the Q21 node can be different from each other during period ②.

[0225] In this way, the sixth capacitor CC2 can be provided between the Q21 node and the input terminal of the (2-1)th clock signal SC2_GCLK1, thereby stably maintaining the low level of the Q21 node at the output timing of the scan signal. The low level of the Q21 node can be maintained in a stable manner, so that the conduction state of the (2-6)th gate transistor T26 can be stably maintained. Even when the threshold voltage of the (2-6)th gate transistor T26 changes due to the degradation of the (2-6)th gate transistor T26, the refresh of the QB2 node can be stably performed and the scan signal can be output normally.

[0226] During period ③, the (2-1)th clock signal SC2_GCLK1 may be at a high level, the (2-2)th clock signal SC2_GCLK2 may be at a low level, and the second start signal SC2_VST may be at a high level.

[0227] The (2-4)th gate transistor T24 may be turned off based on the (2-1)th clock signal SC2_GCLK1. The (2-3)th gate transistor T23 and the (2-7)th gate transistor T27 may be turned on based on the (2-2)th clock signal SC2_GCLK2. The Q21 node and the Q2 node may enter a high level in response to the high-level second start signal SC2_VST. The QB2 node may enter a low level in response to the second gate low voltage VGL2 at a low level. Since the Q2 node is at a high level, the (2-1)th gate transistor T21 may be turned off. Since the QB2 node is at a low level, the (2-2)th gate transistor T22 may be turned on. Accordingly, the high-level second gate high voltage VGH2 may be output to the output terminal of the scan signal via the (2-2)th gate transistor T22.

[0228] Therefore, after outputting the low-level scan signal, the driver circuit can maintain the high-level scan signal. In this way, the driver circuit of the second scan driver 322 can use the sixth capacitor CC2 to stably maintain the voltage level of Q21 at the output timing of the scan signal. Thus, the scan signal can be normally output at the set timing, and the scan signal can be stably maintained at the cut-off level in the next cycle. In addition, due to the presence of the sixth capacitor CC2, the size of the transistor set in the driver circuit can be reduced, and the output margin according to the threshold voltage change can be set wider.

[0229] Fig. 8A is an example of a driver circuit of a shift register of another gate driver according to an exemplary embodiment of the present disclosure, and Figure 8B Yes Fig. 8A An example of an operating waveform diagram of a driver circuit is shown.

[0230] The shift register structure of the third scan driver 323 may be as follows: Fig. 6A The light emission control driver 310 or the shift register of the second scanning driver 322 is configured in a similar manner.

[0231] refer to Fig. 8A , the driver circuit of the third scan driver 323 may include a plurality of gate transistors T31, T32, T33, T34, T35, T36, and TC and at least one capacitor CQ3 and CQB3.

[0232] In the driver circuit of the third scan driver 323, each of at least some of the plurality of gate transistors T31, T32, T33, T34, T35, T36 and TC may be embodied as an N-type thin film transistor, and each of the rest of them may be embodied as a P-type thin film transistor. That is, the (3-5)th gate transistor T35 and the (3-6)th gate transistor T36 may be embodied as an N-type thin film transistor, and the other transistors therein may be embodied as a P-type thin film transistor. In addition, the N-type thin film transistor may be an oxide thin film transistor, and the P-type thin film transistor may be a polysilicon thin film transistor.

[0233] In this regard, a gate transistor embodied as an oxide thin film transistor or a polysilicon thin film transistor may be implemented in the same form in each layer of the oxide thin film transistor or the polysilicon thin film transistor in which the pixel circuit is disposed.

[0234] The (3-1)th gate transistor T31 may pull up the output terminal in response to the signal of the Q3 node, and the (3-2)th gate transistor T32 may pull down the output terminal in response to the signal of the QB3 node.

[0235] The (3-1)th clock signal SC3_GCLK1 may be connected to the gate node of the (3-3)th gate transistor T33 , and the (3-2)th clock signal SC3_GCLK2 may be connected to the gate node of the (3-6)th gate transistor T36 .

[0236] The (3-3)th gate transistor T33 may provide the third start signal SC3_VST or the scan signal SC3(n-1) of the previous stage to the Q31 node in response to the (3-1)th clock signal SC3_GCLK1. The (3-4)th gate transistor T34 may transmit the second gate high voltage to the QB3 node in response to the signal of the Q31 node.

[0237] The (3-6)th gate transistor T36 can be connected to the Q3 node and the gate node of the (3-5)th gate transistor T35 and arranged therebetween, and can be turned on in response to the (3-2)th clock signal SC3_GCLK2, and the (3-5)th gate transistor T35 can deliver the second gate low voltage VGL2 to the QB3 node.

[0238] In addition, the driver circuit may include a seventh capacitor CQ3 electrically connected to the Q3 node and the output terminal of the gate signal and disposed therebetween, and an eighth capacitor CQB3 electrically connected to the QB3 node and the input terminal of the second gate high voltage VGH2 and disposed therebetween. The seventh capacitor CQ3 and the eighth capacitor CQB3 may operate as bootstrap capacitors.

[0239] refer to Figure 8B In each of the (3-1)th clock signal SC3_GCLK1 and the (3-2)th clock signal SC3_GCLK2, one high level period and one low level period may constitute one period thereof, wherein the high level period is slightly longer than the low level period. However, for ease of description, an example will be described in which each of the high level period and the low level period is maintained for 1 horizontal period 1H during each of the periods ① to ⑨ specified in the accompanying drawings.

[0240] In the cycle immediately before cycle ①, the low level (3-1) clock signal SC3_GCLK1 can be applied to the driver circuit of the third scan driver 323, so that the (3-3) gate transistor T33 can be turned on, and the low level third start signal SC3_VST can be applied to the Q31 node.

[0241] Next, during period ①, the (3-1)th clock signal SC3_GCLK1 may be at a high level, the (3-2)th clock signal SC3_GCLK2 may be at a low level, and the third start signal SC3_VST may be at a high level. Since the (3-1)th clock signal SC3_GCLK1 is at a high level, the (3-3)th gate transistor T33 is turned off. Since the (3-2)th clock signal SC3_GCLK2 is at a low level, the (3-6)th gate transistor T36 may be turned on. In response to the second gate low voltage VGL2, the third transfer transistor TC may be continuously turned on. Since the third transfer transistor TC remains in the on state, the Q3 node may be at a low level like the Q31 node. Since the Q3 node is at a low level, the (3-1)th gate transistor T31 may be turned on, and the second gate low voltage VGL2 may be output.

[0242] During periods ②, ④ and ⑥, the (3-1)th clock signal SC3_GCLK1 may be at a low level, the (3-2)th clock signal SC3_GCLK2 may be at a high level, and the third start signal SC3_VST may be at a high level. Since the (3-1)th clock signal SC3_GCLK1 is at a low level, the (3-3)th gate transistor T33 may be turned on. Since the (3-2)th clock signal SC3_GCLK2 is at a high level, the (3-5)th gate transistor T35 and the (3-6)th gate transistor T36 may be turned on. The (3-5)th gate transistor T35 may be turned on, and thus when the second gate low voltage VGL2 is applied to the QB3 node, the (3-2)th gate transistor T32 may be turned on. Therefore, the second gate high voltage VGH2 may be output to the output terminal of the scan signal via the (3-2)th gate transistor T32.

[0243] During periods ③ and ⑤, the (3-1)th clock signal SC3_GCLK1 may be at a high level, the (3-2)th clock signal SC3_GCLK2 may be at a low level, and the third start signal SC3_VST may be at a high level.

[0244] The (3-3)th gate transistor T33 may be turned off based on the high level (3-1)th clock signal SC3_GCLK1. Since the (3-2)th clock signal SC3_GCLK2 is at a low level, the (3-5)th gate transistor T35 and the (3-6)th gate transistor T36 may be turned off.

[0245] In this regard, since each of the seventh capacitor CQ3 and the eighth capacitor CQB3 maintains the voltage stored during periods ②, ④, and ⑥, the Q3 node may be at a high level and the QB3 node may be at a low level. Therefore, the second gate high voltage VGH2 may be output to the output terminal of the scan signal via the (3-2)th gate transistor T32.

[0246] During period ⑦, the (3-1)th clock signal SC3_GCLK1 may be at a high level, the (3-2)th clock signal SC3_GCLK2 may be at a low level, and the third start signal SC3_VST may be at a low level. As in periods ③ and ⑤, during period ⑦, the second gate high voltage VGH2 may be output via the (3-2)th gate transistor T32 in response to the voltage stored in the seventh capacitor CQ3 and the eighth capacitor CQB3.

[0247] During the period ⑧, the (3-1)th clock signal SC3_GCLK1 may be at a low level, the (3-2)th clock signal SC3_GCLK2 may be at a high level, and the third start signal SC3_VST may be at a low level. Since the (3-1)th clock signal SC3_GCLK1 is at a low level, the (3-3)th gate transistor T33 may be turned on. In response to the Q31 node and the Q3 node being at a low level, the (3-1)th gate transistor T31 and the (3-4)th gate transistor T34 may be turned on, and a high-level second gate high voltage VGH2 may be applied to the QB3 node. Accordingly, the (3-2)th gate transistor T32 may be turned off, and the second gate low voltage VGL2 may be output to the output terminal of the scan signal via the (3-1)th gate transistor T31 in the on state.

[0248] During cycle ⑨, the (3-1)th clock signal SC3_GCLK1 may be at a high level, the (3-2)th clock signal SC3_GCLK2 may be at a low level, and the third start signal SC3_VST may be at a low level. The (3-3)th gate transistor T33 may be turned off based on the high level (3-1)th clock signal SC3_GCLK1. Since the (3-2)th clock signal SC3_GCLK2 is at a low level, the (3-5)th gate transistor T35 and the (3-6)th gate transistor T36 may be turned off. Accordingly, the Q31 node, the Q3 node, and the QB3 node may maintain the same state as during cycle ⑧, and the second gate low voltage VGL2 may be output via the (3-1)th gate transistor T31.

[0249] In this way, the driver circuit of the third scan driver 323 operates to output a high-level gate signal during the period ② to ⑥. In addition, during the period ② to ⑥, when the (3-2) clock signal SC3_GCLK2 is at a high level, the (3-5) gate transistor T35 and the (3-6) gate transistor T36 can be turned on. On the contrary, during the period ② to ⑥, when the (3-2) clock signal SC3_GCLK2 is at a low level, the (3-5) gate transistor T35 and the (3-6) gate transistor T36 can be turned off. Thus, although the driver circuit operates to continuously output a high-level gate signal, the threshold voltage of the (3-5) gate transistor T35 can be prevented from shifting. That is, the (3-5) gate transistor T35 having an oxide semiconductor layer that is susceptible to degradation caused by threshold voltage shift may not operate in an on state for a long time during periods ② to ⑥, but may be repeatedly turned on and off during periods ② to ⑥, thereby preventing screen defects that may occur in high temperature or high humidity environments.

[0250] In addition, in the driver circuit of the third scan driver 323, the (3-1)th clock signal SC3_GCLK1 and the third start signal SC3_VST may be applied to the (3-3)th gate transistor T33. The (3-5)th gate transistor T35 and the (3-6)th gate transistor T36 may be embodied as N-type thin film transistors having an oxide semiconductor layer. Thus, the driver circuit of the third scan driver 323 may not have a stabilizing capacitor, thereby reducing its power consumption.

[0251] Various examples and aspects of the present disclosure are described below. These are provided only as examples and do not limit the scope of the present disclosure.

[0252] One aspect of the present disclosure provides a display device, comprising: a display panel including a display area in which a plurality of pixels are arranged and a non-display area arranged around the display area; and a gate driver configured to receive a start signal and a clock signal and supply a gate signal to the display panel, wherein each of the plurality of pixels includes at least one first transistor and at least one second transistor, the at least one second transistor having characteristics different from those of the at least one first transistor, and wherein the gate driver includes at least one third transistor and at least one fourth transistor, the at least one fourth transistor having characteristics different from those of the at least one third transistor.

[0253] According to some features of the display device, the at least one first transistor includes a polysilicon semiconductor layer, and the at least one second transistor includes an oxide semiconductor layer.

[0254] According to some features of the display device, the at least one third transistor includes a polysilicon semiconductor layer, and the at least one fourth transistor includes an oxide semiconductor layer.

[0255] According to some features of the display device, the at least one first transistor is embodied as a P-type thin film transistor, and the at least one second transistor is embodied as an N-type thin film transistor.

[0256] According to some features of the display device, the at least one third transistor is embodied as a P-type thin film transistor, and the at least one fourth transistor is embodied as an N-type thin film transistor.

[0257] According to some features of the display device, the gate driver includes: a pull-up transistor configured to pull up the output terminal in response to a signal of a first control node; a pull-down transistor configured to pull down the output terminal in response to a signal of a second control node; and a fifth transistor as one of the at least one fourth transistors, wherein the fifth transistor is configured to deliver a gate voltage to the second control node, wherein each of the pull-up transistor and the pull-down transistor is embodied as a P-type thin film transistor, and the fifth transistor is embodied as an N-type thin film transistor.

[0258] According to some features of the display device, the gate driver also includes a sixth transistor as one of the at least one fourth transistor, and wherein the sixth transistor is configured to transmit the signal of the first control node to the gate electrode of the fifth transistor in response to a second clock signal.

[0259] According to some features of the display device, the gate driver further includes a bootstrap capacitor connected to the first control node and the output terminal and disposed therebetween.

[0260] According to some features of the display device, the sixth transistor is embodied as an N-type thin film transistor.

[0261] According to some features of the display device, the sixth transistor is configured to transmit the signal of the first control node to the gate electrode of the fifth transistor in response to the clock signal, wherein the fifth transistor is configured to transmit the gate voltage to the second control node in response to the signal of the first control node.

[0262] According to some features of the display device, the gate driver further includes a seventh transistor configured to transmit a start signal or a scan signal of a previous stage to the first node in response to the first clock signal.

[0263] According to some features of the display device, the gate driver further includes a transfer transistor configured to transfer the signal of the first node to the first control node in response to the gate voltage.

[0264] According to some features of the display device, the gate driver further includes an eighth transistor configured to transmit the gate voltage to the second control node in response to the signal of the first node.

[0265] According to some features of the display device, the start signal is applied to the gate driver via a signal line, and the signal line is different from a signal line via which the gate signal of the previous stage is applied to the gate driver.

[0266] According to some features of the display device, a power line is connected to the display area and the gate driver and is disposed therebetween.

[0267] According to some features of the display device, the power line includes a same material as a material of a source electrode or a drain electrode of the at least one first transistor or the at least one second transistor.

[0268] According to some features of the display device, the power line includes at least one of a first initialization voltage bus, a second initialization voltage bus, and a bias voltage bus.

[0269] According to some features of the display device, a DC voltage is applied to at least one pixel of the plurality of pixels via a power link line branched from the power line.

[0270] According to some features of the display device, at least a portion of the power link line includes a same material as a material of a gate electrode of the at least one first transistor or the at least one second transistor.

[0271] According to some features of the display device, at least a portion of the power link line includes a same material as a material of the touch electrode.

[0272] In one or more examples, the first control node may represent Figure 6B , 7B and Q1 node, Q2 node or Q3 node in 8A. In one or more examples, the second control node may represent Figure 6B , 7B and the QB1 node, QB2 node or QB3 node in 8A.

[0273] Although the embodiments of the present disclosure have been described with reference to the accompanying drawings, the present disclosure is not limited to the above embodiments, but can be implemented in various forms. Those skilled in the art will appreciate that the present disclosure can be practiced in other specific forms without changing the technical essence or basic features of the present disclosure. Therefore, it should be appreciated that the embodiments described above are not restrictive but illustrative in all aspects. The scope of protection of the present disclosure should be interpreted based on the attached claims, and all technical features within their equivalent ranges should be interpreted as included within the scope of the present disclosure.

Claims

1. A display device, comprising: A display panel, the display panel comprising a display area in which a plurality of pixels are arranged and a non-display area arranged around the display area; as well as a gate driver configured to receive a start signal and a clock signal and supply a gate signal to the display panel, wherein each of the plurality of pixels includes at least one first transistor and at least one second transistor, the at least one second transistor having characteristics different from those of the at least one first transistor, and The gate driver includes at least one third transistor and at least one fourth transistor, and the at least one fourth transistor has characteristics different from those of the at least one third transistor.

2. The display device according to claim 1, wherein: The at least one first transistor includes a polysilicon semiconductor layer, and the at least one second transistor includes an oxide semiconductor layer.

3. The display device according to claim 1, wherein: The at least one third transistor includes a polycrystalline silicon semiconductor layer, and the at least one fourth transistor includes an oxide semiconductor layer.

4. The display device according to claim 1, wherein: The at least one first transistor is embodied as a P-type thin film transistor, and the at least one second transistor is embodied as an N-type thin film transistor.

5. The display device according to claim 1, wherein: The at least one third transistor is embodied as a P-type thin film transistor, and the at least one fourth transistor is embodied as an N-type thin film transistor.

6. The display device according to claim 1, wherein: The gate driver comprises: a pull-up transistor configured to pull up the output terminal in response to a signal of the first control node; a pull-down transistor configured to pull down the output terminal in response to a signal of a second control node; and a fifth transistor as one of the at least one fourth transistor, wherein the fifth transistor is configured to deliver a gate voltage to the second control node, Wherein, each of the pull-up transistor and the pull-down transistor is embodied as a P-type thin film transistor, and the fifth transistor is embodied as an N-type thin film transistor.

7. The display device according to claim 6, wherein: The gate driver further includes a sixth transistor as one of the at least one fourth transistor, and wherein the sixth transistor is configured to transmit the signal of the first control node to a gate electrode of the fifth transistor in response to a second clock signal.

8. The display device according to claim 7, wherein: The gate driver also includes a bootstrap capacitor connected to the first control node and the output terminal and disposed therebetween.

9. The display device according to claim 7, wherein: The sixth transistor is embodied as an N-type thin film transistor.

10. The display device according to claim 7, wherein: The sixth transistor is configured to transmit the signal of the first control node to the gate electrode of the fifth transistor in response to the clock signal, and The fifth transistor is configured to transmit the gate voltage to the second control node in response to the signal of the first control node.

11. The display device according to claim 7, wherein: The gate driver further includes a seventh transistor configured to transmit a start signal or a scan signal of a previous stage to the first node in response to the first clock signal.

12. The display device according to claim 11, wherein: The gate driver further includes a pass transistor configured to transmit a signal of the first node to the first control node in response to the gate voltage.

13. The display device according to claim 12, wherein: The gate driver further includes an eighth transistor configured to transmit a second gate voltage to the second control node in response to the signal of the first node.

14. The display device according to claim 11, wherein: The start signal is applied to the gate driver via a signal line different from a signal line via which the gate signal of the previous stage is applied to the gate driver.

15. The display device according to claim 1, wherein: A power line is connected to the display area and the gate driver and is disposed therebetween.

16. The display device according to claim 15, wherein: The power line includes a same material as a material of a source electrode or a drain electrode of the at least one first transistor or the at least one second transistor.

17. The display device according to claim 15, wherein: The power line includes at least one of a first initialization voltage bus, a second initialization voltage bus, and a bias voltage bus.

18. The display device according to claim 15, wherein: A direct current voltage is applied to at least one of the plurality of pixels via a power link line branched from the power line.

19. The display device according to claim 18, wherein: At least a portion of the power link line includes a same material as a material of a gate electrode of the at least one first transistor or the at least one second transistor.

20. The display device according to claim 18, wherein: At least a portion of the power link line includes a same material as that of the touch electrodes.

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