Circuit device and display system

Abstract

A circuit device and a display system are provided. The circuit device includes an overlay processing circuit and an error detection circuit. The superimposition processing circuit superimposes the first input image data on a first region of the second input image data, and outputs the result of the superimposition processing as output image data. The error detection circuit calculates a first error code value corresponding to image data of a first region of output image data and a second error code value corresponding to image data of a second region of the output image data that does not overlap the first region. The error detection circuit performs error detection of the output image data by comparing the first error code value with the first expected value and comparing the second error code value with the second expected value.

Description

Technical Field

[0001] The present invention relates to a circuit device, a display system and the like. Background Art

[0002] Patent Document 1 discloses a video processing device that performs image error detection. The video processing device generates a synthesized image by replacing one or more regions of an input image with a synthesized image, and detects whether or not there is an abnormality in the synthesized image.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2022-153871

[0006] In image error detection, the expected value of the error code value and the error code value calculated based on the image are compared. When another image is synthesized with the input image, the expected value of the error code value cannot be obtained for the synthesized image. Therefore, there is a problem that the synthesized image cannot be properly error detected. Patent document 1 records that a CRC value is calculated for the OSD area of ​​the synthesized image and the calculated CRC value is compared with the expected CRC value, but it does not mention the area outside the OSD area. In addition, when the input image is divided into two or more images, there is also a problem that the divided images cannot be properly error detected. Summary of the invention

[0007] One embodiment of the present disclosure relates to a circuit device, which includes: an overlay processing circuit, which performs overlay processing on first input image data on a first area of ​​second input image data, and outputs the result of the overlay processing as output image data; and an error detection circuit, which calculates a first error code value corresponding to image data in the first area of ​​the output image data and a second error code value corresponding to image data in a second area of ​​the output image data that does not overlap with the first area, and compares the first error code value with a first expected value as an expected value of the first error code value, and compares the second error code value with a second expected value as an expected value of the second error code value, thereby performing error detection on the output image data.

[0008] In addition, another aspect of the present disclosure relates to a display system including: the above-mentioned circuit device; and a display device that displays the output image data. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 This is an example of the structure of an electronic device and a display system.

[0010] Figure 2 This is a first structural example of a circuit device.

[0011] Figure 3 It is a diagram for explaining the operation of the circuit device of the first structural example.

[0012] Figure 4 This is a second structural example of the circuit device.

[0013] Figure 5 This is a first flowchart example of the processing performed by the circuit device in the second structural example.

[0014] Figure 6 This is a second flowchart example of the processing performed by the circuit device in the second structural example.

[0015] Figure 7 The diagram is for explaining superimposition processing and area determination when the α channel is used.

[0016] Figure 8 This is a third structural example of the circuit device.

[0017] Fig. 9 This is a fourth structural example of the circuit device.

[0018] Fig.10 It is a diagram for explaining the operation of the circuit device of the fourth structural example.

[0019] Fig.11 is a diagram illustrating effective scanning lines for image segmentation.

[0020] Description of symbols

[0021] 100: Circuit device; 110: Overlay processing circuit; 120: Error detection circuit; 121: First area error determination circuit; 122: Second area error determination circuit; 123: First segmented image error determination circuit; 124: Second segmented image error determination circuit; 125: Error detection area determination circuit; 130: Interface circuit; 140: Interface circuit; 141: Interface circuit; 142: Interface circuit; 150: Expected value calculation circuit; 151: First expected value calculation circuit; 152: Second expected value calculation circuit; 153: First expected value calculation circuit; 154 : second expected value calculation circuit; 155: area determination circuit for expected value calculation; 156: image segmentation circuit for expected value calculation; 160: image segmentation circuit; 200: display device; 300: processing device; 400: display system; 500: electronic device; AR1: first area; AR2: second area; EV1: first expected value; EV2: second expected value; IM: input image data; IM1: first input image data; IM2: second input image data; IMD1: first segmented image data; IMD2: second segmented image data; IMQ: output image data. DETAILED DESCRIPTION

[0022] Hereinafter, preferred embodiments of the present disclosure will be described in detail. In addition, the present embodiment described below does not unduly limit the contents described in the claims, and all the structures described in the present embodiment are not necessarily essential structural elements.

[0023] 1. Electronic equipment and display systems

[0024] Figure 1 The electronic device 500 includes a processing device 300 and a display system 400. As an example, the electronic device 500 is a vehicle-mounted display device including an instrument panel, a central information display, a head-up display, or an electronic mirror, a television device, or an information processing device including a display.

[0025] The display system 400 includes the circuit device 100 and the display device 200. In addition, when the circuit device 100 has an image segmentation function, the display system 400 may include a plurality of display devices.

[0026] Image data is input from the processing device 300 to the circuit device 100. The processing device 300 is, for example, a processor such as a CPU, a microcomputer, a DSP, an ASIC, or an FPGA. CPU is the abbreviation of Central Processing Unit. DSP is the abbreviation of Digital Signal Processor. ASIC is the abbreviation of Application Specific Integrated Circuit. FPGA is the abbreviation of Field Programmable Gate Array.

[0027] The circuit device 100 is a display controller that performs display control of the display device 200. The circuit device 100 may also include a display driver that drives the display panel of the display device 200. The circuit device 100 is, for example, an integrated circuit device in which a plurality of circuit elements are integrated on a semiconductor substrate. In addition, the following describes the portion related to the image error detection of this embodiment, and the description of the display controller function and the display driver function is omitted.

[0028] The circuit device 100 receives first input image data and second input image data from the processing device 300. The circuit device 100 performs superposition processing on the first input image data and the second input image data, and sends the superimposed output image data to the display device 200. The circuit device 100 performs error detection on the output image data. Alternatively, the circuit device 100 receives input image data from the processing device 300, and divides the input image data into a plurality of divided image data. In this case, the display system 400 includes a plurality of display devices. The circuit device 100 sends each divided image data to a corresponding display device among the plurality of display devices. The circuit device 100 performs error detection on each divided image data. In any of the above cases, image data corresponding to a plurality of images are input to the circuit device 100. Such a method of transmitting image data corresponding to a plurality of images may also be any one of single-stream transmission and multi-stream transmission.

[0029] The display device 200 is a liquid crystal display device or an EL display device. EL is an abbreviation for Electro-Luminescence. As an example, when the display system 400 is mounted on a vehicle, the display device 200 is a cluster panel, a navigation display, or a head-up display. The display device 200 includes, for example, a display driver, a display panel, and a backlight. Alternatively, when the display device 200 is a head-up display, the display device 200 also includes a projection optical system.

[0030] 2. First Configuration Example and Second Configuration Example

[0031] Figure 2 The circuit device 100 includes an overlay processing circuit 110 , an error detection circuit 120 , an interface circuit 130 , and an interface circuit 140 . Figure 3 1 is a diagram for explaining the operation of the circuit device of the first structural example. The following shows an example of superimposing one foreground image on a background image, but two or more foreground images may also be superimposed on the background image. In this case, error detection may be performed on the background image and each foreground image.

[0032] The interface circuit 130 receives the first input image data IM1, the second input image data IM2, the first expected value EV1, and the second expected value EV2 from the processing device 300. The interface circuit 130 includes, for example, an image interface circuit of the OpenLVDS Display Interface standard, the Display Port standard, or the Display Serial Interface 2 standard of the Mobile Industry Processor Interface. In addition, the interface circuit 130 may also include an interface circuit of the Serial Peripheral Interface standard or the Inter-Integrated Circuit standard for communicating expected values.

[0033] The superimposition processing circuit 110 performs superimposition processing on the first input image represented by the first input image data IM1 in the first area AR1 of the second input image represented by the second input image data IM2, and outputs the result as the output image data IMQ. The superimposition processing here is as follows: the second input image is used as the background image, the first input image is used as the foreground image, and the first input image is superimposed on a part of the second input image. In addition, hereinafter, "the image represented by the image data" is also simply recorded as "image data". For example, it is recorded that the superimposition processing circuit 110 performs superimposition processing on the first input image data IM1 in the first area AR1 of the second input image data IM2. The first area AR1 can also be set from the processing device 300 via the interface circuit 130, or can be pre-set in a non-volatile memory not shown in the figure. The area other than the first area AR1 in the entire area of ​​the output image data IMQ is set as the second area AR2. The image of the first area AR1 is also called the foreground image, and the image of the second area AR2 is also called the background image. In addition, the second area AR2 can be any area as long as it does not overlap with the first area AR1. That is, when there are a plurality of foreground images to be superimposed, the second area AR2 is an area excluding the areas of the plurality of foreground images in the entire area of ​​the output image data IMQ.

[0034] The interface circuit 140 outputs the output image data IMQ to the display device 200. The interface circuit 140 may be an image interface circuit of the above-mentioned various standards.

[0035] The error detection circuit 120 uses the first expected value EV1 received by the interface circuit 130 to perform error detection on the image of the first area AR1 in the output image data IMQ. In addition, the error detection circuit 120 uses the second expected value EV2 received by the interface circuit 130 to perform error detection on the image of the second area AR2 in the output image data IMQ. The first expected value EV1 and the second expected value EV2 are calculated by the processing device 300. For example, the processing device 300 performs the following operation. Figure 4 The error detection circuit 120 includes an error detection area determination circuit 125 , a first area error determination circuit 121 , and a second area error determination circuit 122 .

[0036] The error detection area determination circuit 125 determines to which area each pixel of the output image data IMQ belongs. The first area AR1 is specified by information that can determine the coordinates of the pixel. For example, when the first area AR1 is a rectangle, the first area AR1 is specified by the coordinates of one vertex of the rectangle, the width of the rectangle, and the height of the rectangle. The output image data IMQ is, for example, stream data that sequentially transmits each pixel data. The error detection area determination circuit 125 is sequentially input with pixel data as stream data, and determines which of the first area AR1 and the second area AR2 the pixel belongs to based on the coordinates of the pixel corresponding to the pixel data and the information specifying the first area AR1. The error detection area determination circuit 125 outputs the pixel data determined to belong to the first area AR1 as the first output image data IMQ1, and outputs the pixel data determined to belong to the second area AR2 as the second output image data IMQ2.

[0037] The first area error determination circuit 121 calculates a first error code value based on the first output image data IMQ1, and compares the first error code value with the first expected value EV1. The first area error determination circuit 121 outputs the comparison result as the first error detection signal ER1 to the interface circuit 140. The second area error determination circuit 122 calculates a second error code value based on the second output image data IMQ2, and compares the second error code value with the second expected value EV2. The second area error determination circuit 122 outputs the comparison result as the second error detection signal ER2 to the interface circuit 140.

[0038] The error code value and the expected value use the same data error checking method. The data error checking method can be various methods, such as CRC, checksum, parity check or Hamming code. CRC is the abbreviation of Cyclic Redundancy Check.

[0039] When at least one of the first error detection signal ER1 and the second error detection signal ER2 indicates an error, the interface circuit 140 stops outputting the image data IMQ. In addition, the use of the error detection signal is not limited to this. For example, the circuit device 100 may also have a register storing the first error detection signal ER1 and the second error detection signal ER2. The processing device 300 may also read the first error detection signal ER1 and the second error detection signal ER2 from the register via the interface circuit 130. Alternatively, the superimposition processing circuit 110 may stop superimposition processing when at least one of the first error detection signal ER1 and the second error detection signal ER2 indicates an error.

[0040] Figure 4 This is a second configuration example of the circuit device. The circuit device 100 includes an expected value calculation circuit 150, an addition processing circuit 110, an error detection circuit 120, an interface circuit 130, and an interface circuit 140. Hereinafter, the parts different from the first configuration example will be mainly described.

[0041] The expected value calculation circuit 150 calculates a first expected value EV1 based on the first input image data IM1 and calculates a second expected value EV2 based on the second input image data IM2. The expected value calculation circuit 150 includes an expected value calculation region determination circuit 155, a first expected value calculation circuit 151, and a second expected value calculation circuit 152.

[0042] Figure 5 This is a first flowchart example of the processing performed by the circuit device in the second configuration example. In addition, the processing other than steps S6 to S8 can also be applied to the first configuration example.

[0043] In step S1 , an image is input to the circuit device 100 . That is, the interface circuit 130 receives first input image data IM1 and second input image data IM2 from the processing device 300 .

[0044] In step S2, the superimposition processing circuit 110 performs superimposition processing. That is, the superimposition processing circuit 110 performs superimposition processing on the first input image data IM1 and the second input image data IM2, and outputs the result as output image data IMQ.

[0045] In step S3, the error detection area determination circuit 125 determines the area to which each pixel of the output image data IMQ belongs based on the coordinates using the horizontal counter and the vertical counter. That is, the horizontal counter counts the coordinates of the pixels in the horizontal scanning line direction, and the vertical counter counts the coordinates of the pixels in the vertical scanning direction. The error detection area determination circuit 125 determines whether the coordinates of the pixels indicated by the outputs of the horizontal counter and the vertical counter belong to the first area AR1.

[0046] In step S4, the error detection area determination circuit 125 performs image segmentation. That is, the error detection area determination circuit 125 divides the output image data IMQ into first output image data IMQ1 and second output image data IMQ2 based on the result of the area determination in step S3. The second output image data IMQ2 is image data obtained by removing the image data of the first area AR1 from the output image data IMQ.

[0047] In step S5, the CRC value is calculated as the error code value. Note that, as described above, the error code value is not limited to the CRC value. Specifically, the first area error determination circuit 121 calculates the first error code value based on the first output image data IMQ1, and the second area error determination circuit 122 calculates the second error code value based on the second output image data IMQ2.

[0048] In step S6, the first expected value calculation circuit 151 generates an expected value by CRC calculation. In addition, as described above, the expected value is not limited to the CRC value. Specifically, the first expected value calculation circuit 151 calculates the first expected value EV1 based on the first input image data IM1.

[0049] In step S7, the expected value calculation area determination circuit 155 determines the area to which each pixel of the second input image data IM2 belongs based on the coordinates using the horizontal counter and the vertical counter. That is, the expected value calculation area determination circuit 155 determines whether the coordinates of the pixel indicated by the output of the horizontal counter and the vertical counter belong to the second area AR2.

[0050] In step S8, the second expected value calculation circuit 152 generates an expected value by CRC calculation. In addition, as described above, the expected value is not limited to the CRC value. Specifically, the second expected value calculation circuit 152 calculates the second expected value EV2 based on the image data of the second area AR2 in the second input image data IM2.

[0051] In step S9, the first area error determination circuit 121 and the second area error determination circuit 122 determine whether the CRC value is consistent with the expected value. That is, the first area error determination circuit 121 compares the first error code value with the first expected value EV1, and outputs the result as the first error detection signal ER1. The second area error determination circuit 122 compares the second error code value with the second expected value EV2, and outputs the result as the second error detection signal ER2.

[0052] When the CRC value is consistent with the expected value in step S9, the interface circuit 140 outputs the output image data IMQ in step S10. That is, when the first error code value is consistent with the first expected value EV1 and the second error code value is consistent with the second expected value EV2, the interface circuit 140 outputs the output image data IMQ.

[0053] If the CRC value is inconsistent with the expected value in step S9, the interface circuit 140 stops outputting the image data IMQ in step S11. That is, if either the first error code value is inconsistent with the first expected value EV1 or the second error code value is inconsistent with the second expected value EV2, the interface circuit 140 stops outputting the image data IMQ.

[0054] Figure 6 This is a second flowchart example of the processing performed by the circuit device in the second structural example. In addition, the processing other than steps S31 to S34 can also be applied to the first structural example. In the second flowchart example, in the error detection of the background image, the error code value and the expected value are calculated based on the image of the first area filled with the foreground image.

[0055] Steps S21 to S23 and Figure 5 Steps S1 to S3 are the same.

[0056] In step S24, the error detection area determination circuit 125 performs image segmentation. That is, the error detection area determination circuit 125 divides the image data of the first area AR1 in the output image data IMQ into small-screen image data based on the result of the area determination in step S23. As shown in step S25, the error detection area determination circuit 125 outputs the small-screen image data as the first output image data IMQ1.

[0057] As shown in step S26, the error detection area determination circuit 125 uses the output image data IMQ as full-screen image data.

[0058] In step S27, the error detection area determination circuit 125 determines the area to which each pixel of the full-screen image data belongs based on the coordinates using the horizontal counter and the vertical counter. That is, the error detection area determination circuit 125 determines whether the coordinates of the pixel indicated by the output of the horizontal counter and the vertical counter belong to the first area AR1. Alternatively, the result of step S23 may be used.

[0059] In step S28, the error detection area determination circuit 125 fills the first area AR1 in the full-screen image data and outputs the result as the second output image data IMQ2. Specifically, the error detection area determination circuit 125 embeds specific image data of the same image size as the first area AR1 in the first area AR1. The specific image data can be any image data as long as it is known image data that can calculate the expected value. As an example, the error detection area determination circuit 125 replaces the pixel data belonging to the first area AR1 with pixel data of a specified color. The specified color is, for example, black, but is not limited to this.

[0060] In step S29 , the first area error determination circuit 121 calculates a first error code value according to the small screen image data, ie, the first output image data IMQ1 .

[0061] In step S30 , the second area error determination circuit 122 calculates a second error code value according to the filled full-screen image data, ie, the second output image data IMQ2 .

[0062] In step S31 , the first expected value calculation circuit 151 calculates a first expected value EV1 according to the first input image data IM1 .

[0063] In step S32 , the expected value calculation area determination circuit 155 determines whether or not each pixel of the second input image data IM2 belongs to the first area AR1 based on the coordinates using the horizontal counter and the vertical counter.

[0064] In step S33, the expected value calculation area determination circuit 155 fills the first area AR1 in the second input image data IM2. Specifically, the expected value calculation area determination circuit 155 embeds specific image data in the first area AR1 of the second input image data IM2. The specific image data here is the same as the specific image data in step S28.

[0065] In step S34 , the second expected value calculation circuit 152 calculates the second expected value EV2 based on the filled second input image data IM2 .

[0066] Steps S35 to S37 and Figure 5 Steps S9 to S11 are the same.

[0067] Figure 7 This is a diagram for explaining superimposition processing and area determination when using the α channel. This method can be applied to any of the first configuration example and the second configuration example.

[0068] The interface circuit 130 receives the first input image data IM1, the second input image data IM2, and the α channel. The α channel is added to the first input image data IM1 as a foreground image, for example. The superimposition processing circuit 110 generates an α channel having the same number of pixels as the second input image data IM2 as a background image based on the information indicating the configuration position of the foreground image and the α channel. Alternatively, the α channel may be added to the second input image data IM2 from the beginning.

[0069] The superimposition processing circuit 110 performs superimposition processing on the first input image data IM1 and the second input image data IM2 using the α channel. The α channel sets a first value for the foreground portion and a second value for the background portion, for example. The second value is different from the first value. Figure 7The example in which the first value is "1" and the second value is "0" is shown. The overlay processing circuit 110 uses the pixel data of the first input image data IM1 for pixels having the first value set in the α channel, and uses the pixel data of the second input image data IM2 for pixels having the second value set in the α channel.

[0070] The error detection area determination circuit 125 and the expected value calculation area determination circuit 155 determine the area to which each pixel belongs based on the α channel. Figure 7 In the case of the α channel, the error detection area determination circuit 125 and the expected value calculation area determination circuit 155 determine the pixel with the first value "1" set in the α channel as the pixel of the first area AR1, and determine the pixel with the second value "0" set in the α channel as the pixel of the second area AR2.

[0071] In the present embodiment, the circuit device 100 includes an overlay processing circuit 110 and an error detection circuit 120. The overlay processing circuit 110 performs overlay processing on the first input image data IM1 on the first area AR1 of the second input image data IM2, and outputs the result of the overlay processing as the output image data IMQ. The error detection circuit 120 calculates a first error code value corresponding to the image data of the first area AR1 of the output image data IMQ and a second error code value corresponding to the image data of the second area AR2 of the output image data IMQ that does not overlap with the first area AR1. The error detection circuit 120 compares the first error code value with a first expected value EV1 as an expected value of the first error code value, and compares the second error code value with a second expected value EV2 as an expected value of the second error code value, thereby performing error detection on the output image data IMQ.

[0072] According to the present embodiment, it is possible to appropriately perform error detection on an image after superimposition processing. That is, for the image data of the first region AR1 in the output image data IMQ where superimposition is performed, error detection is performed by comparing the first error code value with the first expected value EV1. In addition, for the second region AR2 in the output image data IMQ where superimposition is not performed, error detection is performed by comparing the second error code value with the second expected value EV2. Through these error detections, it is possible to substantially perform error detection on the entire superimposed image.

[0073] In addition, you can also Figure 6 As described in , the error detection circuit 120 calculates the second error code value based on the image data in the second area AR2 of the output image data IMQ and the specific image data embedded in the first area AR1 of the output image data IMQ.

[0074] According to the present embodiment, by calculating the second error code value based on the output image data IMQ in which the specific image data is embedded in the first area AR1, it is possible to perform error detection on the second area AR2 of the output image data IMQ. That is, the specific image data is known image data used for calculating the second expected value EV2, and the second expected value is calculated based on the output image data IMQ in which the specific image data is embedded in the first area AR1. Furthermore, by comparing the second error code value with the second expected value EV2, it is possible to perform error detection on the second area AR2.

[0075] In addition, you can also Figure 5 As described in , the error detection circuit 120 calculates the second error code value based on the image data of the second area AR2 obtained by removing the image data of the first area AR1 from the output image data IMQ.

[0076] According to this embodiment, the output image data IMQ obtained by removing the image data of the first area AR1 is the image data of the second area AR2 itself. By comparing the second error code value calculated based on the image data of the second area AR2 with the second expected value EV2, error detection of the second area AR2 can be performed.

[0077] In addition, in the present embodiment, the error detection circuit 120 includes an error detection area determination circuit 125, a first area error determination circuit 121, and a second area error determination circuit 122. The error detection area determination circuit 125 determines whether each pixel of the output image data IMQ belongs to the first area AR1 or the second area AR2. The first area error determination circuit 121 calculates a first error code value for a pixel determined to belong to the first area AR1, and compares the first error code value with a first expected value EV1. The second area error determination circuit 122 calculates a second error code value for a pixel determined to belong to the second area AR2, and compares the second error code value with a second expected value EV2.

[0078] According to the present embodiment, the output image data IMQ can be divided into image data of the first area AR1 and image data of the second area AR2 by performing area determination by the error detection area determination circuit 125. Furthermore, the first area error determination circuit 121 can calculate a first error code value based on the result of the area determination, and the second area error determination circuit 122 can calculate a second error code value based on the result of the area determination.

[0079] In addition, you can also Figure 3 As described in etc., the error detection area determination circuit 125 determines whether each pixel of the output image data IMQ belongs to the first area AR1 or the second area AR2 based on the coordinate information of the first area AR1.

[0080] The coordinate information of the first area AR1 specifies the coordinates of the superimposed first input image data IM1. Since the area where the first input image data IM1 is superimposed is the first area AR1, the error detection area determination circuit 125 can determine the area to which each pixel belongs based on the coordinate information of the first area AR1.

[0081] In addition, you can also Figure 7 As described in , the error detection area determination circuit 125 determines whether each pixel of the output image data IMQ belongs to the first area AR1 or the second area AR2 based on the α channel that sets a first value for pixels belonging to the first area AR1 and a second value for pixels belonging to the second area AR2.

[0082] According to the present embodiment, an image of an arbitrary shape can be superimposed by using the α channel, and the α channel can be used to determine the first area AR1 of an arbitrary shape on which the image is superimposed.

[0083] In addition, in this embodiment, the circuit device 100 may also include an interface circuit 130. Figure 2 As described in , etc., the interface circuit 130 receives first input image data IM1, second input image data IM2, a first expected value EV1, and a second expected value EV2 from the outside.

[0084] According to this embodiment, the interface circuit 130 can receive the first expected value EV1 and the second expected value EV2 calculated externally, and the error detection circuit 120 can perform error detection on the output image data IMQ using the received first expected value EV1 and the second expected value EV2.

[0085] In addition, you can also Figure 4 As described in , etc., the circuit device 100 includes an expected value calculation circuit 150. The expected value calculation circuit 150 may calculate a first expected value EV1 and a second expected value EV2 based on the first input image data IM1 and the second input image data IM2.

[0086] According to the present embodiment, the first expected value EV1 and the second expected value EV2 can be calculated inside the circuit device 100 , and the error detection circuit 120 can perform error detection on the output image data IMQ using the calculated first expected value EV1 and second expected value EV2 .

[0087] In addition, in the present embodiment, the expected value calculation circuit 150 includes a first expected value calculation circuit 151, an expected value calculation area determination circuit 155, and a second expected value calculation circuit 152. The first expected value calculation circuit 151 calculates a first expected value EV1 based on the first input image data IM1. The expected value calculation area determination circuit 155 determines whether each pixel of the second input image data IM2 belongs to the second area AR2. The second expected value calculation circuit 152 calculates a second expected value EV2 for the pixel of the second input image data IM2 determined to belong to the second area AR2.

[0088] According to the present embodiment, the image data of the second area AR2 can be divided from the output image data IMQ by performing area determination by the expected value calculation area determination circuit 155. Furthermore, the second expected value calculation circuit 152 can calculate the second expected value EV2 based on the result of the area determination.

[0089] In this embodiment, the display system 400 includes a circuit device 100 and a display device 200 for displaying output image data IMQ. The display device 200 may also be a head-up display, an instrument panel, a central information display, or an electronic mirror.

[0090] A head-up display, an instrument panel, a central information display, or an electronic mirror is mounted on a mobile body such as a car. In a display device mounted on a mobile body, a so-called picture-in-picture technique of superimposing another image on an image is used. For example, another image is inserted into a local area of ​​an image, or a display object such as an icon is superimposed on an image or an image. According to this embodiment, even when a picture-in-picture is used, it is possible to appropriately detect errors in a displayed image.

[0091] 3. Third and fourth configuration examples

[0092] Figure 8 The third structural example of the circuit device is shown in FIG. 1. The circuit device 100 includes an image segmentation circuit 160, an error detection circuit 120, an interface circuit 130, an interface circuit 141, and an interface circuit 142. The following describes an example of separating the input image data IM into image data of two screens, but the input image data IM may also be separated into image data of three or more screens. Figure 1 The display device 200 includes a first display device and a second display device.

[0093] The interface circuit 130 receives the input image data IM, the first expected value EV1, and the second expected value EV2 from the processing device 300. The first expected value EV1 and the second expected value EV2 are calculated by the processing device 300. For example, the processing device 300 performs communication with the following Fig. 9 The expected value operation circuit 150 performs the same operation.

[0094] The image segmentation circuit 160 performs image segmentation processing. That is, the image segmentation circuit 160 separates the input image data IM into the first segmented image data IMD1 and the second segmented image data IMD2. For example, the interface circuit 130 receives the input image data IM in which the first segmented image and the second segmented image are connected as one image through a single-stream transmission. The image segmentation circuit 160 separates the first segmented image data IMD1 and the second segmented image data IMD2 from the single-stream input image data IM. Alternatively, the interface circuit 130 receives the input image data IM through multi-stream transmission. The multi-stream input image data IM includes the first segmented image data IMD1 and the second segmented image data IMD2 transmitted in a time-division manner. The image segmentation circuit 160 separates the first segmented image data IMD1 and the second segmented image data IMD2 from the multi-stream input image data IM.

[0095] The interface circuit 141 outputs the first divided image data IMD1 to the first display device, and the interface circuit 142 outputs the second divided image data IMD2 to the second display device.

[0096] The error detection circuit 120 includes a first segmented image error determination circuit 123 and a second segmented image error determination circuit 124. The first segmented image error determination circuit 123 calculates a first error code value based on the first segmented image data IMD1, compares the first error code value with a first expected value EV1, and outputs the result as a first error detection signal ER1 to the interface circuit 141. The second segmented image error determination circuit 124 calculates a second error code value based on the second segmented image data IMD2, compares the second error code value with a second expected value EV2, and outputs the result as a second error detection signal ER2 to the interface circuit 142.

[0097] The error code value and the expected value use the same data error checking mode code. As mentioned above, the data error checking mode can be various modes, such as CRC, checksum, parity check or Hamming code mode.

[0098] The interface circuit 141 stops outputting the first segmented image data IMD1 when the first error detection signal ER1 indicates an error. The interface circuit 142 stops outputting the second segmented image data IMD2 when the second error detection signal ER2 indicates an error. In addition, the use of the error detection signal is not limited thereto. For example, the circuit device 100 may also include a register storing the first error detection signal ER1 and the second error detection signal ER2. The processing device 300 may also read the first error detection signal ER1 and the second error detection signal ER2 from the register via the interface circuit 130. Alternatively, the image segmentation circuit 160 may stop the image segmentation processing when at least one of the first error detection signal ER1 and the second error detection signal ER2 indicates an error.

[0099] Fig. 9 The circuit device 100 includes an expected value calculation circuit 150 , an image segmentation circuit 160 , an error detection circuit 120 , an interface circuit 130 , an interface circuit 141 , and an interface circuit 142 . Fig.10 1 is a diagram for explaining the operation of the circuit device of the fourth structural example. Here, an example is shown in which the number of effective scanning lines of the first divided image data and the second divided image data is different, but the number of effective scanning lines of the first divided image data and the second divided image data may be the same. The following mainly describes the parts that are different from the third structural example.

[0100] The expected value calculation circuit 150 includes a first expected value calculation circuit 153 , a second expected value calculation circuit 154 , and an expected value calculation image segmentation circuit 156 .

[0101] The image segmentation circuit 156 for expected value calculation separates the input image data IM into first expected value segmented image data IMV1 and second expected value segmented image data IMV2. The separation method is the same as that of the image segmentation circuit 160. Specifically, the image segmentation circuit 160 separates the first area ARD1 of the input image data IM into the first segmented image data IMD1, and separates the second area ARD2 of the input image data IM into the second segmented image data IMD2. At this time, the image segmentation circuit 156 for expected value calculation separates the first area ARD1 of the input image data IM into the first expected value segmented image data IMV1, and separates the second area ARD2 of the input image data IM into the second expected value segmented image data IMV2.

[0102] The first expected value calculation circuit 153 calculates a first expected value EV1 based on the first expected value divided image data IMV1. The second expected value calculation circuit 154 calculates a second expected value EV2 based on the second expected value divided image data IMV2.

[0103] Fig.11The diagram is a diagram for explaining effective scanning lines for image segmentation. The number of scanning lines of the first display device displaying the first segmented image data IMD1 is m, and the number of scanning lines of the second display device displaying the second segmented image data IMD2 is n. Both m and n are integers greater than 1, and m<n.

[0104] The number of effective scanning lines of the input image data IM is n. The input image data IM is divided into left and right parts according to the specified number of horizontal pixels, and the left side is set as the first area ARD1, and the right side is set as the second area ARD2. The number of scanning lines of the first area ARD1 is n, where m is the number of effective scanning lines. The number of effective scanning lines of the second area ARD2 is the same as the number of effective scanning lines of the input image data IM, which is n.

[0105] At this time, the first divided image error determination circuit 123 uses the data of the valid scanning line m other than the ineffective scanning line nm in the first area ARD1 as the first divided image data IMD1. Similarly, the first expected value calculation circuit 153 uses the data of the valid scanning line m other than the ineffective scanning line nm in the first area ARD1 as the first expected value divided image data IMV1.

[0106] The second divided image error determination circuit 124 uses the data of the effective scanning line n of the second area ARD2 as the second divided image data IMD2. Similarly, the second expected value calculation circuit 154 uses the data of the effective scanning line n of the second area ARD2 as the second expected value divided image data IMV2.

[0107] In the present embodiment, the circuit device 100 includes an image segmentation circuit 160 and an error detection circuit 120. The image segmentation circuit 160 segments the input image data IM into first segmented image data IMD1 and second segmented image data IMD2. The error detection circuit 120 calculates a first error code value based on the first segmented image data IMD1, and compares the first error code value with a first expected value EV1 as an expected value of the first error code value, thereby performing error detection on the first segmented image data IMD1. The error detection circuit 120 calculates a second error code value based on the second segmented image data IMD2, and compares the second error code value with a second expected value EV2 as an expected value of the second error code value, thereby performing error detection on the second segmented image data IMD2.

[0108] According to the present embodiment, error detection can be appropriately performed on the segmented images. That is, error detection is performed on the first segmented image data IMD1 separated from the input image data IM by comparing the first error code value and the first expected value EV1. In addition, error detection is performed on the second segmented image data IMD2 separated from the input image data IM by comparing the second error code value and the second expected value EV2. Thus, error detection is performed on each segmented image, and thus error detection is substantially performed on the entire input image data IM.

[0109] In addition, in this embodiment, the circuit device 100 includes an interface circuit 130. Figure 8 As described in , the interface circuit 130 receives input image data IM, a first expected value EV1, and a second expected value EV2 from the outside.

[0110] According to this embodiment, the interface circuit 130 is capable of receiving a first expected value EV1 and a second expected value EV2 calculated externally, and the error detection circuit 120 is capable of using the received first expected value EV1 to perform error detection on the first segmented image data IMD1, and using the received second expected value EV2 to perform error detection on the second segmented image data IMD2.

[0111] In addition, you can also Fig. 9 As described in , the circuit device 100 includes an expected value calculation circuit 150 for calculating a first expected value EV1 and a second expected value EV2. Fig.11 As described in , the number m of effective scanning lines of the first divided image data IMD1 is smaller than the number n of effective scanning lines of the second divided image data IMD2. The expected value calculation circuit 150 may exclude pixels of ineffective scanning lines of the first divided image data IMD1 in the input image data IM from the calculation of the first expected value EV1.

[0112] According to this embodiment, even when the number m of effective scanning lines of the first display device displaying the first divided image data IMD1 is smaller than the number n of effective scanning lines of the second display device displaying the second divided image data IMD2, the first expected value EV1 can be calculated based on the pixels of the effective scanning lines.

[0113] In addition, the present embodiment is described in detail as described above, but those skilled in the art can easily understand that many modifications can be made without substantially departing from the new matters and effects of the present disclosure. Therefore, all such modifications are included in the scope of the present disclosure. For example, in the specification or the drawings, a term recorded at least once together with a different term in a broader sense or with the same meaning can be replaced with the different term in any part of the specification or the drawings. In addition, all combinations of the present embodiment and the modifications are also included in the scope of the present disclosure. In addition, the structures and actions of the superposition processing circuit, the image segmentation circuit, the error detection circuit, the expected value operation circuit, the interface circuit, the circuit device, the display device, the processing device, and the display system are not limited to the contents described in the present embodiment, and various modifications can be implemented.

Claims

1. A circuit device, characterized in that: The circuit device comprises: an overlay processing circuit for overlaying the first input image data on the first region of the second input image data and outputting the result of the overlay processing as output image data; as well as An error detection circuit calculates a first error code value corresponding to the image data of the first area of ​​the output image data and a second error code value corresponding to the image data of the second area of ​​the output image data that does not overlap with the first area, and compares the first error code value with a first expected value that is an expected value of the first error code value, and compares the second error code value with a second expected value that is an expected value of the second error code value, thereby performing error detection on the output image data.

2. The circuit arrangement according to claim 1, characterized in that The error detection circuit calculates the second error code value based on the image data in the second area of ​​the output image data and the specific image data embedded in the first area of ​​the output image data.

3. The circuit arrangement according to claim 1, characterized in that The error detection circuit calculates the second error code value based on the image data of the second area obtained by removing the image data of the first area from the output image data.

4. The circuit arrangement according to claim 1, characterized in that The error detection circuit comprises: an error detection region determination circuit for determining whether each pixel of the output image data belongs to the first region or the second region; a first area error determination circuit that calculates the first error code value for the pixel determined to belong to the first area and compares the first error code value with the first expected value; as well as The second area error determination circuit calculates the second error code value for the pixel determined to belong to the second area, and compares the second error code value with the second expected value.

5. The circuit arrangement according to claim 4, characterized in that The error detection region determination circuit determines whether each pixel of the output image data belongs to the first region or the second region based on the coordinate information of the first region.

6. The circuit arrangement according to claim 4, characterized in that The error detection area determination circuit determines whether each pixel of the output image data belongs to the first area or the second area based on an alpha channel that sets a first value for pixels belonging to the first area and a second value for pixels belonging to the second area.

7. The circuit arrangement according to claim 1, characterized in that The circuit device includes an interface circuit that receives the first input image data, the second input image data, the first expected value, and the second expected value from the outside.

8. The circuit arrangement according to claim 1, characterized in that The circuit device includes an expected value calculation circuit that calculates the first expected value and the second expected value based on the first input image data and the second input image data.

9. The circuit arrangement according to claim 8, characterized in that The expected value operation circuit comprises: A first expected value calculation circuit, which calculates the first expected value according to the first input image data; an expected value calculation region determination circuit for determining whether each pixel of the second input image data belongs to the second region; as well as A second expected value calculation circuit calculates the second expected value of the pixel determined to belong to the second area with respect to the second input image data.

10. A circuit device, characterized in that: The circuit device comprises: An image segmentation circuit that segments first segmented image data and second segmented image data from input image data; and An error detection circuit calculates a first error code value based on the first segmented image data, compares the first error code value with a first expected value which is an expected value of the first error code value, thereby performing error detection on the first segmented image data, and calculates a second error code value based on the second segmented image data, compares the second error code value with a second expected value which is an expected value of the second error code value, thereby performing error detection on the second segmented image data.

11. The circuit arrangement according to claim 10, characterized in that The circuit device includes an interface circuit that receives the input image data, the first expected value, and the second expected value from the outside.

12. The circuit arrangement according to claim 10, characterized in that The circuit device includes an expected value calculation circuit, the expected value calculation circuit calculating the first expected value and the second expected value based on the input image data, The number of effective scanning lines of the first divided image data is smaller than the number of effective scanning lines of the second divided image data. The expected value calculation circuit excludes pixels of ineffective scanning lines of the first divided image data in the input image data from calculation of the first expected value.

13. A display system, characterized in that: The display system comprises: The circuit arrangement of any one of claims 1 to 9; and A display device displays the output image data.

14. The display system according to claim 13, characterized in that: The display device is a head-up display, an instrument panel, a central information display or an electronic mirror.

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