An LCD pixel driving circuit for color sequential display

Abstract

The application discloses an LCD pixel driving circuit for color sequential display, which comprises a first transistor, a pre-storage capacitor, a second transistor, a holding capacitor, a third transistor and a liquid crystal capacitor, the first source-drain electrode of the first transistor is coupled to a data signal line, the gate electrode is coupled to a control signal line, and the second source-drain electrode is coupled to the first source-drain electrode of the second transistor and one end of the pre-storage capacitor; the gate electrode of the second transistor is coupled to a transfer signal line, and the second source-drain electrode is coupled to the first source-drain electrode of the third transistor, one end of the holding capacitor and one end of the liquid crystal capacitor; one end of the pre-storage capacitor, the holding capacitor and the liquid crystal capacitor away from the transistor is coupled to a first common electrode line or a second common electrode line; the gate electrode of the third transistor is coupled to a first reset signal line or a second reset signal line, and the second source-drain electrode is coupled to the first common electrode line or the first common electrode line.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of pixel driving, in particular to an LCD pixel driving circuit for color sequential display. BACKGROUND

[0002] In field sequential or color sequential display technology, all picture data writing must be completed and the liquid crystal must be deflected to a stable state before the backlight is turned on, otherwise picture confusion will occur. Therefore, the data writing and liquid crystal deflection time greatly compresses the backlight on time, resulting in problems such as difficulty in improving display screen brightness, difficulty in improving refresh rate and resolution, increased power consumption, and increased cost of backlight material.

[0003] A conventional pixel driving circuit, with reference to Figure 7 (Canon's pixel driving circuit in U.S. Patent No. 6181311), which is different from the conventional 1T2C pixel design in that, in addition to the pixel signal writing switch TFT T1, there is a data storage capacitor Cs1, a signal transfer TFT T2, and a reset TFT T3. The signal storage capacitor Cs1 is used to pre-store the pixel data voltage required for the next picture. The signal transfer TFT T2 is used to transfer the pixel data voltage pre-stored in the signal storage capacitor Cs1 to the corresponding pixel voltage storage capacitor Cs2 and the liquid crystal capacitor Clc. The reset TFT T3 is used to eliminate the charge originally remaining on the pixel capacitor, so as to prevent effects such as color deviation and brightness difference caused by residual charge. This circuit design can pre-store the pixel data voltage of the next frame of picture in the signal storage capacitor Cs1 during the backlight illumination time, and when switching pictures, all pixels synchronously read the pixel data voltage in the aforementioned corresponding Cs1. Through this pixel data voltage buffer design, the pixel data writing time can be saved, and the backlight illumination time can be correspondingly increased.

[0004] However, this pixel circuit design faces the problem of voltage reduction accompanied by charge sharing. Assuming that the pre-charge capacitor Cs1 = Cs2 + Clc, Vcom = 0V (i.e., the pixel electrode is reset to 0V before charging), if Clc is to be charged to 5V, then according to the principle of charge conservation, Cs1 needs to be pre-charged to 10V to achieve this. Therefore, this driving method requires an increased range of Data voltage supply to meet the working voltage range of the liquid crystal, which puts higher requirements on the output voltage range of the Source IC, and greatly increases the power consumption. When the Source IC does not meet the requirements, a larger Cs1 capacitor is needed. When Cs1 is much larger than Cs2 + Clc, the voltage drop during charge sharing will be smaller, but this will also reduce the aperture ratio and increase the difficulty of pre-charging Cs1, which is not conducive to the realization of high refresh rate and high resolution.

[0005] In summary, the conventional pixel driving circuit has the problems of low aperture ratio and high driving difficulty. SUMMARY

[0006] In view of the above, the present application provides an LCD pixel driving circuit for color sequential display, which solves the problems of low aperture ratio and high driving difficulty of the conventional pixel driving circuit by improving the circuit structure and corresponding driving timing.

[0007] To solve the above problems, the technical scheme of the present application is an LCD pixel driving circuit for color sequential display, which at least comprises: a first pixel driving unit and a second pixel driving unit, the first pixel driving unit and the second pixel driving unit each comprising a first transistor, a pre-storage capacitor, a second transistor, a holding capacitor, a third transistor and a liquid crystal capacitor, wherein the first source / drain electrode of the first transistor is coupled to a data signal line, the gate electrode is coupled to a control signal line, and the second source / drain electrode is coupled to the first source / drain electrode of the second transistor and one end of the pre-storage capacitor; the gate electrode of the second transistor is coupled to a transfer signal line, the second source / drain electrode is coupled to the first source / drain electrode of the third transistor, one end of the holding capacitor and one end of the liquid crystal capacitor; the ends of the pre-storage capacitor, the holding capacitor and the liquid crystal capacitor of the first pixel driving unit away from the transistor are coupled to a first common electrode line, and the ends of the pre-storage capacitor, the holding capacitor and the liquid crystal capacitor of the second pixel driving unit away from the transistor are coupled to a second common electrode line; the gate electrode of the third transistor of the first pixel driving unit is coupled to a first reset signal line, and the second source / drain electrode is coupled to the second common electrode line; the gate electrode of the third transistor of the second pixel driving unit is coupled to a second reset signal line, and the second source / drain electrode is coupled to the first common electrode line.

[0008] Optionally, during the backlight-on time, the first transistor is controlled to be turned on based on the control signal, the first transistor outputs a pre-charge voltage based on the data signal and stores it to the pre-storage capacitor, until the voltage pre-storage of all pixels is completed.

[0009] Optionally, during the backlight-off time of the Nth frame: first, after the second common voltage jumps to high potential, the first reset signal jumps to high potential, and the third transistor completes the reset of the liquid crystal capacitor and the holding capacitor of the first pixel driving unit; after the first reset signal jumps back to low potential and the second common voltage jumps back to normal potential, the first common voltage jumps to low potential, and then the second reset signal jumps to high potential, completing the reset of the second pixel driving unit; after the second reset signal jumps back to low potential and the first common voltage jumps back to normal potential, the transfer signal jumps to high potential, and the second transistor forms the voltage required for the liquid crystal to flip the target angle on the liquid crystal capacitor; when entering the N+1th frame, the backlight is turned on.

[0010] Optionally, when the backlight is turned off in the N+1th frame: first, the second common voltage jumps to low potential, then the first reset signal jumps to high potential, and the liquid crystal capacitor and the holding capacitor of the first pixel driving unit are reset based on the third transistor; after the first reset signal jumps back to low potential and the second common voltage jumps back to normal potential, the first common voltage jumps to high potential, then the second reset signal jumps to high potential, and the reset of the second pixel driving unit is completed; after the second reset signal jumps back to low potential and the first common voltage jumps back to normal potential, the transfer signal jumps to high potential, and the voltage required for the liquid crystal to form the target angle of rotation on the liquid crystal capacitor is formed based on the second transistor; when entering the N+2th frame, the backlight is turned on.

[0011] Optionally, when the backlight is turned on in the Nth frame, the data signal of the first pixel driving unit is configured as a positive polarity potential, and the data signal of the second pixel driving unit is configured as a negative polarity potential; when the backlight is turned on in the N+1th frame, the data signal of the first pixel driving unit is configured as a negative polarity potential, and the data signal of the second pixel driving unit is configured as a positive polarity potential.

[0012] Optionally, the LCD pixel driving circuit can be further configured such that the gate of the third transistor of the first pixel driving unit and the gate of the third transistor of the second pixel driving unit are both coupled to the same reset signal line.

[0013] Optionally, when the second common voltage jumps to high potential and the first common voltage jumps to low potential, or the second common voltage jumps to low potential and the first common voltage jumps to high potential, the first reset signal jumps to high potential, and the reset of the liquid crystal capacitor and the holding capacitor of the first pixel driving unit and the second pixel driving unit is completed synchronously.

[0014] Optionally, the LCD pixel driving circuit can be further configured such that the pre-storage capacitor, the holding capacitor and the liquid crystal capacitor of the first pixel driving unit and the second pixel driving unit are coupled to the same common electrode line away from one end of the transistor; the second source / drain of the third transistor of the first pixel driving unit is coupled to the first global signal line, and the second source / drain of the third transistor of the second pixel driving unit is coupled to the second global signal line.

[0015] Optionally, when the data signal of the first pixel driving unit is configured as a positive polarity potential and the data signal of the second pixel driving unit is configured as a negative polarity potential, the first global signal in the frame is configured as a high potential and the second global signal is configured as a low potential; when the data signal of the first pixel driving unit is configured as a negative polarity potential and the data signal of the second pixel driving unit is configured as a positive polarity potential, the first global signal in the frame is configured as a low potential and the second global signal is configured as a high potential.

[0016] Optionally, the high potential of the global signal is configured as: common voltage + maximum working voltage of liquid crystal; and the low potential of the global signal is configured as: common voltage - maximum working voltage of liquid crystal.

[0017] The primary improvement of the present application is to provide an LCD pixel driving circuit for color sequential display, by pre-storing a capacitor design, the data signal voltage writing and light emitting are simultaneously performed under color sequential display, while increasing the light emitting time, the present application optimizes the pixel electrode reset circuit, such as multiplexing the Vcom signal line, or adding an additional reset signal source to reset the pixel electrode, so that the positive and negative polarity corresponding pixel electrodes can be reset to different potentials, the required charge for writing pixel data voltage by Cs1 of each row of pixels is reduced, thereby reducing the required data signal voltage range, reducing the driving difficulty and Source IC power consumption, and the additional signal line is introduced less, which does not significantly increase the pixel layout complexity (has less influence on the aperture ratio), and solves the problems of low aperture ratio and large driving difficulty of the traditional pixel driving circuit. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 is a simplified circuit diagram of the LCD pixel driving circuit for color sequential display of the present application;

[0019] Figure 2 is a driving timing diagram of the LCD pixel driving circuit for color sequential display of the present application;

[0020] Figure 3 is a simplified circuit diagram of the LCD pixel driving circuit for color sequential display of a preferred embodiment of the present application;

[0021] Figure 4 is a driving timing diagram of the LCD pixel driving circuit for color sequential display of a preferred embodiment of the present application;

[0022] Figure 5 is a simplified circuit diagram of the LCD pixel driving circuit for color sequential display of another preferred embodiment of the present application;

[0023] Figure 6is a driving timing diagram of an LCD pixel driving circuit for color sequential display, which is another preferred embodiment of the present application;

[0024] Figure 7 is a circuit and a driving timing diagram of prior art shown in the background of the present application. Embodiments

[0025] In order to make the skilled in the art better understand the technical solutions of the present application, the present application will be further described in detail below with the accompanying drawings and specific embodiments.

[0026] In order to make the skilled in the art better understand the technical solutions of the present application, the present application will be further described in detail below with the accompanying drawings and specific embodiments.

[0027] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but only represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts fall within the scope of the present application.

[0028] The embodiments of the technical solutions of the present application will be described in detail below with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present application, and therefore only serve as examples, and cannot limit the protection scope of the present application.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs; the terms used herein are only for the purpose of describing specific embodiments of the present application, and are not intended to limit the present application; the terms "include" and "have" and any variations thereof in the specification and claims of the present application and the above description of drawings are intended to cover non-exclusive inclusion.

[0030] In the description of the embodiments of the present application, the technical terms "first", "second", etc. are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number, specific order or primary and secondary relationship of the indicated technical features. In the description of the embodiments of the present application, the meaning of "a plurality of" is two or more, unless otherwise explicitly and specifically limited.

[0031] Reference to an "embodiment" herein means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily mutually exclusive of one another. As will be apparent to those of ordinary skill in the art, embodiments described herein can be combined with one another.

[0032] In the description of the embodiments of the present application, the term "and / or" is merely an association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the three cases of A existing alone, A and B existing together, and B existing alone. In addition, the character " / " herein generally represents an "or" relationship between the front and rear associated objects. Embodiments

[0033] Specifically, as shown in Figure 1 An LCD pixel driving circuit for color sequential display, characterized in that it comprises at least: a first pixel driving unit and a second pixel driving unit, the first pixel driving unit and the second pixel driving unit each comprising a first transistor T1, a pre-storage capacitor Cs1, a second transistor T2, a holding capacitor Cs2, a third transistor T3, and a liquid crystal capacitor Clc, wherein the first source / drain of the first transistor T1 is coupled to a data signal line Data, the gate is coupled to a control signal line Scan, and the second source / drain is coupled to the first source / drain of the second transistor T2 and one end of the pre-storage capacitor Cs1; the gate of the second transistor T2 is coupled to a transfer signal line Tran, the second source / drain is coupled to the first source / drain of the third transistor T3, one end of the holding capacitor Cs2, and one end of the liquid crystal capacitor Clc; one end of the pre-storage capacitor Cs1, the holding capacitor Cs2, and the liquid crystal capacitor Clc of the first pixel driving unit away from the transistor is coupled to a first common electrode line Vcom-Odd, and one end of the pre-storage capacitor Cs1, the holding capacitor Cs2, and the liquid crystal capacitor Clc of the second pixel driving unit away from the transistor is coupled to a second common electrode line Vcom-Even; the gate of the third transistor T3 of the first pixel driving unit is coupled to a first reset signal line Reset-Odd, and the second source / drain is coupled to the second common electrode line Vcom-Even; the gate of the third transistor T3 of the second pixel driving unit is coupled to a second reset signal line Reset-Even, and the second source / drain is coupled to the first common electrode line Vcom-Odd.

[0034] Specifically, in order to facilitate understanding of the working timing of the pixel driving circuit, as shown in Figure 7

[0035] ​In the backlight-on time of the Nth frame (which can be defined as an odd frame here), the data signal of the first pixel driving unit is configured as a positive polarity potential, the data signal of the second pixel driving unit is configured as a negative polarity potential, the first transistor T1 is controlled to be turned on based on a control signal, the first transistor T1 outputs a pre-charge voltage based on the data signal and stores it to the pre-storage capacitor Cs1, until the voltage pre-storage of all pixels is completed.

[0036] In the backlight-off time of the Nth frame, first, the second common voltage jumps to a high potential, then the first reset signal jumps to a high potential, and the reset of the liquid crystal capacitor Clc and the holding capacitor Cs2 of the first pixel driving unit is completed based on the third transistor T3; after the first reset signal jumps back to a low potential and the second common voltage jumps back to a normal potential, the first common voltage jumps to a low potential, then the second reset signal jumps to a high potential, and the reset of the second pixel driving unit is completed; after the second reset signal jumps back to a low potential and the first common voltage jumps back to a normal potential, the transfer signal jumps to a high potential, and the voltage required for the liquid crystal to form a target angle of rotation on the liquid crystal capacitor Clc is formed based on the second transistor T2.

[0037] In the backlight-on time of the N+1th frame (which can be defined as an even frame here), the data signal of the first pixel driving unit is configured as a negative polarity potential, the data signal of the second pixel driving unit is configured as a positive polarity potential, the first transistor T1 is controlled to be turned on based on a control signal, the first transistor T1 outputs a pre-charge voltage based on the data signal and stores it to the pre-storage capacitor Cs1, until the voltage pre-storage of all pixels is completed.

[0038] In the backlight-off time of the N+1th frame, first, the second common voltage jumps to a low potential, then the first reset signal jumps to a high potential, and the reset of the liquid crystal capacitor Clc and the holding capacitor Cs2 of the first pixel driving unit is completed based on the third transistor T3; after the first reset signal jumps back to a low potential and the second common voltage jumps back to a normal potential, the first common voltage jumps to a high potential, then the second reset signal jumps to a high potential, and the reset of the second pixel driving unit is completed; after the second reset signal jumps back to a low potential and the first common voltage jumps back to a normal potential, the transfer signal jumps to a high potential, and the voltage required for the liquid crystal to form a target angle of rotation on the liquid crystal capacitor Clc is formed based on the second transistor T2.

[0039] When entering the N+2th frame, the backlight is turned on, and the driving timing of the Nth frame is recycled.

[0040] It should be noted that N is an odd number and a positive integer, which can be configured as 1, 3, 5, 7… in the above embodiment, and the present application is complete to show the signal changes required for different polarity of liquid crystal to flip, and the frame is limited to N, N+1, where it is assumed that the liquid crystal needs to be flipped every frame, but the technical solution claimed in the present application is also applicable to the liquid crystal flipped every M frames, M∈(2, +∞), therefore, the description of the Nth frame, the N+1th frame and the like used in the above to accurately describe the technical solution claimed in the present application should not be regarded as a limitation on the protection scope of the present application.

[0041] It should also be noted that the present application is described in the embodiment circuit with N-type TFT, and in the timing diagram, the high potential of the gate control signal (control signal, reset signal and transfer signal) is opened, and the low potential is closed, which can also be extended to P-type TFT, at this time, the low potential is opened, and the high potential is closed, which is included in the protection scope of the present application. At the same time, the "high potential" and "low potential" of the common voltage recorded in the present application refer to: the high and low of the potential compared with the normal (normal) potential during light emission; the "positive polarity potential" of the data signal recorded in the present application is defined as: when the target potential of the pixel electrode-Vcom≥0V, the voltage range of the data signal, and the "negative polarity potential" of the data signal is defined as: when the target potential of the pixel electrode-Vcom≤0V, the voltage range of the data signal. It should be noted that, since the technical solution claimed in the present application uses the jumping common voltage to reset the liquid crystal capacitor Clc, the positive polarity potential and the negative polarity potential may overlap to some extent in range.

[0042] The primary improvement of the present application is to provide an LCD pixel driving circuit for color sequential display, which realizes the simultaneous writing of data signal voltage and light emission under color sequential display through pre-storage capacitor design, and increases the light emission time.

[0043] Meanwhile, the application sets the common voltage as two independent global signals, and sets the reset signal as two independent global signals as well. Both are provided by an IC or other signal generating unit. When resetting in a frame, the first pixel driving unit (odd column pixel node) resets through the corresponding common voltage of the even column as the signal source, and the second pixel driving unit (even column pixel node) resets through the corresponding common voltage of the odd column as the signal source. The odd and even column pixels are reset in time division, and the common voltage signal of the corresponding signal source is changed before resetting, so as to reduce the maximum Pre-Charge node voltage required by the pre-storage capacitor during charge sharing, thereby reducing the data signal voltage range (Data Range) required by the Source IC, saving the power consumption of the Source IC and the power consumption of the Scan output unit (IC or GOA, etc.) of the control signal; the proportion limit of Cs1 and Clc can also be reduced. The aperture ratio is improved and the pre-charge difficulty is reduced. That is, the application resets the pixel electrode through the optimization of the pixel electrode reset circuit, such as multiplexing the Vcom signal line or increasing the additional reset signal source, so as to reset the pixel electrode of the positive and negative polarity to different potentials, reduce the charge required for the Cs1 single writing of the pixel data voltage of each row of pixels (reduce the driving difficulty), and introduce fewer additional signal lines, without significantly increasing the pixel layout complexity (with less influence on the aperture ratio), thereby solving the problems of low aperture ratio and great driving difficulty of the traditional pixel driving circuit.

[0044] It should be noted that the above-mentioned claimed technical solution adopts column inversion mode to realize polarity inversion, that is, the pixel voltage polarity of each pixel is inverted in a frame as a period (the reason is that liquid crystal driving polarity inversion is required. If the liquid crystal is driven by DC voltage, polarization of the liquid crystal will occur, and problems such as direct current residual image and liquid crystal damage will occur).

[0045] Further, still taking Figure 7 (Canon's pixel driving circuit disclosed in U.S. Patent No. 6181311) as an example Figure 7 The Data signal voltage range required by the circuit. It is assumed that all pixel Cs1 is designed as = Cs2 + clc. And under all gray scales, the working voltage between the pixel electrode and the Vcom electrode required by the liquid crystal is 0~Vop_max (Vop_max is the maximum working voltage of the liquid crystal, which is a positive value. The maximum voltage required by Vpixel in positive polarity is Vcom + Vop, and the minimum voltage required by Vpixel in negative polarity is Vcom-Vop), wherein Vpixel is the pixel electrode voltage.

[0046] Taking the odd columns as an example, if the odd columns (the first column and the third column) are driven in negative polarity (Vpixel-Vcom≤0) in the Nth frame (N is a natural number), the N+1th frame should be driven in positive polarity (Vpixel-Vcom≥0) due to the requirement of polarity inversion of liquid crystal. According to the working principle of the pre-storage mode (0000110), Figure 7 ), the data signal voltage corresponding to writing the N+1th frame to Cs1 is required to be written in positive polarity, i.e. a voltage greater than or equal to Vcom. For a certain odd column pixel a, Figure 7 The scheme uses the Reset signal to open T3 to reset the pixel electrode to the Vcom voltage in the transfer stage (Transfer) of a frame, and then uses the Transfer signal to open T2 to transfer the data signal voltage pre-stored in Cs1 to the pixel electrode. Assuming that the pre-written voltage of Cs1 is Vcs1, then for the pixel a, Figure 7 In the pre-storage mode, after the transfer is opened, if Vpixel is equal to the maximum value Vop_max+Vcom, according to the principle of charge conservation, (Vcs1-(Vop_max+Vcom))*Cs1=((Vop_max+Vcom)-Vcom)*(Cs2+Clc), i.e. Vcs1-Vop_max-Vcom=Vop_max, Vcs1=2*Vop_max+Vcom. Similarly, when writing a negative polarity voltage to Cs1, if the minimum value -Vop_max is required, according to the principle of charge conservation, Vs1-(-Vop_max+Vcom)*Cs1=((-Vop_max+Vcom)-Vcom)*(Cs2+Clc), Vs1+Vop_max-Vcom=-Vop_max, Vs1=-2*Vop_max+Vcom. Therefore, the required Data voltage range is (2*Vop_max+Vcom)-(-2*Vop_max+Vcom)=4*Vop_max; and for the Normal 1T2C LCD pixel driving circuit, because there is no pre-storage design, there is no charge sharing, and the Data voltage range is -Vop_max~Vop_max, i.e. 2 times the Vop_max voltage. Therefore, when the Figure 7 scheme is used for driving, the Vdata voltage range needs to be doubled.

[0047] While using the driving method claimed in the present application: after the transfer is opened, if Vpixel is required to be equal to Vop_max+Vcom, at this time the pixel electrode voltage has been reset to Vop_max+Vcom, according to the principle of charge conservation, (Vcs1-(Vop_max+Vcom))*Cs1=((Vop_max+Vcom)-(Vop_max+Vcom))*(Cs2+Clc), that is, Vcs1-Vop_max-Vcom=0, Vcs1=Vop_max+Vcom. If Vpixel is required to be equal to Vcom, (Vcs1-Vcom)*Cs1=(Vcom-(Vop_max+Vcom))*(Cs2+Clc), Vcs1-Vcom=Vcom-(Vop_max+Vcom), Vcs1=Vcom-Vop_max, that is, the required Data voltage range is (Vop_max+Vcom)-(Vcom-Vop_max)=2*Vop_max.

[0048] Similarly, when a negative polarity voltage is written to Cs1 in the next frame, according to the same formula, it can be deduced that the Data voltage range is still between Vop_max+Vcom and Vcom-Vop_max, and thus the overall range of Vdata is 2*Vcop_max, which is comparable to the Normal 1T2C circuit.

[0049] Therefore, by using the technical solution claimed in the present application, through partial or complete overlap of the Vdata voltage range in positive and negative polarities, a significant reduction in the Data voltage range can be achieved.

[0050] At the same time, it can also be known from the charge sharing formula that, in the driving circuit of Figure 3 the smaller Cs1 is, or the larger Clc+Cs2 is, the worse the charge sharing effect is, and the larger the required Data voltage range is. Therefore, this kind of circuit has a large limitation on the size of Cs1, Clc and Cs2, and requires a large Cs1 and a small Cs2+Clc. However, after Cs1 is increased, the aperture ratio will be affected, and after Cs2+Clc is reduced, the pixel voltage will leak more in a frame, and problems such as flicker are likely to occur, thus requiring a higher TFT characteristic. However, the circuit and driving method claimed in the present application do not have such limitations and requirements. Therefore, it is more conducive to improving the aperture ratio and conducive to the driving implementation of high refresh rate and high resolution display products.

[0051] In addition, when the ratio of Cs1 / (Clc+Cs2) is increased, and when it is >1, according to the charge sharing formula, the Data voltage range can also be compressed, which can be less than the voltage range 2*Vop_max required by Normal 1T2C. Thus, the power consumption of the Source IC and the Scan output unit can be further reduced (because the switching voltage difference of the Scan signal is reduced), and the maximum Vds voltage difference when the TFT T1 is closed can also be reduced, so that the leakage current when the TFT is closed can be reduced, and the display quality such as flicker is further improved. Embodiment

[0052] The application also provides a preferred embodiment, as shown in Figure 4 The LCD pixel driving circuit can also be configured such that the gate of the third transistor T3 of the first pixel driving unit and the gate of the third transistor T3 of the second pixel driving unit are both coupled to the same reset signal line.

[0053] At this time, as shown in Figure 5 In the case where the second common voltage jumps to high potential and the first common voltage jumps to low potential, or the second common voltage jumps to low potential and the first common voltage jumps to high potential, the first reset signal jumps to high potential, and the reset of the liquid crystal capacitor Clc and the holding capacitor Cs2 of the first pixel driving unit and the second pixel driving unit is completed synchronously.

[0054] In this embodiment, the first pixel driving unit and the second pixel driving unit use the same reset signal line, that is, use the common Reset signal, and when resetting, still use the opposite Vcom signal as the signal source for simultaneous reset, which can also achieve similar effects. And because the self Vcom also reversely jumps before resetting, the optimal jump voltage of Vcom_Odd and Vcom_Even can also be reduced, and the Vcom voltage as the Reset signal source can jump to Vop_max / 2+Vcom and Vcom-Vop_max_ / 2 respectively in positive and negative polarity. And because the Reset signal is merged into one, the Layout is easier, and the number of control signal channels is reduced, and the timing control complexity is simplified. Embodiment

[0055] As shown in Figure 6As shown, the application also provides another preferred embodiment, wherein the LCD pixel driving circuit can be further configured such that the pre-storage capacitor Cs1, the holding capacitor Cs2 and the liquid crystal capacitor Clc of the first pixel driving unit and the second pixel driving unit are all coupled to the same common electrode line at one end of the transistor; the second source-drain electrode of the third transistor T3 of the first pixel driving unit is coupled to the first global signal line VREF-Odd, and the second source-drain electrode of the third transistor T3 of the second pixel driving unit is coupled to the second global signal line VREF-Even.

[0056] Further, in the present embodiment, as shown in FIG. 6, when the data signal of the first pixel driving unit is configured as a positive polarity potential and the data signal of the second pixel driving unit is configured as a negative polarity potential, the first global signal in the frame is configured as a high potential and the second global signal is configured as a low potential; when the data signal of the first pixel driving unit is configured as a negative polarity potential and the data signal of the second pixel driving unit is configured as a positive polarity potential, the first global signal in the frame is configured as a low potential and the second global signal is configured as a high potential. ​ Further, the high potential of the global signal is configured as the common voltage Vcom + the maximum working voltage of the liquid crystal Vop_max, and the low potential of the global signal is configured as the common voltage Vcom - the maximum working voltage of the liquid crystal Vop_max.

[0057] In the present embodiment, similar effects can also be achieved by using only separate VREF_Odd and VREF2_Even signal lines as the odd-even column reset signal sources, which are provided by a timing control IC or other signal generating units. The advantage of the present embodiment is that the Vcom signal does not need to change throughout the working process, and the stability is better. However, due to the increase of the additional signal lines, the aperture ratio can be affected.

[0058] In summary, the driving timing and mechanism of each embodiment in the present application are described in the column inversion mode, but it can also be extended to the row inversion, dot inversion, multi-column inversion, multi-row inversion and other polarity inversion modes, and the driving principles are not significantly different. The positive and negative polarity inversion pixels are reset to different potentials, and the positive polarity is preferably Vop_max and the negative polarity is preferably -Vop_max. Therefore, the adaptability of the circuit and the driving timing in each embodiment caused by the column inversion mode should not be considered as a limitation on the protection scope of the present application.

[0059]

[0060] ​The above describes the LCD pixel driving circuit for color sequential display provided by the embodiment of the present application. Each embodiment in the description is described in a progressive manner, and each embodiment focuses on the difference from other embodiments, and the same or similar parts between each embodiment can be referred to each other. For the device disclosed by the embodiments, since it corresponds to the method disclosed by the embodiments, the description is relatively simple, and the relevant parts can be referred to the method part. It should be noted that, for those skilled in the art, without departing from the principle of the present application, the present application can be improved and modified in several ways, and these improvements and modifications also fall within the protection scope of the claims of the present application.

[0061] Those skilled in the art will further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, each example has been described in general terms in the above description. Whether the functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application. The steps of the method or algorithm described in conjunction with the embodiments disclosed herein can be directly implemented in hardware, software modules executed by a processor, or a combination of both. The software modules can be placed in random access memory (RAM), memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

Claims

1. An LCD pixel drive circuit for color sequential display, characterized by, At least comprising: The first pixel driving unit and the second pixel driving unit each comprise a first transistor T1, a pre-storage capacitor Cs1, a second transistor T2, a holding capacitor Cs2, a third transistor T3, and a liquid crystal capacitor Clc, a first source-drain electrode of the first transistor T1 is coupled to a data signal line Data, a gate electrode is coupled to a control signal line Scan, a second source-drain electrode is coupled to a first source-drain electrode of the second transistor T2 and one end of the pre-storage capacitor Cs1; a gate electrode of the second transistor T2 is coupled to a transfer signal line Tran, a second source-drain electrode is coupled to a first source-drain electrode of the third transistor T3, one end of the holding capacitor Cs2, and one end of the liquid crystal capacitor Clc; one end of the pre-storage capacitor Cs1, the holding capacitor Cs2, and the liquid crystal capacitor Clc of the first pixel driving unit away from the transistor is coupled to a first common electrode line Vcom-Odd, one end of the pre-storage capacitor Cs1, the holding capacitor Cs2, and the liquid crystal capacitor Clc of the second pixel driving unit away from the transistor is coupled to a second common electrode line Vcom-Even; A gate electrode of the third transistor T3 of the first pixel driving unit is coupled to a first reset signal line Reset-Odd, and a second source-drain electrode is coupled to the second common electrode line Vcom-Even; A gate electrode of the third transistor T3 of the second pixel driving unit is coupled to a second reset signal line Reset-Even, and a second source-drain electrode is coupled to the first common electrode line Vcom-Odd, wherein, When the backlight is turned off in the Nth frame: first, after the second common voltage jumps to a high potential, the first reset signal jumps to a high potential, and the third transistor T3 completes the reset of the liquid crystal capacitor Clc and the holding capacitor (Cs2) of the first pixel driving unit; after the first reset signal jumps back to a low potential and the second common voltage jumps back to a normal potential, the first common voltage jumps to a low potential, then the second reset signal jumps to a high potential, and the reset of the second pixel driving unit is completed; after the second reset signal jumps back to a low potential and the first common voltage jumps back to a normal potential, the transfer signal jumps to a high potential, which is based on the voltage required by the second transistor T2 to form a liquid crystal flip target angle on the liquid crystal capacitor Clc; when entering the N+1th frame, the backlight is turned on; When the backlight is turned off in the N+1th frame: first, after the second common voltage jumps to a low potential, the first reset signal jumps to a high potential, and the third transistor T3 completes the reset of the liquid crystal capacitor Clc and the holding capacitor (Cs2) of the first pixel driving unit; after the first reset signal jumps back to a low potential and the second common voltage jumps back to a normal potential, the first common voltage jumps to a high potential, then the second reset signal jumps to a high potential, and the reset of the second pixel driving unit is completed; after the second reset signal jumps back to a low potential and the first common voltage jumps back to a normal potential, the transfer signal jumps to a high potential, which is based on the voltage required by the second transistor T2 to form a liquid crystal flip target angle on the liquid crystal capacitor Clc; when entering the N+2th frame, the backlight is turned on.

2. The LCD pixel drive circuit of claim 1, wherein, In the backlight-on time, the first transistor T1 is controlled to be turned on based on the control signal, and the first transistor T1 outputs a pre-charge voltage based on the data signal and stores the pre-charge voltage to the pre-storage capacitor Cs1 until all pixels complete voltage pre-storage.

3. The LCD pixel drive circuit of claim 1 or 2, wherein, In the backlight-on time of the Nth frame, the data signal of the first pixel driving unit is configured as a positive polarity potential Vdata1, and the data signal of the second pixel driving unit is configured as a negative polarity potential Vdata2. In the backlight-on time of the N+1th frame, the data signal of the first pixel driving unit is configured as a negative polarity potential Vdata1, and the data signal of the second pixel driving unit is configured as a positive polarity potential Vdata2.

4. The LCD pixel drive circuit of claim 1, wherein, The LCD pixel driving circuit can be further configured as: The gate of the third transistor T3 of the first pixel driving unit and the gate of the third transistor T3 of the second pixel driving unit are coupled to the same reset signal line.

5. The LCD pixel drive circuit of claim 4, wherein, In the case that the second common voltage jumps to a high potential and the first common voltage jumps to a low potential, or the second common voltage jumps to a low potential and the first common voltage jumps to a high potential, The first reset signal jumps to a high potential, and the reset of the liquid crystal capacitor Clc and the holding capacitor Cs2 of the first pixel driving unit and the second pixel driving unit is completed synchronously.

6. The LCD pixel drive circuit of claim 1, wherein, The LCD pixel driving circuit can be further configured as: The one end of the pre-storage capacitor Cs1, the holding capacitor Cs2 and the liquid crystal capacitor Clc of the first pixel driving unit and the second pixel driving unit away from the transistor is coupled to the same common electrode line; The second source-drain electrode of the third transistor T3 of the first pixel driving unit is coupled to the first global signal line VREF-Odd, and the second source-drain electrode of the third transistor T3 of the second pixel driving unit is coupled to the second global signal line VREF-Even.

7. The LCD pixel drive circuit of claim 6, wherein, When the data signal of the first pixel driving unit is configured as a positive polarity potential Vdata1 and the data signal of the second pixel driving unit is configured as a negative polarity potential Vdata2, the first global signal in the current frame is configured as a high potential, and the second global signal is configured as a low potential. When the data signal of the first pixel driving unit is configured as a negative polarity potential Vdata1 and the data signal of the second pixel driving unit is configured as a positive polarity potential Vdata2, the first global signal in the current frame is configured as a low potential, and the second global signal is configured as a high potential.

8. The LCD pixel drive circuit of claim 1, wherein, The high potential of the global signal is configured as: the common voltage Vcom + the maximum working voltage Vop-max of the liquid crystal; and the low potential of the global signal is configured as: the common voltage Vcom - the maximum working voltage Vop-max of the liquid crystal.

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