Address processing system and address conditioning method

Abstract

The present disclosure relates to the field of memory, and particularly relates to an address processing system and an address adjusting method. The address processing system comprises a controller and a storage array; a selection circuit having a selection end, two input ends and an output end; the selection end is used for receiving a bypass control signal transmitted by the controller, one of the two input ends is used for receiving an initial address, the other of the two input ends is used for receiving a replacement address, and the output end is used for outputting an addressing address to the storage array; the selection circuit is configured to output the initial address or the replacement address as the addressing address according to the bypass control signal. The address processing system provided by the embodiment of the present disclosure is used to shorten the read / write time of the storage controller.

Description

Technical Field

[0001] This disclosure relates to the field of memory, and more particularly to an address processing system and address adjustment method. Background Technology

[0002] The memory is the component in a computer that performs the memory function. It is used to store programs and data and is an important part of a microcomputer system. The larger the memory capacity, the more information it can store, and the more fully the computer's processing power can be demonstrated.

[0003] Each storage chip contains multiple storage cells. However, due to limitations in manufacturing technology, the performance of each storage cell in a storage chip varies, and some storage cells malfunction, resulting in a reduced yield of the storage chip.

[0004] To improve the yield of memory chips, redundant memory cells are typically added to the chips to replace the addresses of failed memory cells in the memory array. Before leaving the factory, each memory cell of the chip is scanned, and the addresses of failed memory cells are stored in Content-Addressable Memory (CAM). All addresses input by the memory controller during read / write operations must be processed through CAM, thus completing the address replacement of failed memory cells. Summary of the Invention

[0005] The purpose of this disclosure is to provide an address processing system and address adjustment method to shorten the read / write time of the storage controller.

[0006] This disclosure provides an address processing system, including: a controller and a memory array; a selection circuit having a selection terminal, two input terminals, and an output terminal; the selection terminal is used to receive a bypass control signal transmitted by the controller, one of the two input terminals is used to receive an initial address, the other of the two input terminals is used to receive a replacement address, and the output terminal is used to output an addressing address to the memory array; the selection circuit is configured to output the initial address or the replacement address as the addressing address according to the bypass control signal.

[0007] In some embodiments, the address processing system further includes a mode register connected to the selection terminal, configured to receive a bypass configuration command transmitted by the controller and output the bypass control signal according to the bypass configuration command.

[0008] In some embodiments, the controller is configured to output the bypass control signal to the output terminal according to the initial address.

[0009] In some embodiments, the controller is configured to: determine whether the initial address belongs to a preset address range; when the initial address belongs to the preset address range, send out the bypass control signal to configure the selection circuit to output the addressing address based on the replacement address; when the initial address does not belong to the preset address range, send out the bypass control signal to configure the selection circuit to output the addressing address based on the initial address.

[0010] In some embodiments, the controller is configured to: acquire the raw bit error rate required by the system; when the raw bit error rate is greater than a preset value, send out the bypass control signal to configure the selection circuit to output the addressing address based on the initial address; when the raw bit error rate is less than the preset value, send out the bypass control signal to configure the selection circuit to output the addressing address based on the replacement address.

[0011] In some embodiments, the selection circuit is disposed in the memory chip.

[0012] In some embodiments, the address processing system further includes an address processing circuit configured to receive an initial address and output the replacement address corresponding to the initial address based on an address mapping relationship.

[0013] This disclosure also provides an address adjustment method applied to the address processing system provided in the above embodiments, comprising: outputting an initial address and a bypass control signal to a memory chip through a controller; the selection circuit of the memory chip, based on the bypass control signal, selecting an address based on the initial address or a replacement address mapped from the initial address and outputting an addressing address to the memory array of the memory chip.

[0014] In some embodiments, the address adjustment method further includes: the controller outputting the bypass control signal based on the address range to which the initial address belongs; when the initial address belongs to the preset address range, the bypass control signal controls the selection circuit to output the addressing address based on the replacement address; when the initial address does not belong to the preset address range, the bypass control signal controls the selection circuit to output the addressing address based on the initial address.

[0015] In some embodiments, the address adjustment method further includes: the controller outputting the bypass control signal based on the original bit error rate required by the system; when the original bit error rate is greater than a preset value, the bypass control signal controlling the selection circuit to output the addressing address based on the initial address; when the original bit error rate is less than the preset value, the bypass control signal controlling the selection circuit to output the addressing address based on the replacement address.

[0016] The address processing system provided in this disclosure improves the addressing flexibility of the storage array by determining whether to output a replacement address or an initial address through a bypass control signal. For example, when data read / write accuracy needs to be guaranteed, the replacement address is output as the addressing address; when data read / write speed needs to be guaranteed, the initial address is output as the addressing address to shorten the read / write time of the storage controller.

[0017] Other features and advantages of this disclosure will be described in detail in the following detailed description section. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are merely some embodiments of this disclosure. Those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0019] Figure 1 This is a schematic diagram of the structure of the address processing system provided in the embodiments of this disclosure;

[0020] Figure 2 This is a schematic diagram of the structure of an address processing system for obtaining replacement addresses based on content-addressable memory, provided in an embodiment of this disclosure;

[0021] Figure 3 This is a schematic diagram of a bypass control signal generation method provided in an embodiment of this disclosure. Detailed Implementation

[0022] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the protection scope of this disclosure.

[0023] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, features defined as "first" or "second" may explicitly or implicitly include one or more described features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0024] In this disclosure, the term "exemplary" is used to mean "serving as an example, illustration, or description." Any embodiment described as "exemplary" in this disclosure is not necessarily to be construed as being more preferred or advantageous than other embodiments. The following description is provided to enable any person skilled in the art to make and use the invention. In the following description, details are set forth for purposes of explanation. It should be understood that those skilled in the art will recognize that the invention can be made without using these specific details. In other instances, well-known structures and processes will not be described in detail to avoid obscuring the description of the invention with unnecessary detail. Therefore, the invention is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed herein.

[0025] Furthermore, this disclosure uses specific terms to describe embodiments of the present disclosure. For example, "an embodiment," "one embodiment," and / or "some embodiments" refer to a particular feature, structure, or characteristic associated with at least one embodiment of the present disclosure. Therefore, it should be emphasized and noted that references to "an embodiment," "one embodiment," or "an alternative embodiment" in different locations throughout this specification do not necessarily refer to the same embodiment. Moreover, certain features, structures, or characteristics in one or more embodiments of the present disclosure can be appropriately combined.

[0026] Similarly, it should be noted that, in order to simplify the description of this disclosure and thus aid in the understanding of one or more disclosed embodiments, the foregoing description of the embodiments of this disclosure sometimes combines multiple features into a single embodiment, drawing, or description thereof. However, this disclosure method does not imply that the subject matter of this disclosure requires more features than those mentioned in the claims. In fact, the embodiments contain fewer features than all the features of the single embodiments disclosed above.

[0027] In some embodiments, numbers describing the quantity of components and attributes are used. It should be understood that such numbers used in the description of embodiments are modified in some examples with the terms "approximately," "approximately," or "generally." Unless otherwise stated, "approximately," "approximately," or "generally" indicates that the numbers are allowed to vary by ±20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximate values, which may be changed depending on the characteristics required by individual embodiments. In some embodiments, numerical parameters should be considered for specifying significant digits and employing a general method of digit reservation. Although the numerical ranges and parameters used to confirm their breadth of range in some embodiments of this disclosure are approximate values, in specific embodiments, such values ​​are set as precisely as feasible.

[0028] For each patent, patent application, patent application publication, and other material such as articles, books, specifications, publications, and documents referenced in this disclosure, the entire contents of that publication are incorporated herein by reference, except for historical application documents that are inconsistent with or conflict with the content of this disclosure, and documents that limit the broadest scope of the claims of this disclosure (currently or subsequently appended to this disclosure). It should be noted that if there are any inconsistencies or conflicts between the descriptions, definitions, and / or terms used in the supplementary materials to this disclosure and the examples in this disclosure, the descriptions, definitions, and / or terms used in this disclosure shall prevail.

[0029] As is known from the background technology, each storage chip contains multiple storage cells. However, due to limitations in manufacturing technology, the performance of each storage cell varies, and some storage cells malfunction, reducing the yield of the storage chip. To improve the yield of storage chips, redundant storage cells are typically added to the storage chip, replacing the addresses of failed storage cells in the storage array with the addresses of redundant storage cells.

[0030] When the storage controller sends a read or write command, the storage chip transmits the received address to the Content-Addressable Memory (CAM) for processing. The CAM determines whether the address maps to a new storage cell. If the address maps to a new address, the CAM replaces the original address with the address of the new storage cell and transmits the processed address to the storage array. The storage array then performs read and write operations based on the processed address.

[0031] Since all addresses input to the storage granules by the storage controller are processed through content-addressable memory, this increases the waiting time for the storage array to receive addresses, increases the read latency or write latency of all storage cells, and reduces the data bandwidth when continuously reading / writing the same storage block.

[0032] This disclosure provides an address processing system, including: a controller and a memory array; a selection circuit having a selection terminal, two input terminals, and an output terminal; the selection terminal is used to receive a bypass control signal transmitted by the controller, one of the two input terminals is used to receive an initial address, the other of the two input terminals is used to receive a replacement address, and the output terminal is used to output an addressing address to the memory array; the selection circuit is configured to output the initial address or the replacement address as the addressing address according to the bypass control signal.

[0033] The address processing system provided in this disclosure improves the addressing flexibility of the storage array by determining whether to output a replacement address or an initial address using a bypass control signal. For example, when data read / write accuracy needs to be guaranteed, the replacement address is output as the addressing address; when data read / write speed needs to be guaranteed, the initial address is output as the addressing address to shorten the read / write time of the storage controller.

[0034] The address processing system provided in this embodiment will be described in detail below with reference to the accompanying drawings.

[0035] refer to Figure 1 , Figure 1 This is a schematic diagram of the address processing system provided in this embodiment. The address processing system 100 includes: a controller 201, a memory array 102, and a selection circuit 101.

[0036] Among them, controller 201 is the memory controller (control store). The memory controller is a device that performs necessary control over memory access according to certain timing rules, including the control of address signals, data signals, and various command signals, so that the master device (the device accessing the memory) can use the storage resources on the memory according to its own requirements. The main function of the memory controller is to perform interface conversion, converting read, write, and other commands issued by the master device into signals that the memory can recognize, and also to complete address decoding and data format conversion (such as data bit width) between the master device and the memory.

[0037] The storage array 102 includes multiple storage cells arranged in an array. It also includes multiple word lines and multiple bit lines. Word lines are used for row positioning of storage cells, and bit lines are used for column positioning. Each word line corresponds to a specific word line address, and each bit line corresponds to a specific bit line address. A storage cell can be precisely located using both a word line address and a bit line address, allowing data to be written to or read from that cell. The storage array 102 drives the row driver and column driver to select the target storage cell using the word line address and bit line address in the addressing mechanism.

[0038] Ideally, all memory cells in memory array 102 are formed using the same process, resulting in consistent performance. However, due to limitations in actual production technology, defective memory cells may exist in memory array 102. The performance of defective memory cells is lower than that of normal memory cells, significantly impacting the yield of the memory.

[0039] To improve the yield of memory chips, redundant memory cells are typically added to the memory chips, replacing the addresses of failed memory cells in memory array 102 with the addresses of redundant memory cells. After address replacement, the array composed of redundant memory cells replacing defective memory cells improves the yield of the memory, but it also increases the read latency or write latency of all memory cells and reduces the data bandwidth when continuously reading and writing the same memory block.

[0040] Selection circuit 101 has a selection terminal and two input terminals; the selection terminal is used to receive a bypass control signal, one of the two input terminals is used to receive an initial address, and the other of the two input terminals is used to receive a replacement address. The replacement address is used to adjust the address of the defective storage cell based on the initial address. Selection circuit 101 is configured to output an addressing address based on either the initial address or the replacement address according to the bypass control signal.

[0041] The address processing system 100 provided in this embodiment determines whether to output a replacement address as the addressing address or an initial address as the addressing address by using a bypass control signal, thereby improving the addressing flexibility of the storage array. For example, when it is necessary to ensure the accuracy of data read and write operations, the replacement address is output as the addressing address; when it is necessary to ensure the data read and write speed, the initial address is output as the addressing address to shorten the read and write time of the storage controller.

[0042] In some embodiments, the selection circuit 101 includes a selector, the first input terminal S1 and the second input terminal S2 of the selector are respectively connected to the two input terminals of the selection circuit 101, the output terminal of the selector is connected to the output terminal of the selection circuit 101, and the control terminal S0 of the selector is connected to the selection terminal of the selection circuit.

[0043] It should be noted that, for clarity, in the following description, the first input S1 of the selector is used to receive the initial address, and the second input S2 of the selector is used to receive the replacement address.

[0044] In some embodiments, the initial address is output by the controller 201, that is, the first input terminal S1 is connected to the controller 201 to obtain the initial address; the replacement address can be understood as the address generated by the content addressable memory after processing the initial address, and the addressing address is used for addressing the storage array 102 to perform read or write operations on specific storage units.

[0045] Continue to refer to Figure 1In one example, when the bypass control signal is "1", the selector outputs the addressing address based on the initial address input at the first input terminal S1; when the bypass control signal is "0", the selector outputs the addressing address based on the replacement address input at the second input terminal S2. Alternatively, when the bypass control signal is "0", the selector outputs the addressing address based on the initial address input at the first input terminal S1; when the bypass control signal is "1", the selector outputs the addressing address based on the replacement address input at the second input terminal S2.

[0046] In some embodiments, the address processing system 100 further includes an address processing circuit configured to receive an initial address and output a replacement address based on the initial address.

[0047] In one example, the address processing circuit can process the initial address based on a preset processing method to obtain the replacement address. The preset processing method could be to increase or decrease the initial address by a preset value, or to invert one or more bits of the initial address, etc.

[0048] In some embodiments, the address processing circuit is configured to output the replacement address corresponding to the initial address based on the address mapping relationship.

[0049] In one example, the address processing circuit stores the address mapping relationship between the initial address and the replacement address. Based on the received initial address and address mapping relationship, the address processing circuit outputs the replacement address corresponding to the initial address.

[0050] refer to Figure 2 , Figure 2 This is a schematic diagram of the address processing system for obtaining a replacement address based on a content-addressable memory (CAM) provided in this embodiment. The address processing circuit is based on the CAM (103), which is used to replace the initial address to obtain a replacement address.

[0051] It should be noted that in the following description of this embodiment, based on Figure 2 The example provided is for specific illustration of the address processing system 100 and does not constitute a limitation on the method of generating replacement addresses. In other embodiments, replacement addresses may also be generated by the controller 201 or implemented via registers.

[0052] In some embodiments, reference Figure 3 , Figure 3This is a schematic diagram of a bypass control signal generation method provided in this embodiment. The address processing system 100 also includes a mode register 104, which is connected to the selection terminal of the selection circuit 101. The mode register 104 is configured to receive a bypass configuration command transmitted by the controller 201 and output a bypass control signal according to the bypass configuration command.

[0053] The bypass configuration command is output based on the output terminal of the controller 201. The bypass configuration command is used to control the value of the bypass control signal output by the control mode register 104, thereby realizing the control of the selection circuit 101.

[0054] Specifically, when the bypass configuration command is "0", the configuration mode register 104 outputs a bypass control signal of "1", thereby controlling the selector to output an addressing address based on the initial address input at the first input terminal S1; when the bypass configuration command is "1", the configuration mode register 104 outputs a bypass control signal of "0", thereby controlling the selector to output an addressing address based on the replacement address input at the second input terminal S2. Alternatively, when the bypass configuration command is "1", the configuration mode register 104 outputs a bypass control signal of "1", thereby controlling the selector to output an addressing address based on the initial address input at the first input terminal S1; when the bypass configuration command is "0", the configuration mode register 104 outputs a bypass control signal of "0", thereby controlling the selector to output an addressing address based on the replacement address input at the second input terminal S2.

[0055] In some embodiments, the controller 201 is configured to output a bypass control signal to the output terminal based on the initial address.

[0056] In some embodiments, the controller 201 determines whether to send a bypass control signal based on whether the initial address meets preset conditions. These preset conditions may include whether the initial address belongs to a preset address range, the raw bit error rate (RBER) required by the system, and whether an external command has been received.

[0057] In one example, controller 201 is configured to: determine whether the initial address belongs to a preset address range; when the initial address belongs to the preset address range, send a bypass control signal to configure selection circuit 101 to output the addressing address based on the replacement address; when the initial address does not belong to the preset address range, send a bypass control signal to configure selection circuit 101 to output the addressing address based on the initial address.

[0058] In this example, the preset address range is set based on the abnormal address range. The amount of data in the abnormal address range is generally smaller than the amount of data in the normal address range, so as to reduce the difficulty of the controller 201 in making judgments and reduce the judgment time of the controller 201. In one example, the preset address range can also be set based on the normal address range. In this case, the controller 201 is configured to: determine whether the initial address belongs to the preset address range; when the initial address belongs to the preset address range, send a bypass control signal to configure the selection circuit 101 to output the addressing address based on the initial address; when the initial address does not belong to the preset address range, send a bypass control signal to configure the selection circuit 101 to output the addressing address based on the replacement address.

[0059] For memory cells with abnormal performance that are concentrated within a certain address range, or through address remapping, the memory controller can group these abnormal memory cells into a single address range when accessing memory cells. If the memory controller does not access a memory cell, it can first determine if the access address is within this address range. If it is not, it can control the selection circuit 101 via a command or mode register. The selection circuit 101 generates an addressing address based on the initial address, reducing address processing time and thus reducing read latency or write latency.

[0060] In one example, controller 201 is configured to: acquire the raw bit error rate (RBER) required by the system; when the raw bit error rate (RBER) is greater than a preset value, send out a bypass control selection to configure selection circuit 101 to output an addressing address based on the initial address; when the raw bit error rate (RBER) is less than the preset value, send out a bypass control selection to configure selection circuit 101 to output an addressing address based on the replacement address.

[0061] By obtaining the raw bit error rate (RBER) required by the system, when the required raw bit error rate (RBER) is high, the addressing address is directly output through the initial address to improve the addressing speed of the memory and greatly reduce the read latency or write latency. When the required raw bit error rate (RBER) is low, the addressing address is output through the initial address to ensure the accuracy of memory processing.

[0062] In one example, controller 201 is configured to send a bypass control signal based on an external command to configure selection circuit 101 to output an addressing address based on an initial address.

[0063] Specifically, users can directly control the selection circuit 101 through commands or mode registers. The selection circuit 101 generates the addressing address based on the initial address, which reduces the address processing time, reduces read latency or write latency, and can improve the bandwidth of read data.

[0064] By avoiding the replacement of the initial address in content-addressable memory, the time of a single read or write operation can be reduced by at least 5ns. For scenarios involving continuous read or write operations, this greatly reduces read latency or write latency.

[0065] In some embodiments, the selection circuit 101 is disposed in the memory chip.

[0066] For the memory, the memory includes a first memory controller and multiple memory chips. By setting the selection circuit 101 in the memory chip, different control logics for different memory chips are implemented, which greatly improves the flexibility of memory data storage.

[0067] In addition, the memory mentioned in this embodiment can be random access memory (RAM), such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic memory (SDRAM), read-only memory (ROM), flash memory, or phase change memory (PCM).

[0068] The address processing system provided in this embodiment improves the addressing flexibility of the storage array by determining whether to output a replacement address or an initial address through a bypass control signal. For example, when data read / write accuracy needs to be guaranteed, the replacement address is output as the addressing address; when data read / write speed needs to be guaranteed, the initial address is output as the addressing address to shorten the read / write time of the storage controller.

[0069] It should be noted that, without conflict, the features disclosed in the address processing system 100 provided in the above embodiments can be randomly combined to obtain new embodiments of the address processing system 100.

[0070] Another embodiment of this disclosure also provides an address adjustment method to shorten the read / write time of the storage controller.

[0071] Specifically, the address adjustment method is applied to the address processing system 100 provided in the above embodiments, including steps S1 and S2.

[0072] Step S1: The controller outputs the initial address and bypass control signal to the memory chip.

[0073] The initial address is output by controller 201. The bypass control signal is used to configure the selection circuit to output an addressing address based on the initial address or a replacement address. In one example, the bypass control signal is output by controller 201; in another example, mode register 104 outputs the bypass control signal according to the bypass configuration command. For example, when the bypass configuration command is "0", the configuration mode register 104 outputs a bypass control signal with a value of "1"; when the bypass configuration command is "1", the configuration mode register 104 outputs a bypass control signal with a value of "0". Alternatively, when the bypass configuration command is "1", the configuration mode register 104 outputs a bypass control signal with a value of "1"; when the bypass configuration command is "0", the configuration mode register 104 outputs a bypass control signal with a value of "0".

[0074] In step S2, the selection circuit of the memory chip selects the addressing address of the memory chip's memory array based on the bypass selection signal, or the replacement address after the initial address is mapped.

[0075] The replacement address is obtained after the address processing circuit replaces the initial address. It can be understood as the address generated by the content-addressable memory after processing the initial address.

[0076] For example, when the bypass control signal is "1", the control selector generates an addressing address based on the initial address input at the first input terminal S1; when the bypass control signal is "0", the control selector generates an addressing address based on the replacement address input at the second input terminal S2. Alternatively, when the bypass control signal is "0", the control selector generates an addressing address based on the initial address input at the first input terminal S1; when the bypass control signal is "1", the control selector generates an addressing address based on the replacement address input at the second input terminal S2.

[0077] In some embodiments, before performing step S1, the address adjustment method further includes step S0-1, which involves obtaining a bypass control signal based on a preset address range.

[0078] Specifically, the controller outputs a bypass control signal based on the address range to which the initial address belongs; when the initial address belongs to the preset address range, the bypass control signal controls the selection circuit to output the addressing address based on the replacement address; when the initial address does not belong to the preset address range, the bypass control signal controls the selection circuit to output the addressing address based on the initial address.

[0079] In one example, it is determined whether the initial address belongs to a preset address range; when the initial address belongs to the preset address range, a bypass control signal is sent to configure the selection circuit 101 to output the addressing address based on the replacement address; when the initial address does not belong to the preset address range, a bypass control signal is sent to configure the selection circuit 101 to output the addressing address based on the initial address.

[0080] In one example, storage cells with abnormal performance are concentrated within a certain address range, or address remapping can be used to group these abnormal cells into a single address range. When accessing storage cells, the storage controller can first determine if the access address is within this address range. If it is not, it can control the selection circuit 101 via a command or mode register. The selection circuit 101 generates an addressing address based on the initial address, reducing address processing time and thus reducing read latency or write latency.

[0081] In some embodiments, before performing step S1, the address adjustment method further includes step S0-2, obtaining a bypass control signal based on the raw bit error rate RBER required by the system.

[0082] Specifically, the controller outputs a bypass control signal based on the original bit error rate required by the system; when the original bit error rate is greater than a preset value, the bypass control signal controls the selection circuit to output an addressing address based on the initial address; when the original bit error rate is less than the preset value, the bypass control signal controls the selection circuit to output an addressing address based on the replacement address.

[0083] In one example, the raw bit error rate (RBER) required by the system is obtained; when the raw bit error rate (RBER) is greater than a preset value, a bypass control selection is sent to configure the selection circuit 101 to output an addressing address based on the initial address; when the raw bit error rate (RBER) is less than the preset value, a bypass control selection is sent to configure the selection circuit 101 to output an addressing address based on the replacement address.

[0084] By obtaining the raw bit error rate (RBER) required by the system, when the required raw bit error rate (RBER) is high, the addressing address is directly output through the initial address to improve the addressing speed of the memory and greatly reduce the read latency or write latency. When the required raw bit error rate (RBER) is low, the addressing address is output through the initial address to ensure the accuracy of memory processing.

[0085] In one example, a bypass control signal is sent based on an external command to configure the selection circuit 101 to output an addressing address based on an initial address.

[0086] Specifically, users can directly control the selection circuit 101 through commands or mode registers. The selection circuit 101 generates the addressing address based on the initial address, which reduces the address processing time, reduces read latency or write latency, and can improve the bandwidth of read data.

[0087] By avoiding the replacement of the initial address in content-addressable memory, the time of a single read or write operation can be reduced by at least 5ns. For scenarios involving continuous read or write operations, this greatly reduces read latency or write latency.

[0088] Ideally, all memory cells in memory array 102 are formed using the same process, resulting in consistent performance. However, due to limitations in actual production technology, defective memory cells may exist in memory array 102. The performance of defective memory cells is lower than that of normal memory cells, significantly impacting the yield of the memory.

[0089] To improve the yield of memory chips, redundant memory cells are typically added to the chips, replacing the addresses of failed memory cells in the memory array with the addresses of redundant cells. This address replacement, where redundant cells replace defective ones, improves the memory yield. However, it also increases the read latency or write latency of all memory cells and reduces the data bandwidth when continuously reading and writing to the same memory block.

[0090] The address adjustment method provided in this embodiment improves the addressing flexibility of the storage array by determining whether to output a replacement address or an initial address through a bypass control signal. For example, when data read / write accuracy needs to be guaranteed, the replacement address is output as the addressing address; when data read / write speed needs to be guaranteed, the initial address is output as the addressing address to shorten the read / write time of the storage controller.

[0091] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the detailed descriptions of other embodiments above, which will not be repeated here.

[0092] The basic concepts have been described above. It is obvious that the detailed disclosure above is merely illustrative and does not constitute a limitation of this disclosure. Although not explicitly stated herein, various modifications, improvements, and corrections may be made to this disclosure by those skilled in the art. Such modifications, improvements, and corrections are suggested in this disclosure and therefore remain within the spirit and scope of the exemplary embodiments of this disclosure.

[0093] The above provides a detailed description of an address processing system and address adjustment method provided by the embodiments of this disclosure. Specific examples have been used to illustrate the principles and implementation methods of this disclosure. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this disclosure. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this disclosure. Therefore, the content of this specification should not be construed as a limitation of this disclosure.

Claims

1. An address handling system, characterized by The method comprises: a controller and a memory array; a selection circuit having a selection terminal, two input terminals and an output terminal; the selection terminal is configured to receive a bypass control signal transmitted by the controller, one of the two input terminals is configured to receive an initial address, the other of the two input terminals is configured to receive a replacement address, and the output terminal is configured to output an addressing address to the memory array; the controller is configured to: obtain an original bit error rate required to be controlled by a system; when the original bit error rate is greater than a preset value, send out the bypass control signal to configure the selection circuit to output the addressing address based on the initial address; when the original bit error rate is less than the preset value, send out the bypass control signal to configure the selection circuit to output the addressing address based on the replacement address; the selection circuit is configured to directly output the initial address or the replacement address mapped from the initial address as the addressing address according to the bypass control signal.

2. The address handling system of claim 1, wherein, Further comprising: a mode register connected to the selection terminal and configured to receive a bypass configuration command transmitted by the controller and output the bypass control signal according to the bypass configuration command.

3. The address handling system of claim 1, wherein, the controller is configured to output the bypass control signal to the output terminal according to the initial address.

4. The address handling system of claim 1, wherein, the selection circuit is arranged in a memory chip.

5. The address handling system of claim 1, wherein, Further comprising: an address processing circuit configured to receive an initial address and output a replacement address corresponding to the initial address based on an address mapping relationship.

6. An address adjustment method applied to the address processing system according to any one of claims 1 to 5, characterized by, The method comprises: outputting an initial address and a bypass control signal to a memory chip by a controller; a selection circuit of the memory chip selects to directly output the initial address to a memory array of the memory chip or outputs an addressing address to the memory array of the memory chip based on a replacement address mapped from the initial address based on the bypass control signal.

7. The address adjusting method of claim 6, wherein, The address adjustment method further comprises: the controller outputs the bypass control signal based on an address interval to which the initial address belongs; when the initial address belongs to a preset address interval, the bypass control signal controls the selection circuit to output the addressing address based on the replacement address; when the initial address does not belong to the preset address interval, the bypass control signal controls the selection circuit to output the addressing address based on the initial address.

8. The address adjusting method of claim 6, wherein, The address adjustment method further comprises: the controller outputs the bypass control signal based on an original bit error rate required to be controlled by a system; when the original bit error rate is greater than a preset value, the bypass control signal controls the selection circuit to output the addressing address based on the initial address; when the original bit error rate is less than the preset value, the bypass control signal controls the selection circuit to output the addressing address based on the replacement address.

Images