Work cycle correction method and work cycle correction system
By performing training in the operating cycle correction circuit and recording the results, and updating the correction circuit before the next clock signal switch, the problem of distortion of the clock signal due to external factors is solved, and a more stable clock signal output is achieved.
Patent Information
- Application Number
- CN202311343214.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-09-27
- Filing Date
- 2023-10-17
- Publication Date
- 2025-03-28
AI Technical Summary
In high-speed applications, the clock signal is distorted due to external factors, resulting in changes in the working cycle and affecting the normal operation of the circuit.
By performing training in the operating cycle correction circuit and recording the results, the correction circuit is updated before the next clock signal switch to reduce operating cycle changes.
It reduces the operating cycle changes during clock signal switching, reduces the risk of chip function failure, and provides a more stable clock signal.
Smart Images
Figure CN119724316A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a calibration method and system, and more particularly to a duty cycle calibration method and a duty cycle calibration system. Background Art
[0002] In high-speed applications, clock signals are distorted by external instruments, external packaging, and internal clock paths. At this time, a duty cycle corrector (DCC) is needed to solve this problem. The function of DCC is mainly to correct the duty cycle of the input clock signal and provide an output clock signal with a duty cycle of about 50%. It is widely used in double data rate synchronous dynamic random access memory (DDRSDRAM), double sampling analog-to-digital converter (Double-Sampling ADC), delay locked loop (DLL) and phase locked loop (PLL) and other circuits that need to operate simultaneously on the rising and falling edges of the clock signal. The performance of DCC often depends on the symmetry of the positive and negative half cycles of the reference clock signal.
[0003] Figure 1A and Figure 1B This is a schematic diagram of the execution sequence of traditional DCC training. Please refer to Figure 1A The traditional DCC training method is to perform DCC training after receiving the DCC instruction, and update the DCC training result at time T1 after the DCC training is completed, and then perform data output after receiving the data output instruction. This method takes a long time. Please refer to Figure 1B Another DCC training method is to perform DCC training and data output in sequence after receiving the data output instruction, and update the DCC training result at time T2 after the DCC training is completed, and perform data output at the same time.
[0004] The duty cycle of the output clock signal will vary according to different DCC training results, so the update timing of the training results is very important because the logic function will fail due to the change of the clock signal duty cycle. Summary of the invention
[0005] In view of the above, the present disclosure provides a duty cycle correction method and a duty cycle correction system, which can reduce the duty cycle variation when the clock signal is switched (toggle).
[0006] The present disclosure provides a duty cycle correction method for correcting the duty cycle of a clock signal using a duty cycle correction circuit (DCC). The method comprises the following steps: training the duty cycle correction circuit to correct the clock signal, and recording the training result after the training is completed; and updating the duty cycle correction circuit using the recorded training result before the next clock signal toggle.
[0007] In an embodiment of the present disclosure, the method further includes performing data output while recording the training results.
[0008] In one embodiment of the present disclosure, before the next clock signal switches, the step of updating the duty cycle correction circuit using the recorded training results includes updating the duty cycle correction circuit using the recorded training results before performing training on the duty cycle correction circuit to correct the clock signal when the next data output instruction is received.
[0009] In one embodiment of the present disclosure, training is performed on the duty cycle correction circuit to correct the clock signal, and after the training is completed, the step of recording the training results includes simultaneously performing training and data output on the duty cycle correction circuit, and recording the training results after the training and data output are completed.
[0010] In one embodiment of the present disclosure, before the next clock signal switches, the step of updating the duty cycle correction circuit using the recorded training results includes when the next data output instruction is received, before executing the training of the duty cycle correction circuit and data output, updating the duty cycle correction circuit using the recorded training results.
[0011] In one embodiment of the present disclosure, after simultaneously performing training and data output on the duty cycle correction circuit and recording the training results after the training and data output are completed, the method further includes updating the duty cycle correction circuit using the recorded training results.
[0012] In one embodiment of the present disclosure, the method also includes performing training on the duty cycle correction circuit to correct the clock signal when the power is turned on, and recording the initial training results after the training is completed, and when a data output instruction is received, before the clock signal is switched, updating the duty cycle correction circuit using the recorded initial training results.
[0013] In an embodiment of the present disclosure, the step of training the duty cycle correction circuit to correct the clock signal includes training the duty cycle correction circuit to output an output clock signal with a duty cycle of approximately 50%.
[0014] In one embodiment of the present disclosure, the step of training a duty cycle correction circuit to output an output clock signal with a duty cycle of approximately 50% includes comparing pulse widths generated by delays when a clock signal is input into the duty cycle correction circuit, generating a corresponding duty cycle correction value based on the comparison result, and adjusting the duty cycle of the output clock signal output by the duty cycle correction circuit based on the correction value so that the duty cycle is corrected to approximately 50%.
[0015] In one embodiment of the present disclosure, a duty cycle correction circuit is configured in a semiconductor product to correct the duty cycle of a clock signal provided to the semiconductor product.
[0016] The present disclosure provides a duty cycle correction system, which includes a duty cycle correction circuit, a storage device and a control circuit. The duty cycle correction circuit is used to correct the duty cycle of a clock signal. The storage device is used to record the training result of the duty cycle correction circuit. The control circuit is configured to perform training on the duty cycle correction circuit to correct the clock signal, and after the training is completed, the training result is recorded in the storage device, and before the next clock signal switching, the duty cycle correction circuit is updated using the training result recorded in the storage device.
[0017] In one embodiment of the present disclosure, the control circuit further performs data output to the duty cycle correction circuit while recording the training result.
[0018] In one embodiment of the present disclosure, the control circuit includes updating the duty cycle correction circuit using the recorded training result before performing training on the duty cycle correction circuit to correct the clock signal when receiving the next data output instruction.
[0019] In one embodiment of the present disclosure, the control circuit includes simultaneously executing training and data output for the duty cycle correction circuit, and after the training and data output are completed, recording the training result in a storage device.
[0020] In one embodiment of the present disclosure, the control circuit includes, when receiving the next data output instruction, before executing the training of the duty cycle correction circuit and data output, updating the duty cycle correction circuit using the recorded training results.
[0021] In one embodiment of the present disclosure, after recording the training result, the control circuit updates the duty cycle correction circuit using the recorded training result.
[0022] In one embodiment of the present disclosure, the control circuit further performs training on the duty cycle correction circuit to correct the clock signal when the power is turned on, and records the initial training results after the training is completed. When a data output instruction is received, the control circuit uses the recorded initial training results to update the duty cycle correction circuit before the clock signal switches.
[0023] In one embodiment of the present disclosure, the control circuit includes training the duty cycle correction circuit to output an output clock signal with a duty cycle of approximately 50%.
[0024] In one embodiment of the present disclosure, a duty cycle correction circuit includes a sensing circuit and an adjustment circuit, wherein when a clock signal is input into the adjustment circuit, the sensing circuit compares pulse widths generated by delays with each other and generates a corresponding duty cycle correction value based on the comparison result, and the adjustment circuit adjusts the duty cycle of the output clock signal according to the correction value, so that the duty cycle is corrected to approximately 50%.
[0025] In order to make the aforementioned features and advantages of the present disclosure more comprehensible, embodiments of the drawings are described in detail below. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Figure 1A and Figure 1B It is a schematic diagram of the execution timing of traditional DCC training.
[0027] Figure 2 is a block diagram of a duty cycle correction system according to an embodiment of the present disclosure.
[0028] Figure 3 is a flow chart of a duty cycle correction method according to an embodiment of the present disclosure.
[0029] Figure 4 It is a schematic diagram of a working cycle correction method according to an embodiment of the present disclosure.
[0030] Figure 5 It is a comparative schematic diagram of the working cycle correction method shown in the embodiment of the present disclosure.
[0031] Figure 6 It is a schematic diagram of a working cycle correction method according to an embodiment of the present disclosure.
[0032] Figure 7 It is a schematic diagram of a working cycle correction method according to an embodiment of the present disclosure.
[0033] FIG. 8A to FIG. 8C It is a schematic diagram of a working cycle correction method according to an embodiment of the present disclosure.
[0034] Description of Reference Numerals
[0035] 20: Duty cycle correction system
[0036] 22: Duty cycle correction circuit
[0037] 24: Storage device
[0038] 26: Control circuit
[0039] CLK1, CLK2: clock signal
[0040] S302~S308: Steps
[0041] T1~T10、t1~t6、t1′~t6′、t1″~t7″:time DETAILED DESCRIPTION
[0042] The embodiment of the present disclosure is to modify the update timing of the training result of the duty cycle corrector (DCC) circuit to reduce the duty cycle change when the clock signal is switched (toggle), thereby reducing the risk of chip function failure. The update timing includes before performing DCC training, after performing DCC training and data output, or before performing the next DCC training and data output, wherein the previous DCC training result will be recorded and used for the next update.
[0043] Figure 2 is a block diagram of a duty cycle correction system according to an embodiment of the present disclosure. Figure 2 The duty cycle correction system 20 of the present embodiment includes a duty cycle correction circuit 22 , a storage device 24 and a control circuit 26 .
[0044] The duty cycle correction circuit 22 is used to correct the duty cycle of the input clock signal so that the duty cycle of the output clock signal is closer to 50% than the duty cycle of the input clock signal. In some embodiments, the duty cycle correction circuit 22 includes a sensing circuit and an adjustment circuit. When the input clock signal is provided to the adjustment circuit, the adjustment circuit will adjust the delay to generate different pulses, which are provided to the sensing circuit for comparison. The pulse widths generated by the delay are compared with each other, and different training results are obtained according to different comparison results. The delay of the adjustment circuit is changed according to the training results to obtain an output clock signal of about 50%. This correction value will be provided to the adjustment circuit, and the adjustment circuit will use it to adjust the duty cycle of its output clock signal so that the duty cycle of the output clock signal can be corrected to about 50%.
[0045] In some embodiments, the duty cycle correction circuit 22 is configured in a high-capacity, high-performance semiconductor product such as a 3D NAND flash memory to correct the duty cycle of a clock signal provided to the semiconductor product. The semiconductor product is, for example, a non-volatile / volatile memory such as a flash memory, a dynamic random access memory (DRAM), or a logic device such as a microcontroller, which is not limited in this article.
[0046] The storage device 24 is, for example, an internal circuit or memory, such as a static random access memory (SRAM), a dynamic random access memory (DRAM), a NAND flash memory, a NOR flash memory, or a resistive random access memory (ReRAM) with a 2D or 3D structure, which is not limited in this article. The storage device 24 is used to record the training result of the duty cycle correction circuit 22.
[0047] The control circuit 26 is, for example, an external controller or an internal logic circuit, which is connected to the duty cycle correction circuit 22 and the storage device 24 to control the operation of the duty cycle correction circuit 22. The controller is, for example, a microcontroller or a microprocessor or other processors, which are not limited in this article.
[0048] Figure 3 is a flow chart of a working cycle correction method according to an embodiment of the present disclosure. Figure 2 and Figure 3 The method of this embodiment is suitable for the above-mentioned duty cycle correction system 20, and the detailed steps of the duty cycle correction method of this embodiment will be described below with reference to various circuits and components of the duty cycle correction system 20.
[0049] First, in step S302 , the control circuit 26 performs training on the duty cycle correction circuit 22 to correct the clock signal.
[0050] In step S304, the control circuit 26 determines whether the training of the duty cycle correction circuit 22 is completed. If the training of the duty cycle correction circuit 22 is not completed, the process returns to step S302 to continue the training.
[0051] If the training of the duty cycle correction circuit 22 is completed, then in step S306 , the control circuit 26 records the training result in the storage device 24 .
[0052] In step S308, the control circuit 26 updates the duty cycle correction circuit 22 using the training result recorded in the storage device 24 before the next clock signal toggle. The next clock signal toggle includes before performing DCC training, after performing DCC training and data output, or before performing the next DCC training and data output, and each embodiment will be described in detail below.
[0053] Figure 4 is a schematic diagram of a working cycle correction method according to an embodiment of the present disclosure. Figure 4 The duty cycle correction system, upon receiving the data output instruction, updates the duty cycle correction circuit (DCC) using the previously recorded result of the previous training at time T3 before the duty cycle correction circuit (DCC) is trained, and records the result of this DCC training at time T4 after the DCC training is completed, while performing data output. Thus, a more stable clock signal can be provided when the clock signal is switched.
[0054] In detail, Figure 5 is a comparative schematic diagram of a working cycle correction method according to an embodiment of the present disclosure. Figure 5 , the clock signal CLK1 shows the waveform of the clock signal using the traditional DCC training, which updates the DCC training result and performs data output at the same time at time T5 after the DCC training is performed. Updating the DCC training result will cause the duty cycle to change, resulting in errors in the data output. In contrast, the clock signal CLK2 shows the waveform of the clock signal using the duty cycle correction method of the embodiment of the present invention to perform DCC training, which uses the result of the previous DCC training to update the duty cycle correction circuit at time T6 before performing DCC training, and maintains the duty cycle of the clock signal CLK2 unchanged before receiving the next data read instruction, thereby providing a stable clock signal during the DCC training and data output process.
[0055] Figure 6 is a schematic diagram of a working cycle correction method according to an embodiment of the present disclosure. Figure 6 The duty cycle correction system updates the duty cycle correction circuit using the previously recorded result of the previous training at time T7 before the DCC training and data output when receiving the data output instruction, and records the result of this DCC training at time T8 after the DCC training and data output are completed. Thus, a more stable clock signal can be provided when the clock signal is switched.
[0056] Figure 7 is a schematic diagram of a working cycle correction method according to an embodiment of the present disclosure. Figure 7The duty cycle correction system performs DCC training and data output simultaneously when receiving the data output instruction, and records the result of this DCC training at time T9 after the DCC training and data output are completed, and then uses the recorded DCC training result to update the duty cycle correction circuit at time T10. In this way, a more stable clock signal can be provided when the clock signal is switched.
[0057] It should be noted that, in the aforementioned embodiment, each time the duty cycle correction system 20 receives a data output instruction, its control circuit 26 first uses the previous training result recorded in the storage device 24 to update the duty cycle correction circuit 22, and when the data output instruction is received for the first time, the duty cycle correction circuit 22 is updated using the result of the training performed on the duty cycle correction circuit 22 when the power is turned on.
[0058] In detail, when the power of the duty cycle correction system 20 is turned on, the control circuit 26 performs training on the duty cycle correction circuit 22 to correct the duty cycle of the clock signal, and after the training is completed, the initial training result is recorded in the storage device 24. When receiving a data output instruction, the control circuit 26 uses the initial training result recorded in the storage device 24 to update the duty cycle correction circuit 22 before the clock signal switches.
[0059] For example, FIG. 8A to FIG. 8C is a schematic diagram of a working cycle correction method according to an embodiment of the present disclosure. Fig. 8A , when the power is turned on, the duty cycle correction system performs training on the duty cycle correction circuit to correct the clock signal, and after the training is completed, records the initial training result. When the data output instruction is received for the first time, the duty cycle correction system uses the previously recorded initial training result to update the duty cycle correction circuit at time t1 before performing DCC training, and records the result of this DCC training at time t2 after the training is completed, and performs data output at the same time. When the data output instruction is received for the second time, the duty cycle correction system uses the DCC training result recorded at time t2 to update the duty cycle correction circuit at time t3 before performing DCC training, and records the result of this DCC training at time t4 after the training is completed, and performs data output at the same time. When the data output instruction is received for the third time, the duty cycle correction system uses the DCC training result recorded at time t4 to update the duty cycle correction circuit at time t5 before performing DCC training, and records the result of this DCC training at time t6 after the training is completed, and performs data output at the same time. By analogy, the duty cycle correction system will continue to perform DCC training, record DCC training results, perform data output, and update the duty cycle correction circuit operations to continuously provide a stable clock signal.
[0060] Please refer to Figure 8B , when the power is turned on, the duty cycle correction system performs training on the duty cycle correction circuit to correct the clock signal, and records the initial training result after the training is completed. When the data output instruction is received for the first time, the duty cycle correction system uses the previously recorded initial training result to update the duty cycle correction circuit at time t1′ before the DCC training and data output are performed, and records the result of this DCC training at time t2′ after the DCC training and data output are completed. When the data output instruction is received for the second time, the duty cycle correction system uses the training result recorded at time t2′ to update the duty cycle correction circuit at time t3′ before the DCC training and data output are performed, and records the result of this DCC training at time t4′ after the DCC training and data output are completed. When the data output instruction is received for the third time, the duty cycle correction system uses the training result recorded at time t4′ to update the duty cycle correction circuit at time t5′ before the DCC training and data output are performed, and records the result of this DCC training at time t6′ after the DCC training and data output are completed. By analogy, the duty cycle correction system will continue to perform DCC training and data output, record DCC training results, and update the duty cycle correction circuit operations to continuously provide a stable clock signal.
[0061] Please refer to Figure 8CWhen the power is turned on, the duty cycle correction system performs training on the duty cycle correction circuit to correct the clock signal, and records the initial training results after the training is completed. When the data output instruction is received for the first time, the duty cycle correction system uses the previously recorded initial training results to update the duty cycle correction circuit at time t1″ before performing DCC training and data output, and records the results of this DCC training at time t2″ after the DCC training and data output are completed, and then uses the recorded DCC training results to update the duty cycle correction circuit at time t3″. When the data output instruction is received for the second time, the duty cycle correction system first performs DCC training and data output, and records the results of this DCC training at time t4″ after the DCC training and data output are completed. As a result, and then at time t5″, the duty cycle correction circuit is updated using the recorded DCC training result. When the data output instruction is received for the third time, the duty cycle correction system first performs DCC training and data output, and at time t6″ after the DCC training and data output are completed, records the result of this DCC training, and then at time t7″, the duty cycle correction circuit is updated using the recorded DCC training result. Similarly, the duty cycle correction system will continue to perform DCC training and data output, record DCC training results, and update the duty cycle correction circuit to continuously provide a stable clock signal.
[0062] In summary, according to the embodiments of the present disclosure, a duty cycle correction method and a duty cycle correction system are proposed. By modifying the update timing of the training result of the duty cycle correction circuit, the duty cycle change when the clock signal is switched (toggle) can be reduced, thereby reducing the risk of chip function failure. The training result can be updated at a time when the clock signal has not yet switched, including before performing DCC training, after performing DCC training and data output, or before performing the next DCC training and data output. In this way, the duty cycle correction circuit can continue to provide a stable clock signal.
[0063] Although the present disclosure has been disclosed by the above-mentioned embodiments, the embodiments are not intended to limit the present disclosure. It will be apparent to those skilled in the art that various modifications and changes may be made to the structure of the present disclosure without departing from the scope or spirit of the present disclosure. Therefore, the protection scope of the present disclosure falls within the scope of the appended claims.
Claims
1. A duty cycle correction method for correcting the duty cycle of a clock signal using a duty cycle correction circuit, the method comprising the following steps: Performing training on the duty cycle correction circuit to correct the clock signal, and recording the training result after the training is completed; and Before the next switching of the clock signal, the duty cycle correction circuit is updated using the recorded training result.
2. The duty cycle correction method according to claim 1, further comprising: While recording the training results, data output is performed.
3. The duty cycle correction method according to claim 2, wherein before the next switching of the clock signal, the step of updating the duty cycle correction circuit using the recorded training result comprises: When the next data output instruction is received, before the training is performed on the duty cycle correction circuit to correct the clock signal, the duty cycle correction circuit is updated using the recorded training result.
4. The duty cycle correction method according to claim 1, wherein the step of performing training on the duty cycle correction circuit to correct the clock signal and recording the training result after the training is completed comprises: The training and data output of the duty cycle correction circuit are performed simultaneously, and after the training and the data output are completed, the training result is recorded.
5. The duty cycle correction method according to claim 4, wherein before the next switching of the clock signal, the step of updating the duty cycle correction circuit using the recorded training result comprises: When the next data output instruction is received, before executing the training of the duty cycle correction circuit and the data output, the duty cycle correction circuit is updated using the recorded training result.
6. The duty cycle correction method according to claim 4, wherein after simultaneously performing the training and the data output of the duty cycle correction circuit and recording the training result after the training and the data output are completed, the method further comprises: The duty cycle correction circuit is updated using the recorded training results.
7. The duty cycle correction method according to claim 1, further comprising: When the power is turned on, performing the training on the duty cycle correction circuit to correct the clock signal, and after the training is completed, recording the initial training result; as well as When a data output instruction is received, the duty cycle correction circuit is updated using the recorded initial training result before the clock signal is switched.
8. The duty cycle correction method according to claim 1, wherein the step of performing training on the duty cycle correction circuit to correct the clock signal comprises: The duty cycle correction circuit is trained to output an output clock signal with approximately a 50% duty cycle.
9. The duty cycle correction method of claim 8, wherein the step of training the duty cycle correction circuit to output an output clock signal with a duty cycle of approximately 50% comprises: When the clock signal is input into the duty cycle correction circuit, the pulse widths generated by the delay are compared with each other, and a corresponding duty cycle correction value is generated according to the comparison result; as well as The duty cycle of the output clock signal output by the duty cycle correction circuit is adjusted according to the correction value, so that the duty cycle is corrected to about 50%. 10 . The duty cycle correction method according to claim 1 , wherein the duty cycle correction circuit is disposed in a semiconductor product to correct the duty cycle of the clock signal provided to the semiconductor product.
11. A duty cycle correction system comprising: A duty cycle correction circuit, for correcting the duty cycle of a clock signal; A storage device for recording the training result of the duty cycle correction circuit; as well as A control circuit is configured to: Performing training on the duty cycle correction circuit to correct the clock signal, and after the training is completed, recording the training result in the storage device; as well as Before the next switching of the clock signal, the duty cycle correction circuit is updated using the training result recorded in the storage device.
12. The duty cycle correction system of claim 11, wherein The control circuit further performs data output while recording the training result.
13. The duty cycle correction system of claim 12, wherein The control circuit includes updating the duty cycle correction circuit using the recorded training result before performing the training on the duty cycle correction circuit to correct the clock signal when receiving the next data output instruction.
14. The duty cycle correction system of claim 11, wherein The control circuit includes executing the training and data output of the duty cycle correction circuit simultaneously, and recording the training result in the storage device after the training and the data output are completed.
15. The duty cycle correction system of claim 14, wherein The control circuit includes, when receiving the next data output instruction, before executing the training of the duty cycle correction circuit and the data output, updating the duty cycle correction circuit using the recorded training result.
16. The duty cycle correction system of claim 14, wherein After recording the training result, the control circuit further updates the duty cycle correction circuit using the recorded training result.
17. The duty cycle correction system of claim 11, wherein The control circuit further performs the training on the duty cycle correction circuit to correct the clock signal when the power is turned on, and records the initial training result after the training is completed, and when the data output instruction is received, before the clock signal is switched, updates the duty cycle correction circuit using the recorded initial training result.
18. The duty cycle correction system of claim 11, wherein The control circuit includes training the duty cycle correction circuit to output an output clock signal with a duty cycle of approximately 50%.
19. The duty cycle correction system according to claim 18, wherein the duty cycle correction circuit comprises a sensing circuit and an adjustment circuit, wherein When the clock signal is input into the adjustment circuit, the sensing circuit compares the pulse widths generated by the delay with each other, and generates a corresponding correction value of the duty cycle according to the comparison result; and The adjustment circuit adjusts the duty cycle of the output clock signal according to the correction value, so that the duty cycle is corrected to about 50%. 20 . The duty cycle correction system of claim 11 , wherein the duty cycle correction circuit is disposed in a semiconductor product to correct the duty cycle of the clock signal provided to the semiconductor product.