Tilt mitigation in self-aligned assisted assembly of IC die

Abstract

The title of the invention is "tilt mitigation in self-aligned assisted assembly of IC die". A surface of at least one of an integrated circuit (IC) die structure or a substrate structure to which the IC die structure is to be bonded includes an amphiphilic region adapted for liquid droplet confinement and droplet-based fine alignment of the IC die structure with the substrate structure. The amphiphilic region may include an inner region surrounded by a bonding region or between an adjacent pair of bonding regions. In particular, the internal region may improve fine alignment if there is a substantial amount of tilt between the bonding surface of the IC die structure and the bonding surface of the substrate structure during placement. The inner region may, for example, facilitate constraining two or more droplets on the bonding region. The inner or outer region of the amphiphilic structure may be segmented or continuous, and the intersecting IC die edges may also be non-orthogonal.

Description

Background Art

[0001] Integrated circuit (IC) dies may be assembled using solder attach techniques, where solder features are brought into contact with each other to bond the die to a host or base substrate structure. However, solder assembly techniques are difficult to scale down to solder joint feature pitches of tens of microns, e.g., 10-25 μm.

[0002] Alternatively, a hybrid bonding technique may be used to assemble the IC die, in which the metal bonding sites of the IC die are directly interdiffused with the corresponding metal bonding sites of the host or base substrate structure. Such bonding is called "hybrid" because bonding is also formed between dielectric materials adjacent to the metal bonding sites. During the hybrid bonding process, components (e.g., dies) with corresponding bonding sites are put together to butt against each other. At room temperature, the dielectric materials (e.g., due to van der Waals forces) are sufficiently adhered to establish an initial bond. Thermal annealing can then fuse the complementary metal bonding sites and also increase the strength of the dielectric material bonding interface. Hybrid bonding techniques can be fully reduced to below a bonding feature pitch of 1 μm. However, such nano-pitch assembly techniques rely on nanoscale (e.g., <500nm) fine alignment of the IC die to the base substrate structure, which may be time-consuming and / or expensive to implement.

[0003] Therefore, techniques and architectures for nanoscale hybrid bonding in high-volume manufacturing are commercially advantageous. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The materials described herein are shown in the accompanying drawings by way of example and not by way of limitation. For simplicity and clarity of illustration, the elements shown in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. In addition, where deemed appropriate, reference numerals have been repeated among the drawings to indicate corresponding or similar elements. In the drawings:

[0005] Figure 1 is a flow chart illustrating a method for self-alignment assisted assembly (SA3) of an integrated circuit (IC) die structure according to some embodiments;

[0006] Figure 2A is a cross-sectional view of a wafer or panel including a plurality of base substrate structures, each base substrate structure including a biphilic structure having an inner region that divides an IC die bonding area, according to some embodiments;

[0007] Figure 2B According to some embodiments Figure 2A A plan view of a base wafer or panel as shown in;

[0008] Figure 3Ais a cross-sectional view of an IC die structure including one or more amphiphilic structures within an IC die bonding region according to some embodiments;

[0009] Figure 3B According to some embodiments Figure 3A A plan view of the IC die structure shown in ;

[0010] Figure 4A is a cross-sectional view of a plurality of liquid droplets on an IC die bonding area of ​​a base substrate structure according to some embodiments;

[0011] Figure 4B According to some embodiments Figure 3A A plan view of a plurality of liquid droplets on a base substrate structure shown in FIG.

[0012] Figure 5A is a cross-sectional view of an IC die structure roughly aligned and placed on a plurality of liquid droplets according to some embodiments;

[0013] Figure 5B According to some embodiments Figure 5A A plan view of the alignment and placement of the IC die structure shown in ;

[0014] Fig. 6A is a cross-sectional view of a composite structure including an IC die structure hybrid bonded to a bonding region of a base substrate structure according to some embodiments;

[0015] Figure 6B According to some embodiments Fig. 6A A plan view of the composite structure shown in;

[0016] Figure 7 is a plan view of a liquid droplet on a bonding area of ​​a base substrate structure according to some alternative embodiments;

[0017] Figure 8 is a plan view of a bonding area on an IC die structure according to some alternative embodiments;

[0018] Fig. 9 is a plan view of a bonding area on an IC die structure according to some alternative embodiments;

[0019] Fig.10 is a cross-sectional view of a system including a host assembly and a heat sink assembled with a hybrid-bonded composite structure according to some embodiments;

[0020] Fig.11 illustrates a mobile computing platform and a data server machine using a multi-chip package according to some embodiments; and

[0021] Fig.12is a functional block diagram of an electronic computing device according to some embodiments. DETAILED DESCRIPTION

[0022] Embodiments are described with reference to the accompanying drawings. Although specific configurations and arrangements are depicted and discussed in detail, this is done for illustrative purposes only. Those skilled in the relevant art will recognize that other configurations and arrangements are possible without departing from the spirit and scope of the present description. Those skilled in the relevant art will appreciate that the techniques and / or arrangements described herein may be employed in a wide variety of other systems and applications beyond those described in detail herein.

[0023] In the following detailed description, reference is made to the accompanying drawings, which form a part of the description and illustrate exemplary embodiments. In addition, it is to be understood that other embodiments may be utilized, and structural and / or logical changes may be made without departing from the scope of the claimed subject matter. It should also be noted that directions and references (e.g., upward, downward, top, bottom, etc.) may be used only to facilitate the description of features in the figures. Therefore, the following detailed description is not to be considered restrictive, and the scope of the claimed subject matter is limited only by the appended claims and their equivalents.

[0024] In the following description, many details are set forth. However, it will be appreciated by those skilled in the art that embodiments may be practiced without these specific details. In some cases, well-known methods and devices are shown in block diagram form rather than in detail to avoid hiding the embodiments. References to "embodiment" or "one embodiment" or "some embodiments" throughout this specification mean that the specific features, structures, functions or characteristics described in conjunction with the embodiment are included in at least one embodiment. Therefore, the appearance of the phrase "in an embodiment" or "in one embodiment" or "some embodiments" throughout this specification does not necessarily refer to the same embodiment. In addition, in one or more embodiments, specific features, structures, functions or characteristics may be combined in any suitable manner. For example, the first embodiment may be combined with the second embodiment as long as the specific features, structures, functions or characteristics associated with the two embodiments are not mutually exclusive.

[0025] As used in the description and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0026] The terms "coupled" and "connected" together with their derivatives can be used in this article to describe the functional or structural relationship between components. These terms are not intended to be synonymous with each other. On the contrary, in a particular embodiment, "connected" can be used to indicate that two or more elements are in direct physical, optical or electrical contact with each other. "Coupled" can be used to indicate that two or more elements are in direct or indirect (there are other intermediary elements between them) physical or electrical contact, and / or two or more elements cooperate or interact with each other (e.g., as in a cause-and-effect relationship).

[0027] As used herein, the terms "above," "below," "between," and "on" refer to the relative position of one component or material with respect to other components or materials where such physical relationship is noteworthy. For example, in the context of materials, a material or layer may be in direct contact with or may have one or more intervening materials or layers above or below another material or layer. Additionally, a material between two materials or layers may be in direct contact with the two materials / layers or may have one or more intervening materials / layers. In contrast, a first material or layer that is "above" a second material or layer is in direct contact with the second material / layer. Similar distinctions are made in the context of component assemblies.

[0028] As used throughout this description and in the claims, a list of items linked by the term "at least one of" or "one or more of" may mean any combination of the listed terms. For example, the phrase "at least one of A, B, or C" may mean A; B; C; A and B; A and C; B and C; or A, B, and C.

[0029] Unless otherwise specified in the specific context of use, the term "predominantly" means more than 50%, or more than half. For example, a component that is predominantly the first component means that more than half of the component is the first component (e.g., <50 at.%). The term "primarily" means the most or largest portion. For example, a component that is predominantly the first component means that the component has more of the first component than any other component. A component that is predominantly the first and second components means that the component has more of the first and second components than any other component. The term "substantially" means only incidental variations. For example, a component that is predominantly the first component means that the component may further include <1% of any other component. A component that is predominantly the first and second components means that the component may further include <1% of any component that replaces or is the first or second component.

[0030] As previously described, hybrid bonding techniques provide advantages in assembling an IC die structure to other IC die structures (active or passive) or some other host component (such as a package substrate structure, an interposer structure, etc.). As used herein, an IC die structure may include any monolithic integrated circuit device that provides electrical, computing, memory, or similar functionality. The IC die structure itself may include more than one monolithic integrated circuit device. For example, the IC die structure may include two vertically stacked or coplanar IC dies. The IC dies within the IC die structure may be directly bonded to each other, or coupled through some intermediate wiring structures. For example, an IC die structure according to an embodiment of the present invention may be referred to as a "chiplet", "chiplet die", "die", "chiplet" or "chip". Although the terms chiplet and IC die or chip may be used interchangeably, a full-function ASIC is generally considered to be an IC die or chip, while a chiplet or chiplet may have more limited functionality, such as supplementing one or more other IC chiplets to be part of the same multi-chiplet device. The chiplet or die may be, for example, a wireless radio circuit, a microprocessor core, an electronic memory circuit, a floating point gate array (FPGA), a power management and / or power supply circuit, or include a MEMS device.

[0031] In the context of hybrid bonded IC die structures, self-aligned assisted assembly (SA3) can promote die-to-wafer hybrid bonding (D2W HB) throughput growth by reducing the fine alignment burden. In some exemplary SA3 processes, the bonding area is incorporated into or an "amphiphilic" or "heterogeneous" structure on the IC die structure or the base substrate structure (or both). As used herein, the amphiphilic / heterogeneous structure includes a surface with a high wettability contrast between different regions thereof. As further described herein, a high wettability contrast can be obtained by physical patterning (e.g., creating grooves around the bonding area to constrain the liquid via the canthotaxis effect), chemical patterning (e.g., depositing a hydrophobic coating around the bonding area to reduce the surface energy), or a combination of the two (e.g., creating grooves with sidewalls with a hydrophobic coating around the bonding area).

[0032] In the amphiphilic structure, one area has high wettability relative to another low wettability area. This wettability contrast can improve the control of the spread of liquid droplets, so that the liquid droplets can be constrained to the bonding area of ​​the IC die structure or the base wafer (or both). When the droplets evaporate, the surface tension of the droplets acts to passively finely align the IC die structure, so that the bonding area remains in contact and is ready for hybrid bonding. At room temperature, the surface attraction between the dielectric area on the IC die structure and the base substrate structure may be sufficient to temporarily stick the two. Subsequently, a hybrid bond can be formed by applying pressure and / or increasing the temperature to form and / or strengthen the bond between the metal features (e.g., copper pads) dispersed in the surrounding dielectric material. Once bonded, the metal features form composite metal features that electrically interconnect the IC die structure and the base substrate structure. However, in some embodiments, the bond (e.g., for thermal applications or some RF applications) may be only dielectric-dielectric or only metal-metal.

[0033] Thus, with SA3, the bonder can pick and place the IC die structure on the base substrate structure with coarse alignment (e.g., ~25-50 μm), enabling rapid assembly. When the liquid droplet is constrained to the bonding area between the IC die structure and the base substrate structure, the capillary force and the liquid surface tension cause alignment with high positioning accuracy (e.g., <200 nm) due to the amphiphilic structures present on the mating surfaces of the IC die structure and / or the base substrate structure. Therefore, such amphiphilic or heterogeneous structures may be more specifically referred to as "self-aligned features" or "SA3 features."

[0034] The inventors have noted that, while the relationship between droplet energy and IC die alignment is favorable for bonding surfaces with a high degree of coplanarity, the lowest energy state of the droplet surface may not correspond to an ideal alignment condition when the bonding surfaces are not substantially parallel planes, but rather one bonding surface has some non-zero tilt relative to the other bonding surface. For example, when a die bonding head places an IC die structure on a droplet, the head surface may have some tilt relative to a reference plane of the complementary bonding surface, which may be further defined by a workpiece chuck or base of the bonder. The IC die structure, when released from the head and becomes supported by the droplet, may likewise be non-parallel to the reference plane.

[0035] While the design of SA3 features may be primarily intended to achieve lateral fine alignment by correcting in-plane displacements or rotations of the IC die structure caused by inaccuracies in coarse alignment, if such features are not capable of correcting out-of-plane tilt, then any incoming tilt of the IC die structure (e.g., due to lack of coplanarity between the bond head and the pedestal) may be magnified when the die structure is released onto the liquid droplet. Unless the SA3 technology adequately addresses the challenges associated with tilt, this may result in assembly yield losses due to bonding or misalignment issues.

[0036] As further described below, embodiments herein include hybrid bonding of an IC die structure to a substrate structure as facilitated by fine alignment of liquid droplets. To ensure excellent alignment performance, the IC die structure and / or substrate structure include an amphiphilic structure that includes one or more internal regions dispersed within the die bonding site region. These internal regions can be continuous to bifurcate or divide the die bonding site into completely separate bonding regions in which different droplets may be contained. Alternatively, these internal regions can be segmented, for example to modulate how one or more droplets within a continuous bonding region may respond to non-coplanarity between a bonding site and a complementary bonding site to which it is to be bonded. As further described below, the peripheral region outside the bonding region may also be segmented, for example to modulate how one or more droplets within the bonding region may respond to non-coplanarity.

[0037] Figure 1 1 is a flow chart illustrating a self-aligned assisted assembly (SA3) method for an integrated circuit (IC) die structure according to some embodiments. In method 101, a plurality of liquid droplets are formed on a bonding site of either or both of an IC die structure or a base substrate structure to be bonded to the IC die structure. For example, method 101 may be practiced to form one or more of the assemblies described elsewhere herein. Method 101 is illustrated as including several discrete blocks to ensure clarity of description. However, in practice, the number of blocks and / or the order of the blocks may be modified without departing from the principles illustrated in method 101.

[0038] Method 101 begins with input 110, where a base substrate structure is received. The base substrate structure can be any wafer, panel, strip, etc. suitable for direct bonding with one or more IC die structures. The bonding sites to which the IC die structures are to be attached are integrated into one or more amphiphilic structures suitable for SA3 assembly.

[0039] Figure 2A2 is a cross-sectional view of a wafer (or panel) 200 including a plurality of aggregated "base" or "host" substrate structures 201A, 201B, 201C. In the example shown, each base substrate structure 201A-201C includes one or more amphiphilic structures on a first (e.g., top) side of one or more substrate materials 201.

[0040] The substrate material 201 may vary widely depending on the implementation. In some embodiments, where each base substrate structure 201A-201C is a package substrate structure or a package insert layer, the substrate material 201 may include one or more layers of structural materials, such as silicon (e.g., single crystal), sapphire, or glass. The substrate material 201 may include any of those found in integrated circuit wafers, such as semiconductor materials (e.g., silicon, germanium, GaN, GaAs, InP, InGaAS, etc.), on-die interconnect layers (e.g., copper, aluminum, tantalum, other metals), and on-die dielectrics (e.g., silicon dioxide, carbon-doped silicon dioxide, silicon nitride, silicon carbide, etc.). For glass embodiments, the structural material may be mostly silica (e.g., silicon and oxygen), and may further include one or more elements, such as hydrogen, carbon, and / or metals (such as, but not limited to, copper, silver, gold, aluminum, beryllium, magnesium, calcium, strontium barium, or radium). Additional dopants (e.g., boron, phosphorus) may also be present in the structural material (e.g., borosilicate glass, etc.).

[0041] The encapsulation substrate structure or interposer may include one or more metallization redistribution or electrical wiring levels (not depicted) embedded in the encapsulation dielectric material. For example, the encapsulation dielectric material may have been built on one or more sides of the structural material layer. The structural material layer may be retained or eventually discarded so that the substrate material 201 may include only the encapsulation dielectric material and the embedded wiring metallization. The encapsulation dielectric material may be any organic dielectric, such as epoxy resin, phenolic glass, or resin film (such as GX series films commercially available from Ajinomoto Fine-Techno Co., Inc. (ABF)). The encapsulation dielectric material may include an epoxy resin (e.g., an acrylate of a phenolic varnish, such as epoxy phenol novolac (EPN) or epoxy cresol novolac (ECN)). In other examples, the encapsulation dielectric material includes an aliphatic epoxy resin, which may be monofunctional (e.g., dodecanol glycidyl ether), difunctional (butylene glycol diglycidyl ether), or have a higher functionality (e.g., trimethylolpropane triglycidyl ether).

[0042] The substrate material 201 may include one or more IC die structures (not depicted). In some embodiments, the IC die structures are embedded within a packaging dielectric material. In other embodiments, each of the base substrate structures 201A-201C is an IC die structure. Such IC die structures may be fully functional ASICs, or may be chiplets or chips of more limited functionality to supplement one or more other IC die structures to be part of the same multi-chip device. For embodiments in which the base substrate structures 201A-201C are IC die structures, the substrate material 201 may include any of those typical materials of monolithically manufactured IC dies, such as, but not limited to, device material layers and / or silicon (e.g., single crystal) layers, and inorganic dielectric materials (e.g., including at least 20 atomic % of one or more of silicon, oxygen, or nitrogen).

[0043] The basic substrate structure 201A-201C has an amphiphilic surface structure, wherein there is a wettability contrast between the peripheral region 204 of low wettability and the adjacent bonding regions 203A and 203B of high wettability, and liquid droplets are formed in each bonding region. Although the liquid is variable (polar or non-polar, etc.), in the exemplary SA3 embodiment using water, the bonding regions 203A and 203B of high wettability are hydrophilic (i.e., causing the water droplets to have a contact angle of less than 90°). Therefore, when the liquid minimizes its surface energy, the water droplets will tend to spread over the regions 203A and 203B. The adjacent peripheral region 204 of low wettability is hydrophobic (i.e., causing the water droplets to have a large contact angle greater than 90°). The water droplets on the regions 203A and 203B will tend to minimize contact with the peripheral region 204.

[0044] For example embodiments in which regions 203A, 203B are hydrophilic materials, regions 203A, 203B may advantageously include one or more metal features 230 embedded in and / or dispersed over dielectric material 218. Each of metal features 230 may include any metal known to be suitable for direct bonding. For example, metal features 230 may most likely be Cu. One or more of metal features 230 advantageously electrically couple to host component wiring metallization and / or circuit modules (not depicted). Thus, metal features 230 are intended to electrically couple and physically adhere base substrate structures 201A-201C to IC die structures.

[0045] The dielectric material 218 may have any chemical composition suitable for hybrid bonding. The dielectric material 218 is advantageously an inorganic material, for example, including at least 20 atomic % of one or more of silicon, oxygen, or nitrogen. In some embodiments, the dielectric material 218 is primarily silicon and oxygen (e.g., SiO 2 ), mainly silicon and nitrogen (e.g., Si 3 N2 ), or mainly silicon, oxygen, and nitrogen (e.g., Si x O y N x ), any of which may further include one or more dopants, such as carbon. However, inorganic dielectric materials are different from organic dielectrics (e.g., epoxy resins and phenolic glasses), which have much higher carbon contents and a higher percentage of carbon-hydrogen bonds.

[0046] For some exemplary embodiments in which the peripheral region 204 is a hydrophobic material, the peripheral region 204 may include any chemical coating or film material and / or morphological structure that creates a hydrophobic boundary adjacent to one or more edges of the bonding region 203A, 203B. In some embodiments, the hydrophobic material is a self-assembled monolayer (SAM) material, such as an alkyl or fluoroalkyl silane (e.g., ODS, FDTS), a thiol (e.g., hexadecanethiol), a phosphonic acid (e.g., octadecyl or perfluorooctanephosphonic acid), or an alkanoic acid (e.g., heptadecanoic acid). Other SAM embodiments may include disulfides, amines, azoles, amides, imides, pyridine derivatives, cyanoacrylate derivatives, or other parts containing sulfur atoms or nitrogen atoms. SAM reactions typically form monolayer molecules aligned to each other in a uniform manner. Such molecules can be introduced in the gas phase and "self-assembled" by forming a highly selective bond on the surface and orienting themselves perpendicular to the surface. However, non-SAM-based materials or films are also possible. In some embodiments, the peripheral region 204 is or includes a polymer film, such as siloxane (e.g., PDMS and derivatives, HMDSO), silazane (HMDS), polyolefin (e.g., PP), or fluorinated polymer (e.g., PTFE, PFPE, PFDA, C 4 F 8 In some advantageous embodiments, region 204 includes a material having a chemical composition of at least 10 atomic percent (at.%) carbon or at least 10 at.% fluorine.

[0047] The peripheral region 204 may additionally or alternatively include a topographic feature that increases the wettability contrast relative to the junction region 203A, 203B. The topographic grooves in the peripheral region 204 may, for example, improve the wettability contrast between the region 204 and the junction region 203A, 203B. Such topographic features can change the effective contact angle of the liquid droplet to greater than 90°, thereby changing the surface energy characteristics of the droplet. In some further embodiments, the average surface roughness of the peripheral region 204 is significantly higher than that of the junction region 203A, 203B. Any surface texturing technique (such as laser surface roughening) can be used to roughen the region 204. The roughened surface may have any surface roughness greater than the surface roughness of the junction region 203A, 203B. For example, the junction region 203A, 203B may have a low surface roughness (e.g., <30nm average roughness), while the peripheral region 204 has a high surface roughness (e.g., >50nm average roughness). In some embodiments, the average surface roughness of the peripheral region 204 is at least twice the average surface roughness of the surface of the joining region 203A, 203B, and may be five, ten, or twenty times the average surface roughness of the surface of the joining region 203A, 203B. As used herein, the average roughness (or centerline average) is as described in ASME B46.1. The average roughness is the arithmetic mean of the absolute value of the deviation of the profile height relative to the average line recorded for the evaluation length. For example, a profilometer including a stylus moving back and forth over the surface can be used to measure the average roughness. For a region 204 having a longitudinal length in a first dimension (e.g., coinciding with the x-axis), the average roughness can be measured at a distance of approximately 60-70% of the longitudinal length, while remaining near the centerline of the lateral width of the region 204, which is in a dimension substantially orthogonal to the first dimension (e.g., coinciding with the y-axis).

[0048] like Figure 2A As further shown in FIG. 1 , the inner region 204' is between two adjacent joining regions 203A and 203B. The inner region 204' also has a wettability contrast with the joining regions 203A and 203B. The inner region 204' may have any of the composition, topographical features, and / or surface characteristics described for the peripheral region 204. In some exemplary embodiments, the inner region 204' has substantially the same chemical composition, surface morphology, and / or surface characteristics as the peripheral region 204. Alternatively, the inner region 204' may have a different chemical composition, surface morphology, and / or surface characteristics than the peripheral region 204.

[0049] Figure 2B is a plan view of a base wafer or panel 200 according to some embodiments. Figure 2B Indicated by the dotted line Figure 2AThe A-A' cross section shown in FIG. Figure 2B As further shown in, bonding area 203A, 203B are two of the four bonding areas further including area 203C and 203D. Therefore, each basic substrate structure 201A-201C has four bonding areas 203A-203D, and peripheral area 204 is adjacent to the outer edge of area 203A-203D. Bonding area 203A-203D is further delimited by inner area 204' (distinguished by thick dotted lines). In this example, inner area 204' is substantially adjacent to peripheral area 204. Peripheral area 204 is a continuous peripheral frame, and inner area 204' is a continuous intermediary twelve-sided polygon that separates a quarter of a 2D grid. In each quarter is one of area 203A-203D. As further described below, this 2D array of bonding areas may be advantageous for alleviating the tilt or non-planarity that may be in one or more dimensions in the x dimension or y dimension between bonding sites.

[0050] The joining regions 203A-D may have contrasting feature shapes, and / or contrasting surface roughness, and / or contrasting chemical compositions relative to the inner region 204' and the peripheral region 204. Figure 2A-2B In the example shown, both the peripheral region 204 and the inner region 204' are in contact with the sidewalls of the bonding regions 203A-D. As described further below, the bonding regions 203A-D match the desired layout of the individual IC die structures to be attached to each of the base substrate structures 201A-201C. In this example, the peripheral region 204 and the inner region 204' are within grooves formed in one or more substrate materials 201. Alternatively, the bonding regions 203A-B can each be a pedestal or mesa above the substrate material 201.

[0051] The peripheral region 204 and the inner region 204' are each adjacent to a plurality of non-parallel edges of each bonding region (e.g., 203A, 203B). The regions 204, 204' may be formed on the sidewalls of the bonding regions 203A-D according to any (one or more) suitable techniques. For example, a conformal hydrophobic material layer may be formed on the exposed surfaces of the bonding regions 203A-D, such as by spin coating or conformal vapor deposition processes. The conformal hydrophobic material layer may then be patterned using an anisotropic "spacer" etch.

[0052] Return to Figure 1, method 101 receives an IC die structure at a second input 115. The IC die structure received at input 115 may include a single IC die, or may include any number of IC dies assembled (e.g., hybrid bonded) into a coplanar or 3D IC die structure. The IC die structure may, but need not, further include an organic dielectric material and / or metallization levels built on the IC die surface using a suitable semi-additive process (SAP).

[0053] Figure 3A is a cross-sectional view of an IC die structure 301 including one or more amphiphilic structures within a bonding site, according to some embodiments. Figure 3B According to some embodiments Figure 3A The plan view of the IC die structure shown in . Figure 3B middle, Figure 3A The section line shown in FIG. 1 is indicated by a dotted line AA'.

[0054] exist Figure 3A and Figure 3B In the exemplary embodiment shown, the IC die structure 301 includes an IC die substrate material 317, a device layer 310 in contact with the IC die substrate material 317, and an IC die metallization level 315 above the device layer 310. Although not shown, the IC die structure 301 may include a substrate structure via (TSV) extending from the device layer 310 into the IC die substrate material 317. The chemical composition of the IC die substrate material 317 may vary with implementation. In an exemplary embodiment, the IC die substrate material 317 is a silicon (e.g., single crystal) layer. The IC die substrate material 317 may also have alternative compositions, such as, but not limited to, germanium (Ge), silicon germanium alloy (SiGe), gallium arsenide alloy (GaAs), indium phosphide alloy (InP), gallium nitride alloy (GaN), silicon carbide alloy (SiC), etc. The device layer 310 includes active devices (not depicted). In some embodiments, the active devices within the device layer 310 are field effect transistors (FETs). The FETs may be of any architecture (e.g., planar, non-planar, single-gate, multi-gate, stacked nanosheets, etc.) and may have a characteristic pitch of 5-30 nm. Additionally or alternatively, the device layer 310 may include active devices other than FETs. For example, the device layer 310 may include electronic memory structures, spin valves, and the like.

[0055] The IC die structure 301 includes an IC die metallization level 315 on the front side of the device layer 310. In an exemplary embodiment, the metallization level 315 includes a die metallization feature 330 embedded in a dielectric material 318. Although the IC die metallization feature 330 can have any (one or more) components with sufficient electrical conductivity, in an exemplary embodiment, the IC die metallization feature 330 is mostly Cu. In other examples, the metallization feature 330 is mostly other than Cu, such as but not limited to mostly Ru or mostly W.

[0056] The IC die structure 301 further includes a base substrate structure corresponding to the base substrate structure 201A ( Figure 2A -B) on the amphiphilic structure of the complementary structure. For the IC die structure 301 ( Figure 3A ), the bonding regions 303A and 303B include the uppermost one of the metallization features 330. The bonding regions 303A and 303B may have a bonding region 203A, 203B ( Figure 2A ) compatible with any feature pitch. In some exemplary embodiments, the metallization feature 330 ( Figure 3A ) corresponds to metallization feature 230 ( Figure 2A ), for example, both have a feature pitch in the range of 20 nm to 1 μm. As an example, metallization feature 330 ( Figure 3A ) may have any suitable composition and may have a similar composition to the metallization feature 230 ( Figure 2A ) are substantially the same composition. The bonding regions 303A, 303B ( Figure 3A ) further includes a dielectric material 318, which may have any of the inorganic compositions described for dielectric material 218. Therefore, the bonding regions 330A, 330B are highly compatible with the bonding regions of the corresponding base substrate structure in terms of hybrid bonding.

[0057] The IC die structure 301 further includes a peripheral region 304 adjacent to one or more outer edges of the bonding regions 203A, 203B. The peripheral region 304 is located within the footprint of the IC die structure 301 defined by the die edge sidewalls 305. The peripheral region 304 may have the same characteristics as those described elsewhere herein for the peripheral region 204 ( Figure 2A ) In some embodiments, the bonding regions 203A, 203B and the peripheral region 304 are fabricated according to any of the techniques discussed above for the corresponding amphiphilic regions of the base substrate structure. The amphiphilic surface structure on the base substrate structure and the amphiphilic structure on the IC die structure may be substantially the same (as shown), or they may be compositionally and / or structurally different.

[0058] like Figure 3A As shown in FIG. 1 , the inner region 304′ is between two adjacent junction regions 303A and 303B. The inner region 304′ also has a wettability contrast with the junction regions 303A and 303B. The inner region 304′ may have a wettability contrast with the inner region 204′ ( Figure 2B ), the peripheral area 204 or the peripheral area 304 ( Figure 3A , 3B ) In some exemplary embodiments, the inner region 304' has substantially the same chemical composition, surface morphology, and / or surface characteristics as the peripheral region 304. Alternatively, the inner region 304' may have a different chemical composition, surface morphology, and / or surface characteristics than the peripheral region 304.

[0059] like Figure 3B As shown in , the bonding regions 303A, 303B are two of the four bonding regions further including regions 303C and 303D. Therefore, the IC die structure 301 has four bonding regions 303A-303D, and the peripheral region 304 is adjacent to the outer edges of the regions 303A-303D. The bonding regions 303A-303D are further delineated by the inner region 304' (distinguished by a thick dashed line). In this example, the inner region 304' is substantially adjacent to the peripheral region 304. The peripheral region 304 is a continuous peripheral frame, while the inner region 304' is a continuous intermediate dodecagon that separates one quarter of the 2D grid. Within each quarter is one of the regions 303A-303D. Relative to the inner region 304' and the peripheral region 304, the bonding regions 303A-D may have contrasting feature shapes, and / or have contrasting surface roughness, and / or have contrasting chemical compositions. In Figure 3A-3B In the example shown, both the peripheral region 304 and the inner region 304' are in contact with the sidewalls of the bonding regions 303A-D. As described further below, the bonding regions 303A-D match complementary structures of the base substrate structure to which the IC die structure 301 is to be bonded. In this example, both the peripheral region 304 and the inner region 304' are in trenches formed in the dielectric material 318. Alternatively, the bonding regions 303A-B can each be a pedestal or mesa above the IC die metallization level 315.

[0060] Regions 304, 304' are each adjacent to a plurality of non-parallel edges of each bonding region (e.g., 303A, 303B). Peripheral region 304 and inner region 304' may be formed on the sidewalls of bonding regions 303A-D according to any (one or more) suitable techniques. For example, a conformal hydrophobic material layer may be formed on the exposed surfaces of the bonding side regions 303A-D, such as by spin coating or conformal vapor deposition processes. The conformal hydrophobic material layer may then be patterned using an anisotropic "spacer" etch.

[0061] The peripheral region 304 and the inner region 304 ′ may be a single continuous material and / or structure having a hydrophobic surface. Alternatively, the regions 304 , 304 ′ may include a plurality of discontinuous segments of hydrophobic material and / or structure that define a perimeter around two or more edges of the joining region 303 . Figure 3A and Figure 3B An example is shown in which the IC die structure 301 includes a 2D x-y grid of bonding areas. As described further below, such a 2D array may be advantageous for mitigating tilt or non-planarity between bonding surfaces that may be in one or more of the x- or y-dimensions.

[0062] Return to Figure 1 , method 101 continues at block 120, where liquid droplets are formed on each of the plurality of bonding regions of the base substrate structure and / or the corresponding IC die structure. Any technique suitable for the particular liquid, such as vapor condensation or direct liquid dispensing (i.e., printing), may be practiced at block 120, as the embodiments are not limited in this regard. In some exemplary embodiments, aqueous (e.g., water) droplets are dispensed at block 120. However, depending on the nature of the wettability contrast of the amphiphilic structure on the base substrate structure and / or the IC die structure, a selected polar liquid (e.g., alcohol) or a non-polar liquid (e.g., solvent) may be dispensed at block 120.

[0063] Figure 4A is a cross-sectional view of a base substrate structure 201A having a plurality of liquid droplets 405A, 405B on IC die bonding areas 203A, 203B, respectively. Figure 4B4 is a plan view of a base substrate structure 201A, further illustrating that droplets 405A and 405B are two of four liquid droplets 405A-405D. Each droplet 405A-405D is constrained to a corresponding bonding region 203A-203D. The constraints of the liquid droplets 405A-405D by the peripheral region 204 and the inner region 204' are similar to the constraints of the liquid droplets formed over one or more base substrate structures to be coupled with multiple IC die structures. However, according to embodiments herein, the base substrate structure 201A is to receive a single IC die structure with multiple liquid droplets 405A-405D to mitigate non-planarity between the base substrate structure 201A and the IC die structure to which it is to be bonded.

[0064] The presence of multiple droplets at a single die junction increases the freedom to independently vary the droplet volume across the multiple droplets and / or otherwise manipulate the properties of each droplet. For example, in some embodiments, liquid droplets 405A-405D contain significantly different liquid volumes. Figure 4A and 4B As shown in , for example, liquid droplet 405B has a larger volume than liquid droplet 405A. For embodiments where junction region 203B has substantially the same area as junction region 203A (e.g., Figure 4B ), the larger liquid volume causes droplet 405B to have a vertical (e.g., z-dimension) height H2 that is greater than height H1 of droplet 405A. Such variations in droplet volume and / or height can mitigate non-planarity between the xy plane of base substrate structure 201A and the xy plane of the IC die to be bonded.

[0065] In other embodiments, even in the case where the droplet volume is substantially the same across all droplets 405A-405D, the interior region 204' and / or the peripheral region 204 may have significant variations due to their (one or more) polygonal shapes or surface characteristics, thereby independently changing the wetted area of ​​each droplet across multiple droplets. For example, although the junction regions 203A-203D are shown as all being substantially the same xy dimensions, one or more junction regions may instead be smaller (larger) in area than the remaining regions. For example, in the case where the junction region 203B is smaller in area than the junction region 203A, even if the two droplets 405A and 405B have substantially the same liquid volume, the droplet 405B may have a vertical (e.g., z-dimension) height H2 that is greater than the height H1 of the droplet 405A.

[0066] As the droplets are formed, method 101 ( Figure 1) continues at block 130, where the IC die structure received at input 115 is placed over the bonding site of the base substrate structure received at input 110. For example, block 130 may be implemented using a pick-and-place machine associated with some limited positioning precision and accuracy.

[0067] Figure 5A is a cross-sectional view of an IC die structure 301 roughly aligned and placed on a plurality of liquid droplets including droplets 405A, 405B, according to some embodiments. Figure 5B is a plan view of the alignment and placement of the IC die structure 301 . Figure 5A A non-zero tilt, elevation or inclination angle θ is shown associated with the IC die head 550. Depending on the machine setup, the head tilt angle θ may deviate from horizontal by as much as several degrees (eg, 0.1°-2°) relative to a reference xy plane that is horizontal and supports a pedestal or chuck of the substrate structure 201A.

[0068] The head tilt angle θ can be mapped to a corresponding xy component. Non-zero tilt θ can be mitigated, for example, by an assembly qualification process whereby a test IC die structure is repeatedly positioned on liquid droplets 405A-405D of varying size as a control variable, and the resulting xy fine alignment is measured for each pass as a response variable in order to derive a menu of liquid droplet properties that minimize misalignment. Figure 5A In the example shown in , the head tilt angle θ has an x ​​component, causing the bonding region 303A to lag behind the bonding region 303B during the approach to the base substrate structure 201A. The liquid droplet 405B having a larger height H2 can ensure that the die leading edge sidewall 305 remains suspended on the droplet 405B despite the approach angle, which otherwise can cause premature contact between the die leading edge sidewall 305 and the bonding surface of the base substrate structure 201A. Although Figure 5A Only the x component is shown in FIG. 1 , but the head tilt angle may also have a non-zero y-dimensional component, which may be similarly expressed by, for example, the liquid droplets 405A and 405C ( Figure 4B ) and / or changing the droplet height between droplets 405B and 405D to mitigate. Thus, while as few as two die bonding areas may be provided for a given die bonding site, providing at least three die bonding areas may advantageously define a plane for accommodating or mitigating tilt in both the x and y dimensions.

[0069] exist Figure 5BSome lateral (xy) alignment errors are shown in FIG, where liquid (e.g., water) droplets 405A-405D correct for misalignment during a passive fine alignment phase (e.g., via capillary forces, etc.) until the droplets evaporate. In an exemplary embodiment, fine alignment is advantageously within 200 nm in each of the x-dimension and the orthogonal y-dimension. Such fine alignment can be obtained from a coarse alignment within 25 μm in each of the x-dimension and the orthogonal y-dimension, assuming that any non-zero tilt angle θ is reduced to a point where the fine alignment process can proceed substantially unimpeded.

[0070] Return to Figure 1 The method 101 continues at block 140 by evaporating the liquid droplet between the IC die structure and the base substrate structure to bring the IC die structure bonding region into direct contact with the base substrate structure bonding region. The IC die structure is then bonded to the base substrate structure according to any (one or more) suitable hybrid bonding techniques. Fig. 6A An exemplary hybrid-bonded composite structure 601 is shown in which the IC die structure 301 is now in contact with the base substrate structure 201A along the bonding interface 450 represented by the thick dashed line. As shown, the metal feature 230 is in direct contact with at least a portion of a corresponding one of the metal features 330. The dielectric material 218 of the base substrate structure 201A is also in direct contact with the dielectric material 318 of the IC die structure 301. In each of the x- and y-dimensions, the extent of the lateral offset between the metal features 230 and 330 along the bonding interface 450 indicates the tolerance achieved by the self-aligned fine alignment process.

[0071] In the illustrated example, the peripheral region 204 of the amphiphilic structure on the base substrate structure 201A is co-located with the corresponding peripheral region 304 on the IC die structure 301. The peripheral region 204 may also be in direct contact with the peripheral region 304 along the bonding interface 450, although the two may not diffuse or fuse with each other to form a unified composite structure even after the thermal and / or compression bonding process. The peripheral region 204 may also be physically separated from the peripheral region 304 on both sides of the bonding interface 450. The inner region 204' is similarly co-located with the corresponding inner region 304'. The inner regions 204', 304' may also be in direct contact, although they may not diffuse or fuse with each other to form a unified composite structure even after the thermal and / or compression bonding process. The inner regions 204', 304' may also be physically separated on both sides of the bonding interface 450, depending on the topography of the amphiphilic surface structure.

[0072] Return to Figure 1, method 101 ends at output 180, wherein the IC die package is completed according to any known technique. For example, a packaging or filling material may be deposited over the bonded IC die structure and over the portion of the base substrate structure not obscured by the IC die structure. The filling material is advantageously a dielectric material, and may be an inorganic or organic dielectric material, such as any of those described above. In some embodiments, the filling material is deposited to a thickness at least equal to the thickness of the IC die structure. The filling material may be deposited by any known technique suitable for the selected material composition and thickness. Depending on the deposition process, the dielectric filling material may be flat along the length spanning the IC die structure and beyond the edge of the IC die structure. The packaging and / or filling material may also be flattened, for example, using a chemical mechanical planarization (CMP) system or other suitable grinder and / or polisher. The flattening process may also significantly thin the bonded IC die structure. The flattening process may thin the bonded IC die structure to the limit of the total thickness variation (TTV) of the workpiece. In some embodiments, the thickness of the IC die substrate structure (eg, silicon layer) is reduced by at least 30%, and advantageously by at least 80%.Afterwards, any known process may be performed to obtain a singulated hybrid-bonded IC die package / assembly.

[0073] In some embodiments, one or more of the periphery or interior regions of the amphiphilic structure include segments separated by one or more bonding regions. For embodiments where the interior region includes segments surrounded by continuous bonding regions, the segment design can regulate how a liquid droplet in one bonding region can migrate to another bonding region, for example in response to an approaching IC die structure that is not perfectly coplanar with the bonding regions. Figure 7 203A, 203B, 203C, and 203D, respectively. As shown, the inner region 204' includes four segments surrounded by continuous bonding regions 203A-203D. The liquid migration path around the inner region 204' is represented by arrows. Therefore, the liquid droplets 405A-405D may start as four discrete droplets and then merge into fewer droplets, for example, in response to contact with corresponding bonding regions (e.g., on the IC die structure). Such intra-site liquid migration can alleviate the lack of coplanarity between two opposing bonding site surfaces to be bonded, and / or otherwise improve the fine alignment of the IC die structure with the underlying substrate structure.

[0074] like Figure 7As further shown in , the peripheral region 204 is similarly segmented, having two orthogonally oriented peripheral region segments that distinguish the perimeter of each bonding region 203A-203D. The segmentation of the peripheral region 204 can provide liquid migration paths through which a certain volume of liquid can escape the bonding region 203A-203D, for example, in response to contact with a corresponding bonding region (e.g., on an IC die structure). Such inter-site liquid migration can also alleviate the lack of coplanarity between two opposing bonding site surfaces to be bonded, and / or otherwise improve fine alignment. Although Figure 7 , both segmented inner and outer regions are shown, but either may be implemented without the other.

[0075] Figure 8 FIG. 3 is a plan view of a bonding site of an IC die structure 301 according to some alternative embodiments. As shown, bonding regions 303A-303D have Figure 7 The metallization pattern of the bonding area 203A-203D shown in FIG. 303A-303D is similarly surrounded by the segmented peripheral area 304. The bonding area 303A-303D also similarly surrounds the segmented inner area 304'. Such segmentation can also provide liquid migration paths within and between the bonding sites, through which a certain volume of liquid can move into / out of one or more of the bonding areas 303A-303D, for example, in response to non-planarity between the bonding sites.

[0076] In some embodiments, the IC die structure has a polygonal shape other than a rectangle.The non-rectangular shape may, for example, help regulate liquid migration to / from one or more bonding sites during a liquid droplet-based fine alignment process. Fig. 93 is a plan view of a bonding site of an IC die structure 301 according to some alternative embodiments. As shown, the IC die structure 301 has four orthogonal edge sidewalls 305. Two edge sidewalls 305 each intersect with a third edge sidewall 901. In the example shown, the third edge sidewall 901 chamfers each corner of the IC die structure 301, resulting in an octagonal shape. Such a polygon can react to non-planarity between bonding sites in a different way than a rectangular IC die structure. In the example shown, each edge sidewall 901 also intersects with a bonding area 303A-303D, so that there is a break in the peripheral area 304 at each chamfered corner. The peripheral area 304 is thus segmented again, although this is segmented by the IC die edge sidewalls 901 rather than by patterning of the amphiphilic surface structure. Therefore, the peripheral area 304 extends the entire length of the IC die edge sidewalls 305. The inner region 304' is again shown as a discrete segment surrounded by the die bonding regions 303A-303D. Alternatively, the inner region 304' may be contiguous with the peripheral region 304, or be completely absent, as the various embodiments described herein may be combined together or implemented individually, for example, as one or more means of regulating a liquid droplet-based fine alignment process.

[0077] Fig.10 1 is a cross-sectional view of a system 1000 including a heat sink 1004 and a host assembly 1011 assembled with a hybrid bonded composite structure 601, the hybrid bonded composite structure 601 further including a hybrid bonded IC die. Although shown as an integration of the composite structure 601, the system 1000 may similarly include a composite structure containing one or more of the alternative IC die structures and / or base substrate structures described herein. The system 1000 may include any number of such composite structures mounted to the host assembly 1011 via an interconnect 1009, which is optionally embedded in an underfill material 1012. For example, the host assembly 1011 may be a cored or coreless package substrate structure, an interposer, or a board (such as a motherboard).

[0078] The system 1000 further includes a power supply 1056 coupled to one or more of the host component 1011 (i.e., a board, package substrate structure, or interposer), the composite structure 601, and / or other components of the system 1000. The power supply 1056 may include a battery, a voltage converter, a power supply circuit module, etc. The system 1000 further includes a thermal interface material (TIM) 1001 above the composite structure 601. The TIM 1001 may include any suitable thermal interface material. The system 1000 further includes an integrated heat sink (IHS) and / or cover 1002 in contact with the TIM 1001 and extending above the composite structure 601. The system 1000 further includes another TIM 1003 in contact with the top surface of the IHS 1002. The TIM 1003 may include any suitable thermal interface material and may have the same or different composition as the TIM 1001. The system 1000 includes a heat sink 1004 (eg, an exemplary heat sink or thermal solution) in contact with the TIM 1003. For example, the system 1000 may be further integrated into a computer such as a mobile device or a server.

[0079] Fig.11 An exemplary computer platform 1105 is shown including a composite structure including a bonded IC die having an amphiphilic feature near a hybrid bonding interface indicative of a droplet-based fine alignment technique. For example, platform 1105 may be a mobile computing platform and / or a data server machine. The server machine may be any commercial server, for example, including any number of high performance computing platforms arranged in a rack and networked together for electronic data processing. Platform 1105 may be any portable device configured for electronic data display, electronic data processing, wireless electronic data transmission, and the like. Platform 1105 may include an integrated system 1110 at a chip level or a package level and a battery 1115. In some examples, the disclosed system may be implemented in a decomposed subsystem 1160.

[0080] Subsystem 1160 may include memory circuit module and / or processor circuit module 1150 (e.g., RAM, microprocessor, multi-core microprocessor, graphics processor, etc.), power management integrated circuit (PMIC) 1130, and radio frequency integrated circuit (RFIC) 1125 (e.g., including a broadband RF transmitter and / or receiver (TX / RX)). As shown, one or more IC dies such as memory circuit module and / or processor circuit module 1150 may be co-packaged and / or co-assembled within a composite structure, for example, as described herein, the composite structure including an IC die having an amphiphilic structure near a hybrid bonding interface.

[0081] In some embodiments, RFIC 1125 includes a digital baseband and an analog front-end module, which further includes a power amplifier on the transmit path and a low noise amplifier on the receive path. Functionally, PMIC 1130 can perform battery power regulation, DC to DC conversion, etc., and thus has an input coupled to battery 1115 and an output that provides current supply to other functional modules. Fig.11 As further shown in the , in an exemplary embodiment, the output of the RFIC 1125 is coupled to an antenna (not shown) to implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth and its derivatives, and any other wireless protocols named 3G, 4G, 5G and above. The memory circuit module and / or the processor circuit module 1150 can provide memory functionality, high-level control, data processing, etc. for the subsystem 1160.

[0082] Fig.12 1 is a block diagram of a cryogenically cooled computing device 1200 according to some embodiments. For example, one or more components of the computing device 1200 may include any of the devices or structures discussed elsewhere herein. Some components are Fig.12 1200, however, any one or more of these components may be omitted or repeated as appropriate for the application. In some embodiments, some of the components included in computing device 1200 may be attached to one or more printed circuit boards (e.g., motherboards). In some embodiments, various of these components may be fabricated on a single system-on-chip (SoC) die, or implemented using multiple chiplets or dies that are packaged together without integration. Additionally, in various embodiments, computing device 1200 may not include Fig.12 1200, but the computing device 1200 may include an interface circuit module for coupling to one or more components. For example, the computing device 1200 may not include the display device 1203, but may include a display device interface circuit module (e.g., a connector and a driver circuit module) and the display device 1203 may be coupled to the circuit module.

[0083] The computing device 1200 may include a processing device 1201 (e.g., one or more processing devices). As used herein, the term processing device or processor indicates a device that processes electronic data from registers and / or memory to convert the electronic data into other electronic data that can be stored in registers and / or memory. The processing device 1201 may include a memory 1221, a communication device 1222, a refrigeration / active cooling device 1223, a battery / power regulation device 1224, a logic 1225, an interconnect 1226, a thermal regulation device 1227, and a hardware security device 1228.

[0084] Processing device 1201 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (specialized processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing devices.

[0085] The processing device 1201 may include a memory 1202, which may itself include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or a hard drive. In some embodiments, the processing device 1201 shares a package with the memory 1202. This memory may be used as a cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

[0086] The computing device 1200 may include a thermal conditioning / cooling device 1223. The thermal conditioning / cooling device 1223 may maintain the processing device 1201 (and / or other components of the computing device 1200) at a predetermined low temperature during operation. This predetermined low temperature may be any temperature discussed elsewhere herein.

[0087] In some embodiments, computing device 1200 may include a communication chip 1207 (e.g., one or more communication chips). For example, communication chip 1207 may be configured to manage wireless communications for transferring data to and from computing device 1200. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc. that can communicate data using modulated electromagnetic radiation through a non-solid medium.

[0088] The communication chip 1207 may implement any of a number of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE802.16-2005 amendment), Long Term Evolution (LTE) project, and any modifications, updates and / or revisions (e.g., Advanced LTE project, Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc.). IEEE 802.16-compatible broadband wireless access (BWA) networks are generally referred to as WiMAX networks, which is an acronym for Worldwide Interoperability for Microwave Access, which is a certification mark for products that have passed the conformance and interoperability tests of the IEEE 802.16 standard. The communication chip 1207 may operate according to a Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 1207 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 1207 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO) and its derivatives, and any other wireless protocols named 3G, 4G, 5G and above. In other embodiments, the communication chip 1207 may operate in accordance with other wireless protocols. The computing device 1200 may include an antenna 1213 to facilitate wireless communication and / or receive other wireless communications (such as AM or FM radio transmissions).

[0089] In some embodiments, the communication chip 1207 may manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As noted above, the communication chip 1207 may include multiple communication chips. For example, a first communication chip 1207 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, while a second communication chip 1207 may be dedicated to longer-range wireless communications, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, the first communication chip 1207 may be dedicated to wireless communications, while the second communication chip 1207 may be dedicated to wired communications.

[0090] Computing device 1200 may include battery / power circuit module 1208. Battery / power circuit module 1208 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuit modules for coupling components of computing device 1200 to an energy source separate from computing device 1200 (e.g., AC line power).

[0091] Computing device 1200 may include a display device 1203 (or a corresponding interface circuit module, as discussed above). For example, display device 1203 may include any visual indicator, such as a head-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light emitting diode display, or a flat panel display.

[0092] Computing device 1200 may include audio output device 1204 (or corresponding interface circuit modules, as discussed above). For example, audio output device 1204 may include any device that generates audible indications, such as a speaker, headphones, or earbuds.

[0093] The computing device 1200 may include an audio input device 1210 (or a corresponding interface circuit module, as discussed above). The audio input device 1210 may include any device that generates a signal representing sound, such as a microphone, a microphone array, or a digital instrument (e.g., an instrument with a Musical Instrument Digital Interface (MIDI) output).

[0094] Computing device 1200 may include a global positioning system (GPS) device 1209 (or a corresponding interface circuit module, as discussed above). As is known in the art, GPS device 1209 may communicate with a satellite-based system and may receive the location of computing device 1200.

[0095] Computing device 1200 may include another output device 1205 (or corresponding interface circuit module, as discussed above). Examples include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0096] The computing device 1200 may include another input device 1211 (or a corresponding interface circuit module, as discussed above). Examples may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device (such as a mouse), a stylus, a touchpad, a barcode reader, a quick response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0097] The computing device 1200 may include a security interface device 1212. The security interface device 1212 may include any device that provides security measures for the computing device 1200, such as intrusion detection, biometric authentication, security encoding or decoding, management access lists, malware detection, or spyware detection.

[0098] Computing device 1200 or a subset of its components may have any suitable form factor, such as a handheld or mobile computing device (e.g., a cellular telephone, a smart phone, a mobile Internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device.

[0099] Although certain features set forth herein have been described with reference to various implementations, this description is not intended to be interpreted in a limiting sense. Therefore, various modifications of the implementations described herein and other implementations that are obvious to those skilled in the art to which the present disclosure belongs are considered to fall within the spirit and scope of the present disclosure.

[0100] In a first example, a device includes an integrated circuit (IC) die structure, the IC die structure including a device layer and a metallization level above the device layer. The metallization level includes one or more bonding regions, the bonding regions further including metal features and inorganic dielectric materials. The metallization level includes an inner region that is either surrounded by the bonding region or between an adjacent pair of bonding regions. The inner region includes a material having a composition of at least 10 atomic percent carbon or at least 10 atomic percent fluorine.

[0101] In a second example, for any of the examples in the first example, the bonding region is a first bonding region, the metallization level is a first metallization level, the metal feature is a first metal feature, the inner region is a first intervening region, and the device further includes a substrate structure including a second metallization level. The second metallization level includes one or more second bonding regions, the second bonding regions further include substantially coplanar second metal features and an inorganic dielectric material, wherein the second metal features are in contact with at least a portion of corresponding ones of the first metal features, and the second inner region is either surrounded by the second bonding region or between an adjacent pair of the second bonding regions, wherein the second inner region includes a material having a composition of at least 10 atomic percent carbon or at least 10 atomic percent fluorine.

[0102] In a third example, for any of the first to second examples, the substrate structure includes one or more solder features on a side opposite the IC die structure.

[0103] In a fourth example, for any of the first to third examples, the metallization level includes at least four of the bonding regions, each of the bonding regions occupying a quarter of the IC die structure, and the interior region extends continuously between each of the bonding regions.

[0104] In a fifth example, for any of the first to fourth examples, the metallization level includes a continuous bonding region.The interior region is one of a plurality of interior regions, each of the plurality of interior regions being surrounded by the continuous bonding region.

[0105] In a sixth example, for any of the first to fifth examples, the metallization level includes one or more external regions outside of the bonding region. The external regions include a material having a composition of at least 10 atomic percent carbon or at least 10 atomic percent fluorine.

[0106] In a seventh example, for any of the sixth examples, the outer region includes a single outer region that substantially surrounds the engagement region, and the single outer region is contiguous with the inner region.

[0107] In an eighth example, for any of the sixth to seventh examples, the bonding area has at least two orthogonal edges within the plane of the metallization level, and wherein the outer region includes a plurality of outer regions, at least one of the outer regions being adjacent to each of the at least two orthogonal edges.

[0108] In a ninth example, for any of the first to eighth examples, the IC die structure has at least two orthogonal edge sidewalls, wherein both orthogonal edge sidewalls intersect the third edge sidewall, and wherein the third edge sidewall intersects the bonding region.

[0109] In a tenth example, for any of the first to ninth examples, the metallization level includes one or more external regions outside the bonding region. The external regions include a material having a composition of at least 10 atomic percent carbon or at least 10 atomic percent fluorine, and the third edge sidewall intersects at least one of the external regions.

[0110] In an eleventh example, a device includes an integrated circuit (IC) die structure, the IC die structure including a device layer and a first metallization level above the device layer. The first metallization level includes one or more first bonding areas, the first bonding areas further including substantially coplanar first metal features and inorganic dielectric materials. The device includes a substrate structure, the substrate structure includes a second metallization level. The second metallization level includes one or more second bonding areas, the second bonding areas further including substantially coplanar second metal features and inorganic dielectric materials. The second metal feature contacts at least a portion of a corresponding first metal feature in the first metal features. At least one of the first or second metallization levels includes an inner region, the inner region is either surrounded by the first or second bonding area, or is between an adjacent pair of the first or second bonding areas, and the inner region includes a hydrophobic structure.

[0111] In a twelfth example, for any of the eleventh examples, the first metallization level includes a first inner region that is either surrounded by the first bonding region or is between an adjacent pair of first bonding regions, and the second metallization level includes a second inner region that is either surrounded by the second bonding region or is between an adjacent pair of second bonding regions.

[0112] In a thirteenth example, for any of the eleventh to twelfth examples, a side of the substrate structure opposite the IC die structure includes one or more solder features.

[0113] In a fourteenth example, for any of the eleventh to thirteenth examples, at least one of the first or second metallization levels includes at least four bonding areas, each of the four bonding areas occupies a quarter of the metallization level, and the interior area extends continuously between each of the four bonding areas.

[0114] In a fifteenth example, for any of the eleventh to fourteenth examples, at least one of the metallization levels includes a continuous bonding region, and the interior region is one of a plurality of interior regions, each of the plurality of interior regions being surrounded by the continuous bonding region.

[0115] In a sixteenth example, for any of the eleventh to fifteenth examples, at least one of the first or second metallization levels includes one or more external regions outside of the bonding region, and wherein the external regions include the hydrophobic structure.

[0116] In a seventeenth example, a method includes receiving an integrated circuit (IC) die structure. A surface of the IC die structure includes one or more first bonding regions. The method includes receiving a substrate structure, wherein the surface of the substrate structure includes one or more second bonding regions. The method includes forming a plurality of liquid droplets on each of the first bonding regions or on each of the second bonding regions; and bonding the first bonding region to the second bonding region after the liquid droplets disappear.

[0117] In an eighteenth example, for any of the sixteenth to seventeenth examples, each of the first bonding regions includes substantially coplanar first metal features and inorganic dielectric materials, each of the second bonding regions includes substantially coplanar second metal features and inorganic dielectric materials, and a surface of at least one of the IC die structure or the substrate structure includes an interior region that is either surrounded by the first or second bonding regions or is located between an adjacent pair of the first or second bonding regions.

[0118] In a nineteenth example, for any of the eighteenth examples, the method includes aligning the IC die structure with the substrate structure based on a wettability contrast between the inner region and the first or second bonding region.

[0119] In a twentieth example, for any of the nineteenth examples, a surface of the IC die structure includes a first interior region surrounded by a continuous first bonding region or located between a pair of adjacent first bonding regions, and a surface of the substrate structure includes a second interior region surrounded by a continuous second bonding region or located between a pair of adjacent second bonding regions.

[0120] It will be appreciated that the principles of the present disclosure are not limited to the embodiments described above, but may be practiced through modification and alteration without departing from the scope of the appended claims. The above-described embodiments may include employing only a subset of such features, employing a different order of such features, employing a different combination of such features, and / or employing additional features in addition to those features explicitly listed. Therefore, the scope of the embodiments should be determined by reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims

1. A device comprising: An integrated circuit (IC) die structure, the IC die structure comprising a device layer and a metallization level above the device layer, wherein the metallization level comprises: one or more bonding regions, the bonding regions further comprising metallic features and inorganic dielectric materials; and An inner region is either surrounded by the bonding region or between an adjacent pair of bonding regions, wherein the inner region includes a material having a composition of at least 10 atomic percent carbon or at least 10 atomic percent fluorine.

2. The apparatus of claim 1, wherein: The joining region is a first joining region; The metallization level is a first metallization level; The metal feature is a first metal feature; The inner region is a first intermediate region; as well as The apparatus further comprises a substrate structure comprising a second metallization level, wherein the second metallization level comprises: one or more second bonding regions, the second bonding regions further comprising substantially coplanar second metallic features and an inorganic dielectric material, wherein the second metallic features contact at least a portion of a corresponding first metallic feature of the first metallic features; and A second inner region, the second inner region is either surrounded by the second bonding region or between an adjacent pair of second bonding regions, wherein the second inner region includes a material having a component of at least 10 atomic percent carbon or at least 10 atomic percent fluorine.

3. The device according to any one of claims 1 to 2, wherein: The substrate structure includes one or more solder features on a side opposite the IC die structure.

4. The device according to any one of claims 1 to 2, wherein: The metallization level includes at least four of the bonding regions, each of the bonding regions occupying a quarter of the IC die structure, and the interior region extends continuously between each of the bonding regions.

5. The device according to any one of claims 1 to 2, wherein: The metallization level comprises a continuous bonding area, and wherein the inner region is one of a plurality of inner regions, each of the plurality of inner regions being surrounded by the continuous bonding area.

6. The device according to any one of claims 1 to 2, wherein: The metallization level includes one or more outer regions outside the bonding region, and wherein the outer regions include a material having a composition of at least 10 atomic percent carbon or at least 10 atomic percent fluorine.

7. The device of claim 6, wherein: The outer region comprises a single outer region substantially surrounding the engagement region, and wherein the single outer region is contiguous with the inner region.

8. The device of claim 6, wherein: The bonding area has at least two orthogonal edges within the plane of the metallization level, and wherein the outer region comprises a plurality of outer regions, at least one of the outer regions being adjacent to each of the at least two orthogonal edges.

9. The device according to any one of claims 1 to 2, wherein: The IC die structure has at least two orthogonal edge sidewalls, wherein both of the orthogonal edge sidewalls intersect a third edge sidewall, and wherein the third edge sidewall intersects the bonding region.

10. The apparatus of claim 9, wherein: The metallization level includes one or more external regions outside the bonding region; said outer region comprising said material having a composition of at least 10 atomic percent carbon or at least 10 atomic percent fluorine; as well as The third edge sidewall intersects at least one of the outer regions.

11. A device comprising: an integrated circuit (IC) die structure comprising a device layer and a first metallization level above the device layer, wherein the first metallization level comprises one or more first bonding regions, the first bonding regions further comprising substantially coplanar first metal features and an inorganic dielectric material; and A substrate structure comprising a second metallization level, wherein: the second metallization level comprising one or more second bonding regions, the second bonding regions further comprising substantially coplanar second metal features and an inorganic dielectric material; the second metal feature being in contact with at least a portion of a corresponding one of the first metal features; At least one of the first metallization level or the second metallization level includes an inner region, the inner region being either surrounded by the first bonding region or the second bonding region or between an adjacent pair of the first bonding region or the second bonding region; and The interior region includes a hydrophobic structure.

12. The apparatus of claim 11, wherein: The first metallization level includes a first inner region, the first inner region is either surrounded by the first bonding region or between an adjacent pair of the first bonding regions; as well as The second metallization level includes a second inner region, which is either surrounded by the second bonding regions or between an adjacent pair of the second bonding regions.

13. The device according to any one of claims 11 to 12, wherein: A side of the substrate structure opposite the IC die structure includes one or more solder features.

14. The device according to any one of claims 11 to 12, wherein: At least one of the first metallization level or the second metallization level comprises at least four bonding areas, each of the four bonding areas occupying a quarter of the metallization level, and the inner area extends continuously between each of the four bonding areas.

15. The device according to any one of claims 11 to 12, wherein: At least one of the metallization levels comprises a continuous bonding region, and wherein the inner region is one of a plurality of inner regions, each of the plurality of inner regions being surrounded by the continuous bonding region.

16. The device according to any one of claims 11 to 12, wherein: At least one of the first metallization level or the second metallization level comprises one or more external regions outside the bonding region, and wherein the external regions comprise a hydrophobic structure.

17. A method comprising: receiving an integrated circuit (IC) die structure, wherein a surface of the IC die structure includes one or more first bonding regions; receiving a substrate structure, wherein a surface of the substrate structure includes one or more second bonding regions; forming a plurality of liquid droplets on each of the first joining regions or on each of the second joining regions; and The first joining region is joined to the second joining region after the liquid droplet disappears.

18. The method of claim 17, wherein: Each of the first bonding regions includes a substantially coplanar first metal feature and an inorganic dielectric material; Each of the second bonding regions includes a substantially coplanar second metal feature and an inorganic dielectric material; as well as The surface of at least one of the IC die structure or the substrate structure includes an inner region that is either surrounded by the first bonding region or the second bonding region or is located between an adjacent pair of the first bonding region or the second bonding region.

19. The method of claim 18, further comprising: The IC die structure is aligned with the substrate structure based on a wettability contrast between the inner region and the first bonding region or the second bonding region.

20. The method of claim 19, wherein: The surface of the IC die structure includes a first inner region, the first inner region being surrounded by a continuous first bonding region or being located between a pair of adjacent first bonding regions; and the surface of the substrate structure comprises a second inner region surrounded by a continuous second bonding region, Or located between a pair of adjacent second bonding areas.

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