Bridging packaging interconnection method

Abstract

The invention discloses a bridging packaging interconnection method, which comprises the following steps of S1, preparing a dipping interface, coating nano-particle slurry or depositing solid nano-particles on the surface of a dipping substrate to obtain the dipping interface containing a nano-particle layer, and the thickness of the nano-particle layer is less than 1 [mu] m; s2, the dipping body and the substrate are cleaned up and then pretreated; s3, sucking the dipping body with the copper cylinder end by a suction head of the bonding machine, immersing the copper cylinder end into the dipping interface for dipping, and then lifting up; s4, introducing protective gas, aligning the copper column end on the dipping body to a corresponding welding area on the substrate through an optical system of a bonding machine, and applying corresponding pressure, ultrasound and temperature to carry out bonding; and S5, cooling at room temperature after bonding to obtain the super-fine pitch bridging packaging structure. According to the invention, the problems that super-fine pitch interconnection between a silicon bridge and a chip cannot be realized and the requirement of high-density packaging cannot be met in the fields of chiplet and heterogeneous integration are solved.

Description

Technical Field

[0001] The present invention relates to the field of chiplets and heterogeneous integrated packaging, and in particular to a bridge packaging interconnection method. Background Art

[0002] At present, the slowdown of Moore's Law and the diversification trend of integrated circuit product applications have jointly promoted the rapid development of advanced packaging technology. Advanced interconnect technology is the core of advanced packaging, which has shown significant advantages in high-speed, high-frequency transmission, power consumption, ultra-fine pitch interconnection and system integration capabilities. As an important solution for chiplets and heterogeneous integrated packaging, silicon bridge technology has narrower metal wiring line width and smaller line spacing, thus achieving higher wiring density. This design can achieve local high-density interconnection between multiple chips at a lower cost and is widely used in processors, memory, and RF devices.

[0003] At present, in the field of chiplets and heterogeneous integration, silicon bridges and chips are interconnected mainly by bumps or micro-bumps. The combination of various electronic components in a single package is becoming more and more important. The size and functionality of each electronic component are increased while the structural size is further reduced. However, because tin has the reflow characteristic, traditional lead-free solder bumps will collapse during the reflow process, which makes it impossible to ensure the height of the bumps when making ultra-fine pitch bumps, and it is impossible to achieve ultra-fine pitch interconnection, which cannot meet the requirements of high-density packaging, and is prone to failure in high-temperature working environments. It cannot meet the requirements of low-temperature sintering and high-temperature service, and the interconnection effect is poor. Summary of the invention

[0004] In view of the above-mentioned defects, the purpose of the present invention is to propose a bridge packaging interconnection method to solve the problem that in the field of chiplet and heterogeneous integration, ultra-fine pitch interconnection between silicon bridge and chip cannot be achieved and the requirements of high-density packaging cannot be met.

[0005] To achieve this object, the present invention adopts the following technical solutions:

[0006] A bridge package interconnection method comprises the following steps:

[0007] S1, preparing a dipping interface, coating a nanoparticle slurry or depositing solid nanoparticles on the surface of a dipping substrate to obtain a dipping interface containing a nanoparticle layer, wherein the thickness of the nanoparticle layer is less than 1 μm;

[0008] S2, cleaning the dipped body and the substrate and then pre-treating them; the dipped body is a chip with a copper column end, and the substrate includes a substrate and a silicon bridge;

[0009] S3, the suction head of the bonding machine absorbs the dipping body with the copper column end, immerses the copper column end into the dipping interface, dips it, and then lifts it up;

[0010] S4, introducing protective gas, aligning the copper column end on the dipped body with the corresponding welding area on the substrate through the optical system of the bonding machine, and applying corresponding pressure, ultrasound and temperature for bonding;

[0011] S5. After bonding, the ultra-fine pitch bridge package structure is obtained after cooling at room temperature.

[0012] Furthermore, in step S4, the time required for the copper column end to be immersed in the dipping interface for dipping is 1s-3min.

[0013] Furthermore, in the step S1, the solid content of the nanoparticle slurry is ≥60%, and the particle size is ≤500nm; the solid nanoparticles are prepared by any one or more of ball milling, arc discharge, laser ablation and gas phase steam synthesis, and the particle size is ≤100nm.

[0014] Preferably, in step S1, the nanoparticles are one or more of nano-copper, nano-silver, nano-gold, nano-tin, nano-silver-copper, nano-silver-copper alloy, nano-silver-copper solid solution and nano-tin-zinc alloy.

[0015] Preferably, in step S2, the silicon bridge is arranged in a groove of the substrate, and the substrate material of the silicon bridge is silicon or glass.

[0016] Further, in step S2, at least two of the chips are flipped on the same silicon bridge through the copper column ends to form a bridge packaging structure, the surface of the silicon bridge is provided with a high-density wiring layer, and the substrate is provided with a copper pad, and the welding area described in step S5 is the high-density wiring layer of the silicon bridge and the copper pad of the substrate.

[0017] Preferably, in step S3, the diameter of the copper column ends is 1 μm-50 μm, and the spacing between the copper column ends is 1 μm-50 μm.

[0018] Preferably, in the step S1, the dipping substrate is glass or silicon wafer, and the surface flatness of the dipping substrate is Ra≤10 nm; in the step S2, the pretreatment includes one or more of acid treatment, plasma treatment and SAM.

[0019] Preferably, in step S5, the protective gas is an inert gas or a reducing gas, the inert gas is nitrogen, argon or helium, and the reducing gas is hydrogen, formaldehyde or carbon monoxide.

[0020] Preferably, in step S5, the bonding process is carried out under an environment of 120°C-260°C, 0-50MPa pressure, and 0-120kHz ultrasonic driving frequency.

[0021] The technical solution provided by the present invention may include the following beneficial effects:

[0022] In the field of chiplets and heterogeneous integrated packaging, the method connects the chip, substrate and silicon bridge, and utilizes the size effect of nanoparticles to meet the requirements of ultra-fine pitch interconnection while achieving low-temperature sintering and high-temperature service. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 FIG. 1 is a schematic diagram of dipping nanoparticle slurry according to an embodiment of the present invention.

[0024] Figure 2 It is a schematic diagram of dipping solid nanoparticles according to an embodiment of the present invention.

[0025] Figure 3 It is a schematic diagram of the interconnection structure of an embodiment of the present invention.

[0026] Among them: a dipping body 1, a copper column end 2, a base 3, a substrate 31, and a silicon bridge 32. DETAILED DESCRIPTION

[0027] The technical solution of the present invention is further illustrated below through specific implementation methods.

[0028] In order to facilitate the understanding of the present invention, the present invention is described more fully below. The present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0029] If no specific techniques or conditions are specified in the examples, the techniques or conditions described in the literature in the field or the product instructions are used. If no manufacturer is specified for the reagents or instruments used, they are all conventional products that can be purchased commercially.

[0030] The present invention provides a bridge package interconnection method, comprising the following steps:

[0031] S1, preparing a dipping interface, coating a nanoparticle slurry or depositing solid nanoparticles on the surface of a dipping substrate to obtain a dipping interface containing a nanoparticle layer, wherein the thickness of the nanoparticle layer is less than 1 μm;

[0032] S2, cleaning the dip body 1 and the substrate 3 and then pre-treating them; the dip body 1 is a chip with a copper column end 2, and the substrate 3 includes a base plate 31 and a silicon bridge 32;

[0033] S3, the suction head of the bonding machine absorbs the dipping body 1 with the copper column end 2, immerses the copper column end 2 into the dipping interface, dips it, and then lifts it up;

[0034] S4, introducing protective gas, aligning the copper column end 2 on the dipped body 1 with the corresponding welding area on the substrate 3 through the optical system of the bonding machine, and applying corresponding pressure, ultrasound and temperature for bonding;

[0035] S5. After bonding, the ultra-fine pitch bridge package structure is obtained after cooling at room temperature.

[0036] Specifically, through the above steps S1-S5, the dipping interface is prepared, the dipping body 1 and the substrate 3 are pretreated, the bonding machine absorbs the dipping body 1 with the copper column end 2 and flips it so that the copper column end 2 faces outward, and under certain reaction conditions, the chip and the silicon bridge 32 are bonded together, breaking through the current problem that in the field of chiplet and heterogeneous integration, the silicon bridge and the chip are mainly interconnected by bumps or micro-bumps, which cannot meet the requirements of high-density packaging. Because tin has a reflow characteristic, the traditional lead-free solder bumps will collapse during the reflow process, and this collapse may cause bridging between adjacent solder ball bumps, thereby causing a circuit short circuit. The problem is that the height of the bump cannot be guaranteed when making ultra-fine pitch bumps, ultra-fine pitch interconnection cannot be achieved, and the requirements of high-density packaging cannot be met. This solution uses a bonding machine to absorb a dipping body 1 with a copper pillar end 2 to dip the dipping interface so that the end surface of the copper pillar end 2 is adhered with nano-particle material, replacing the solder ball bumps currently used in the chiplet and heterogeneous integration fields, and realizing ultra-fine pitch interconnection between the substrate, the silicon bridge and the chip, that is, the pitch is between 5μm and 60μm, solving the problem that ultra-fine pitch interconnection cannot be achieved and the requirements of high-density packaging cannot be met in the chiplet and heterogeneous integration fields.

[0037] The dipping body 1 with the copper column end is sucked up by the suction head of the bonding machine, and the copper column end 2 is immersed in the dipping interface and lifted up after dipping. The dipping body 1 dips the nanoparticles to connect. Due to the dipping process, the thickness of the nanoparticle layer in the dipping interface is further limited, and the thickness of the nanoparticle layer is specifically limited to less than 1μm, so that the solder dipped on the end face of the copper column end 2 is limited to meet the interconnection. During the interconnection, the deformation of the copper column end 2 of the dipping body 1 is significantly reduced. During the remelting and reflow process, the copper column end 2 almost maintains its shape unchanged, which helps to improve the reliability of electronic devices and meet the requirements of high-temperature service.

[0038] Furthermore, in step S4, the time required for the copper column end 2 to be immersed in the dipping interface for dipping is 1 s-3 min.

[0039] Specifically, if the time is less than 1 second, the time is too short, and the copper column end 2 of the dipping body 1 has too few nanoparticles dipped in, which does not meet the requirements of subsequent bonding. A long time allows the dipping body 1 to dip in more nanoparticles, but the increase in the number of dipped nanoparticles will reach a threshold as time goes by. If the time is longer than 3 minutes, the nanoparticles dipped in by the dipping body 1 will no longer increase significantly, and unnecessary time costs will be added. Dipping within this time range can meet the interconnection while reducing the deformation of the copper column end 2 and reducing costs.

[0040] Furthermore, in the step S1, the solid content of the nanoparticle slurry is ≥60%, and the particle size is ≤500nm; the solid nanoparticles are prepared by any one or more of ball milling, arc discharge, laser ablation and gas phase steam synthesis, and the particle size is ≤100nm.

[0041] Specifically, Figure 1 and Figure 2 As shown, in the step S1, the coating operation is to use a coater to evenly apply a layer of nanoparticle slurry on the surface of the dipped substrate; the deposition operation is to carry the nanoparticles through gas to gather on the surface of the dipped substrate, and the deposition methods include diffusion deposition, stamping deposition, direct deposition and filtration deposition.

[0042] A layer of nanoparticle slurry is coated on the surface of the dipping substrate, wherein the solid content of the nanoparticle slurry is ≥60% and the particle size is ≤500nm, that is, the solid content of the nanoparticle slurry is relatively high, which is beneficial for preparing nanoparticle film and facilitating the dipping process, making it easier for the dipping body 1 to dip nanoparticles.

[0043] The solid nanoparticles are prepared by any one or more of ball milling, arc discharge, laser ablation and gas phase steam synthesis, and the particle size of the nanoparticles is limited to no more than 100 nm. Under conditions allowing the process range, the smaller the particle size of the nanoparticles, the lower the sintering temperature required for the nanosize effect and the better the sintering effect, thereby reducing the process temperature required for connection during bonding and achieving a better sintering effect.

[0044] Preferably, in step S1, the nanoparticles are one or more of nano-copper, nano-silver, nano-gold, nano-tin, nano-silver-copper, nano-silver-copper alloy, nano-silver-copper solid solution and nano-tin-zinc alloy.

[0045] It is worth noting that in the step S1, the nanoparticles are specifically nanometal particles, and further the nanoparticles are one or more of nanocopper, nanosilver, nanogold, nanotin, nanosilver-copper, nanosilver-copper alloy, nanosilver-copper solid solution and nanotin-zinc alloy. These nanoparticles play the role of electrical conduction, thermal conduction and mechanical support in the ultra-fine pitch silicon bridge interconnection structure. The melting point of tin is 231.96°C, which means that at higher temperatures, tin may melt, resulting in structural failure, unable to meet the requirements of low-temperature sintering and high-temperature service, and poor interconnection effect. This solution uses nanometal particle sintering technology, and uses the size effect of nanometal particles to reduce the process temperature required for connection during bonding. The connection layer formed after the nanoparticles are sintered can approach the melting point of the bulk material of the same material, thereby achieving connection at a lower temperature. At the same time, the nanoparticle sintering connection layer also has a higher connection strength, good electrical and thermal conductivity, and can maintain stability at high temperatures.

[0046] Preferably, in step S2 , the silicon bridge 32 is disposed in a groove of the substrate 31 , and the substrate material of the silicon bridge 32 is silicon or glass.

[0047] like Figure 3 As shown, the silicon bridge 32 is arranged in the groove of the substrate 31. When performing step S5, the copper column end on the dipping body 1 is aligned with the corresponding welding area on the base 3, and corresponding pressure, ultrasound and temperature are applied for bonding, that is, the chip is located between the substrate 31 and the silicon bridge 32, so that the substrate, chip and silicon bridge are easily connected to achieve faster and more intensive signal transmission between chips.

[0048] The substrate material of the silicon bridge 32 is silicon or glass. Silicon, as a substrate material, has the advantages of low cost and large size. The glass substrate has high surface flatness and low roughness, and has excellent thermal stability. It can maintain stable performance in a high temperature environment. Its thermal expansion coefficient is close to that of silicon, which helps to reduce stress problems caused by thermal mismatch during the packaging process, and can effectively achieve higher I / O density and lower transmission delay and power consumption.

[0049] Further, in step S2, at least two of the chips are flipped on the same silicon bridge 32 through the copper column end 2 to form a bridge packaging structure, the surface of the silicon bridge 32 is provided with a high-density wiring layer, and the substrate 31 is provided with a copper pad, and the welding area described in step S5 is the high-density wiring layer of the silicon bridge 32 and the copper pad of the substrate 31.

[0050] Specifically, in step S2, at least two chips are flipped on a silicon bridge 32 through the copper column end 2 to form a bridge packaging structure, that is, the two chips are connected through the silicon bridge. In the field of chiplet and heterogeneous integration, silicon bridge technology can realize local high-density interconnection between multiple chips, connect the chip with the silicon bridge 32, and realize interconnection between chips at a lower cost, and realize faster and denser signal transmission between chips.

[0051] The surface of the silicon bridge 32 is provided with a high-density wiring layer, and the width of the lines and the line spacing in the wiring layer are in the range of 1-100μm. The substrate 31 is provided with a copper pad. The welding area described in step S5 is one or more of the high-density wiring layer of the silicon bridge 32 and the copper pad of the substrate 31. Through the optical system of the bonding machine, the copper column end on the dip body 1 is aligned with the corresponding welding area on the base 3, and corresponding pressure, ultrasound and temperature are applied for bonding, so that the substrate, chip and silicon bridge are connected as needed, which helps to realize more signal transmission channels and enhance data transmission capabilities.

[0052] Preferably, in the step S3, the diameter of the copper column ends 2 is 1 μm-50 μm, and the spacing between the copper column ends 2 is 1 μm-50 μm.

[0053] Specifically, the diameter of the copper pillar end 2 is 1μm-50μm, and the copper pillar spacing is 1μm-50μm. It is known that the pitch is the sum of the copper pillar diameter and the copper pillar spacing; accordingly, the pitch achieved by this scheme is smaller and can reach a pitch of 2μm, which meets the purpose of ultra-fine pitch interconnection. If the diameter of the copper pillar end 2 is less than 1 micron and the spacing of the copper pillar end 2 is less than 1 micron, the existing chip production process cannot be achieved and cannot be mass-produced.

[0054] Preferably, in the step S1, the dipping substrate is glass or silicon wafer, and the surface flatness of the dipping substrate is Ra≤10 nm; in the step S2, the pretreatment includes one or more of acid treatment, plasma treatment and SAM.

[0055] Specifically, the dipping substrate is a glass sheet or a silicon sheet, which can meet the requirement of a clean and flat surface. The surface flatness of the dipping substrate Ra≤10nm, which meets the requirements of actual production while meeting the requirements of the dipping process. If the flatness is greater than 10 nanometers, the flatness is high. In order to prepare the required nanoparticle film, more nanoparticle raw materials are required, which will bring higher production costs and is not conducive to production. Therefore, the surface flatness of the dipping substrate is limited to less than 10 nanometers, which is conducive to the dipping process, meets production requirements, and reduces production costs.

[0056] In step S2, ensure that the surfaces of the dipping body 1 and the substrate 3 remain clean and tidy, and the pretreatment includes using one or more of acid treatment, plasma treatment and SAM to remove oxides on the surface of the chip and the substrate, and activate the dipping surface and the interconnection surface layer to facilitate bonding.

[0057] Preferably, in step S5, the protective gas is an inert gas or a reducing gas, the inert gas is nitrogen, argon or helium, and the reducing gas is hydrogen, formaldehyde or carbon monoxide. In step S5, the above-mentioned inert gas or reducing gas is introduced, and the protective bonding process can proceed smoothly, with good protective effect and high safety.

[0058] Preferably, in step S5, the bonding process is carried out in an environment of 120°C-260°C, 0-50MPa pressure, and 0-120kHz ultrasonic drive frequency. Specifically, the bonding process is carried out in an environment of 120°C-260°C, 0-50MPa pressure, and 0-120kHz ultrasonic drive frequency, which is lower than the temperature required by the prior art and meets the conditions for low-temperature sintering.

[0059] The present invention is further described below in conjunction with embodiments.

[0060] Example 1

[0061] A bridge package interconnection method comprises the following steps:

[0062] S1, preparing a dipping interface, coating a layer of nano copper slurry with a thickness of less than 1 μm, a particle size of less than 500 nm, and a solid content of 80% on the surface of the dipping substrate to obtain a dipping interface containing a nano particle layer;

[0063] S2, cleaning the chip with a pitch of 20 μm, the substrate 31 and the silicon bridge 32, and then performing a 2% concentration of dilute sulfuric acid pickling, and a plasma cleaning pretreatment;

[0064] S3, the bonding machine suction head sucks up the chip with a copper pillar end 2 and a pitch of 20 μm, dips the copper pillar end 2 into the dipping interface, and lifts it up after dipping for 1 second;

[0065] S4, 5% hydrogen + 95% argon mixed protective gas is introduced, the copper column end 2 and the corresponding welding area are aligned through the optical system of the bonding machine and a pressure of 10 MPa, an ultrasonic wave of 50 kHz, a temperature of 260°C and a time of 10 min are applied for bonding;

[0066] S5, after cooling to room temperature, an ultra-fine pitch bridge packaging structure is obtained. The overall shear strength is 31.59Mpa, the resistivity is 5.8μΩ*cm, and the high temperature storage test pass rate is 95%.

[0067] Example 2

[0068] A bridge package interconnection method comprises the following steps:

[0069] S1, preparing a dipping interface, coating a layer of nanosilver slurry with a thickness of less than 1 μm, a particle size of less than 500 nm, and a solid content of 70% on the surface of the dipping substrate to obtain a dipping interface containing nanosilver;

[0070] S2, cleaning the relevant chips, substrate 31 and silicon bridge 32, then performing pickling with 2% dilute sulfuric acid and plasma cleaning pretreatment;

[0071] S3, the bonding machine suction head sucks up the chip with the copper pillar end, dips the copper pillar end 2 into the dipping interface, and lifts it up after dipping for 3 seconds;

[0072] S4, 5% hydrogen + 95% argon mixed protective gas is introduced, the copper column end 2 and the corresponding welding area are aligned through the optical system of the bonding machine and a pressure of 10 MPa, an ultrasonic wave of 30 kHz, a temperature of 220°C and a time of 8 min are applied for bonding;

[0073] S6, after cooling to room temperature, an ultra-fine pitch bridge packaging structure was obtained. The overall shear strength was found to be 28.23Mpa, the resistivity was 6.2μΩ*cm, and the high temperature storage test pass rate was 98%.

[0074] Example 3

[0075] A bridge package interconnection method comprises the following steps:

[0076] S1, preparing a dipping interface, depositing a layer of solid nano copper particles with a thickness of less than 100 nm and a particle size of less than 20 nm on the surface of the dipping substrate, to obtain a dipping interface containing nano copper;

[0077] S2, cleaning the relevant chips, substrate 31 and silicon bridge 32 and then pre-treating them with 2% dilute sulfuric acid;

[0078] S4, the bonding machine suction head sucks the chip with the copper pillar end 2, dips the copper pillar end 2 into the dipping interface, and lifts it up after dipping for 30 seconds;

[0079] S5, 5% hydrogen + 95% argon mixed protective gas is introduced, the copper column end 2 and the corresponding welding area are aligned through the optical system of the bonding machine and a pressure of 10 MPa, an ultrasonic wave of 50 kHz, a temperature of 260°C and a time of 10 min are applied for bonding;

[0080] S6, after cooling to room temperature, an ultra-fine pitch bridge packaging structure was obtained. The overall shear strength was found to be 54.26Mpa, the resistivity was 4.6μΩ*cm, and the high temperature storage test pass rate was 99%.

[0081] Example 4

[0082] A bridge package interconnection method comprises the following steps:

[0083] S1, preparing a dipping interface, depositing a layer of solid nano silver copper solid solution with a thickness of less than 100 nm and a particle size of less than 20 nm on the surface of the dipping substrate, to obtain a dipping interface containing solid nano silver copper;

[0084] S2, cleaning the relevant chips, substrate 31 and silicon bridge 32 and then pre-treating them with 2% dilute sulfuric acid;

[0085] S4, the bonding machine suction head sucks the chip with the copper pillar end 2, dips the copper pillar end 2 into the dipping interface, and lifts it up after dipping for 30 seconds;

[0086] S5, 5% hydrogen + 95% argon mixed protective gas is introduced, the copper column end 2 and the corresponding welding area are aligned through the optical system of the bonding machine and a pressure of 8MPa, a temperature of 260°C and a time of 30min are applied for bonding;

[0087] S6, after cooling to room temperature, an ultra-fine pitch bridge packaging structure was obtained. The overall shear strength was found to be 36.59 MPa, the resistivity was 6.7 μΩ*cm, and the high temperature storage test pass rate was 94%.

[0088] Comparative Example 1

[0089] The comparative example is to use solder ball reflow soldering for interconnection, including the following steps:

[0090] S1, cleaning the relevant chips, substrate 31 and silicon bridge 32, then performing pickling with 2% dilute sulfuric acid and plasma cleaning pretreatment;

[0091] S2, the bonding machine suction head picks up the chip with the copper pillar end 2, and aligns the copper pillar end 2 with the corresponding welding area for mounting;

[0092] S3, forming solder balls between the chip and the substrate pad using a solder reflow process;

[0093] S4, after cooling to room temperature, it was found that solder balls with a pitch of 20μm could not be formed between the flip-chip reflow soldering. The solder balls would stick to each other and collapse in the case of fine pitch, resulting in interconnection failure, and the required ultra-fine pitch bridge packaging structure could not be formed.

[0094] In summary, it can be known from the above-mentioned Examples 1 to 4 that the overall shear strength of the ultra-fine pitch bridge packaging structure is 28.23Mpa-54.26Mpa, the resistivity is 4.6μΩ*cm-6.7μΩ*cm, and the high-temperature storage test pass rate is 94%-99%. The overall shear strength is high, the resistivity is small, and the high-temperature storage test pass rate is high. While meeting the ultra-fine pitch connection, it is not easy to fail under high temperature conditions, and realizes the needs of low-temperature sintering and high-temperature service, and meets the requirements of high-density packaging. However, Comparative Example 1 cannot form the ultra-fine pitch bridge packaging structure of Examples 1-4, and does not meet the high-density packaging requirements. At the same time, due to the low melting point characteristics of tin, the chip soldered by the reflow soldering process cannot meet the characteristics of high-temperature service.

[0095] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0096] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A bridge package interconnection method, characterized in that: The following steps are involved: S1, preparing a dipping interface, coating a nanoparticle slurry or depositing solid nanoparticles on the surface of a dipping substrate to obtain a dipping interface containing a nanoparticle layer, wherein the thickness of the nanoparticle layer is less than 1 μm; S2, cleaning the dipped body and the substrate and then pre-treating them; the dipped body is a chip with a copper column end, and the substrate includes a substrate and a silicon bridge; S3, the suction head of the bonding machine absorbs the dipping body with the copper column end, immerses the copper column end into the dipping interface, dips it, and then lifts it up; S4, introducing protective gas, aligning the copper column end on the dipped body with the corresponding welding area on the substrate through the optical system of the bonding machine, and applying corresponding pressure, ultrasound and temperature for bonding; S5. After bonding, the ultra-fine pitch bridge package structure is obtained after cooling at room temperature.

2. A bridge package interconnection method according to claim 1, characterized in that: In step S4, the time required for the copper column end to be immersed in the dipping interface for dipping is 1s-3min.

3. A bridge package interconnection method according to claim 2, characterized in that: In the step S1, the solid content of the nanoparticle slurry is ≥60%, and the particle size is ≤500nm; the solid nanoparticles are prepared by any one or more of ball milling, arc discharge, laser ablation and gas phase steam synthesis, and the particle size is ≤100nm.

4. A bridge package interconnection method according to claim 2, characterized in that: In the step S1, the nanoparticles are one or more of nano-copper, nano-silver, nano-gold, nano-tin, nano-silver-copper, nano-silver-copper alloy, nano-silver-copper solid solution and nano-tin-zinc alloy.

5. A bridge package interconnection method according to claim 1, characterized in that: In step S2, the silicon bridge is disposed in the groove of the substrate, and the substrate material of the silicon bridge is silicon or glass.

6. A bridge package interconnection method according to claim 5, characterized in that: In step S2, at least two chips are flipped on the same silicon bridge through the copper column ends to form a bridge packaging structure, the surface of the silicon bridge is provided with a high-density wiring layer, and the substrate is provided with a copper pad. The welding area described in step S5 is the high-density wiring layer of the silicon bridge and the copper pad of the substrate.

7. A bridge package interconnection method according to claim 1, characterized in that: In the step S3, the diameter of the copper column ends is 1 μm-50 μm, and the spacing between the copper column ends is 1 μm-50 μm.

8. The bridge package interconnection method according to claim 1, characterized in that: In the step S1, the dipped substrate is glass or silicon wafer, and the surface flatness of the dipped substrate is Ra≤10nm; in the step S2, the pretreatment includes one or more of acid treatment, plasma treatment and SAM.

9. The bridge package interconnection method according to claim 1, characterized in that: In step S5, the protective gas is an inert gas or a reducing gas, the inert gas is nitrogen, argon or helium, and the reducing gas is hydrogen, formaldehyde or carbon monoxide.

10. The bridge package interconnection method according to claim 1, characterized in that: In the step S5, the bonding process is carried out under the conditions of 120°C-260°C, 0-50MPa pressure, and 0-120kHz ultrasonic driving frequency.

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