Metal silicide thickness monitoring method and semiconductor device manufacturing method

Abstract

The invention provides a metal silicide thickness monitoring method and a semiconductor device manufacturing method, and the method comprises the steps: providing a test structure which comprises a substrate and a bipolar junction transistor, and forming metal silicide layers on the surfaces of an emitter region, a base region and a collector region of the bipolar junction transistor, an emitter, a base and a collector are formed on the metal silicide layers on the surfaces of the emitter region, the base region and the collector region; collecting electrode current IC and base electrode current IB when the bipolar junction transistor works in an amplification state are detected, a direct current amplification coefficient HFE is obtained through calculation, and HFE = IC / IB; and according to the experimental data of the thickness of the metal silicide layer and the experimental data of the direct current amplification coefficient HFE, fitting to obtain a linear relational expression between the thickness of the metal silicide layer and the direct current amplification coefficient HFE, so as to monitor whether the thickness of the metal silicide layer in the production process meets a set specification or not according to the linear relational expression. According to the technical scheme, the cost can be reduced while the thickness of the metal silicide is effectively monitored.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a method for monitoring the thickness of metal silicide and a method for manufacturing a semiconductor device. Background Art

[0002] Currently, the thickness of metal silicide during the production process cannot be effectively monitored and can only be confirmed through slicing, which consumes a lot of time and resources.

[0003] Therefore, how to effectively monitor the thickness of metal silicide while reducing costs is a technical problem that needs to be solved urgently. Summary of the invention

[0004] The object of the present invention is to provide a method for monitoring the thickness of metal silicide and a method for manufacturing a semiconductor device, so that the thickness of the metal silicide can be effectively monitored while reducing the cost.

[0005] To achieve the above object, the present invention provides a method for monitoring the thickness of metal silicide, comprising:

[0006] A test structure is provided, the test structure comprising a substrate and a bipolar junction transistor formed in the substrate, the bipolar junction transistor comprising an emitter region, a base region and a collector region extending from the surface of the substrate into the substrate, the base region wraps the emitter region, the collector region wraps the base region, metal silicide layers are formed on the surfaces of the emitter region, the base region and the collector region, and an emitter, a base and a collector are formed on the metal silicide layers on the surfaces of the emitter region, the base region and the collector region, respectively;

[0007] Detecting the collector current I when the bipolar junction transistor is operating in an amplifying state C and the base current I B , to calculate the DC current amplification factor HFE, HFE = I C / I B ;

[0008] Based on the experimental data of the measured thickness of the metal silicide layer and the calculated experimental data of the DC current amplification factor HFE, a linear relationship between the thickness of the metal silicide layer and the DC current amplification factor HFE is fitted to monitor whether the thickness of the metal silicide layer in the production process meets the set specifications based on the linear relationship.

[0009] Optionally, the collector current I of the bipolar junction transistor when it is operating in an amplification state is detected. C and the base current I B The steps include:

[0010] A fixed positive voltage is applied between the collector and the emitter, and a positive voltage varying from small to large is applied between the base and the emitter until the collector current I can be detected. C ;

[0011] Detecting the base current I B .

[0012] Optionally, the collector current I C Greater than or equal to 1μA.

[0013] Optionally, the step of fitting a linear relationship between the thickness of the metal silicide layer and the DC current amplification factor HFE comprises:

[0014] Detecting the collector current I of the plurality of test structures C and the base current I B , so as to calculate and obtain experimental data of a plurality of the DC current amplification factors HFE;

[0015] Slicing a plurality of the test structures to measure and obtain experimental data of the thickness of a plurality of the metal silicide layers;

[0016] The linear relationship is obtained by fitting a plurality of experimental data of the metal silicide layer thicknesses with a plurality of experimental data of the DC current amplification factors HFE.

[0017] Optionally, the doping type of the emitter region is the same as the doping type of the collector region, and the doping type of the emitter region is opposite to the doping type of the base region.

[0018] Optionally, the bipolar junction transistor also includes a first doping region and a second doping region, the first doping region is formed at the top of the base region, the doping type of the first doping region is the same as the doping type of the base region, and the doping concentration of the first doping region is greater than the doping concentration of the base region; the second doping region is formed at the top of the collector region, the doping type of the second doping region is the same as the doping type of the collector region, and the doping concentration of the second doping region is greater than the doping concentration of the collector region.

[0019] Optionally, the first doping region surrounds the emitting region, and the second doping region surrounds the first doping region.

[0020] Optionally, the test structure further includes a shallow trench isolation structure, and the shallow trench isolation structure is formed between the emitter region and the first doping region, and between the first doping region and the second doping region.

[0021] Optionally, the depth of the shallow trench isolation structure is greater than the depths of the emitter region, the first doping region and the second doping region, and the depth of the shallow trench isolation structure is less than the depth of the base region.

[0022] The present invention also provides a method for manufacturing a semiconductor device, comprising:

[0023] Providing a structure to be tested, the structure to be tested comprising a substrate and a bipolar junction transistor formed in the substrate, the bipolar junction transistor comprising an emitter region, a base region and a collector region extending from a surface of the substrate into the substrate, the base region wrapping the emitter region, and the collector region wrapping the base region;

[0024] Forming a metal silicide layer on the surfaces of the emitter region, the base region and the collector region;

[0025] Forming an emitter, a base and a collector on the metal silicide layer on the surface of the emitter region, the base region and the collector region respectively;

[0026] Detecting the collector current I when the bipolar junction transistor is operating in an amplifying state C and the base current I B , to calculate the DC current amplification factor HFE, HFE = I C / I B ;

[0027] Substituting the calculated DC current amplification factor HFE into the linear relationship obtained by the metal silicide thickness monitoring method according to any one of claims 1 to 9 to calculate the thickness of the metal silicide layer in the structure to be tested;

[0028] Determine whether the thickness of the metal silicide layer in the structure to be tested is within a set specification; if so, continue to form a metal silicide layer on the semiconductor structure to be produced.

[0029] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0030] 1. The method for monitoring the thickness of metal silicide of the present invention utilizes the fact that the current amplification characteristic of a bipolar junction transistor is related to the thickness of a metal silicide layer. When the bipolar junction transistor is operating in an amplification state, a linear relationship between the thickness of the metal silicide layer and the DC current amplification factor HFE is obtained by fitting, so as to monitor whether the thickness of the metal silicide layer in the production process meets the set specification according to the linear relationship, so that in the production process, only a metal silicide layer needs to be formed on a structure to be tested including the bipolar junction transistor, and the collector current I of the structure to be tested is detected. C and the base current IB By calculating the DC current amplification factor HFE, the thickness of the metal silicide layer formed under the current production process can be obtained, thereby realizing rapid and effective monitoring of the thickness of the metal silicide layer, saving the cost and time required for slicing the product, etc., and reducing costs.

[0031] 2. The method for manufacturing a semiconductor device of the present invention comprises first forming a metal silicide layer on a structure to be tested including the bipolar junction transistor, and detecting the collector current I of the structure to be tested. C and the base current I B The DC current amplification factor HFE is then calculated to obtain the thickness of the metal silicide layer formed under the current production process, so that the thickness of the metal silicide layer formed on the semiconductor structure to be produced can be ensured to meet the set specifications, thereby improving the device yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a flow chart of a method for monitoring the thickness of metal silicide according to an embodiment of the present invention;

[0033] Figure 2 is a schematic top view of a test structure according to an embodiment of the present invention;

[0034] Figure 3 yes Figure 2 The cross-sectional view of the test structure along the AA' direction is shown.

[0035] Among them, Figure 1 to Figure 3 The reference numerals are described as follows:

[0036] 10 - substrate; 101 - third doping region; 11 - emitter region; 12 - base region; 121 - first doping region; 13 - collector region; 131 - second doping region; 14 - shallow trench isolation structure. DETAILED DESCRIPTION

[0037] In order to make the purpose, advantages and features of the present invention more clear, the metal silicide thickness monitoring method and the semiconductor device manufacturing method proposed by the present invention are further described in detail below. It should be noted that the drawings are all in a very simplified form and are not in precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0038] An embodiment of the present invention provides a method for monitoring the thickness of metal silicide. Figure 1 ,from Figure 1 It can be seen that the method for monitoring the thickness of the metal silicide includes:

[0039] Step S1, providing a test structure, the test structure comprising a substrate and a bipolar junction transistor formed in the substrate, the bipolar junction transistor comprising an emitter region, a base region and a collector region extending from the surface of the substrate into the substrate, the base region wraps the emitter region, the collector region wraps the base region, metal silicide layers are formed on the surfaces of the emitter region, the base region and the collector region, and an emitter, a base and a collector are formed on the metal silicide layers on the surfaces of the emitter region, the base region and the collector region, respectively;

[0040] Step S2, detecting the collector current I when the bipolar junction transistor is operating in an amplifying state C and the base current I B , to calculate the DC current amplification factor HFE, HFE = I C / I B ;

[0041] Step S3, fitting a linear relationship between the thickness of the metal silicide layer and the DC current amplification factor HFE based on the experimental data of the measured thickness of the metal silicide layer and the calculated experimental data of the DC current amplification factor HFE, so as to monitor whether the thickness of the metal silicide layer in the production process meets the set specifications based on the linear relationship.

[0042] See below Figure 2-Figure 3 The method for monitoring the thickness of metal silicide provided in this embodiment is described in detail.

[0043] According to step S1, a test structure is provided, the test structure comprising a substrate 10 and a bipolar junction transistor (BJT) formed in the substrate 10, the bipolar junction transistor comprising an emitter region 11, a base region 12 and a collector region 13 extending from the surface of the substrate 10 into the substrate 10, the base region 12 wraps the emitter region 11, the collector region 13 wraps the base region 12, a metal silicide layer (not shown) is formed on the surfaces of the emitter region 11, the base region 12 and the collector region 13, an emitter (not shown), a base (not shown) and a collector (not shown) are respectively formed on the metal silicide layers on the surfaces of the emitter region 11, the base region 12 and the collector region 13.

[0044] Voltages can be applied to the emitter region 11, the base region 12 and the collector region 13 respectively through the emitter, the base and the collector, and the metal silicide layer is used to reduce the contact resistance between the emitter, the base and the collector and the emitter region 11, the base region 12 and the collector region 13 respectively.

[0045] The metal in the metal silicide layer is, for example, cobalt, nickel, titanium, etc.

[0046] The doping type of the emitter region 11 is the same as the doping type of the collector region 13 , and the doping type of the emitter region 11 is opposite to the doping type of the base region 12 .

[0047] When the doping types of the emitter region 11 and the collector region 13 are N-type and the doping type of the base region 12 is P-type, the bipolar junction transistor is an NPN bipolar junction transistor; when the doping types of the emitter region 11 and the collector region 13 are P-type and the doping type of the base region 12 is N-type, the bipolar junction transistor is a PNP bipolar junction transistor.

[0048] In one embodiment, the bipolar junction transistor further includes a first doping region 121 and a second doping region 131, wherein the first doping region 121 is formed on the top of the base region 12, the doping type of the first doping region 121 is the same as the doping type of the base region 12, the doping concentration of the first doping region 121 is greater than the doping concentration of the base region 12, and the first doping region 121 is used to lead out the base region 12; the second doping region 131 is formed on the top of the collector region 13, the doping type of the second doping region 131 is the same as the doping type of the collector region 13, the doping concentration of the second doping region 131 is greater than the doping concentration of the collector region 13, and the second doping region 131 is used to lead out the collector region 13. The metal silicide layer is formed on the surfaces of the first doping region 121 and the second doping region 131.

[0049] The first doping region 121 surrounds the emitting region 11 , and the second doping region 131 surrounds the first doping region 121 .

[0050] The test structure further includes a shallow trench isolation structure 14 . The shallow trench isolation structure 14 is formed between the emitter region 11 and the first doping region 121 , and between the first doping region 121 and the second doping region 131 , so as to play an isolation role.

[0051] The depth of the shallow trench isolation structure 14 is greater than the depths of the emitter region 11 , the first doping region 121 , and the second doping region 131 , and the depth of the shallow trench isolation structure 14 is less than the depth of the base region 12 .

[0052] The doping type of the substrate 10 is opposite to the doping type of the collector region 13. In one embodiment, a third doping region 101 is further formed on the top of the substrate 10 outside the collector region 13, the doping type of the third doping region 101 is the same as the doping type of the substrate 10, the doping concentration of the third doping region 101 is greater than the doping concentration of the substrate 10, and the third doping region 101 is used to lead out the substrate 10. The metal silicide layer is also formed on the surface of the third doping region 101.

[0053] The third doping region 101 surrounds the second doping region 131 . The shallow trench isolation structure 14 is also formed between the third doping region 101 and the second doping region 131 . The depth of the shallow trench isolation structure 14 is greater than the depth of the third doping region 101 .

[0054] An insulating dielectric layer (not shown) is also formed on the substrate 10, and the insulating dielectric layer covers the metal silicide layer on the surface of the emitter region 11, the first doping region 121, the second doping region 131 and the third doping region 101, and the shallow trench isolation structure 14. The emitter, the base and the collector are respectively formed in the insulating dielectric layer on the metal silicide layer on the surface of the emitter region 11, the first doping region 121 and the second doping region 131, and the emitter, the base and the collector are exposed on the surface of the insulating dielectric layer.

[0055] According to step S2, the collector current I of the bipolar junction transistor when it is operating in the amplification state is detected. C and the base current I B , to calculate the DC current amplification factor HFE, HFE = I C / I B .

[0056] When the bipolar junction transistor is operating in an amplifying state, the emitter junction (i.e., the junction between the emitter and the base) is forward biased and the collector junction (i.e., the junction between the collector and the base) is reverse biased; that is, by applying a positive voltage (i.e., V BE >0), and a negative voltage (i.e., V BC <0), which enables the bipolar junction transistor to operate in an amplifying state.

[0057] Among them, V BE >0 is the base voltage V B >Emitter voltage V E ; V BC <0 means base voltage V B <Collector voltage V CTherefore, the collector voltage V C >Emitter voltage V E , that is, V CE >0, that is, the bipolar junction transistor can be operated in an amplification state by applying a positive voltage between the collector and the emitter.

[0058] In one embodiment, the collector current I of the bipolar junction transistor when it is operating in the amplification state is detected. C and the base current I B The steps include: first, applying a fixed positive voltage between the collector and the emitter, and applying a positive voltage varying from small to large between the base and the emitter until the collector current I can be detected. C Then, the base current I is detected B .

[0059] The positive voltage applied between the collector and the emitter and the positive voltage applied between the base and the emitter are both within the voltage range that the bipolar junction transistor can withstand, so as to avoid burning the bipolar junction transistor due to excessive applied voltage.

[0060] Furthermore, when the positive voltage applied between the base and the emitter is small, the collector current I C will also be small, causing the collector current I C Therefore, the positive voltage applied between the base and the emitter is gradually increased from small to large until the collector current I C can be measured, ensuring that the collector current I C If the detection is accurate, then detect the base current I under the current applied voltage B , so that the calculated DC current amplification factor HFE can be ensured to be more accurate.

[0061] In one embodiment, a positive voltage varying from small to large is applied between the base and the emitter until the collector current I C Greater than or equal to 1μA.

[0062] According to step S3, a linear relationship between the thickness of the metal silicide layer and the DC current amplification factor HFE is fitted based on the experimental data of the measured thickness of the metal silicide layer and the calculated experimental data of the DC current amplification factor HFE, so as to monitor whether the thickness of the metal silicide layer in the production process meets the set specifications based on the linear relationship.

[0063] In one embodiment, the step of fitting a linear relationship between the thickness of the metal silicide layer and the DC current amplification factor HFE comprises:

[0064] First, a plurality of the test structures are provided, and the collector currents I of the plurality of the test structures are detected according to step S2. C and the base current I B , so as to calculate and obtain experimental data of a plurality of the DC current amplification factors HFE; wherein the metal silicide layer in each of the test structures can be formed under different process conditions, so that the thickness of the metal silicide layer in each of the test structures is different;

[0065] Then, by detecting the collector current I C and the base current I B Then, the plurality of test structures are sliced ​​to measure and obtain experimental data of the thickness of the plurality of metal silicide layers; wherein the test structure can be sliced ​​along a direction perpendicular to the surface of the substrate 10 to expose the cross section of the test structure, and the thickness of the metal silicide layer is measured by using a TEM (Transmission Electron Microscope) or a SEM (Scanning Electron Microscope);

[0066] Then, the linear relationship is obtained by fitting a plurality of experimental data of the metal silicide layer thicknesses with a plurality of experimental data of the DC current amplification factors HFE.

[0067] The linear relationship may be y=ax+b, wherein y is the thickness of the metal silicide layer, x is the DC current amplification factor HFE, and a and b are constants obtained by fitting.

[0068] The principle of a linear relationship between the thickness of the metal silicide layer and the DC current amplification factor HFE is explained below:

[0069] Since the collector current I C is from the emitter through the emitter region 11, the base region 12 and the collector region 13 to the collector, and the base current I B It flows from the emitter through the emitter region 11 and the base region 12 to the base. Therefore, the collector current I C The flow path of the base current I B The flow path is longer, the collector current I C The flow path area is larger than the base current I BThe flow path area is larger, which affects the collector current I C The size of the first total resistor area ratio affects the base current I B The area of ​​the second total resistance is larger, which in turn affects the collector current I C The resistance of the first total resistor is greater than the resistance that affects the base current I B The resistance value of the second total resistor.

[0070] Among them, the influence of the collector current I C The first total resistance of magnitude includes the first substrate resistance of the emitter region 11, the base region 12 and the collector region 13 and the first contact resistance of the region where the metal silicide layer on the surface of the emitter region 11 and the collector region 13 is located; the base current I B The second total resistance of magnitude includes a second substrate resistance in the area where the emitter region 11 and the base region 12 are located and a second contact resistance in the area where the metal silicide layer on the surface of the emitter region 11 and the base region 12 is located. The first substrate resistance is connected in series with the first contact resistance, and the second substrate resistance is connected in series with the second contact resistance. The resistance value of the first substrate resistance is significantly greater than the resistance value of the second substrate resistance.

[0071] Furthermore, since the area of ​​the collector region 13 in a direction parallel to the surface of the substrate 10 is larger than the area of ​​the base region 12 in a direction parallel to the surface of the substrate 10 , the resistance value of the first substrate resistor is further larger than the resistance value of the second substrate resistor.

[0072] Since the metal silicide layer is formed by depositing metal on the surface of the substrate 10 and the metal reacts with the material of the substrate 10 at high temperature, a partial thickness of the metal silicide layer will be located inside the substrate 10, so that when the thickness of the metal silicide layer on the surface of the emitter region 11, the base region 12 and the collector region 13 changes, the thickness of the metal silicide layer located inside the substrate 10 will also change, thereby causing the area of ​​the substrate 10 in the region where the emitter region 11, the base region 12 and the collector region 13 are located (referring to the area in the direction perpendicular to the surface of the substrate 10) to change, thereby causing the resistance values ​​of the first substrate resistor and the second substrate resistor to change. Therefore, when the thickness of the metal silicide layer changes, not only the resistance values ​​of the first contact resistance and the second contact resistance change, but also the resistance values ​​of the first substrate resistance and the second substrate resistance change; and, since the first substrate resistance and the second substrate resistance account for a larger proportion of the first total resistance and the second total resistance respectively than the first contact resistance and the second contact resistance, the change in the resistance values ​​of the first substrate resistance and the second substrate resistance has a greater impact on the resistance values ​​of the first total resistance and the second total resistance.

[0073] For example, when the thickness of the metal silicide layer on the surface of the emitter region 11, the base region 12 and the collector region 13 increases, the thickness of the metal silicide layer in the substrate 10 will also increase, so that the area of ​​the substrate 10 in the region where the emitter region 11, the base region 12 and the collector region 13 are located is reduced, thereby increasing the resistance values ​​of the first contact resistance and the second contact resistance, and reducing the resistance values ​​of the first substrate resistance and the second substrate resistance. However, the reduction in the resistance value of the first substrate resistance is greater than the increase in the resistance value of the first contact resistance, and the reduction in the resistance value of the second substrate resistance is greater than the increase in the resistance value of the second contact resistance, so the resistance values ​​of the first total resistance and the second total resistance are both reduced; and because the resistance value of the first total resistance is greater than the resistance value of the second total resistance, the reduction ratio of the resistance value of the first total resistance is less than the reduction ratio of the resistance value of the second total resistance, thereby causing the collector current I C The increase ratio is smaller than the base current I B of the increase ratio, thereby reducing the DC current amplification factor HFE.

[0074] Therefore, when the thickness of the metal silicide layer increases, the DC current amplification factor HFE decreases; conversely, when the thickness of the metal silicide layer decreases, the DC current amplification factor HFE increases, that is, there is a linear relationship between the thickness of the metal silicide layer and the DC current amplification factor HFE.

[0075] It can be seen from the above content that the current amplification characteristic of the bipolar junction transistor is related to the thickness of the metal silicide layer. When the bipolar junction transistor works in the amplification state, a linear relationship between the thickness of the metal silicide layer and the DC current amplification factor HFE is obtained by fitting, so as to monitor whether the thickness of the metal silicide layer in the production process meets the set specifications according to the linear relationship, so that in the production process, it is only necessary to form a metal silicide layer on the structure to be tested including the bipolar junction transistor, and detect the collector current I of the structure to be tested. C and the base current I B By calculating the DC current amplification factor HFE, the thickness of the metal silicide layer formed under the current production process can be obtained, thereby realizing rapid and effective monitoring of the thickness of the metal silicide layer, saving the cost and time required for slicing the product, etc., and reducing costs.

[0076] In summary, the present invention provides a method for monitoring the thickness of metal silicide, comprising: providing a test structure, the test structure comprising a substrate and a bipolar junction transistor formed in the substrate, the bipolar junction transistor comprising an emitter region, a base region and a collector region extending from the surface of the substrate into the substrate, the base region wraps the emitter region, the collector region wraps the base region, the surfaces of the emitter region, the base region and the collector region are all formed with a metal silicide layer, and the metal silicide layers on the surfaces of the emitter region, the base region and the collector region are respectively formed with an emitter, a base and a collector; detecting the collector current I of the bipolar junction transistor when it is working in an amplified state C and the base current I B , to calculate the DC current amplification factor HFE, HFE = I C / I B ; According to the measured data of the thickness of the metal silicide layer and the calculated data of the DC current magnification factor HFE, a linear relationship between the thickness of the metal silicide layer and the DC current magnification factor HFE is fitted to monitor whether the thickness of the metal silicide layer in the production process meets the set specifications according to the linear relationship. The monitoring method of the metal silicide thickness provided by the present invention can effectively monitor the thickness of the metal silicide while reducing costs.

[0077] An embodiment of the present invention provides a method for manufacturing a semiconductor device, the method comprising:

[0078] First, a structure to be tested is provided, wherein the structure to be tested includes a substrate and a bipolar junction transistor formed in the substrate, wherein the bipolar junction transistor includes an emitter region, a base region and a collector region extending from a surface of the substrate into the substrate, wherein the base region wraps around the emitter region, and the collector region wraps around the base region;

[0079] Then, a metal silicide layer is formed on the surfaces of the emitter region, the base region and the collector region; wherein the process parameters for forming the metal silicide layer are the same as the process parameters for subsequently forming a metal silicide layer on the semiconductor structure to be produced;

[0080] Then, an emitter, a base and a collector are formed on the metal silicide layer on the surface of the emitter region, the base region and the collector region respectively;

[0081] Then, the collector current I of the bipolar junction transistor when it is working in the amplification state is detected. C and the base current I B , to calculate the DC current amplification factor HFE, HFE = I C / I B ; The specific process of this step is the same as the content of step S2 in the method for monitoring the thickness of the metal silicide, and will not be repeated here;

[0082] Then, the calculated DC current amplification factor HFE is substituted into the linear relationship obtained by the metal silicide thickness monitoring method to calculate the thickness of the metal silicide layer in the structure to be tested; the metal silicide thickness monitoring method is referred to the above content and will not be described in detail here;

[0083] Then, it is determined whether the thickness of the metal silicide layer in the structure to be tested is within a set specification; if so, the metal silicide layer is continuously formed on the semiconductor structure to be produced.

[0084] It should be noted that the composition of the structure to be tested, the structures of the metal silicide layer, the emitter, the base and the collector are the same as the composition of the test structure in the method for monitoring the thickness of the metal silicide, and will not be repeated here.

[0085] From the above content, it can be known that during or before the production process, a metal silicide layer is first formed on the structure to be tested including the bipolar junction transistor, and the collector current I of the structure to be tested is detected. C and the base current I BThe DC current amplification factor HFE is then calculated to obtain the thickness of the metal silicide layer formed under the current production process, so that the thickness of the metal silicide layer formed on the semiconductor structure to be produced can be ensured to meet the set specifications, thereby improving the device yield.

[0086] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for monitoring the thickness of metal silicide, characterized in that: include: A test structure is provided, the test structure comprising a substrate and a bipolar junction transistor formed in the substrate, the bipolar junction transistor comprising an emitter region, a base region and a collector region extending from the surface of the substrate into the substrate, the base region wraps the emitter region, the collector region wraps the base region, metal silicide layers are formed on the surfaces of the emitter region, the base region and the collector region, and an emitter, a base and a collector are formed on the metal silicide layers on the surfaces of the emitter region, the base region and the collector region, respectively; Detecting the collector current I when the bipolar junction transistor is operating in an amplification state C and the base current I B , to calculate the DC current magnification factor HFE, HFE = I C / I B ; Based on the experimental data of the measured thickness of the metal silicide layer and the calculated experimental data of the DC current amplification factor HFE, a linear relationship between the thickness of the metal silicide layer and the DC current amplification factor HFE is fitted to monitor whether the thickness of the metal silicide layer in the production process meets the set specifications based on the linear relationship.

2. The method for monitoring the thickness of metal silicide according to claim 1, characterized in that: Detecting the collector current I when the bipolar junction transistor is operating in an amplification state C and the base current I B The steps include: A fixed positive voltage is applied between the collector and the emitter, and a positive voltage varying from small to large is applied between the base and the emitter until the collector current I can be detected. C ; Detecting the base current I B .

3. The method for monitoring the thickness of metal silicide according to claim 2, characterized in that: The collector current I C Greater than or equal to 1μA.

4. The method for monitoring the thickness of metal silicide according to claim 1, characterized in that: The step of fitting a linear relationship between the thickness of the metal silicide layer and the DC current amplification factor HFE comprises: Detecting the collector current I of the plurality of test structures C and the base current I B , so as to calculate and obtain experimental data of a plurality of the DC current amplification factors HFE; Slicing a plurality of the test structures to obtain experimental data of the thickness of a plurality of the metal silicide layers; The linear relationship is obtained by fitting a plurality of experimental data of the metal silicide layer thicknesses with a plurality of experimental data of the DC current amplification factors HFE.

5. The method for monitoring the thickness of metal silicide according to claim 1, characterized in that: The doping type of the emitter region is the same as the doping type of the collector region, and the doping type of the emitter region is opposite to the doping type of the base region.

6. The method for monitoring the thickness of metal silicide according to claim 1, characterized in that: The bipolar junction transistor also includes a first doping region and a second doping region, wherein the first doping region is formed at the top of the base region, the doping type of the first doping region is the same as the doping type of the base region, and the doping concentration of the first doping region is greater than the doping concentration of the base region; the second doping region is formed at the top of the collector region, the doping type of the second doping region is the same as the doping type of the collector region, and the doping concentration of the second doping region is greater than the doping concentration of the collector region.

7. The method for monitoring the thickness of metal silicide according to claim 6, characterized in that: The first doping region surrounds the emitting region, and the second doping region surrounds the first doping region.

8. The method for monitoring the thickness of metal silicide according to claim 7, characterized in that: The test structure further includes a shallow trench isolation structure formed between the emitter region and the first doping region and between the first doping region and the second doping region.

9. The method for monitoring the thickness of metal silicide according to claim 8, characterized in that: The depth of the shallow trench isolation structure is greater than the depths of the emitter region, the first doping region, and the second doping region, and the depth of the shallow trench isolation structure is less than the depth of the base region.

10. A method for manufacturing a semiconductor device, characterized in that: include: Providing a structure to be tested, the structure to be tested comprising a substrate and a bipolar junction transistor formed in the substrate, the bipolar junction transistor comprising an emitter region, a base region and a collector region extending from a surface of the substrate into the substrate, the base region wrapping the emitter region, and the collector region wrapping the base region; Forming a metal silicide layer on the surfaces of the emitter region, the base region and the collector region; Forming an emitter, a base and a collector on the metal silicide layer on the surface of the emitter region, the base region and the collector region respectively; Detecting the collector current I when the bipolar junction transistor is operating in an amplification state C and the base current I B , to calculate the DC current magnification factor HFE, HFE = I C / I B ; Substituting the calculated DC current amplification factor HFE into the linear relationship obtained by the metal silicide thickness monitoring method according to any one of claims 1 to 9 to calculate the thickness of the metal silicide layer in the structure to be tested; Determining whether the thickness of the metal silicide layer in the structure to be tested is within a set specification; If yes, then continue to form a metal silicide layer on the semiconductor structure to be produced.

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