Semiconductor device having self-aligned nitride

Abstract

The invention relates to a semiconductor device with self-aligned nitride for power isolation. A method of forming an integrated circuit (100) includes forming a first trench (114) that extends into a semiconductor substrate (108). A silicon nitride layer (410) is deposited over the semiconductor substrate (108). The silicon nitride layer (410) extends into the first trench (114). A second trench (430) is formed, the second trench extending through the silicon nitride layer (410) into the semiconductor substrate (108). The second trench (430) is spaced apart from the first trench (114). An oxide layer (420A) is formed, which fills the second trench (430). And removing the silicon nitride layer (410) outside the first groove (114).

Description

[0001] Related Applications

[0002] This application is related to commonly owned U.S. patent application No. 18 / 361,880, filed on July 30, 2023, entitled “Semiconductor Device with a High K Field Relief Dielectric Structure,” which is hereby incorporated herein by reference in its entirety. Technical Field

[0003] The present application relates to a semiconductor device having a self-aligned nitride for power isolation. Background Art

[0004] Semiconductor components are continually improving to operate reliably with smaller feature sizes. Manufacturing semiconductor devices with increasingly higher performance while meeting reliability specifications is challenging. Summary of the invention

[0005] This Summary is provided to introduce a brief selection of disclosed concepts in a simplified form that are further described below in the Detailed Description including the provided figures. This Summary is not intended to limit the scope of the claimed subject matter.

[0006] In a first example, a method of forming an integrated circuit includes forming a power isolation trench extending into a semiconductor substrate. Depositing a silicon nitride layer over the semiconductor substrate. The silicon nitride layer extending into the power isolation trench. Forming a shallow isolation trench extending through the silicon nitride layer into the semiconductor substrate. The shallow isolation trench is spaced apart from the power isolation trench. Forming an oxide layer, the oxide layer filling the shallow isolation trench. Removing the silicon nitride layer outside the power isolation trench.

[0007] In a second example, a semiconductor device includes a semiconductor material of a substrate, a first trench, and a second trench. The semiconductor material includes a body region having a first conductivity type and a drain drift region having a second conductivity type. The first trench extends into the body region and is at least partially filled with a dielectric material. The second trench extends into the drain drift region and is at least partially filled with a silicon nitride layer. The silicon nitride layer extends above a top surface of the drain drift region. The silicon nitride layer forms a protruding trench above the second trench. The protruding trench is at least partially filled with the dielectric material.

[0008] In a third example, a semiconductor device includes a semiconductor material of a substrate, a first trench, and a second trench. The semiconductor material includes a body region having a first conductivity type and a drain drift region having a second conductivity type. The first trench extends into the body region and is at least partially filled with a dielectric material. The second trench extends into the drain drift region and is at least partially filled with a silicon nitride layer. The silicon nitride layer has a top surface coplanar with a top surface of the drain drift region. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 and 2 are cross sections of example microelectronic devices including transistors at various stages of formation.

[0010] Figures 3A to 3C yes Figure 1 and 2 0026] A cross section of two separate portions of an example microelectronic device showing a power isolation region and a shallow trench isolation region of a transistor at successive stages of formation.

[0011] Figures 4A to 4E yes Figure 1 and 2 A cross-section of a microelectronic device showing a power isolation region and a shallow trench isolation region in successive stages of formation according to a first process flow. The first process flow can be found in reference Figure 2 or Figures 3A to 3C The corresponding process flow described is then carried out.

[0012] Figures 5A to 5F yes Figure 1 and 2 A cross-section of a microelectronic device showing a power isolation region and a shallow trench isolation region in successive stages of formation according to a second process flow. The second process flow can be found in reference Figure 2 or Figures 3A to 3C The corresponding process flow described is then carried out. DETAILED DESCRIPTION

[0013] The present disclosure is described with reference to the accompanying drawings. The same reference numerals or other reference indicators are used in the drawings to represent (functionally and / or structurally) the same or similar features. The drawings are not drawn to scale and are provided only for illustrating the present disclosure. Several aspects of the present disclosure are described below with reference to examples for illustration. It should be understood that many specific details, relationships and methods are set forth to provide an understanding of the present disclosure. The present disclosure is not limited to the described ordering of actions or events, because some actions may occur in different orders and / or simultaneously with other actions or events. In addition, not all described actions or events are required to implement the method according to the present disclosure.

[0014] In addition, although some of the examples described herein are shown with two-dimensional views of various regions having depth and width, it should be clearly understood that these regions are only illustrations of a portion of a device that is actually a three-dimensional structure. Therefore, when manufactured on an actual device, these regions will have three dimensions, including length, width, and depth. In addition, although the present disclosure is described by examples directed to active devices, these descriptions are not intended to limit the scope or applicability of the present disclosure. The active devices of the present disclosure are not intended to be limited to the physical structures described. These structures are included to demonstrate the practicality and application of the present disclosure.

[0015] Microelectronic devices are constantly being improved to operate reliably with smaller feature sizes. It is challenging to manufacture such microelectronic devices that meet area scaling and reliability requirements. Certain metal oxide semiconductor (MOS) transistors include features for supporting high voltage operation, for example, the voltage applied to its drain (or drain structure) is about 20V, 30V, 40V or even greater. Such MOS transistors may include a drain diffusion profile (or drain junction profile) designed to support a high voltage applied to the drain--for example, with an extension portion to distribute the voltage drop across a wider area. Therefore, such MOS transistors may be referred to as drain extended MOS transistors, for example, drain extended n-channel MOS (DENMOS) transistors, drain extended p-channel MOS (DEPMOS) transistors, lateral diffusion MOS (LDMOS) transistors, and DENMOS and DEPMOS transistor groups (which may be referred to as complementary drain extended MOS or DECMOS transistors).

[0016] The described examples include doped regions of various semiconductor structures, which can be characterized as p-doped and / or n-doped regions or portions, and include regions having a particular type of primary dopant, such as an n-type dopant (providing electrons as charge carriers) or a p-type dopant (providing holes as charge carriers). For the purposes of this description, the first type of doping can be n-type doping (n-doping, first conductivity type), and the second type of doping can be p-type doping (p-doping, second conductivity type).

[0017] The disclosed examples include a microelectronic device having an improved process flow for a power isolation (PI) region and a shallow trench isolation (STI) region of an LDMOS transistor 101. Although the LDMOS transistor 101 described herein is an n-channel type (or an n-channel LDMOS), a p-channel type LDMOS transistor (or a p-channel LDMOS) can be formed according to the present disclosure when an n-doped region is replaced by a p-doped region and a p-doped region is replaced by an n-doped region.

[0018] refer to Figure 1 , 2 and Figures 4A to 4EA first example process flow for forming a microelectronic device including an LDMOS transistor is described. Figure 1 , 2 and Figures 5A to 5F A second exemplary process flow for forming a microelectronic device including an LDMOS transistor is described. The first or second process flow may further include certain intermediate processes involving local oxidation of silicon (LOCOS), as described herein with reference to Figures 3A to 3C described.

[0019] The first example process flow uses a self-aligned underfill process, wherein the underfill is used to prevent the removal of the STI nitride hard mask from the PI region during the STI process. Therefore, the first example process flow can facilitate the formation of the PI region with a fewer number of process steps for forming the PI region and the STI region (e.g., a reduced number of photolithography patterns and etching processes), thereby providing cost savings and simplification. The first example process flow can also provide cost savings and simplification by using only a single chemical mechanical planarization (CMP) process when forming the PI region, compared to using multiple CMP processes.

[0020] The second example process flow uses a thick STI hard mask for nitride filling and is also reused in the same manner as the hard mask when forming the STI region. The second example process flow can provide cost savings and simplification by reducing the number of overall process steps for forming the PI region and the STI region of the transistor (e.g., reducing the number of photolithography patterning and etching processes).

[0021] Figure 1 A cross-section of a microelectronic device, generally referred to as device 100, is shown at an early stage of fabrication, with a base wafer 105 comprising a layer of semiconductor material, referred to herein as substrate 103. Substrate 103 has a top surface 104. Base wafer 105 may comprise, for example, an epitaxial layer over a bulk semiconductor wafer, or may be part of a silicon-on-insulator (SOI) wafer, or one or more other structures suitable for forming a microelectronic device such as electronic device 400 and / or electronic device 500 as described below.

[0022] An n-type buried layer (NBL) 106 may be optionally formed over the base wafer 105. For example, the base wafer 105 may be p-type with a dopant concentration of 1×10 17 atoms / cm3 3 ) to 1×10 18 atoms / cm3. Alternatively, the base wafer 105 may be lightly doped, with an average dopant concentration of less than 1×10 16 atoms / cm3. For example, NBL 106 may be 2 to 10 microns thick and may have a 1×10 17atoms / cm3 to 1×10 18 In the illustrated example, an epitaxial layer 107 of silicon is located above the NBL 106. For example, the epitaxial layer 107 is part of the substrate 103 and can be 2 microns to 12 microns thick. For example, the epitaxial layer 107 can be p-type with a dopant concentration of 1×10 15 atoms / cm3 to 1×10 16 The epitaxial layer 107 may be located directly on the base wafer 105. As will become apparent in the discussion, the epitaxial layer 107 may serve as the body region 108 of the LDMOS transistor 101. The body region 108 has a first conductivity type, which in the current example is p-type.

[0023] In an earlier process step, a pad oxide layer 118 of silicon dioxide has been formed on the substrate 103. The pad oxide layer 118 may include silicon dioxide formed by a thermal oxidation process or a chemical vapor deposition (CVD) process. The pad oxide layer 118 may provide stress relief between the substrate 103 and subsequent layers. For example, the pad oxide layer 118 may be 5 nm to 50 nm thick. In an earlier process step, a silicon nitride layer 120 may also be deposited on the pad oxide layer 118.

[0024] refer to Figure 2 , a patterned photomask (not specifically shown) has been formed to define an opening corresponding to the groove 114. The photomask serves to mask the silicon nitride layer 120, and the photomask may include a photosensitive organic material that is coated, exposed, and developed. One or more etching processes (e.g., plasma etching or dry etching) may be used to remove the silicon nitride layer 120 and optionally the pad oxide layer 118 in the exposed areas of the photomask. In a first example, a LOCOS process may be used to form the groove 114. In this example, a LOCOS oxide layer (not shown) is grown by any suitable LOCOS process. The groove 114 is formed when the epitaxial layer 107 is consumed by forming the LOCOS oxide layer, and remains after the LOCOS oxide layer is removed, for example, by HF stripping. In a second example, the groove 114 may be formed by selectively removing a portion of the epitaxial layer 108 exposed by the opening in the silicon nitride layer 120 using plasma etching. However, the trench 114 is formed, and structures associated therewith may be referred to hereinafter using the term "LOCOS" formed in the PI without implying limitation.

[0025] Figures 3A to 3C3 is a cross-section of two separate portions of the microelectronic device 300 , which represents the microelectronic device 100 at a later stage of fabrication, wherein the PI region 310 and the STI region 320 are representatively shown in successive stages of formation.

[0026] Figure 3A Device 300 is shown after processing including a LOCOS option, using LOCOS furnace oxidation 124 to form dielectric layer 126, contained within trench 114. Any suitable LOCOS process may be used, such as steam oxidation. Dielectric layer 126 may be formed to have a thickness that overfills PI trench 114. In various examples, dielectric layer 126 has a thickness in a range between 50nm and 150nm. Dielectric layers such as dielectric layer 126 resulting from LOCOS type processing may have tapered edges, becoming thinner near their periphery and ending in a "bird's beak" shape where the field release dielectric layer 126 joins epitaxial layer 107. At Figure 3A At the formation stage shown in , the STI region 320 does not yet have an STI trench formed therein, and the pad oxide layer 118 is formed on the top surface 104 , and the silicon nitride layer 120 is located on the second pad oxide layer 118 .

[0027] exist Figure 3B At the stage of formation shown in , dielectric layer 126 has been removed, for example, by HF stripping, leaving unfilled PI trench 114. STI region 320 does not yet have an STI trench formed therein, and pad oxide layer 118 remains on top surface 104, and second silicon nitride layer 120 remains on second pad oxide layer 118. In the example where PI trench 114 is formed by removing a portion of epitaxial layer 108 with a dry etch, bird's beak and other artifacts of LOCOS formation may not be present. If dielectric layer 126 is formed within PI trench 114 at PI region 310, as shown in FIG. Figure 3A As shown in , the dielectric layer 126 can then be removed from the PI trench 114 .

[0028] refer to Figure 3C , an in-situ steam generated (ISSG) oxide liner layer 318 is formed within the PI trench 114, and thereafter, a nitride strip is used to remove the silicon nitride layer 120 as shown.

[0029] Figures 4A to 4C is in Figure 3C 4 is a cross-section of two separate portions of a microelectronic device 400 formed in a first example process flow starting with the device 300 shown in FIG. PI region 310 and STI region 320 are shown at successive stages of formation using a self-aligned underfill process. Figure 4A , a silicon nitride layer 410 is formed on the oxide layers 118 and 318, including Figure 3C104. The formation of the nitride layer 410 in and around the PI trench 114 results in the formation of a recess having dimensions generally conforming to the underlying PI trench 114, such that the recess is referred to herein as a protruding trench 415. The silicon nitride layer 410 may be formed to have a thickness less than the depth of the PI trench 114, such that the silicon nitride layer 410 does not completely fill the PI trench 114, and such that the top surface of the portion of the silicon nitride layer 410 at the bottom of the protruding trench 415 is not coplanar with the top surface of the pad oxide layer 118 above the top surface 104.

[0030] Figure 4B The PI region 310 and STI region 320 of the microelectronic device 400 are shown after forming the STI trench 430. The STI trench 430 extends through the silicon nitride layer 410, the corresponding portion of the pad oxide layer 118 and into the body region 108. A precursor dielectric layer (not explicitly shown) has been formed and partially removed, for example by CMP, to produce a filling dielectric 420A within the STI trench 430 and a filling dielectric 420B within the protruding trench 415. In order to prepare the underlying surface before forming the dielectric layer (from which the filling dielectrics 420A and 420B are formed), a photomask (not specifically shown) can be formed, the photomask containing a photosensitive organic material that is applied, exposed and developed. The STI trench 430 itself can be formed using one or more etching processes (e.g., plasma etching or dry etching) that selectively remove portions of the silicon nitride layer 410 and the pad oxide layer 118 in the exposed areas of the photomask. Once formed, the STI trenches 430 may then be filled with a precursor dielectric layer.

[0031] A precursor dielectric layer is formed on silicon nitride layer 410, within STI trenches 430 in STI region 320, and within protruding trenches 415 in PI region 310. The dielectric layer is formed with a sufficient thickness to fill the area within protruding trenches 415 in PI region 310 and the area within STI trenches 430 in STI region 320. The dielectric layer may contain any suitable dielectric material, such as a high density plasma (HDP) oxide. The dielectric layer is then partially removed or planarized by chemical mechanical planarization (CMP) to provide Figure 4B The planarized top surface is representatively shown in FIG. 4 and a filling dielectric 420A is formed in the STI trench 430 and a filling dielectric 420B is formed in the protruding trench 415 .

[0032] Figure 4CPI region 310 and STI region 320 of microelectronic device 400 are shown after forming PI structure 426 within PI region 310 and forming STI structure 440 within STI region 320. Structures 426 and 440 may be formed, for example, using a wet clean to selectively remove most or all of silicon nitride layer 410 above top surface 104. The presence of fill dielectric 420B within PI trench 114 allows a portion of silicon nitride layer 410 to remain between fill dielectric 420B and oxide liner 318. Figure 4C As shown in FIG. 4 , the remaining portion of silicon nitride layer 410 forms sidewalls over PI trench 114, which may extend over pad oxide layer 118. The sidewalls may also define a cup-like structure surrounding a portion of fill dielectric 420B over PI trench 114. (See below Figure 5A )

[0033] Removing silicon nitride layer 410 in STI region 320 produces STI structure 440 having a step height extending above the outer surface of pad oxide layer 118. Forming STI structure 440 with a minimum step height above the outer surface of pad oxide layer 118 can minimize the risk of the top surface of fill dielectric 420A recessing into trench 430 during subsequent process steps, which can be beneficial to the operation and reliability of device 400.

[0034] Due to the reference Figure 4C In the described example process, the PI structure 426 and the STI structure 440 may each have a respective planar top surface formed by the fill dielectric 420A and the fill dielectric 420B and having the same step height relative to a planar top surface parallel to the pad oxide layer 118 .

[0035] Figure 4D The PI region 310 and the STI region 320 of the microelectronic device 400 are shown after the pad oxide layer 118 is removed (eg, using a plasma etching process). Figure 2 The presence of the silicon nitride layer 410 within the ) can at least partially protect the oxide liner layer 318 from being removed in the same process. Figure 4D As shown in , removal of pad oxide layer 118 may also result in removal of relatively small portions of fill dielectric 420A and fill dielectric 420B, such that the illustrated sidewalls of silicon nitride layer 410 may extend slightly above the planar outer surface of fill dielectric 420B of PI structure 426 .

[0036] In some applications, it may be advantageous to have the remaining portion of the silicon nitride layer 410 fully cover the oxide liner layer 318. For example, when forming the PI region 310, the depicted configuration may facilitate the omission of certain additional process steps (e.g., replacing the removed oxide and subsequently performing reverse LOCOS patterning, etching, etc.). In addition, compared to other process flows that require more than one CMP step, the illustrated configuration may be more convenient to implement. Figures 4A to 4D The exemplary process flow described may be performed by using only a single CMP step (see Figure 4B Description) to provide cost savings and simplification.

[0037] Figure 4E The microelectronic device 400 is shown after additional processing steps for completing the LDMOS transistor 401 are completed. At any suitable point in the processing, the source region 478, the drain region 480, and the back gate region 488 of the LDMOS transistor 401 are formed at respective locations within the substrate 103 so that each has a respective outer surface coplanar with the top surface 104 of the substrate 103. The p-type well region 466, the p-type shallow well region 448, and the drain drift region 438 can be formed in respective portions of the body region 408. An optional p-type buried layer (PBL) 439 can also be formed in the body region 408 using a high energy p-type implant (not specifically shown) to add p-type doping to the epitaxial layer 107. The high energy p-type implant can include a dose of 1×10 12 cm -2 Up to 1×10 13 cm -2 and boron with an energy of 400keV to 3 megaelectronvolts (MeV). Indium may also be used as an implant species. For a low voltage (e.g., 20V) version of the LDMOS transistor 401, the high energy p-type implant may be a blanket implant, while for a higher voltage (e.g., >30V) version of the LDMOS transistor 401, the high energy p-type implant may be a masked implant to allow selective placement. Optionally, an n-type dopant such as arsenic or antimony may also be added to the source side of the LDMOS transistor 401 to form an n-type stay region 468.

[0038] A pre-metal dielectric (PMD) layer 490 is formed over the top surface 104 of the substrate 103, and a contact 492 may be formed through the PMD layer 490. The contact 492 may be formed, for example, by patterning and etching a hole through the PMD layer 490. The contact 492 may be filled by sputtering titanium to form a titanium adhesion layer, followed by forming a titanium nitride diffusion barrier. The tungsten core may then be formed by using tungsten hexafluoride (WF 6 ) process. Tungsten, titanium nitride and titanium are then removed from the top surface of the PMD layer 490 by a plasma etching process, a tungsten CMP process or a combination of the two, thereby leaving a contact 492 extending to the top surface of the PMD layer 490.

[0039] Interconnect 494 may be formed on contact 492. Contact 492 and interconnect 494 may provide electrical contact between LDMOS transistor 401 and other components (e.g., integrated circuits) of microelectronic device 400. In a version of this example where interconnect 494 has an etched aluminum structure, for example, interconnect 494 may be formed by depositing an adhesion layer, an aluminum layer, and an anti-reflective layer, and forming an etching mask (not explicitly shown), followed by a reactive ion etching (RIE) process to etch the anti-reflective layer, the aluminum layer, and the adhesion layer exposed by the etching mask, and then removing the etching mask.

[0040] In a version of this example where the interconnect 494 has a damascene structure, processing may include forming an intermetal dielectric (IMD) layer (not specifically shown) on the PMD layer 490, and etching an interconnect trench through the IMD layer to expose the contact 492. The interconnect trench may be filled with a barrier liner and copper. The copper and barrier liner may then be removed from the top surface of the IMD layer by a copper CMP process.

[0041] The gate polysilicon layer 452 may be formed on the gate dielectric layer 450 and the corresponding portion of the PI structure 426. The polysilicon layer 452 may be used to form a gate electrode 458 having a rear surface in contact with the sidewall 470. The sidewall 470 may be formed, for example, by blanket formation, wherein one or more conformal layers of dielectric material are provided above the substrate 103 and above the gate electrode 458. The dielectric material is then removed from the horizontal surface, i.e., the surface substantially parallel to the top surface 104 of the substrate 103, by an anisotropic etching process such as an RIE process, thereby leaving the dielectric material on the side surface of the gate electrode 458 as the sidewall 470. The sidewall 470 may include a dielectric material, such as silicon dioxide, silicon nitride, or both. The sidewall 470 may extend from the side edge of the gate electrode 458 by 50 nanometers to 200 nanometers.

[0042] In another example, Figures 5A to 5F So Figure 3C 300 shown in FIG. 5 . Figures 4A to 4D The PI region 310 and the STI region 320 are formed in successive stages of the process flow of the thicker silicon nitride hard mask used in the present invention. Figures 5A to 5F In the drawings, like numbers refer to like features previously described.

[0043] refer to Figure 5A, a silicon nitride layer 510 is formed on the oxide layer 118 and the oxide layer 318. The silicon nitride layer 510 has a thickness sufficient to completely fill the PI trench 114 in the PI region 310, wherein the overfill is sufficient to achieve a certain step height for the STI structure to be formed later. (See below Figures 5C to 5F ) The silicon nitride layer 510 at least partially conformally fills the PI trench 114 , thereby forming a protruding trench 515 .

[0044] Figure 5B The PI region 310 and STI region 320 of the microelectronic device 500 are shown after forming STI trenches 530 extending through the silicon nitride layer 510 and the corresponding portions of the pad oxide layer 118 and into the body region 108, and after forming a dielectric layer (not explicitly shown). In order to prepare the underlying surface before forming the dielectric layer, a photomask (not specifically shown) can be formed, which includes a photosensitive organic material that is applied, exposed, and developed. The STI trenches 530 themselves can be formed using one or more etching processes (e.g., plasma etching or dry etching) that selectively remove portions of the silicon nitride layer 510 and the pad oxide layer 118 in the exposed areas of the photomask. Once formed, the STI trenches 530 can then be filled with a dielectric layer.

[0045] A dielectric layer is formed on silicon nitride layer 510, within STI trenches 530, and within raised trenches 515. The dielectric layer is formed with a sufficient thickness to fill raised trenches 515 and STI trenches 530. The dielectric layer may contain any suitable dielectric material, such as HDP oxide.

[0046] The dielectric layer may be partially removed by a planarization process (eg, using non-selective CMP). In a first planarization example, the planarization process may be controlled to form Figure 5B The configuration representatively shown in FIG. 1 ends when the respective fill dielectric 520B and fill dielectric 520A remain within the protruding trench 515 and within the STI trench 530 .

[0047] Optionally and as Figure 5C As shown in , the planarization process can be controlled to remove the filling dielectric 520B while leaving a step height of the filling dielectric 520A above the oxide liner layer 318. Alternatively, the filling dielectric 520B can be removed and the silicon nitride layer 510 can be thinned by using a dry etching process that is non-selective to silicon oxide and silicon nitride. Providing a sufficient step height of the filling dielectric 520A above the top surface of the pad oxide layer 118 can minimize the risk of the top surface of the filling dielectric 520A being recessed into the trench 530 when subjected to subsequent process steps, which may otherwise reduce the performance and / or reliability of the microelectronic device 500.

[0048] Figure 5D The PI region 310 and STI region 320 of the microelectronic device 500 are shown after the silicon nitride layer 510 over the oxide layer 118 is removed using a selective etch back (e.g., wet clean) leaving the fill dielectric 520A and the oxide layers 118 and 318 substantially undisturbed. The selective etch back is configured to allow the nitride-filled portion 525 of the silicon nitride layer 510 to remain within the PI trench 114 of the PI region 310, so that the PI trench 114 remains filled with silicon nitride until a plane coplanar with the top surface 104 of the substrate 103 or the top surface of the pad oxide layer 118.

[0049] Figure 5E The PI region 310 and STI region 320 of the microelectronic device 500 are shown after the pad oxide layer 118 is removed (e.g., using a plasma etching process). Removing the pad oxide layer 118 can form a recessed bowl-shaped LOCOS structure 526 having a top surface that is nearly coplanar with the top surface 104 of the substrate 103. The LOCOS structure 526 includes an oxide liner layer 318 and a nitride fill portion 525. Removing the silicon nitride layer 510 in the STI region 320 leaves an STI structure 540 having a step height extending above the top surface of the pad oxide layer 118. As stated above, forming the STI structure 540 with a minimum step height above the outer surface of the pad oxide layer 118 can provide certain advantages, including minimizing the risk of the fill dielectric 520A being recessed into the trench 530 when subjected to subsequent process steps, which could otherwise degrade the performance of the LDMOS transistor 101.

[0050] Fig. 5F The microelectronic device 500 is shown after additional processing steps for completing the LDMOS transistor 501 have been completed. These additional processing steps may be as described with respect to Figure 4E described, wherein Fig. 5F The same reference numerals in Figure 4E The same features can be formed as previously described.

[0051] Thus, the microelectronic device 500 may be at least partially implemented using the reference Figure 1 , 2 , 3A, 3B or 3C, then refer to Figures 5A to 5F Such a process flow may use a thick STI hard mask for LOCOS nitride fill and also reuse it in the same manner as the hard mask when forming the STI region 320. Among other advantages, this example process flow may provide cost savings and simplification by reducing the number of overall process steps for forming the PI region 310 and the STI region 320 of the LDMOS transistor 101.

[0052] As used herein, “or” is inclusive and not exclusive, unless expressly indicated otherwise or the context indicates otherwise. Thus, as used herein, “A or B” means “A, B, or both,” unless expressly indicated otherwise or the context indicates otherwise. Furthermore, “and” is both conjunctive and individual, unless expressly indicated otherwise or the context indicates otherwise. Thus, as used herein, “A and B” means “A and B jointly or individually,” unless expressly indicated otherwise or the context indicates otherwise. To assist the Patent Office and any reader of any patent issued in this application in interpreting the appended claims, Applicant notes that any appended claims are not intended to invoke 35 U.S.C. §112(f), as it exists on the date of filing this application, unless the phrase “means for” or “step for” is expressly used in the claim language.

[0053] In the foregoing description, for the purpose of explanation, many specific details are set forth to provide a thorough understanding of one or more examples. However, the present disclosure may be practiced without some or all of these specific details, as will be apparent to those skilled in the art. In other cases, well-known process steps or structures have not yet been described in detail to avoid unnecessary confusion of the present disclosure. In addition, although the present disclosure is described in conjunction with illustrative examples, this specification is not intended to limit the present disclosure to the described examples. On the contrary, this specification is intended to cover alternatives, modifications and equivalents that may be included in the spirit and scope of the present disclosure as defined by the appended claims.

[0054] In this description, the term "coupled" may encompass connections, communications, or signal paths that enable a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B through a direct connection; or (b) in a second instance, device A is coupled to device B through an intermediate component C, provided that the intermediate component C does not change the functional relationship between device A and device B, so that device B is controlled by device A via the control signal generated by device A.

[0055] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function when manufactured by a manufacturer, and / or may be configured (or reconfigured) by a user after manufacture to perform the function and / or other additional or alternative functions. Configuration may be performed through firmware and / or software programming of the device, through the construction and / or layout of the device's hardware components and interconnections, or a combination thereof.

[0056] As used herein, the terms "terminal", "node", "interconnect", "pin" and "lead" are used interchangeably. Unless specifically stated otherwise, these terms are generally used to refer to interconnects between device elements, circuit elements, integrated circuits, devices or other electronic devices or semiconductor components or their terminals.

[0057] While certain elements of the described examples may be included in an integrated circuit and other elements may be external to the integrated circuit, in other examples, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features depicted as external to the integrated circuit may be included in the integrated circuit, and / or some features depicted as internal to the integrated circuit may be incorporated external to the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that: (i) are incorporated in / on a semiconductor substrate; (ii) are incorporated in a single semiconductor package; (iii) are incorporated in the same module; and / or (iv) are incorporated in / on the same printed circuit board.

[0058] It should be noted that terms such as top, bottom, over, above, and below may be used in the present disclosure. These terms should not be construed as limiting the position or orientation of structures or elements, but should be used to provide spatial relationships between structures or elements. The terms "lateral" and "laterally" refer to directions parallel to a plane corresponding to a surface of a layer, such as a top surface of a semiconductor substrate.

[0059] In this specification, unless otherwise specified, “about”, “approximately” or “substantially” preceding a parameter means within + / - 10% of the parameter, or if the parameter is zero, within a reasonable value range of about zero.

[0060] Modifications to the examples described are possible and modifications to other examples are possible within the scope of the present disclosure.

Claims

1. A method of forming an integrated circuit, comprising: forming a first trench extending into the semiconductor substrate; Depositing a silicon nitride layer over the semiconductor substrate, the silicon nitride layer extending into the first trench; forming a second trench extending through the silicon nitride layer into the semiconductor substrate, the second trench being spaced apart from the first trench; forming an oxide layer, wherein the oxide layer fills the second trench; and The silicon nitride layer outside the first trench is removed. 2 . The method of claim 1 , wherein the first trench is a power isolation trench, and the second trench is a shallow isolation trench. 3 . The method of claim 1 , wherein forming the first trench comprises forming and removing a LOCOS oxide region extending into the first trench. 4 . The method of claim 1 , wherein forming the silicon nitride layer creates a protruding first trench over the first trench, and the oxide layer fills the protruding first trench. 5 . The method of claim 1 , wherein a top surface of the silicon nitride layer within the first trench is below a top surface of the semiconductor substrate. The method of claim 1 , wherein after removing the silicon nitride layer, a portion of the oxide layer remains over the first trench. 7 . The method of claim 1 , wherein after removing the silicon nitride layer, a portion of the silicon nitride layer remains within the first trench, the silicon nitride layer portion having a top surface that is coplanar with a top surface of the semiconductor substrate. 8 . The method of claim 1 , wherein after removing the silicon nitride layer outside the first trench, a remaining portion of the silicon nitride layer within the first trench extends above a top surface of the semiconductor substrate.

9. The method of claim 1, further comprising polishing the oxide layer, thereby removing the oxide layer over a planar portion of the silicon nitride layer and leaving a remaining portion of the oxide layer over the first trench.

10. The method of claim 9, further comprising non-selectively etching the planar portion of the silicon nitride layer and the remaining portion of the oxide layer, thereby removing the remaining portion of the oxide layer.

11. The method of claim 1, wherein the oxide layer filling the shallow isolation trench is a field release dielectric layer of a transistor.

12. A semiconductor device comprising: A semiconductor layer located above the substrate, the semiconductor layer comprising a body region having a first conductivity type and a drain drift region having a second different conductivity type; a first trench extending into the body region, the first trench at least partially filled with a dielectric material; and A second trench extends into the drain drift region, the second trench being at least partially filled with a silicon nitride layer, the silicon nitride layer extending above a top surface of the drain drift region, the silicon nitride layer forming a protruding trench above the second trench, the protruding trench being at least partially filled with the dielectric material. The semiconductor device according to claim 12 , wherein the second trench is wider than the first trench. 14 . The semiconductor device of claim 12 , wherein an oxide layer is located between the silicon nitride layer and a top surface of the second trench extending into the well region. 15 . The semiconductor device of claim 12 , wherein a portion of the drain drift region has a top surface that is coplanar with a top surface of a portion of the well region. 16 . The semiconductor device of claim 12 , further comprising a gate of the transistor, a portion of the gate being located on the dielectric material filling the protruding trench above the second trench.

17. A semiconductor device comprising: a semiconductor material of a substrate, the semiconductor material comprising a body region having a first conductivity type and a drain drift region having a second conductivity type; a first trench extending into the body region, the first trench at least partially filled with a dielectric material; and A second trench extends into the drain drift region, the second trench being at least partially filled with a silicon nitride layer having a top surface coplanar with a top surface of the drain drift region. 18 . The semiconductor device of claim 17 , wherein the second trench is wider than the first trench, and an oxide layer is located between the silicon nitride layer and a top surface of the second trench extending into a well region. 19 . The semiconductor device of claim 17 , wherein a portion of the drain drift region has a top surface that is coplanar with a top surface of a portion of the well region. 20 . The semiconductor device according to claim 17 , further comprising a gate of the transistor, a portion of the gate being located on the silicon nitride layer above the second trench.

Images