Quad flat no-lead package with enhanced corner pads for board level reliability

Abstract

The invention relates to a quad flat no-lead package with enhanced corner pads for board level reliability. An electronic device (100) includes: a package structure (108) having four lateral corners (113); a semiconductor die (116) at least partially enclosed inside the package structure (108) and attached to a die attachment pad (114); conductive leads (107) at least partially exposed outside the package structure (108) along four lateral sides (103, 104, 105, 106), a first of the conductive leads (107) being electrically connected to the semiconductor die (116); an example of a first conductive feature (109) partially exposed outside the package structure (108) at each of the corners (113); and an instance of a second conductive feature (110) partially exposed outside the package structure (108) at each of the corners (113) and contacting a respective instance of the first conductive feature (109), the instance of the second conductive feature (110) being exposed outside the package structure (108) along the first side (101).

Description

Technical Field

[0001] The present disclosure relates generally to electrical devices, and more particularly, to a quad flat no-lead package with enhanced corner pads for board level reliability. Background Art

[0002] Electronic devices may be packaged in a variety of different package structures, such as a quad flat no-lead (QFN) package with leads along four lateral sides. Board-level reliability (BLR), also known as system-level reliability, may be affected by thermal effects during manufacturing processing, during installation in a host system, and during power-on operation when soldered to a host printed circuit board (PCB). Device BLR may be affected by the materials and structure of the package design as well as PCB thickness and coefficient of thermal expansion (CTE) mismatch between the lead frame and mold compound materials, with the corner pins or leads experiencing the highest thermo-mechanical stresses to interconnect the QFN package to the system PCB. However, many design factors cannot be easily changed, and poor BLR performance is often discovered only after lengthy development times. Summary of the invention

[0003] In one aspect, an electronic device includes: a packaging structure having four lateral corners; a semiconductor die at least partially enclosed within the packaging structure and attached to a die attach pad; conductive leads at least partially exposed outside the packaging structure along four lateral sides, a first of the conductive leads being electrically connected to the semiconductor die; an instance of a first conductive feature partially exposed outside the packaging structure at each of the corners; and an instance of a second conductive feature partially exposed outside the packaging structure along one side at each of the corners and contacting a corresponding instance of the first conductive feature, the instance of the second conductive feature being exposed outside the packaging structure.

[0004] In another aspect, an electronic device includes: a packaging structure having four lateral corners; a semiconductor die at least partially enclosed within the packaging structure and attached to a die attach pad; conductive leads at least partially exposed outside the packaging structure along four lateral sides, a first of the conductive leads being electrically connected to the semiconductor die; an instance of a first conductive feature partially exposed outside the packaging structure at each of the corners; and an instance of a second conductive feature including a conductive film partially exposed outside the packaging structure along the first side at each of the corners.

[0005] In another aspect, a method of manufacturing an electronic device includes: providing a conductive metal lead frame having rows and columns of cell regions, each cell region being bonded to an adjacent cell region having an adjacent row or column, each cell region having a die attach pad and four corner regions including respective instances of a first conductive feature; and attaching a semiconductor die to the die attach pad in each cell region. The method also includes: forming in each cell region an instance of a package structure enclosing the semiconductor die and having opposing first and second sides, four lateral sides, and four lateral corners; forming in each cell region an instance of a second conductive feature partially exposed outside the first side of the package structure at each of the corners; and separating the electronic device from the lead frame. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a top perspective view of a quad flat no-lead (QFN) electronic device with enhanced corner pads according to one aspect.

[0007] Figure 1A yes Figure 1 A bottom plan view of an electronic device.

[0008] Figure 1B It is a display Figure 1 and 1A A top plan view of the internal details of an electronic device.

[0009] Figure 1C is along Figure 1B Partial cross-sectional side view taken along line 1C-1C.

[0010] Figure 2 is a flow chart illustrating a method for manufacturing an electronic device according to another aspect.

[0011] Figures 3 to 10 It is based on experience Figure 2 Embodiments of the method of manufacturing a process Figures 1 to 1C of an electronic device.

[0012] Fig.11 is a top perspective view of another example QFN electronic device with enhanced corner pads according to another aspect.

[0013] Fig.11A yes Fig.11 A bottom plan view of an electronic device.

[0014] Fig. 11B is along Fig.11A A partial cross-sectional side view taken along line 11B-11B.

[0015] Fig. 11Cis a flow chart showing another example method for manufacturing an electronic device according to another aspect.

[0016] Fig.12 is a bottom plan view of another example QFN electronic device with enhanced corner pads according to another aspect.

[0017] Fig. 12A yes Fig.12 A top plan view of an electronic device.

[0018] Fig. 12B is along Fig. 12A A partial cross-sectional side view taken along line 12B-12B.

[0019] Fig. 12C is a flow chart showing another example method for manufacturing an electronic device according to another aspect.

[0020] Fig.13 is a top perspective view of another example QFN electronic device with enhanced corner pads according to another aspect.

[0021] Fig.13A yes Fig.13 A bottom plan view of an electronic device.

[0022] Fig. 13B yes Fig.13 and 13A A top plan view of an electronic device.

[0023] Fig. 13C is along Fig. 13B Partial cross-sectional side view taken along line 13C-13C.

[0024] Fig.13D is a flow chart showing another example method for manufacturing an electronic device according to another aspect.

[0025] Fig.14 is a graph of simulated solder joint damage for different pins of a modeled QFN electronic device.

[0026] Fig.14A is a partial top view of a first modeled QFN electronic device having corner tie bars without corner pads.

[0027] Fig. 14B is a partial top view of a first modeled QFN electronic device having corner tie bars and corner pads formed as part of a single lead frame.

[0028] Fig. 14Cis a partial top view of a first modeled QFN electronic device having corner tie bars formed as part of a first lead frame and enhanced corner pads formed as part of a second lead frame. DETAILED DESCRIPTION

[0029] In the drawings, the same reference numerals refer to the same elements throughout the text, and the various features are not necessarily drawn to scale. In addition, the term "couple" or "couples" includes indirect or direct electrical connections or mechanical connections or combinations thereof. For example, if a first device is coupled to or coupled to a second device, the connection may be by direct electrical connection, or by indirect electrical connection via one or more intervening devices and connections. One or more operating characteristics of various circuits, systems and / or components are described below in the context of functions, which in some cases are generated by the configuration and / or interconnection of various structures when the circuit system is powered on and operated. In the following discussion and claims, the term "including", "includes", "having", "has", "with" or its variations are intended to be inclusive in a manner similar to the term "comprising", and should therefore be interpreted as meaning "including but not limited to".

[0030] Unless otherwise stated, "about," "approximately," or "substantially" preceding a value means + / - 10% of the stated value. One or more operating characteristics of various circuits, systems, and / or components are described below in the context of functionality, which in some cases is caused by the configuration and / or interconnection of various structures when the circuit system is powered on and in operation. For ease of description in conjunction with specific figures, one or more structures, features, aspects, components, etc. may be referred to as first, second, third, etc. in this article, such as first and second terminals, first, second and third wells, etc., which should not be construed as limitations on the claims. The various disclosed methods and devices of the present disclosure can be advantageously applied to drain extension transistors in electronic devices such as integrated circuits. Although such examples can be expected to provide various improvements, the present invention does not require specific results unless explicitly stated in a specific claim.

[0031] First reference Figures 1 to 1C , Figure 1 A top perspective view of a QFN electronic device 100 is shown. Figure 1A and 1B Show the corresponding bottom and top views, and Figure 1C Display along Figure 1B1C-1C of the electronic device 100. The electronic device 100 includes an enhanced corner pad 110 to facilitate improved board and system level reliability. The electronic device 100 is shown in an example position or orientation in a three-dimensional space having a first direction X, a perpendicular (orthogonal) second direction Y, and a third direction Z perpendicular (orthogonal) to the respective first direction X and second direction Y, and structures or features along any two of these directions are orthogonal to each other.

[0032] The electronic device 100 has conductive leads 107 partially exposed along four lateral sides of a package structure 108 (e.g., molded plastic), and the electronic device has opposing first and second (e.g., bottom and top) sides 101 and 102, respectively, spaced apart from each other along a third direction Z, such as Figure 1 and 1C In the illustrated orientation, the package structure 108 and the electronic device 100 have laterally opposing third and fourth sides 103 and 104 spaced apart from each other along a first direction X, and laterally opposing fifth and sixth sides 105 and 106 spaced apart from each other along a second direction Y ( Figures 1 to 1B ). In one example, the sides 101-106 have a substantially planar outer surface. In other examples, one or more of the sides 101-106 have curves, inclined features, or other non-planar surface features.

[0033] like Figures 1 to 1B 1 , the conductive leads 107 are at least partially exposed outside each of the four lateral sides 103-106 of the package structure 108. The lateral sides 103-106 form lateral corners 113 of the package structure 108 and the electronic device 100. The electronic device 100 includes an instance of a first conductive feature 109 that is partially exposed outside the package structure 108 at each of the corners 113. Additionally, the electronic device 100 includes an instance of a second conductive feature 110 that is partially exposed outside the package structure 108 at each of the corners 113. In the illustrated example, individual second conductive features 110 contact corresponding instances of the first conductive features 109. The second conductive features 110 are exposed outside the package structure 108 along the bottom or first side 101.

[0034] An instance of the second conductive feature 110 at each respective corner 113 is spaced apart from a nearest neighbor of the conductive leads 107 by a first spacing distance 111 along each respective lateral side 103-106. Neighbors of the conductive leads 107 are spaced apart from each other by a second spacing distance 112 along each respective lateral side 103-106, and the first spacing distance 111 is less than the second spacing distance 112.

[0035] The electronic device includes a conductive metal die attach pad 114 ( Figure 1A and1B ). In one example, the first conductive feature 109 is a conductive metal tie bar feature that extends outwardly from and abuts the die attach pad 114, but this is not a requirement for all possible implementations. The electronic device also includes a semiconductor die 116 at least partially enclosed within the package structure 108 and attached to the die attach pad 114. Figure 1B , the electronic device includes bond wires 118 that provide various electrical interconnects, including electrical connections between one or more of the conductive leads 107 and the semiconductor die 116. In other implementations, different electrical connection structures (e.g., clips, substrates, etc., not shown) may be used alone or in combination with one or more bond wires 118. In the illustrated example, one or more of the bond wires 118 form an electrical connection between a corresponding one of the conductive leads 107 and a corresponding bond pad or other conductive terminal of the semiconductor die 116.

[0036] The second conductive features 110 at each respective corner 113 promote good BLR performance of the electronic device 100. The second conductive features 110 are not electrically connected to the leads 107 or the semiconductor die 116 in the electronic device 100. In fact, the second conductive features 110 can be soldered to corresponding pads of a host printed circuit board (not shown), but do not need to be electrically connected to any circuitry of the host system.

[0037] In the illustrated example, the second conductive feature 110 is a metal pad at the corner 113 that contacts a portion of the respective tie-bar first conductive feature 109 and extends from the first conductive feature 109 to the bottom or first side 101 of the electronic device 100. An instance of the second conductive feature 110 at each respective corner 113 is exposed outside the package structure 108 along portions of two respective ones of the lateral sides 103-106 at the respective corner 113.

[0038] Compared to dummy leads or other features of a single starting leadframe, the instantiation of the second conductive feature 110 advantageously mitigates the adverse effects of CTE mismatch and has advanced size and spacing advantages. In particular, manufacturing tolerances (e.g., copper etching processes) may limit the spacing distance 112 between adjacent leads 107 during the manufacture of the starting leadframe including features that ultimately form the conductive leads 107, tie bars 109, and die attach pads 114. For example, manufacturing the second conductive feature 110 separately as a metal pad allows for closer spacing (e.g., 112) than the second spacing distance 112 between adjacent conductive leads 107. Figures 1 to 1B This provides the freedom to enlarge the size of the metal pad second conductive feature 110 compared to alternatively introducing a dummy pad or additional dummy lead in the corner 113 of the starting lead frame.

[0039] In the illustrated electronic device 100, for example, since the lower first spacing distance 111 exceeds the possible size of the dummy lead provided in a single starting lead frame, the second conductive feature 110 is enlarged to mitigate thermal impact and enhance BLR performance. In addition, the thickness of the dummy lead or dummy pin structure provided in a single starting lead frame along the third direction Z can be further limited to the thickness of the starting lead frame structure itself, while the second conductive feature 110 can have a different thickness independent of the starting lead frame design. The reliability improvement of the second conductive feature 110 is beneficial to the example leadless wire bonded QFN package structure of the illustrated electronic device 100, and similar benefits can be applied to other forms and shapes of packaged electronic devices. In one example, the size of the additional second conductive feature 110 (e.g., metal pad) is only limited by the surface mounting process requirements (e.g., typically 200μm).

[0040] The location of the second conductive feature 110 at or near the corner 113 operates as a structural anchor to provide the particular advantage of mitigating the effects of thermal expansion and / or contraction on the corner or end leads 107, and reducing the thermo-mechanical stress on the end leads 107 along the lateral sides 103 to 106 and the inner leads 107 when the electronic device 100 is connected to a host PCB. This allows for greater freedom in selecting materials for the package structure 108 (e.g., mold compound) and its conductive metal features (e.g., metals being or including copper, aluminum, etc.), as well as in selecting plating or coating materials along portions of the conductive leads 107 and / or the exposed bottom side of the die attach pad 114 to promote solder wetting, thereby improving solder connection to the PCB.

[0041] In operation, providing the second conductive feature 110 at the corner 113 can help enhance BLR performance without changing other design parameters of the electronic device 100 and without delaying the product design cycle manufacturing implementation. In addition, the corner anchor pad size of the second conductive feature 110 is not limited by the tie bar size of the first conductive feature 109. In particular, the second conductive feature 110 can be changed without affecting the design of the starting lead frame, for example, by using a second lead frame including the second conductive feature 110, as described below in conjunction with Figure 2 In this regard, the second lead frame may be modified according to the BLR performance target without affecting the design of the first lead frame.

[0042] like Figure 1C, in the illustrated example, a first or starting leadframe is used to form a die attach pad 114 having a thickness of approximately 8 mils, wherein a half-etched or thinner feature includes an adjacent tie bar 109 having a thickness of approximately 4 mils in the third direction Z in the illustrated orientation. In this example, the thickness of the second leadframe used to make the second conductive feature 110 is approximately 4 mils, although other thicknesses and ranges may be used in different implementations. In the illustrated example, the added second leadframe may have a nominal thickness of 8 mils or greater, wherein the thicker corner structures of the electronic device 100 may prevent or mitigate wrinkling of large leadframe panel array structures and assist in improving the BLR performance of the finished electronic device 100.

[0043] Reference now Figures 2 to 10 , Figure 2 A method 200 for manufacturing an electronic device using a first lead frame and a second lead frame is shown, and Figures 3 to 10 2 is a diagram of an electronic device 100 undergoing a manufacturing process according to an implementation of method 200. The example implementation of method 200 adds only a single processing step to the package assembly and does not require changes to other package assembly processes. In the illustrated example, the second conductive feature 110 remains in contact with the first conductive feature 109 of its corresponding lead frame during molding and thereafter remains in contacting relationship due to the molded package structure 108. In other implementations, the conductive features may be adhered to each other, such as using rivets (e.g., hereinafter Figures 12 to 12C ).

[0044] Method 200 Figure 2 The process begins at 201 by providing a starting or first lead frame. Figure 3 A portion of an example first lead frame 302 is shown formed into a panel or strip known as a lead frame panel array, where conductive metal features (eg, copper, aluminum, etc.) are formed into rows and columns by a manufacturing process 300 such as stamping, etching, etc. Figure 3 A portion of an example cell region 304 is shown, as well as portions of two adjacent or neighboring columns and portions of an adjacent row in an array configuration. The illustrated example has thick portions and thin portions, for example, thinned by an etching process or other suitable manufacturing step, wherein the conductive metal features in each cell region 304 correspond to the leads 107, tie bars 109, and die attach pads 114 of the finished electronic device 100 described above. Each cell region 304 is joined to an adjacent cell region 304 having an adjacent row or column. In addition, each cell region 304 has a die attach pad 114 and four corner regions 306 including corresponding instances of the first conductive features 109 (e.g., portions of the starting tie bars), wherein the adjacent cell regions are initially joined by conductive connectors, which may be referred to as barrier bars, tie bars, etc.

[0045] Method 200 comprises Figure 2 The die attach process at 202 in FIG. 3 includes attaching a semiconductor die 116 to a die attach pad 114 in each cell region 304 . Figure 4 An example is shown in which a die attach process 400 is performed to attach semiconductor die 116 to die attach pads 114 in each column and row of the lead frame panel array 302. The die attach process 400 may also include attaching other semiconductor die in one or more cell regions of the lead frame panel array 302, such as by dispensing, printing, or otherwise providing solder or a conductive or non-conductive adhesive in selected portions of the top side of certain lead frame features, and placing the semiconductor die and / or passive components in corresponding locations on the solder paste or adhesive (e.g., using automated pick and place equipment, not shown), and subsequent solder reflow and / or curing processes (e.g., thermal reflow, thermal adhesive curing, UV adhesive curing, etc.) for adhering the semiconductor die to the corresponding locations of the lead frame panel array.

[0046] Method 200 continues Figure 2 Wire bonding or other electrical connection processing at 204. Figure 5 An example is shown in which a wire bonding process 500 is performed that produces bonding wires 118 in each unit area 304 for circuit connection of semiconductor die 116 and corresponding ones of leads 107. In another embodiment, additional and / or different bonding wires (not shown) and / or soldering metal clips (not shown) may be produced and / or installed at 204, for example, to provide desired circuit connections in each unit area 304.

[0047] exist Figure 2 At 206 , the second lead frame is secured or otherwise attached to the first lead frame 302 (eg, to the first lead frame). Figure 6 A top view of one example is shown in which a securing process 600 is performed to secure a second lead frame 602 to a first lead frame 302. In the illustrated example, the second lead frame 602 is mounted partially in contact with a backside or bottom side of the first lead frame 302, wherein portions of instances of the second conductive features 110 are in contact with portions of the tie-bar first conductive features 109 in each corner region 306 in each cell region 304 of the first lead frame 302. Fig. 6A Display along Figure 6 A partial cross-sectional side view of the first lead frame 302 and the second lead frame 602 taken along line 6A-6A in the top view of FIG.

[0048] Figure 6BA bottom plan view of a second lead frame 602 is shown having an array configuration with rows and columns of cell areas corresponding to respective cell areas 304 of the first lead frame 302 . Figure 6B and 6C The fastener 604 in the second lead frame 602 is fixed to the first lead frame 302, wherein a portion of the top side of the second conductive feature 110 is expected to contact a portion of the bottom side of the corresponding tie bar first conductive feature 109, as shown in FIG. Figure 1A As shown in .

[0049] Figure 6C Display along Figure 6B A partial cross-sectional side view of the fastener 604 and the edge portion 606 of the second lead frame taken along line 6C-6C. Figure 6C , in this example, the edge portion 606 of the second lead frame 602 is thicker than the inner portion including the intended second conductive feature 110. In addition, in the illustrated example, the fastener 604 includes a hole or port 608 that allows a vacuum connection to apply a holding force (e.g., Figure 6C The second lead frame 602 is connected to the first lead frame 302 by the first conductive feature 109 and the second conductive feature 110, and the second conductive feature 110 is connected to the first lead frame 302 by the second conductive feature 109 and the second conductive feature 110. The second lead frame 602 is connected to the first lead frame 302 by the first conductive feature 110, wherein the second lead frame 602 has an instance of the second conductive feature 110 in contact with each corner region 306 in each unit region 304 of the first lead frame 302, as shown in FIG. Figure 6 As shown in .

[0050] Method 200 Figure 2 The molding process continues at 208 in order to form a molded package structure 108 along the columns and rows of the lead frame panel array 302 and the second lead frame 602 . Figure 7 An example is shown in which a molding process 700 is performed using a mold (not shown). The molded package structure 108 extends over the first conductive features 109 in each cell region 304 and between the first lead frame 302 and the second lead frame 602. The package structure 108 encloses an upper portion of the die attach pad 114 (e.g., as shown above). Figure 1C ), and encloses the semiconductor die 116 and bonding wires 118 in each unit area 304 of the array, as shown in Figure 7 As shown in .

[0051] The method 200 continues at 210 with column-direction package separation. Figure 8An example is shown in which a separation process 800 is performed along lines 802 (e.g., along the second direction Y in the illustrated orientation) to separate adjacent columns of cell regions 304 from each other. In one example, the separation process 800 is a saw blade cutting operation using one or more cutting blades, such as a single cutting blade performing one cut at a time along the corresponding line 802. In another embodiment, laser cutting and / or separation steps can be used alone or in combination with blade cutting to perform single or multiple separations along the line 802.

[0052] exist Figure 2 At 212 , the method 200 includes row-wise separation to separate individual packaged electronic devices 100 from each other along each column in the array. Fig. 9 An example is shown in which a separation process 900 is performed (eg, saw blade cutting, laser cutting, chemical etching, a combination thereof, etc.). The separation process 900 is performed along Fig. 9 The lines 902 shown in separate adjacent rows from each other. Fig.10 The resulting packaged electronic device 100 is shown, in this case a QFN device having conductive leads extending along the cut sidewalls 103-106 produced by the separation processes 800 and 900. The molding and separation processes at 208-212 form an example of a package structure 108 enclosing a semiconductor die 116 and having opposing (e.g., bottom and top) first and second sides 101 and 102, four lateral sides 103-106, and four lateral corners 113 in each cell region 304 of the starting array arrangement, and separates the packaged electronic device from the starting first lead frame 302. In addition, the separation processes at 210 and 212 cut through the molded package structure and conductive features of the first lead frame 302 and the second lead frame 602 in the region between adjacent cell regions 304, which is referred to as the region along the cut sidewalls 103-106. Figure 8 and 9 The sawing streets of corresponding lines 802 and 902 are shown in FIG. 1 , wherein the addition of the second lead frame 602 does not modify or alter the separation process.

[0053] Also refer to Figures 11 to 11C , Figures 11 to 11B Another example QFN electronic device 1100 is shown, and Fig. 11C An example method 1120 for manufacturing an electronic device is shown. Figures 11 to 11B The electronic device 1100 includes the above-mentioned Figures 1 to 1C The structures, features, and dimensions described above correspond to the structures, features, and dimensions 101 to 109 and 111 to 114, and further include a semiconductor die and one or more bonding wires (e.g., 116 and 118 above) that form electrical connections between the semiconductor die and the leads. Figures 11 to 11C10). In this example, the electronic device 1100 includes: a first conductive feature 109 at a corner 113, such as a tie bar extending to and adjacent to a die attach pad 114; and a second conductive feature 1110 to provide an enhanced corner pad structure to promote good board level reliability.

[0054] As described above, an example of the first conductive feature 109 in the electronic device 1100 is partially exposed outside the package structure 108 at each of the corners 113. Figures 11 to 11B In the example electronic device 1100 of , an example of the second conductive feature 1110 includes a conductive film partially exposed outside the package structure 108 along the bottom or first side 101 at each of the corners 113 .

[0055] Fig. 11C Another example method 1120 for manufacturing an electronic device such as the electronic device 1100 is shown. The method 1120 includes providing a first lead frame at 1121, such as the one described above. Figure 3 At 1122, a die attach process is performed, for example, to attach a semiconductor die 116 to a die attach pad 114 (eg, as described above) in each unit region 304 of the starting first lead frame 302. Figure 4 The method 1120 also includes wire bonding or other electrical connection processing at 1124, such as to form bonding wires 118 to interconnect the semiconductor die 116 with one or more of the conductive leads 107 in each unit area 304 of the first lead frame panel array 302 (e.g., the above Figure 5 ).exist Fig. 11C A molding process is performed at 1126 to form a molded package structure (eg, Figure 7 108 in ).

[0056] Fig. 11CThe method 1120 also includes an example of forming a second conductive feature 1110 in a corner region of each unit region of the panel array at 1128. The second conductive feature 1110 is produced at 1128 by forming a conductive film on the bottom or first side 101 of the package structure 108 near the lateral corner 113 in each unit region 304. In one example, the conductive film is formed at 1128 by a coating process (not shown). In another example, a deposition process such as sputtering can be used. In another example, an electroplating process can be used to form the second conductive feature 1110 as a conductive film at 1128. In these examples, the conductive film formation advantageously allows the size and location of the second conductive feature to be unrestricted by the lead frame manufacturing process limitations, for example, to promote good board-level reliability of the finished electronic device 1100. The instances of the second conductive features 1110 at each respective corner 113 in the electronic device 1100 are spaced apart from the nearest neighbor of the conductive leads 107 along each respective lateral side 103-106 by a first spacing distance 111 (eg, Fig.11 and 11A Adjacent ones of the conductive leads 107 are spaced apart from each other by a second spacing distance 112 along each respective lateral side 103 to 106 , and the first spacing distance 111 is smaller than the second spacing distance 112 .

[0057] In one embodiment example, Fig. 11C The molding process at 1126 in provides a generally planar bottom or first side 101 that can be substantially or nearly flush with the bottom of the conductive leads 107 and the exposed bottom side of the die attach pad 114 (e.g., Fig. 11B In this example, the conductive film forming the second conductive feature 1110 may be deposited to any suitable thickness to accommodate good board-level reliability, and the bottom side of the second conductive feature may extend beyond the first side 101 of the electronic device 1100 .

[0058] In another example, the molding at 1126 uses a mold having slightly raised features near the corners of the individual cell areas 304 of the lead frame panel array 302 to produce a molded package structure 108 having slightly concave corners (e.g., not strictly coplanar with the bottom side 101), and Fig. 11C The conductive film at 1128 in the embodiment is formed such that the bottom side of the second conductive feature 1110 is substantially coplanar with the bottom side or first side 101 of the finished electronic device 1100 .

[0059] Fig. 11C The method 1120 in the embodiment continues the column and row separation process at 1130 and 1132, respectively. In one example, the separation process at 1130 and 1132 is the same as described above. Figure 2The processing at 210 and 212 in is the same (for example, Figures 8 to 10 ) to provide Figures 11 to 11B The individual packaged electronic devices 1100 shown in FIG.

[0060] Figures 12 to 12B Another example QFN electronic device 1200 is shown, and Fig. 12C An example method 1220 for manufacturing an electronic device is shown. Figures 12 to 12B The electronic device 1200 includes the above-mentioned Figures 1 to 1C The structures, features and dimensions described above correspond to structures, features and dimensions 101 to 109 and 111 to 114, 116 and 118. In this example, the electronic device 1200 includes: a first conductive feature 109 at a corner 113, such as a tie bar extending to and adjacent to a die attach pad 114; and a metal plate second conductive feature 110, which is used to provide an enhanced corner pad structure to promote good board-level reliability. In one embodiment, the second conductive feature 110 is formed as a metal plate, for example, using a second lead frame installed during the manufacturing process (e.g., before molding, such as after die attach and wire bonding processes).

[0061] in addition, Figures 12 to 12B The electronic device 1200 in FIG. 1 includes one or more rivets 1202 that attach respective instances of the second conductive feature 110 to instances of the first conductive feature 109 proximate each respective corner 113. In the illustrated example, a rivet 1202 is disposed at each corner 113 to provide a secure contact attachment of the second conductive feature 110 to the first conductive feature 109. Fig. 12B Display along Fig. 12A 12B-12B of the electronic device 1200, illustrating the attachment of the metal plate second conductive feature 110 to a portion of the tie bar first conductive feature 109 in the illustrated corner 113 of the electronic device 1200. Fig. 12B and one As shown in the example, the bottom of the rivet 1202 can extend beyond the plane of the bottom or first side 101 of the electronic device 1200, and the riveting process and tools used to form the rivet 1202 can be customized to provide a substantially flat bottom of the rivet 1202, for example, to facilitate soldering the second conductive feature 110 and the rivet 1202 to a conductive pad of a host printed circuit board when desired by an end user.

[0062] As described above, an instance of the first conductive feature 109 in the electronic device 1200 is partially exposed outside the package structure 108 at each of the corners 113. Figures 1 to 1BAs with the dual leadframe example of the present invention, the size and location of the second conductive features 110 are not limited by the leadframe manufacturing process limitations, for example, to promote good board-level reliability of the finished electronic device 1200. The example of the second conductive features 110 at each respective corner 113 in the electronic device 1200 is spaced apart from the nearest neighbor of the conductive leads 107 by a first spacing distance 111 (e.g., Fig.12 and 12A Adjacent ones of the conductive leads 107 are spaced apart from each other by a second spacing distance 112 along each respective lateral side 103 to 106 , and the first spacing distance 111 is smaller than the second spacing distance 112 .

[0063] Fig. 12C Demonstration for making e.g. Figures 12 to 12B Another example method 1210 of an electronic device of the electronic device 1200 in FIG. The method 1210 includes providing a first lead frame at 1201, such as the above-described Figure 3 At 1212, a die attach process is performed, for example, to attach a semiconductor die 116 to a die attach pad 114 (eg, as shown above) in each unit region 304 of the starting first lead frame 302. Figure 4 The method 1210 also includes wire bonding or other electrical connection processing at 1214, such as to form bonding wires 118 to interconnect the semiconductor die 116 with one or more of the conductive leads 107 in each unit area 304 of the first lead frame panel array 302 (e.g., the above Figure 5 ).

[0064] exist Fig. 12C At 1216 in FIG. 1 , a second lead frame is secured or otherwise attached to a first lead frame (e.g., to the first lead frame) using a riveting process and tool (not shown) to provide an example of a second conductive feature 110 attached to a corresponding first conductive feature 109 in each intended corner region by one or more rivets 1202. Attachment by vacuum or other fasteners can provide a contact arrangement of the conductive features 110 and 109 through a molding operation. The use of rivets 1202 at 1216 helps mitigate the risk of lead frame wrinkling, particularly for thin lead frames (e.g., approximately 4 mil thick copper). For example, in various different embodiments, such as during lead frame manufacturing, the riveted attachment of the two lead frames can be performed at any suitable point in the manufacturing process prior to the molding operation, and can be performed prior to the die attach process at 1212 and / or prior to wire bonding at 1214.

[0065] like Fig. 12B, the riveting process at 1216 secures the second conductive feature 110 of the second lead frame in contact with the tie bar first conductive feature 109 of the first lead frame. In the illustrated example, the second lead frame is mounted partially in contact with the back side or bottom side of the first lead frame, with portions of instances of the second conductive feature 110 in contact with a portion of the tie bar first conductive feature 109 in each corner region of each unit region of the first lead frame.

[0066] exist Fig. 12C A molding process is performed at 1218 to form a molded package structure (eg, Figure 7 108 in the method 1210). The method 1210 further includes performing package separation by applying column and row separation processing at 1220 and 1222, respectively. In one example, the separation processing at 1220 and 1222 is the same as described above. Figure 2 The processing at 210 and 212 in is the same (for example, Figures 8 to 10 ) to provide Figures 12 to 12B 1. The individual packaged electronic devices 1200 shown in FIG.

[0067] Figures 13 to 13C Another example QFN electronic device 1300 is shown, and Fig.13D An example method 1320 for manufacturing an electronic device is shown. Figures 13 to 13C The electronic device 1300 includes the above-mentioned Figures 1 to 1C The described structures, features and dimensions correspond to structures, features and dimensions 101 to 109 and 111 to 114 , 116 and 118 . Fig.13 Show a top-down perspective view. Fig.13A Show bottom view, Fig. 13B Show a top view, and Fig. 13C Display along Fig. 13B 13C-13C of the electronic device 1300. In this example, the electronic device 1300 includes: a first conductive feature 109 at the corner 113, such as a tie bar extending to and adjacent to the die attach pad 114; and a second conductive feature 1310, which is at least partially bent from the starting material of the first lead frame to provide an enhanced corner pad structure, thereby promoting good board level reliability.

[0068] As described above, an instance of the first conductive feature 109 in the electronic device 1300 is partially exposed outside the package structure 108 at each of the corners 113. Figures 13 to 13C In the example electronic device 1300 , an example of the second conductive feature 1310 includes a bent or folded portion that is partially exposed outside the package structure 108 along the bottom or first side 101 at each of the corners 113 .

[0069] Fig.13D Demonstration for making e.g. Figures 13 to 13C Another example method 1320 of an electronic device of the electronic device 1300. The method 1320 includes providing a starting lead frame at 1321, such as the one described above. Figure 3 At 1322, a die attach process is performed, for example, to attach a semiconductor die 116 to a die attach pad 114 (eg, as described above) in each unit region 304 of the starting first lead frame 302. Figure 4 The method 1320 also includes wire bonding or other electrical connection processing at 1324, such as to form bonding wires 118 to interconnect the semiconductor die 116 with one or more of the conductive leads 107 in each unit area 304 of the starting lead frame 302 (e.g., the above Figure 5 ).

[0070] exist Fig.13D At 1326 in the method 1320, the method 1320 further includes partial barrier bar metal trimming, such as using a punch or other suitable cutting or trimming equipment (not shown) to trim or otherwise remove barrier bar segments that intersect the row and column direction saw cuts between adjacent cell regions of the lead frame panel array 302. This operation leaves remaining barrier bar material and connected tie bars 109, thereby allowing subsequent forming operations.

[0071] In this example, method 1320 continues at 1328 to form the remaining barrier bar metal in the corners between the cell regions of lead frame panel array 302. In one example, the forming operation at 1328 includes bending and / or folding, such as using a suitable forming die and fasteners (not shown) that fold the separated barrier bar material under the channel portion of the tie bar first conductive feature 109, such as Fig. 13C1328 . In this example, the instances of the first conductive feature 109 and the second conductive feature 1310 at each respective corner 113 are contiguous, and a portion of the instance of the second conductive feature 1310 is folded under a portion of the instance of the first conductive feature 109 at each respective corner 113. In this example, the folded or underlying portion 1310 forms a second conductive feature that contacts the first conductive feature 109 at each corner 113 of the electronic device 1300, and in one example, the bottom side of the folded second conductive feature 1310 extends substantially coplanar with the bottom or first side 101 of the electronic device 1310, but coplanarity is not a strict requirement for all possible implementations. In another implementation (not shown), the formation process at 1328 partially folds or bends some of the starting metal to form the second conductive feature 1310, which remains contiguous with the first conductive feature 109, but does not need to be completely folded to contact the bottom side of the first conductive feature 109.

[0072] Method 1320 Fig.13D At 1330 in the process, a molded package structure (eg, Figure 7 108) molding process. Fig.13D The method 1320 in the embodiment continues the column and row separation process at 1332 and 1334, respectively. In one example, the separation process at 1332 and 1334 is the same as described above. Figure 2 The processing at 210 and 212 in is the same (for example, Figures 8 to 10 ) to provide Figures 13 to 13C 13. After partial trimming at 1326, the barrier bar portion may be folded at 1328 to form a corner pad (either bottom pad or sidewall pad) in the finished device. Unlike the above examples, the corner pad size depends on the tie bar size and is not completely independent of the manufacturing process used to manufacture the initial starting lead frame 302.

[0073] Also refer to Figures 14 to 14C , Fig.14 A graph 1400 is shown having solder joint damage number curves 1401 , 1402 , and 1403 showing comparative simulated solder joint damages for different pins of different modeled QFN electronic devices. Fig.14A The lower right quadrant of a first modeled QFN electronic device 1410 is shown having tie bars 109 extending to corner 113, without anchoring structures such as dummy pads of the initial starting lead frame, and without additional second conductive features providing anchoring structures in the device corners. Fig.14Curve 1401 in shows relatively high solder joint damage for this simulated implementation, particularly for the pins (eg, pin number 1, pin number 8, etc.).

[0074] Fig. 14B A similar quadrant is shown for a second modeled QFN electronic device 1420 having tie bars 109 extending to corners 113, and integrated dummy pads 1421 formed as part of the starting leadframe. Fig.14 The curve 1402 in corresponds to Fig. 14B The number of simulated solder joint failures of the model of the electronic device 1420 is shown in FIG. Fig.14A Adding dummy pad structure 1421 as part of tie bar 109 near corner 113 helps reduce the number of solder joint failures compared to the simulated number of solder joint failures for QFN device model 1410. However, as previously discussed, this approach is limited by manufacturing tolerances and process limitations associated with manufacturing the starting lead frame.

[0075] Fig. 14C Display and above Figures 1 to 1C In a comparative quadrant of a modeled QFN electronic device 1430 corresponding to the electronic device 100, a second lead frame is used during manufacturing to produce a second conductive feature 1431, which is initially formed as part of the second lead frame and is in contact with a portion of the overlying tie bar first conductive metal structure 109. Fig.14 Curve 1403 in graph 1400 shows Fig. 14C The simulated solder joint damage count results for the modeled electronic device 1430 provide a significant reduction in solder joint damage caused by thermal and / or mechanical stress of the corresponding electronic device compared to the results shown in curves 1401 and 1402.

[0076] Figures 14 to 14C The simulation and modeling of corresponds to a 64-pin QFN package design with dimensions of approximately 9×9×0.9 mm and a spacing of 0.5 mm between adjacent leads along a given one of the lateral sides, using a die size of approximately 6×6 mm. The simulation conditions included solder attachment to a 1.6 mm thick host printed circuit board (not shown), thermal cycling from -40°C to +125°C, with each cycle using 60 minutes, and the indicated pin number 17 in the graph 1400 corresponds to the device thermal pad, such as Figures 1 to 1C 14. The number of simulated solder joint damages represented by curves 1401 to 1403 represents a number indicating a higher risk of solder joint cracking and earlier board level reliability degradation. In addition to significantly reducing end or corner pin (lead) solder joint damages, the second conductive feature of the illustrated example also provides benefits for the internal or non-end / corner conductive leads of the electronic device 100.

[0077] Modifications are possible in the described examples and other implementations are possible within the scope of the claims.

Claims

1. An electronic device, comprising: a package structure having opposing first and second sides, four lateral sides, and four lateral corners; a semiconductor die at least partially enclosed within the package structure and attached to a die attach pad; conductive leads at least partially exposed outside the package structure along the four lateral sides, a first one of the conductive leads being electrically connected to the semiconductor die; an instance of a first conductive feature that is partially exposed outside of the package structure at each of the corners; and An instance of a second conductive feature is partially exposed outside the package structure along the first side at each of the corners and contacts a respective instance of the first conductive feature. 2 . The electronic device of claim 1 , wherein the instance of the second conductive feature at each respective corner is exposed outside the package structure along portions of two respective ones of the lateral sides at the respective corners.

3. The electronic device according to claim 2, wherein: the instance of the second conductive feature at each respective corner being spaced apart from a nearest one of the conductive leads by a first spacing distance along each respective lateral side; Adjacent ones of the conductive leads are spaced apart from each other by a second spacing distance along each respective lateral side; and The first spacing distance is smaller than the second spacing distance.

4. The electronic device according to claim 1, wherein: the instance of the second conductive feature at each respective corner being spaced apart from a nearest one of the conductive leads by a first spacing distance along each respective lateral side; Adjacent ones of the conductive leads are spaced apart from each other by a second spacing distance along each respective lateral side; and The first spacing distance is smaller than the second spacing distance.

5. The electronic device of claim 1, wherein the instance of the first conductive feature at each respective corner abuts the die attach pad.

6. The electronic device of claim 5, wherein the instance of the second conductive feature at each respective corner is a metal pad.

7. The electronic device of claim 6, comprising a rivet attaching the instance of the second conductive feature to the instance of the first conductive feature proximate each respective corner.

8. The electronic device of claim 5, comprising a rivet attaching the instance of the second conductive feature to the instance of the first conductive feature proximate each respective corner.

9. The electronic device according to claim 5, wherein: The instances of the first conductive feature and the second conductive feature at each respective corner are contiguous; and A portion of the instance of the second conductive feature is folded under a portion of the instance of the first conductive feature at each respective corner.

10. The electronic device according to claim 1, wherein: the instance of the second conductive feature at each respective corner being spaced apart from a nearest one of the conductive leads by a first spacing distance along each respective lateral side; Adjacent ones of the conductive leads are spaced apart from each other by a second spacing distance along each respective lateral side; and The first spacing distance is smaller than the second spacing distance.

11. The electronic device of claim 1 comprising a rivet attaching the instance of the second conductive feature to the instance of the first conductive feature proximate each respective corner.

12. The electronic device according to claim 1, wherein: The instances of the first conductive feature and the second conductive feature at each respective corner are contiguous; and A portion of the instance of the second conductive feature is folded under a portion of the instance of the first conductive feature at each respective corner.

13. An electronic device comprising: a package structure having opposing first and second sides, four lateral sides, and four lateral corners; a semiconductor die at least partially enclosed within the package structure and attached to a die attach pad; conductive leads at least partially exposed outside the package structure along the four lateral sides, a first one of the conductive leads being electrically connected to the semiconductor die; an instance of a first conductive feature that is partially exposed outside of the package structure at each of the corners; and An example of a second conductive feature includes a conductive film partially exposed outside the package structure along the first side at each of the corners.

14. The electronic device of claim 13, wherein the instance of the second conductive feature at each respective corner is exposed outside the package structure along portions of two respective ones of the lateral sides at the respective corners.

15. The electronic device according to claim 13, wherein: the instance of the second conductive feature at each respective corner being spaced apart from a nearest one of the conductive leads by a first spacing distance along each respective lateral side; Adjacent ones of the conductive leads are spaced apart from each other by a second spacing distance along each respective lateral side; and The first spacing distance is smaller than the second spacing distance.

16. The electronic device of claim 13, wherein the instance of the first conductive feature at each respective corner abuts the die attach pad.

17. A method of manufacturing an electronic device, the method comprising: providing a conductive metal lead frame having rows and columns of cell regions, each cell region bonded to an adjacent cell region having an adjacent row or column, each cell region having a die attach pad and four corner regions including respective instances of a first conductive feature; attaching a semiconductor die to the die attach pads in each cell area; forming in each cell region an instance of a package structure enclosing the semiconductor die and having opposing first and second sides, four lateral sides, and four lateral corners; an instance of a second conductive feature formed in each cell region at each of the corners partially exposed outside the first side of the package structure; and The electronic device is separated from the lead frame.

18. The method of claim 17, wherein: The conductive metal lead frame is a first lead frame; and The instance of forming the second conductive feature includes fixing a second lead frame to the first lead frame, the second lead frame having an instance of the second conductive feature contacting each corner region in each unit region of the first lead frame.

19. The method of claim 17, wherein the instance of forming the second conductive feature includes forming a conductive film on the first side of the package structure proximate the lateral corner in each cell region.

20. The method of claim 17, wherein forming the instances of the second conductive feature comprises bending a portion of the lead frame under each respective instance of a first conductive feature.

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