Packaged semiconductor device and method of making same

Abstract

The invention relates to a packaged semiconductor device and a manufacturing method thereof. Disclosed is a packaged semiconductor device having a first main package surface and a second main package surface and comprising: a packaged die having a plurality of die contact pads on a first main die surface; a molding compound; and a plurality of exposed pads, each exposed pad including a flattened lower surface of the wedge-shaped bonding wire; wherein the plurality of exposed pads surround a peripheral region of the second main package surface and are spaced apart by the molding compound; and wherein the plurality of pads are electrically connected to the contact pads through at least one set of bonding wires. A corresponding method is also disclosed.

Description

Technical Field

[0001] The present disclosure relates to integrated circuit (IC) packaging. More particularly, the present disclosure relates to packaged semiconductor devices and methods of making the same. Background Art

[0002] As the electronics industry develops, semiconductor devices are moving toward higher power, higher voltage, and higher current.

[0003] Packages such as Enhanced Small Outline Integrated Circuit (ESOIC) packages and Power Quad Flat No-Lead (PQFN) packages are usually suitable for very high currents. However, to accommodate high currents and high powers, heavy aluminum wires are usually used for such packages, and the leadframes of the packages are usually expensive: the leadframe can account for 50-60% of the package material cost. Reducing the cost of such packages has become a big challenge. Summary of the invention

[0004] According to a first aspect of the present disclosure, a packaged semiconductor device is provided, the packaged semiconductor device having a first main package surface and a second main package surface and comprising: an encapsulated die having a plurality of die contact pads on its first main die surface; a molding compound; and a plurality of exposed pads, each of which comprises a flattened lower surface of a wedge-bonded short column; wherein the plurality of exposed pads surround a peripheral region of the second main package surface and are spaced apart by the molding compound; and wherein the plurality of pads are electrically connected to the contact pads by at least one set of bonding wires. Therefore, the package does not require the use of a lead frame. Specifically, the die contact pad is not part of the lead frame. Alternatively, the die contact pad is formed by flattening the wire during a wedge bonding process: the wedge bond produced by the wedge bonding process includes a section of flattened wire that forms a bond with the substrate after the wedge bonding process. This flattened lower surface can be exposed by performing a wedge bond in place and then removing the substrate. The flattened lower surface can then serve as a contact pad or bonding pad in the package.

[0005] In one or more embodiments, the package further comprises an exposed area of ​​conductive material, the exposed area being in a central region of the second main package surface, electrically connected to the second die main surface, and spaced apart from the exposed pad by the molding compound. The conductive material may be epoxy resin.

[0006] In one or more embodiments, at least one group of bonding wires includes a first group of bonding wires, each of which is bonded to a corresponding contact pad at a first end, and each of which includes a wedge bonding stub at a corresponding second end. Thus, the wedge bonding stub can be "independent" in the sense that a separate electrical connection of the bonding wire to the tube core is required, or can be "integral" with the wire bonding electrical connection to the tube core and form one end of such electrical connection. Each bonding wire in the first group of bonding wires can include or consist of a wedge bonding wire. This can reduce process complexity relative to embodiments in which different wires are used because a separate wire bonding process may not be required.

[0007] In one or more embodiments, either or both of the first set of bond wires and the wedge bond wires may include aluminum wires. Aluminum wires may be relatively cheap, relatively ductile, and / or may provide relatively high current density.

[0008] In one or more embodiments, the at least one group of bonding wires includes a second group of bonding wires, wherein each bonding wire is bonded between a corresponding one of the plurality of contact pads and a corresponding opposing surface of one of the exposed contact pads. Such bonding wires can be bonded to the opposing surfaces by known techniques (e.g., ball-bonding) and can be thinner than wedge-shaped bonding wires. This can reduce the bill of materials and, relative to embodiments in which the bonding wires all include wedge-shaped bonding wires, can additionally allow for a relatively high "pin-out" or packing density and therefore a larger number of electrical connections.

[0009] In one or more embodiments, the package further includes at least one of flux or plating on the bottom surface of the exposed pads. Coating the exposed pads with flux or plating can facilitate electrical connection to, for example, a circuit board on which the package is to be mounted.

[0010] In one or more embodiments, the length of each exposed pad is in the range between 0.3 and 0.8 mm, and the width of each exposed pad is in the range between 0.2 and 0.4 mm. In one or more embodiments, the diameter of each aluminum wire is in the range between 0.1 and 0.5 mm. Such dimensions are suitable for the size of available production equipment and typical packaging devices. However, the present disclosure is not limited thereto.

[0011] According to a second aspect of the present disclosure, there is provided a method for manufacturing a packaged semiconductor device having a first main package surface and a second main package surface, the method comprising: providing a semiconductor die having a plurality of die contact pads on a first main die surface of the semiconductor die; bonding the second main die surface of the semiconductor die to a substrate; providing a plurality of pads by forming a wedge bond on the substrate, each pad being formed by a flattened lower surface of a wedge bond stub surrounding and away from the semiconductor die; forming at least one set of electrical connections between the plurality of pads and the contact pads by a first set of bonding wires; encapsulating the semiconductor die and the wedge bond stub; and removing the substrate, thereby exposing the pads on the second main package surface. The wedge bond may be formed directly on the substrate. Thus, the need to use a lead frame during assembly may be avoided.

[0012] In one or more embodiments, the step of bonding the second main die surface of the semiconductor die to the substrate includes bonding the second main die surface of the semiconductor die to the substrate through a conductive epoxy material, and the step of removing the substrate includes exposing the conductive epoxy material on the second main package surface. Using a conductive material such as a conductive epoxy material can be convenient because such conductive materials are commonly used in the semiconductor industry to bond semiconductor dies to lead frames. Subsequent removal of the substrate to expose the conductive material such as a conductive epoxy material can allow a direct low resistance electrical connection to the second surface of the die.

[0013] In one or more embodiments, forming at least one set of electrical connections between the plurality of bonding pads and the contact pads includes forming a plurality of wire bonds between corresponding contact pads among the plurality of contact pads and corresponding wedge bond stubs at relatively flattened surfaces of the bonding pads. The wire bonds between the semiconductor die and the wedge bond stubs acting as contacts to the outside of the package can facilitate providing a low resistance electrical connection to the die from the outside of the package.

[0014] In one or more embodiments, forming at least one set of electrical connections includes forming a plurality of wedge bonds starting from a wedge bond stub between corresponding contact pads in a plurality of contact pads, and each wedge bond includes the wedge bond stub at a corresponding second end. In such embodiments, the wire used to form the wedge bond stub that acts as a solder pad can be directly connected to the semiconductor die. In one or more embodiments, each of the second set of bonding wires includes a wedge bond stub. Since the diameter of the wire typically used for the solder pad is larger than the diameter of the wire that can be used for other wire bonds, using this wire to provide all electrical connections to the die within the package can provide particularly low resistance electrical connections, such as those suitable for high power devices.

[0015] In one or more embodiments, the second set of bonding wires includes aluminum wires. In addition, the wedge bonding stubs may include aluminum wires. Aluminum may be a suitable material that provides a good compromise between hardness, conductivity, and cost. However, the present disclosure is not limited thereto.

[0016] In one or more embodiments, the method further includes providing at least one of a flux or a plating layer on the bottom surface of the exposed pad.

[0017] In one or more embodiments, the length of each exposed pad is in the range between 0.3 and 0.8 mm, and the width of each exposed pad is in the range between 0.2 and 0.4 mm. In addition, the diameter of each aluminum wire may be in the range between 0.1 and 0.5 mm.

[0018] These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Embodiments will be described, by way of example only, with reference to the accompanying drawings, in which

[0020] Figure 1 A wedge joint, which may also be referred to as an ultrasonic wedge joint, is shown;

[0021] Figure 2 A process for producing a wedge bond stud or a wedge bond line is pictorially illustrated;

[0022] Figure 3A is a plan view and cross section of a substrate on a carrier producing a subassembly;

[0023] Figure 3B is a cross-sectional view of a substrate on a carrier;

[0024] Figure 4A illustrates a plan view of a partially assembled semiconductor package according to one or more embodiments of the present disclosure;

[0025] Figure 4B illustrates a cross-section of a partially assembled semiconductor package according to one or more embodiments of the present disclosure;

[0026] Figure 5A illustrates a plan view of a partially assembled semiconductor package at a later stage of assembly according to one or more embodiments of the present disclosure;

[0027] Figure 5B illustrates a cross-section of a partially assembled semiconductor package at a later stage of assembly according to one or more embodiments of the present disclosure;

[0028] Fig. 6Aillustrates a plan view of a partially assembled semiconductor package at a still later stage of assembly according to one or more embodiments of the present disclosure;

[0029] Figure 6B illustrates a cross-section of a partially assembled semiconductor package at a still later stage of assembly according to one or more embodiments of the present disclosure;

[0030] Figure 7 illustrates a cross-section of a partially assembled semiconductor package at a still later stage of assembly according to one or more embodiments of the present disclosure;

[0031] Figure 8 illustrates a cross-section of a partially assembled semiconductor package at a still later stage of assembly according to one or more embodiments of the present disclosure;

[0032] Fig. 9 illustrates a cross-section of a partially assembled semiconductor package at a still later stage of assembly according to one or more embodiments of the present disclosure;

[0033] Fig.10 illustrates a cross-sectional plan view of a packaged semiconductor device according to one or more embodiments;

[0034] Fig.11 A view showing a second main surface of a packaged semiconductor device according to one or more embodiments; and

[0035] Fig.12 A flow chart illustrating a method according to one or more embodiments of the present disclosure.

[0036] It should be noted that the figures are diagrammatic and not drawn to scale. For clarity and convenience in the figures, the relative sizes and proportions of the parts of these figures have been shown by being enlarged or reduced in size. The same reference numerals are generally used to refer to corresponding or similar features in modified and different embodiments. DETAILED DESCRIPTION

[0037] Detailed description embodiments of the present invention are disclosed herein. However, for the purpose of describing the exemplary embodiments of the present invention, the specific structural and functional details disclosed herein are merely representative. The present invention may be embodied in many alternative forms and should not be construed as being limited to the embodiments set forth herein. In addition, the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the exemplary embodiments of the present invention.

[0038] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the terms "comprises, comprising, includes and / or including" specify the presence of stated features, steps or components, but do not exclude the presence or addition of one or more other features, steps or components. It should also be noted that in some alternative embodiments, the functions / actions indicated may not occur in the order indicated in the figures. For example, depending on the functions / actions involved, two figures shown in succession may actually be executed substantially simultaneously, or may sometimes be executed in reverse order.

[0039] Reference Figure 1 , which shows a wedge bonder 100 that may also be referred to as an ultrasonic wedge bonder. As is familiar to the skilled person, during the wedge bonding process, pressure is applied to the wire material, typically while ultrasonic vibrations (frequency range generally between 40 and 125 kHz) are applied. Due to the application of pressure, as shown, a wire 110 having a starting diameter D is deformed over a length L near a wire tail 112 having a length T. The deformed section of the wire has a flattened lower surface 120. Due to the friction induced by the ultrasonic vibrations, this lower surface is heated and begins to bond to the substrate material. The precise bonding mechanism, for example, whether the bond is solid or there is local melting of the material, depends on the combination of the wire and the substrate and is not relevant to the scope of the present disclosure. However, the inventors have realized that this flattened lower surface of the wedge bond stub can be used in a packaged semiconductor device instead of a contact pad typically provided by a lead frame. Therefore, it is possible to provide a packaged semiconductor device without using a contact pad from a lead frame or even without a lead frame at all.

[0040] As will be described in more detail below, in one or more embodiments, the wedge bond wires may extend beyond the wedge bond stub itself and serve as some or all of the bond wires to the semiconductor chip embedded in the package. In other embodiments, the wedge bond wires are not used as bond wires to the semiconductor die. In fact, the wedge bond stubs are only used as contact pads for the package. In such embodiments, it is necessary to provide such wedge bond stubs that have only a short wire tail at one end and a short wire post 114 at the other end. Such independent wedge bonds may be referred to as "wedge bond stubs", "wedge bond wire stubs" or "independent wedge bonds" or simply "wire wedge bonds". Figure 2The process for producing such a wedge-joined short column is illustrated. At step (i), the bonding tool 202 is lowered to apply pressure to the exposed portion 204 of the wire 110, such as an aluminum wire, fed by the tool. At this stage, the wire is not clamped to the tool. The wire is thus flattened, thereby presenting a short flattened tail 206, and ultrasonic vibration is applied to perform the bonding of the exposed flattened wire to the substrate 230. The wire is then lifted, as shown at (ii), and the wire is clamped to the tool by a fixture 208 as shown. Then, the tool is moved laterally so that the wire is extended and broken at the breakpoint 116 where the wire has been subjected to the stress of the wedge-joined process. An independent wedge-joined piece joined to the substrate is obtained. This structure can be identifiable and is referred to as a "wedge-joined short column". The lower surface of the structure can be referred to as a "flattened wedge-joined wire". The structural features of this component may be readily identifiable, and thus the term "flattened wedge bond line" may be used to refer to the structure itself rather than to the process used to form the structure.

[0041] Figure 3A and Figure 3B A plan view and a cross section of a substrate 230 producing a subassembly on a carrier 310 are shown respectively. The substrate 230 may be bonded to the carrier 310 by means of glue or other adhesives. In one or more embodiments, the substrate 230 may be fixed to the carrier 310 using UV tape. The substrate 230 may be made of a suitable metal such as copper, gold, silver, tin or other metals or alloys including at least one of these metals, as long as the metal can be welded or bonded to a wedge-shaped bonding short column, which is usually aluminum. This will be discussed in more detail below. The carrier 310 may be made of stainless steel, copper and other suitable materials. The thickness of the substrate 230 may be 0.01-0.05 mm. The upper and lower ends of the substrate 230 or the carrier 310 may be provided with reference marks or reference marks 320 to assist in positioning and placing components during the entire assembly process. Reference marks may be used to indicate distances. The reference marks 320 may therefore be used for position alignment, package separation and etching processes of components (including dies, bonding pads, etc.). The size, position, shape, etc. of the reference mark 320 can be determined according to the requirements of different die sizes and package sizes. The reference mark can be a cross, square, triangle, star, or other suitable shapes.

[0042] Figure 4A and Figure 4BA plan view and a cross-section, respectively, of a partially assembled semiconductor package according to one or more embodiments are shown. A semiconductor die 410 is shown bonded to a substrate 230 by means of a conductive material 420. The conductive material 420 may be, for example, a conductive epoxy or a die attach film (DAF). The semiconductor die 410 includes a plurality of die contact pads 430 on a first major surface thereof, which may be a top surface as shown. The die contact pads 430 may be of uniform size and shape, or include a subset of larger or differently sized pads, shown as 435 in the figure.

[0043] although Figure 4A and Figure 4B A single semiconductor die 410 is shown bonded to substrate 230, but the skilled person will appreciate that multiple dies may be bonded to a substrate of appropriate size. Through such a mechanism, multiple dies may be packaged together in the same package, or at least a portion of the package assembly process may be performed on multiple packages simultaneously. Thus, embodiments of the present disclosure are at least partially compatible with so-called wafer scale packaging.

[0044] Figure 5A and Figure 5B A plan view and a cross-section, respectively, of a partially assembled semiconductor package according to one or more embodiments are shown. As shown, a plurality of individual wedge bond sites 510 or flattened wedge bonds have been formed on substrate 230. These wedge bonds are around a peripheral region of the final package, which may be defined by fiducial marks as shown. The lower surfaces of the wedge bonds, that is, the flattened wedge bonds, are generally planar and bonded to substrate 230. As will be described in more detail below, these lower surfaces will form solder pads for the final packaged device. As shown from Figure 2 It is obvious in Figure 5A As shown in , the overall shape of the flattened wedge bond wire is roughly an elongated oval, and can equally be viewed as a rectangle with rounded corners. The exact shape will depend on the length of the wedge tool relative to the diameter of the wire, and the degree to which the wire deforms during the wedge bonding process. Typically, the wedge bond wire 510 is aluminum, and the diameter of the aluminum wire can be 0.1-0.5 mm. The length of each first wedge bond 510 can be typically 0.3-0.8 mm, and the width can be 0.2-0.4 mm.

[0045] Also in Figure 5A and Figure 5BOther wedge bonding sites 520 are shown in . These wedge bonding sites 520 do not form independent wedge bonds, but are formed at one end of a wire or bonding wire 530 that provides electrical connection to the semiconductor die, the other end of the wire being bonded by conventional means, typically by a wedge bond at a wedge bond 540, because ball bonding is not feasible for thicker wires: as the skilled person will appreciate, forming a free air ball (FAB) is not feasible for wires thicker than about 100 μm. These wedge bonds are manufactured to a subset of the semiconductor die contact pads 435. It should be understood that the use of wires including wedge bonds connected to the substrate will generally involve larger diameter wires than typical wires used for wire bonding between semiconductor dies and contact pads that include portions of the lead frame. The electrical connection provided by such bonding wires 530 may be particularly suitable for high power and especially high current devices. In one or more embodiments, all electrical connections to the semiconductor die 410 are provided by wedge bond wires 530. In such embodiments, any separate wedge bond wires 510 may not be required.

[0046] Fig. 6A and Figure 6B A plan view and a cross section of a partially assembled semiconductor package during a later stage of assembly are shown, respectively, according to one or more embodiments. The first wedge bond 510 is electrically connected to the die on the semiconductor die by means of a set of bonding wires 630. Individual bonding wires of these bonding wires connect individual die contact pads 430 to the top surface of the corresponding independent wedge bond short column 510. At this stage of assembly, this top surface is exposed; however, as will become clearer below, in the completed package, this top surface is encapsulated, and the bottom surface of the wedge bond short column that has been flattened in the process of forming the wedge bond connected to the substrate will be exposed. Therefore, when considered from the perspective of the final device, the bonding wire 630 is bonded to the opposite surface of an exposed contact pad. In general, the bonding wire may have a different material from the wedge bonding wire. In addition, since the bonding wire may generally but not exclusively carry signals rather than high power, the diameter of the bonding wire may be smaller than the diameter of the wedge bonding wire. Typically, the bonding wire may have a diameter ranging between 25 and 33 μm. The bond wires may be bonded to the wedge bond stubs by known techniques such as ball bonding or wedge bonding. Ball bonding is the preferred technique because ball bonding is substantially faster than wedge bonding. In addition, a first bond is typically made to the die contact pads using a FAB and a second bond is made to a separate wedge bond wire. The bond wires 630 may be made of any suitable material, which may include copper, gold, silver, tin, or other metals or alloys including at least one of these metals.

[0047] Embodiments of the present disclosure, for example Fig. 6A and Figure 6BAn embodiment of the partial process schematically illustrated in can advantageously be capable of providing high power electrical connections to a semiconductor die via relatively large diameter and low resistivity bond wires integral with wedge bonds while providing a relatively large number of electrical connections using relatively small diameter bond wires 630.

[0048] Figure 7 7 shows a cross section of a partially assembled semiconductor package during a later stage of assembly according to one or more embodiments. An encapsulant or molding compound 710 is introduced over the entire device to provide strength and environmental protection. Figure 7 As shown in , the molding compound 710 may be provided on a single device, and in particular, the final package may include only a single semiconductor die. However, the skilled person will appreciate that in other embodiments, multiple semiconductor dies may be included in a single package, and in such embodiments, the encapsulant or molding compound 710 may be provided across multiple dies, ultimately resulting in a single package. In yet other embodiments, multiple dies may be bonded to a single substrate and carrier subassembly combination to provide multiple packages assembled on a carrier.

[0049] Figure 8 A cross section of a partially assembled semiconductor package according to one or more embodiments during a still later stage of assembly is shown. As can be seen from the figure, the carrier 310 has been removed. As described above, the substrate 230 can be relatively thin, and in the case of a metal foil, the substrate can typically have a thickness of between 0.01 mm and 0.05 mm. It should be understood that the substrate is not sufficiently stable to support the die, but since the die is now encapsulated in the molding compound 710, the assembly has sufficient strength and rigidity so that the carrier 310 is no longer required. As also discussed above, the substrate 230 can be bonded to the carrier 310 by means of a UV adhesive or the like. Separation of the substrate from the carrier can then be performed, for example, by exposure to UV light to thereby soften the adhesive. Other suitable means can be used to bond the substrate to the carrier and subsequently remove the carrier.

[0050] Fig. 9 2 shows a cross-section of a partially assembled semiconductor package according to one or more embodiments during a still later stage of assembly. As can be seen from the figure, the substrate 230 has been removed. This results in a packaged semiconductor device according to one or more embodiments of the present disclosure. Fig. 9In the device shown in , the conductive material or conductive epoxy 420 is exposed at the first main surface of the package, which can be the bottom surface. A plurality of pads 515 including the exposed surfaces of the wedge bonding members 510 and 520 are spaced apart from the first main surface and spaced apart from the first main surface by the molding compound. The wedge bonding stub 510 is an independent stub of the wedge bonding wire, which is encapsulated by the molding compound 710. The stub is electrically connected to the die contact pad by a corresponding bonding wire in a set of bonding wires 630, which are generally formed by wires thinner than the wedge bonding member. Although the present disclosure is not limited to this, the use of thinner wires facilitates bonding to the wedge bonding member. The wedge bonding member 520 is integrated with the bonding wire 530, which provides electrical connection between these bonding pads and the die contact pad 435.

[0051] Skilled artisans will appreciate that the present disclosure extends to embodiments including only stand-alone wedge bonds 510 or only integral wedge bonds 520. Furthermore, embodiments may include one or more unconnected wedge bonds 510 that are not electrically connected to the semiconductor die.

[0052] In e.g. Fig. 9 In the embodiment shown in , a single package is formed by a molding process. In such a package, in a method familiar to the skilled person, the sides of the package 910 can be formed by the inner surface of a molding tool used to inject molding compound to form the package.

[0053] Despite Fig. 9 310 and substrate 230. In one or more other embodiments, a single package is shown, but multiple packages may be assembled on a single carrier 310 and substrate 230. In such embodiments, after removing the carrier 310 and after removing the substrate 230 or before removing the substrate 230, the individual packages may be singulated by means of sawing lines between the packages or other suitable means.

[0054] Fig.10A cross-sectional plan view of a packaged semiconductor device according to one or more embodiments is shown, wherein the molding compound has been partially removed (or rendered transparent). In the illustrated embodiment, the bonding wires are a combination of a first group of bonding wires 630 comprising relatively thin wire materials and a second group of bonding wires 530 comprising wedge bonding wires. As shown, the semiconductor die may have a plurality of different contact pad subsets suitable for the first group of bonding wires and the second group of bonding wires, respectively. The contact pad subsets may be at different locations of the die (e.g., the die contact pads for the wedge bonding wires may be further away from the periphery). This may, for example, help ensure the integrity of the semiconductor die during the bonding of the wedge bonding wires, which may require additional force relative to the bonding of the first group of bonding wires. In addition, the wedge bonding with the relatively thick wire is usually completed in the same process step as the formation of the wedge bonding stub and therefore before the bonding of the relatively thin wire. To facilitate the tool to take the thinner wire, it may be preferred that the die contact pads for the thinner wire bonding pieces are closer to the periphery. In other embodiments, there may be a single set of die contact pads around the periphery of the semiconductor die. Other configurations will be familiar to the skilled artisan and are within the scope of the present disclosure.

[0055] Fig.11 A view of a second major surface of a packaged semiconductor device according to one or more embodiments is shown. In the orientation of the figure, the second major surface may be a bottom surface, and the package may be viewed from below. The figure shows exposed conductive material or conductive epoxy 420 in a generally central region of the package. A plurality of solder pads 510 and 520 are positioned around a generally peripheral region of the package. Although it will be apparent from the above that solder pads 510 correspond to exposed surfaces of independent wedge bond stubs and solder pads 520 correspond to exposed surfaces of wedge bond wires integral with solder wires 530, this is not intended to be construed as a limitation on the present invention. Fig.11 From below, the package appears similar to a conventional packaged semiconductor device, except that the conductive center region includes epoxy or other conductive material, whereas in conventional packaged semiconductor devices this region typically includes a die pad or die paddle that is part of the lead frame. Fig.11 The packaged semiconductor device shown in FIG. 1 is different from a conventional packaged semiconductor device in the shapes of the pads 510 and 520. In a conventional device, the pads are formed by the exposed lower surface of a portion of the lead frame, and the shape of the pads is therefore generally rectangular, whereas Fig.11 As shown in , pads according to embodiments of the present disclosure are generally oval or rectangular with rounded corners and / or rounded ends. As will be apparent from this disclosure, the shape of the exposed pad is generated by the degree of flattening of the generally circular bond wire that occurs during wedge bonding.

[0056] Fig.12A flow chart of a method according to one or more embodiments of the present disclosure is shown. At 1210, a semiconductor die is provided. The semiconductor die may have a plurality of die contact pads on a first main die surface thereof. The first main die surface may correspond to a top surface of the die, which may also be referred to as an active surface of the die, at or in which an electrically active layer is provided, which may provide electronic circuit elements such as transistors and diodes resistors.

[0057] The die is bonded to the substrate at 1220. Specifically, the second major surface of the semiconductor die can be bonded to the substrate, for example, by means of a conductive material or conductive epoxy or other suitable bonding member.

[0058] At 1230, a wedge bond stud is formed on the substrate. The wedge bond stud may be formed from a wedge bond wire, and the lower surface of the wedge bond, that is, the surface bonded to the substrate, will be exposed in the final device to provide a pad on the second major surface of the package, and may correspond to the bottom surface.

[0059] At 1240, the wedge bond stubs are electrically connected to the semiconductor die. Thus, the pads of the final package are electrically connected to the die contact pads. The electrical connection can be provided by the first set of bond wires or the second set of bond wires or a combination of the first set of bond wires and the second set of bond wires.

[0060] At 1250, the die is encapsulated. Encapsulation may be provided by injection molding a molding compound around the die and wedge bonds. Encapsulation may be performed at a single device level or around multiple devices. In the latter case, the resulting encapsulation may include multiple packaged semiconductor devices that may be singulated at a later stage in the process by sawing or the like.

[0061] At 1260, the substrate is removed, thereby exposing the wedge bond stubs. Thus, the exposed wedge bonds, and in particular the exposed lower surface, can serve as solder pads for the packaged device, instead of the more conventionally used separate portion of the lead frame.

[0062] In accordance with one or more embodiments, exposed surfaces of wedge bonds may be provided with flux or plating to facilitate electrically connecting the packaged semiconductor device to a circuit board.

[0063] In one or more embodiments, the method further includes: singulating the semiconductor device in the peripheral region of the second wedge joint and the joint region. Optionally, the semiconductor device is an array of semiconductor devices, and the entire array needs to be divided into individual semiconductor devices. The scribe line region is located in the peripheral region of the wedge joint where the semiconductor device can be divided.

[0064] It will be apparent to the skilled artisan that any range or device value given herein may be expanded or altered without losing the effect sought.

[0065] Although the present invention has been described in the context of an IC package having a single die and a single electrical connector, it will be appreciated that the present invention may be implemented in the context of an IC package having any suitable number of dies and any suitable number of electrical connectors.

[0066] Moreover, for the purposes of this specification, the term "connect, connecting or connected" refers to any means known in the art or subsequently developed, which allows energy to be transferred between two or more elements, and the insertion of one or more additional elements is expected, but not required. In contrast, the terms "directly coupled", "directly connected", etc., imply the absence of such additional elements.

[0067] The use of figure numbers and / or reference numerals in the claims is intended to identify one or more possible embodiments of the claimed subject matter to aid in the interpretation of the claims. Such use should not be construed as necessarily limiting the scope of those claims to the embodiments shown in the corresponding figures.

[0068] Unless expressly stated otherwise, each numerical value and range should be interpreted as approximations as if the word "about" or "approximately" preceded the stated value or range.

[0069] It will be appreciated that persons skilled in the art may make various changes in the details, materials and arrangements of parts which have been described and shown to explain embodiments of the invention without departing from the embodiments of the invention as encompassed in the appended claims.

[0070] It should be understood that the steps of the exemplary methods set forth herein do not necessarily need to be performed in the order described, and the order of the steps of such methods should be understood to be exemplary only. Similarly, additional steps may be included in such methods, and certain steps may be omitted or combined in methods consistent with various embodiments of the present invention.

[0071] Even though in the accompanying method claims, if present, elements are recited in a specific order with corresponding labels, those elements are not necessarily intended to be limited to being implemented in that specific order unless the claim recitation otherwise implies a specific order for implementing some or all of those elements.

[0072] Reference herein to "one embodiment" or "embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present invention. The appearances of the phrase "in one embodiment" in various places in this specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments necessarily mutually exclusive of other embodiments. The same applies to the term "implementation".

[0073] Although the attached claims refer to specific combinations of features, it should be understood that the scope of the disclosure of the present invention also includes any novel feature or any novel combination of features or any generalized form thereof disclosed explicitly or implicitly herein, regardless of whether it relates to the same invention currently claimed in any claim or whether it alleviates any or all technical problems that are the same as the technical problems alleviated by the present invention.

[0074] From reading this disclosure, other variations and modifications will be apparent to the skilled person.Such variations and modifications may involve equivalent and other features which are already known in the art of semiconductor device packaging and which may be used instead of or in addition to features described herein.

[0075] It should be noted that one or more embodiments above have been described with reference to different subject matters. Specifically, some embodiments may be described with reference to method-type claims, while other embodiments may be described with reference to apparatus-type claims. However, those skilled in the art should understand from the above that, unless otherwise indicated, any combination of features related to different subject matters, in addition to any combination of features belonging to one type of subject matter, in particular, a combination of features of a method-type claim with features of an apparatus-type claim, is also considered to be disclosed with this document.

[0076] Features described in the context of separate embodiments may be provided in combination in a single embodiment. Conversely, various features that are, for brevity, described in the context of a single embodiment may also be provided separately or in any suitable subcombination.

[0077] For the sake of completeness, it is also stipulated that the term "comprising" does not exclude other elements or steps, the term "a" or "an" does not exclude that a plurality, a single processor or other unit can realize the functions of several components described in the claims [delete if not relevant], and the reference numerals in the claims should not be interpreted as limiting the scope of the claims. In addition, the word "may" is used in a permissive sense (i.e., meaning having the possibility of...) rather than a mandatory sense (i.e., meaning must). Similarly, the words "include / including / includes" mean including but not limited to.

Claims

1. A packaged semiconductor device, characterized in that: having a first main package surface and a second main package surface, and comprising: an encapsulated die having a plurality of die contact pads on a first main die surface; Molding compounds; and a plurality of exposed pads, each exposed pad comprising a planarized lower surface of a wedge-bonded stub; wherein the plurality of exposed pads surround a peripheral region of the second major package surface and are separated by the molding compound; and The plurality of bonding pads are electrically connected to the contact pads through at least one set of bonding wires.

2. The packaged semiconductor device according to claim 1, wherein: Also included is an exposed region of conductive material in a central region of the second major package surface, electrically connected to the second die major surface, and spaced apart from the exposed pad by the molding compound.

3. The packaged semiconductor device according to claim 1, wherein: The at least one set of bond wires includes a first set of bond wires, wherein each bond wire is bonded to a respective contact pad at a first end, and wherein each bond wire includes the wedge-shaped bond stub at a respective second end.

4. The packaged semiconductor device according to claim 3, wherein: Each bond wire in the first set of bond wires comprises a wedge-shaped bond wire.

5. The packaged semiconductor device according to claim 1, wherein: The at least one set of bond wires includes a second set of bond wires, wherein each bond wire is bonded between a respective one of the plurality of die contact pads and a respective opposing surface of one of the exposed contact pads.

6. A method for manufacturing a packaged semiconductor device, characterized in that: The packaged semiconductor device has a first main packaging surface and a second main packaging surface, The method comprises: providing a semiconductor die having a plurality of die contact pads on a first main die surface of the semiconductor die; bonding a second main die surface of the semiconductor die to a substrate; providing a plurality of bonding pads by forming wedge bonds on the substrate, each bonding pad being formed by a flattened lower surface of a wedge bond stub surrounding and distal from the semiconductor die; forming at least one set of electrical connections between the plurality of bonding pads and the contact pads via a first set of bonding wires; encapsulating the semiconductor die and wedge bond wires; and The substrate is removed, thereby exposing the pads on the second major package surface.

7. The method according to claim 6, characterized in that The step of bonding the second main die surface of the semiconductor die to a substrate includes bonding the second main die surface of the semiconductor die to a substrate via a conductive epoxy material, And the step of removing the substrate includes exposing the conductive epoxy material on the second main package surface.

8. The method according to claim 6, characterized in that Forming at least one set of electrical connections includes forming a plurality of wedge bonds starting from the wedge bond line between respective ones of the plurality of contact pads, and each wedge bond includes the wedge bond stub at a respective second end.

9. The method according to claim 6, characterized in that Forming at least one set of electrical connections between the plurality of bonding pads and the contact pads includes forming a plurality of wire bonds between corresponding contact pads of the plurality of contact pads and corresponding wedge bond stubs at relatively planarized surfaces of the bonding pads.

10. The method according to claim 6, characterized in that Additionally, at least one of flux and plating is included on the bottom surface of the exposed pad.

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