Electronic circuit

Abstract

The invention relates to an electronic circuit. An electronic circuit includes a first die having a GaN transistor and a second die, the first die and the second die being stacked such that elements of the second die electrically connect first and second nodes of the first die, the first and second nodes being coupled to a conductive node and a control node of the GaN transistor, respectively.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of priority to French patent application No. 2310184, entitled “Circuit électronique,” ​​filed on September 26, 2023, which is hereby incorporated by reference to the maximum extent permitted by law. Technical Field

[0002] The present disclosure relates generally to electronic circuits and associated methods. Background Art

[0003] In connection with the manufacture of electronic circuits, it may be useful to test certain components of a circuit before the circuit is fully completed or assembled with other circuits. Summary of the invention

[0004] It would be beneficial to provide electronic circuits having components that can be tested during manufacture, while also reducing manufacturing and design costs.

[0005] Embodiments of the present disclosure overcome all or part of the disadvantages of known circuits.

[0006] One embodiment provides an electronic circuit including a first die having a GaN transistor and a second die, the first die and the second die being stacked such that an element of the second die electrically connects a first node and a second node of the first die, the first node and the second node being coupled to a conduction node and a control node of the GaN transistor, respectively.

[0007] One embodiment provides a method of manufacturing an electronic circuit, comprising: A first die having a GaN transistor and a second die are stacked such that an element of the second die electrically connects a first node and a second node of the first die, which are respectively coupled to a conduction node and a control node of the GaN transistor.

[0008] A circuit according to claim 1 or a method according to claim 2, wherein the component of the second die comprises a conductive track arranged on the first surface of the second die.

[0009] According to an embodiment, the second die is a silicon based die.

[0010] According to an embodiment, the second die includes at least one transistor.

[0011] According to an embodiment, the transistors of the second die are of MOS type and the GaN transistors of the first die are of HEMT type.

[0012] According to an embodiment, the transistor of the second die has: a first conductive node connected via the element to a first node of the first die; and The second conductive node is connected to a control node of a transistor of the first die via another element.

[0013] According to an embodiment, the electrical contact between the element of the second die and the first node and the second node of the first die is a weld or solder.

[0014] According to an embodiment, the second node of the first die is coupled to the control node of the GaN transistor via the electronic component.

[0015] According to an embodiment, the electronic components are active or passive.

[0016] According to an embodiment, the electronic components are configured to allow establishing an automatic operating point of the GaN transistor.

[0017] According to an embodiment, the electronic component is a resistor.

[0018] According to an embodiment, before stacking the first die and the second die, the first node and the second node of the first die are disconnected from each other.

[0019] According to an embodiment, before stacking the first die and the second die, testing of the electronic component is performed.

[0020] In one embodiment, an electronic circuit includes a first die. The first die includes a GaN transistor having a control node and a conduction node. The first die includes a first node coupled to the conduction node and a second node coupled to the control node. The electronic circuit includes a second die stacked with the first die and including an element electrically coupling the first node to the conduction node and electrically coupling the second node to the control node.

[0021] In one embodiment, a method of manufacturing an electronic circuit includes stacking a first die and a second die. The stacking includes electrically coupling a first node of the first die to a conduction node of a GaN transistor of the first die using an element of the second die, and electrically coupling a second node of the first die to a control node of the GaN transistor using the element.

[0022] In one embodiment, a device includes a first die. The first die includes: a first GaN transistor including a control node and a conduction node; a first surface; a first conductive track coupled to the conduction node and exposed at the first surface; and a second conductive track coupled to the control node and exposed at the first surface. The device includes a second die. The second die includes a second surface mounted to the first surface of the first die and a third conductive track exposed at the second surface and electrically coupled to the first conductive track and the second conductive track. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The foregoing features and advantages and other features and advantages will be described in detail in the following disclosure of specific embodiments given by way of illustration and not limitation, with reference to the accompanying drawings, in which: Figure 1 schematically illustrates a portion of an electronic circuit according to an embodiment; Figure 2 Pictured Figure 1 A top view of an electronic circuit portion of an embodiment of the present invention; Figure 3 schematically illustrates a top view of an embodiment of an electronic circuit; Figure 4 Schematically illustrates Figure 3 A cross-sectional view AA of a portion of an electronic circuit of an embodiment; Figure 5 Schematically illustrates a Figure 3 electronic circuits; and Figure 6 Pictured Figure 3 A method for manufacturing an electronic circuit. DETAILED DESCRIPTION

[0024] The same features in the various figures are indicated by the same reference numerals. In particular, common structural and / or functional features in various embodiments may have the same reference numerals and may have the same structure, size and material properties.

[0025] For clarity, only the steps and elements that are helpful for understanding the embodiments are illustrated and described in detail.

[0026] Unless otherwise specified, when two elements are referred to as being connected together, this means a direct connection without any intermediate elements except conductors, and when two elements are referred to as being coupled together, this means the two elements may be connected or they may be coupled via one or more other elements.

[0027] In the following description, when referring to terms that define absolute positions (such as terms "front", "back", "top", "bottom", "left", "right", etc.), or terms that define relative positions (such as terms "above", "below", "upper", "lower", etc.), or terms that define directions (such as terms "horizontal", "vertical", etc.), unless otherwise specified, reference is made to the orientation of the accompanying drawings.

[0028] Unless otherwise indicated, the expressions "about," "approximately," "substantially," and "approximately" mean plus or minus 10%, preferably plus or minus 5%.

[0029] Figure 1 An electronic circuit 170 according to an embodiment is schematically illustrated.

[0030] More specifically, Figure 1 A first circuit of an electronic circuit 170 formed in a first die 100 is shown, which includes a GaN transistor 102. A first node N1 of the first die 100 is coupled to a conduction node 142, 144 (e.g., a source) of the GaN transistor 102. A second node N2 of the first die 100 is coupled to a control node 130, 132 (e.g., a gate) of the GaN transistor 102. The transistor 102 also includes another conduction node 110 (e.g., a drain).

[0031] In the example shown, the conductive nodes 142, 144 and the control nodes 130, 132 each include two rails, however, it is contemplated that they each have a single rail.

[0032] In an example, the GaN transistor is a high electron mobility type (HEMT).

[0033] The term "GaN transistor" refers to transistors whose substrate is an alloy based on gallium nitride (although other elements may also be incorporated into this basic alloy). This particularly includes transistors containing one or more heterojunctions formed from alloys such as AlGaN / InGaN, AlInAs / GaInAs, GaInAs / AlGaAs, AlGaAs / AlGa.

[0034] In the example shown, the second node N2 of the first die 100 is coupled to the control node 132 of the GaN transistor via the electronic component 120. In an example, the electronic component 120 is configured to allow an automatic operating point of the GaN transistor to be established. In another example, the electronic component 120 is an active or passive component. The electronic component 120 is, for example, a resistor.

[0035] In the example shown, nodes N1 and N2 are disconnected, in other words have no direct connection. This enables test measurements to be performed, for example, to determine physical parameters of component 120 , such as its resistance, and / or the leakage current of gate 132 of transistor 102 .

[0036] Figure 2 Pictured Figure 1 1 is a top view of a portion of an electronic circuit 170 of an embodiment. More specifically, Figure 2A first die 100 is shown. In the example shown, the connection pads of the conductive node 110 (e.g., drain) of the GaN transistor 102 are arranged on the upper part of the die 100, in the form of a rectangle, for example, arranged inside and / or on top of a substrate 202 (e.g., made of GaN). The connection pads coupled to the tracks 130, 132 forming the control node are arranged in the corner opposite to the conductive node 110 on the same surface of the substrate 202. The connection pads coupled to the tracks 142, 144 forming the source of the transistor 102 are arranged, for example, inside and / or on top of the same surface of the substrate 202, and this is between the pads coupled to the tracks 130 and 132. An electronic component 120 is located between the connection pads coupled to the tracks 142, 144, which in this example is a resistor arranged on the same surface of the substrate 202. On the first die 100, the electronic component 120 is electrically insulated from the connection pads coupled to the tracks 142, 144. In a manner not shown, the electronic component 120 is coupled to the tracks 130 and 132 , for example, by vias and / or conductive tracks in the substrate 202 .

[0037] Figure 1 and Figure 2 The example enables one or more physical parameters of the electronic component 120 to be measured, for example. However, in the case where a measurement or test is performed, in order to form a complete circuit, the nodes N1 and N2 must be electrically connected, for example. This is the case when it is desired to implement a cascode structure from the first die 100, for example.

[0038] Such a connection can be made by performing a wire bond between nodes N1 and N2. However, this is expensive and can cause reliability issues as well as introduce parasitics into the signal.

[0039] The described embodiment provides a second die as a complement to the first die 100, which is stacked with the first die so that the elements of the second die are electrically connected to the first node N1 and the second node N2 of the first die. This enables measurements to be performed on the first die (e.g., the electronic component 120), and enables a complete circuit to be obtained when forming an assembly using the second die, for example a circuit of the common source and common gate type. Another advantage is that, in contrast to the use of wire bonding, the presence of parasitic elements of the "RLC" type is limited. This further leads to better stability during signal conversion and limits the costs associated with soldering parts and additional materials.

[0040] Figure 3 A top view of an embodiment of an electronic circuit 370 is schematically illustrated.

[0041] Circuit 370 includes a circuit similar to Figure 1 and Figure 2The first die 100 of the first die described in the embodiment of the present invention and the second die 300. The first die and the second die 100, 300 are stacked. In an example, the second die 300 is a die based on silicon or a semiconductor. In another example, the second die 300 includes at least one circuit having a transistor.

[0042] In the example shown, the second die 300 is stacked above the first die. The second die 300 comprises an element 350, which is arranged on a surface of the second die 300, which faces the surface located at the front of the first die 100. The element 350 of the second die comprises, for example, a conductive track, which is, for example, metallic or made of a heavily doped semiconductor. The conductive track is, for example, formed by or connected to the drain 340 or source or gate of the transistor of the second die 300.

[0043] exist Figure 3 In the example of FIG. 1 , it can be seen through the transparency that the second die covers the connection pads coupled to the tracks 142 , 144 and the electronic component 120 .

[0044] In the example shown, the element 350 partially covers the connection pads coupled to the tracks 142, 144. In another example, the element 350 completely covers these pads. Figure 1 As shown in , in one embodiment, the source of the transistor 102 is divided into two parts 142, 144, both of which are connected to the node N1. The element 350 electrically connects the first node N1 and the second node N2 of the first die 100, in other words, the element 350 electrically connects the source of the transistor 102 to the second node N2, which itself is connected to the electronic component 120. In the example where the source of the transistor 102 is formed by a single conductive track, the element 350 electrically connects this track to the second node N2, thereby electrically connecting the source of the transistor 102 to the second node N2.

[0045] In an example, the electrical contact between the elements of the second die 300 and the first and second nodes N1, N2 of the first die is formed by welding or soldering. In another example, the electrical contact is formed via a die attach adhesive film, which contains, for example, silver and / or nickel, and / or copper and / or gold and / or palladium. In one embodiment, a heat treatment with or without the application of pressure is also used to form the contact.

[0046] In contrast to the fragile wire connections, which have a reduced contact surface area, Figure 3 The example enables increasing the contact surface area between the first die and the second die to form the contact between the nodes N1 and N2.

[0047] Figure 4Schematically illustrates Figure 3 AA cross-section of a portion of an electronic circuit of an embodiment of the present invention. The AA cross-section cuts the first die 100 and the second die 300 at the level of the connection pads of the sources 142 , 144 and the electronic components 120 and the element 350 .

[0048] In the example shown, the pads of the sources 142, 144 are arranged in the substrate 202 from the surface of the first die 100 facing the second die 300. The element 350 is arranged in the substrate 402 of the second die 300 from the surface of the second die facing the first die. The element 350 partially covers the pads of the sources 142, 144 of the transistor 102 of the first die 100 at the level of the node N1, which is distributed over the pads of the sources 142, 144. The element 350 also covers the element 120 at the level of the node N2, which is distributed over the surface of the component 120. This covering and possibly associated solder or solder form electrical contacts between the sources 142, 144 of the transistor 102 and a second node N2 connected to the gate of the transistor 102.

[0049] In the example, the element 350 is part of a conducting node of a transistor of the second die, for example the drain 340. This enables the connection length to be limited as much as possible.

[0050] Figure 5 Schematically illustrates a Figure 3 electronic circuits.

[0051] In the example shown, the first die 100 includes Figure 1 Similar to the circuit of FIG. 4 , the element 350 of the second die 300 is part of the drain 340 of the transistor 502 of the second die 300. In an example, the transistor 502 of the second die 300 is of MOS (Metal Oxide Semiconductor) type, and the substrate 402 is silicon based.

[0052] In the example shown, the source 542 of the transistor 502 is coupled (preferably connected) to the control nodes 130, 132 of the GaN transistor 102 of the first die 100. For example, the connection is performed similarly to the connection of the first and second nodes N1, N2. In this example, the source 542 of the transistor 502 is connected to the substrate of the transistor 502. The drain 340 of the transistor 502 is connected to the element 350 and thus also to the nodes N1 and N2. The transistor 502 also includes a control node 530.

[0053] therefore, Figure 5The example forms a cascode type circuit, in which the source 142 , 144 of the GaN transistor 102 is connected in series with the drain 340 of the transistor 502 , and the gate 130 , 132 of the transistor 102 is connected to the source 542 of the transistor 502 .

[0054] Figure 6 Illustration of manufacturing Figure 3 method of electronic circuits.

[0055] In a first step 600 (stacking GaN and MOS dies), the first and second dies 100, 300 are stacked, for example to place the element 350 in front of the pads of the sources 142, 144 and the surface of the electronic component 120. The nodes N1 and N2 are disconnected at this stage.

[0056] In a second step 602 (connecting the first and second nodes of the GaN die with an element of the second die), the nodes N1 and N2 of the first die 100 are electrically connected through the element 350 of the second die. The connection is either direct or via a solder or a weld and / or via an alloy and / or by applying heat treatment and / or applying pressure.

[0057] Prior to step 600 , nodes N1 and N2 are disconnected and, for example, the resistance of component 120 and / or the leakage current of the gate of GaN transistor 102 may be tested.

[0058] A variety of embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these various embodiments and variations can be combined, and those skilled in the art will recognize other variations. In particular, in some embodiments, element 350 is formed by a plurality of points or conductive surfaces.

[0059] Finally, based on the functional indications given above, the practical implementation of the described embodiments and variants is within the capabilities of a person skilled in the art. In particular, in one embodiment, the element 350 is a conductive track, or can also be implemented by a conductive or control node or also a control node of the rear gate of the transistor 502 of the second die 300. In one embodiment, the element 350 can also be implemented by a part of an electronic component, such as for example a node of a diode or a node of an inductor or a node of a capacitive element.

[0060] In the depicted example, the second die 300 is stacked on the first die 100 . However, in one embodiment, the first die 100 is stacked on the second die 300 .

[0061] In one embodiment, the electronic circuit is implemented in an automotive application, or in other applications that use electrical power.

[0062] In one embodiment, an electronic circuit (370) includes a first die (100) having a GaN transistor (102) and a second die (300), the first die (100) and the second die (300) being stacked such that an element (350) of the second die (300) electrically connects a first node (N1) and a second node (N2) of the first die (100), the first node (N1) and the second node (N2) being coupled to a conduction node (140, 142) and a control node (130, 132) of the GaN transistor (102), respectively.

[0063] In one embodiment, a method of manufacturing an electronic circuit (370) stacks a first die (100) having a GaN transistor (102) and a second die (300) such that an element (350) of the second die (100) electrically connects a first node (N1) and a second node (N2) of the first die, the first node (N1) and the second node (N2) being coupled to a conduction node (142, 144) and a control node (130, 132) of the GaN transistor (102), respectively.

[0064] In one embodiment, the element (350) of the second die (300) comprises a conductive track arranged on the first surface of the second die (300).

[0065] In one embodiment, the second die (300) is a silicon based die.

[0066] In one embodiment, the second die (300) includes at least one transistor (502).

[0067] In one embodiment, the transistor (502) of the second die (300) is of MOS type and the GaN transistor (102) of the first die (100) is of HEMT type.

[0068] In one embodiment, the transistor (502) of the second die (300) includes: a first conductive node (340) connected to the first node (N1) of the first die (100) via the element (350); and a second conductive node (542) connected to the control node (130, 132) of the transistor (102) of the first die (100) via another element.

[0069] In one embodiment, the electrical contact between the element (350) of the second die and the first and second nodes (N1, N2) of the first die (100) is a bond or solder.

[0070] In one embodiment, the second node (N2) of the first die is coupled to a control node of the GaN transistor (102) via the electronic component (120).

[0071] In one embodiment, the electronic component (120) is active or passive.

[0072] In one embodiment, the electronic component (120) is configured to allow an automatic operating point of the GaN transistor (102) to be established.

[0073] In one embodiment, the electronic component (120) is a resistor.

[0074] In one embodiment, before stacking the first die and the second die (100, 300), the first node and the second node (N1, N2) of the first die (100) are disconnected from each other.

[0075] In one embodiment, before stacking the first die and the second die (100, 300), testing is performed on the electronic component (350).

[0076] These and other changes can be made to the embodiments in light of the above detailed description. In general, in the following claims, the terms used should not be interpreted to limit the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full range of equivalents to which these claims are entitled. Therefore, the claims are not limited by the disclosure.

Claims

1. An electronic circuit comprising: The first die comprises: A GaN transistor having a control node and a conduction node; a first node coupled to the conductive node; and a second node coupled to the control node; and A second die is stacked with the first die and includes elements electrically coupling the first node to the conduction node and the second node to the control node. 2 . The electronic circuit of claim 1 , wherein the components of the second die comprise conductive tracks arranged on the first surface of the second die. The electronic circuit of claim 1 , wherein the second die is a silicon-based die. The electronic circuit of claim 1 , wherein the second die comprises at least one transistor.

5. The electronic circuit according to claim 4, wherein the transistor of the second die is of MOS type and the GaN transistor of the first die is of HEMT type.

6. The electronic circuit of claim 4, wherein the transistor of the second die comprises: a first conductive node connected to a first node of a first die via the element; as well as A second conductive node is connected to a control node of a transistor of the first die via a second element.

7. The electronic circuit of claim 1, wherein the electrical contact between the element of the second die and the first node and the second node of the first die is a bond or solder.

8. The electronic circuit of claim 1, wherein the second node of the first die is coupled to a control node of the GaN transistor via an electronic component.

9. The electronic circuit of claim 8, wherein the electronic component is active or passive.

10. The electronic circuit of claim 8, wherein the electronic components are configured to allow an automatic operating point of the GaN transistor to be established.

11. The electronic circuit according to claim 8, wherein the electronic component is a resistor.

12. A method of manufacturing an electronic circuit, comprising: stacking a first die and a second die, wherein the stacking comprises: electrically coupling the first node of the first die to a conductive node of a GaN transistor of the first die using an element of the second die; and The second node of the first die is electrically coupled to a control node of the GaN transistor using the element.

13. The method according to claim 12, wherein: Prior to stacking the first die and the second die, the first node and the second node of the first die are disconnected from each other.

14. The method according to claim 13, wherein: After said stacking, the second node of the first die is coupled to the control node of the GaN transistor via the electronic component.

15. The method of claim 14, comprising performing testing of the electronic component prior to stacking the first die and the second die.

16. A device comprising: The first die comprises: A first GaN transistor including a control node and a conduction node; and a first surface; a first conductive track coupled to the conductive node and exposed at the first surface; and a second conductive track coupled to the control node and exposed at the first surface; and The second die comprises: a second surface mounted to the first surface of the first die; and A third conductive track is exposed at the second surface and electrically coupled to the first conductive track and the second conductive track. The device of claim 16 , wherein the second die comprises a second transistor.

18. The device of claim 17, wherein the second transistor comprises a conductive node electrically coupled to the third conductive track.

19. The device of claim 16, comprising an adhesive film between the third conductive track and the first and second conductive tracks.

20. The device of claim 16, wherein the first die comprises a fourth conductive track coupled to the conductive node, wherein the fourth conductive track is exposed at the first surface and electrically coupled to the third conductive track.

Images