Board-level packaging structure, packaging method and board-level packaging system

Abstract

The embodiment of the invention provides a board-level packaging structure, a packaging method and a board-level packaging system. The packaging structure comprises a square panel, a plurality of bridging chips, a plastic packaging layer, a rewiring layer, a chip operation layer and a connection module, the bridging chip is arranged on the surface of the square panel; the plastic packaging layer is arranged on the surface of the square panel and wraps the plurality of bridging chips; the rewiring layer is arranged on the surface, deviating from the square panel, of the plastic packaging layer and the surface of the bump of the bridging chip, and is electrically connected with the bridging chip; the chip operation layer and the connection module are arranged on the rewiring layer and are electrically connected with the rewiring layer. According to the structure, a large-area square panel is adopted, the chip containing capacity, the area utilization rate and the I / O density are remarkably improved, the system performance is remarkably improved, and high computing power integration is achieved; the chip operation layer realizes high-density interconnection by means of a plurality of bridging chips, and does not need to depend on construction of a fine circuit structure in an RDL.

Description

Technical Field

[0001] The embodiments of the present disclosure belong to the field of semiconductor packaging technology, and specifically relate to a board-level packaging structure and packaging method, and a board-level packaging system. Background Art

[0002] SoW (System on wafer) integrates a certain number of computing chips onto a whole wafer as a whole to form an ultra-high performance (HPC) chip system.

[0003] SoW uses FO technology to reconstruct the computing chip into a wafer with a glass carrier as the carrier, completes the interconnection between chips through plastic packaging and rewiring, peels off the carrier, and interconnects the power device with the computing chip through flip-chip on the reconstructed wafer to form the entire on-wafer system.

[0004] Due to the limitation of wafer size, the overall performance of a single SoW system is limited.

[0005] In view of the above problems, it is necessary to propose a board-level packaging structure and packaging method, and a board-level packaging system that are reasonably designed and effectively solve the above problems. Summary of the invention

[0006] The embodiments of the present disclosure aim to solve at least one of the technical problems existing in the prior art and provide a board-level packaging structure and packaging method, and a board-level packaging system.

[0007] An aspect of an embodiment of the present disclosure provides a board-level packaging structure, including:

[0008] Square panels;

[0009] A plurality of bridge chips are arranged on the surface of the square panel;

[0010] A plastic packaging layer, disposed on the surface of the square panel and wrapping the plurality of bridge chips;

[0011] A redistribution layer is disposed on a surface of the plastic packaging layer away from the square panel and a bump surface of the bridge chip, and is electrically connected to the bridge chip;

[0012] The chip operation layer and the connection module are both arranged on the redistribution layer and electrically connected to the redistribution layer.

[0013] Optionally, a plurality of data relay chips are further included, and the plurality of data relay chips are arranged on the surface of the square panel and wrapped in the plastic packaging layer.

[0014] Optionally, the square panel is a glass panel.

[0015] Optionally, the connection module includes a plurality of connectors arranged on the redistribution layer and cables arranged on the connectors.

[0016] Optionally, the connection module further includes a plurality of photoelectric conversion chips arranged in the redistribution layer and optical fibers arranged in the photoelectric conversion chips.

[0017] Another aspect of the present disclosure provides a board-level packaging method, the packaging method comprising:

[0018] Available in square panels;

[0019] Mounting a plurality of bridge chips on the surface of the square panel;

[0020] Forming a plastic encapsulation layer on the surface of the square panel to wrap the plurality of bridge chips, and thinning the plastic encapsulation layer to expose the bumps of the bridge chip;

[0021] forming a redistribution layer on the surface of the plastic packaging layer away from the square panel and the surface of the bump;

[0022] The chip operation layer and the connection module are mounted on the rewiring layer.

[0023] Optionally, when mounting the plurality of bridge chips on the surface of the square panel, the method further comprises:

[0024] A plurality of data relay chips are mounted on the surface of the square panel.

[0025] Optionally, mounting the connection module on the redistribution layer includes:

[0026] Mounting a plurality of connectors provided with cables on the redistribution layer; or,

[0027] A plurality of photoelectric conversion chips provided with optical fibers are mounted on the redistribution layer.

[0028] Optionally, the square panel is a glass panel.

[0029] Another aspect of the present disclosure provides a board-level packaging system, comprising at least one board-level packaging structure as described above; wherein:

[0030] When the board-level packaging system includes a plurality of board-level packaging structures, the plurality of board-level packaging structures are electrically connected through the connection module.

[0031] The board-level packaging structure, packaging method, and board-level packaging system of the embodiments of the present disclosure each adopt a large-area square panel, which significantly improves the chip capacity, area utilization, and I / O density, and significantly improves the system performance, thereby solving the problem of limited performance of a single SoW system and achieving high computing power integration; the chip computing layer achieves high-density interconnection with the help of multiple bridge chips, and no longer needs to rely on building a sophisticated circuit structure in the RDL. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A cross-sectional view of a board-level packaging structure according to an embodiment of the present disclosure;

[0033] Figure 2 A cross-sectional view of a board-level packaging structure of another embodiment of the present disclosure;

[0034] Figure 3 A cross-sectional view of a board-level packaging structure of another embodiment of the present disclosure;

[0035] Figure 4 A cross-sectional view of a board-level packaging structure of another embodiment of the present disclosure;

[0036] Figure 5 It is a plan view of a board-level packaging structure of another embodiment of the disclosed embodiment;

[0037] Figure 6 A schematic diagram of a process of a board-level packaging method according to another embodiment of the present disclosure;

[0038] Figure 7 Figure 12 is a process schematic diagram of a board-level packaging method according to an embodiment of the present disclosure;

[0039] Fig.13 It is a schematic diagram of mounting a bridge chip and a data relay chip according to another embodiment of the present disclosure;

[0040] Fig.14 It is a cross-sectional view of a board-level packaging structure mounted with a data relay chip according to another embodiment of the present disclosure;

[0041] Fig.15 It is a cross-sectional view of a board-level packaging structure mounted with a data relay chip according to another embodiment of the present disclosure;

[0042] Fig.16 It is a plan view of a board-level packaging system according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0043] In order to enable those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, the embodiments of the present disclosure are further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0044] like Figures 1 to 5 As shown, one aspect of an embodiment of the present disclosure provides a board-level packaging structure 100, including a square panel 22, a plurality of bridge chips 24, a plastic encapsulation layer 26, a redistribution layer, a chip computing layer 32 and a connection module.

[0045] A plurality of bridge chips 24 are disposed on the surface of the square panel 22. Specifically, the non-functional surfaces of the plurality of bridge chips 24 are disposed on the surface of the square panel 22. The plurality of bridge chips 24 are distributed in a matrix, and the number and distribution of the plurality of bridge chips 24 are not specifically limited in this embodiment and can be selected according to actual needs.

[0046] The plastic packaging layer 26 is disposed on the surface of the square panel 22 and wraps the plurality of bridge chips 24 , thereby protecting the plurality of bridge chips 24 .

[0047] The redistribution layer is disposed on the surface of the plastic packaging layer 26 facing away from the square panel 22 and the bump surface of the bridge chip 24 , and is electrically connected to the bridge chip 24 .

[0048] The chip operation layer 32 and the connection module are both arranged on the redistribution layer and are both electrically connected to the redistribution layer. Figures 1 to 5 As shown, the chip computing layer 32 is disposed in the central area of ​​the redistribution layer, and the connection module is disposed in the edge area of ​​the redistribution layer.

[0049] The board-level packaging structure of the disclosed embodiment, each board-level packaging structure adopts a large-area square panel, which significantly improves the chip capacity, area utilization and I / O density, and significantly improves the system performance, thereby solving the problem of limited performance of a single SoW system and realizing high computing power integration; the chip computing layer achieves high-density interconnection with the help of multiple bridge chips, and no longer needs to rely on building a sophisticated circuit structure in the RDL.

[0050] For example, Figures 1 to 4 As shown, in this embodiment, the redistribution layer includes a dielectric layer 28 and a metal layer 30. The dielectric layer 28 is disposed on the surface of the plastic layer 26 away from the square panel 22 and the bump surface of the bridge chip 24. The dielectric layer 28 is provided with a plurality of openings, each of which is provided with a metal layer 30, and the metal layer 30 is electrically connected to the bridge chip 24.

[0051] For example, Figure 3 and Figure 4As shown, in one embodiment, the board-level packaging structure further includes a plurality of data relay chips 42, which are disposed on the surface of the square panel 22 and wrapped in the plastic layer 26. In other words, the plurality of bridge chips 24 and the plurality of data relay chips 42 are both disposed on the surface of the square panel 22.

[0052] In this embodiment, the board-level packaging structure can improve the data transmission rate by providing multiple data relay chips.

[0053] For example, in this embodiment, the square panel 22 is a glass panel. In the prior art, the carrier is peeled off during the packaging process, and the final packaging structure does not contain the carrier. However, the board-level packaging structure of the disclosed embodiment retains the square glass panel, and the rigidity of the glass panel is used to effectively control the warping of the board-level packaging structure, solve the problem of large-area EMC and chip CTE mismatch, and improve the reliability of the board-level packaging structure.

[0054] For example, Figure 1 and Figure 3 As shown, in one embodiment, the connection module includes a plurality of connectors 34 disposed on the redistribution layer and cables 36 disposed on the connectors 34 .

[0055] Specifically, Figure 5 As shown, a plurality of connectors 34 are disposed on the redistribution layer at the edge region of the square panel 22 , and a cable 36 is disposed on each connector 34 .

[0056] For example, Figure 2 and Figure 4 As shown, in another embodiment, the connection module further includes a plurality of photoelectric conversion chips 38 disposed in the redistribution layer and optical fibers 40 disposed in the photoelectric conversion chips 38 .

[0057] Specifically, Figure 5 As shown, a plurality of photoelectric conversion chips 38 are disposed on a redistribution layer in an edge region of the square panel 22 , and a cable 36 is disposed on each connector 34 .

[0058] Exemplarily, the chip computing layer 32 may include only a plurality of computing chips, or the chip computing layer 32 may include a plurality of computing chips and a plurality of storage chips. Of course, the chip computing layer 32 may also include other types of chips. The chips in the chip computing layer 32 are electrically interconnected through the redistribution layer and the bridge chip 24.

[0059] In this embodiment, according to the area of ​​the square panel, the chip computing layer 32 is distributed in a matrix, which can significantly improve the chip capacity, area utilization and I / O density of the entire packaging structure.

[0060] It should be noted that there is no specific limitation on the type and quantity of the chip computing layer 32 , and they can be selected according to actual needs.

[0061] like Figure 6 As shown, another aspect of the embodiment of the present disclosure provides a board-level packaging method S100, the board-level packaging method S100 comprising:

[0062] S110, provide square panel.

[0063] like Figure 7 As shown, a square panel 22 is provided. In this embodiment, preferably, the square panel 22 is a glass panel.

[0064] The board-level packaging structure of the disclosed embodiment retains the square glass panel and utilizes the rigidity of the glass panel to effectively control the warping of the board-level packaging structure, thereby solving the problem of large-area EMC and chip CTE mismatch and improving the reliability of the board-level packaging structure.

[0065] S120, mounting a plurality of bridge chips on the surface of the square panel.

[0066] like Figure 7 As shown, the non-functional surfaces of the plurality of bridge chips 24 are mounted and fixed on the surface of the square panel 22. The plurality of bridge chips 24 are distributed in a matrix. The number and distribution of the plurality of bridge chips 24 are not specifically limited in this embodiment and can be selected according to actual needs.

[0067] Exemplarily, when a plurality of bridge chips 24 are mounted on the surface of the square panel 22, the method S100 further includes:

[0068] like Fig.13 As shown, multiple data relay chips 42 are mounted on the surface of the square panel 22. In this embodiment, multiple data relay chips 42 and multiple bridge chips 24 are mounted on the surface of the square panel 22, and the data relay chips 42 can increase the data transmission rate.

[0069] Among them, Fig.14 and Fig.15 It is a schematic structural diagram of a board-level packaging structure 100 obtained by mounting a bridge chip 24 and a data relay chip 42 on a square panel 22 at the same time and then packaging the resultant structure.

[0070] S130, forming a plastic packaging layer covering the plurality of bridge chips on the surface of the square panel, and thinning the plastic packaging layer until the bumps of the bridge chips are exposed.

[0071] like Figure 8As shown, a plastic packaging layer 26 is formed on one side of the square panel 22 facing the bridge chips 24 , and the plastic packaging layer 26 wraps the plurality of bridge chips 24 to protect the bridge chips 24 .

[0072] like Fig. 9 As shown, the side of the plastic packaging layer 26 facing away from the square panel 22 is thinned by grinding or other processes to expose the bumps (not shown) on the functional surface of the bridge chip 24 .

[0073] S140, forming a redistribution layer on a surface of the plastic packaging layer facing away from the square panel and on a surface of the bump.

[0074] like Fig.10 As shown, first, a dielectric layer 28 is formed by coating on the surface of the plastic packaging layer 26 facing away from the square panel 22 and the bump surface of the functional surface of the bridge chip 24 .

[0075] Then, the dielectric layer 28 is patterned by photolithography and etching processes to form a plurality of openings on the dielectric layer 28 .

[0076] Next, a metal layer 30 is formed at the opening by electroplating or sputtering, wherein the metal layer 30 is electrically connected to the bridge chip 24 .

[0077] S150, mounting the chip computing layer and the connection module on the redistribution layer.

[0078] like Fig.11 , Fig.12 , Fig.14 and Fig.15 As shown, in this embodiment, the chip computing layer 32 is mounted on the central area of ​​the redistribution layer, and the connection module is mounted on the edge area of ​​the redistribution layer to form a board-level packaging structure 100.

[0079] like Fig.11 and Fig.14 As shown, in one embodiment, mounting the connection module on the edge area of ​​the redistribution layer includes:

[0080] A plurality of connectors 34 provided with cables 36 are mounted on the edge area of ​​the redistribution layer. In other words, the plurality of connectors 34 are distributed on the edge area of ​​the square panel 22.

[0081] like Fig.12 and Fig.15 As shown, in another embodiment, the connection module is mounted on the edge area of ​​the redistribution layer, and further includes:

[0082] A plurality of photoelectric conversion chips 38 provided with optical fibers 40 are mounted on the edge region of the redistribution layer. In other words, the plurality of photoelectric conversion chips 38 are distributed on the edge region of the square panel 22 .

[0083] It should be noted that there is no specific limitation on the specific type of the connection module, and it can be selected according to actual needs.

[0084] The board-level packaging method of the disclosed embodiment includes: providing a square panel; mounting multiple bridge chips on the surface of the square panel; forming a plastic packaging layer on the surface of the square panel to wrap the multiple bridge chips, and thinning the plastic packaging layer to expose the bumps of the bridge chips; forming a redistribution layer on the surface of the plastic packaging layer away from the square panel and the surface of the bumps; mounting the chip operation layer and the connection module on the redistribution layer; the board-level packaging structure formed in the method adopts a large-area square panel, which significantly improves the chip capacity, area utilization and I / O density, and significantly improves the system performance, thereby solving the problem of limited performance of a single SoW system and realizing high computing power integration; the chip operation layer realizes high-density interconnection with the help of multiple bridge chips, and no longer needs to rely on building a fine circuit structure in the RDL.

[0085] like Fig.16 As shown, another aspect of the embodiment of the present disclosure provides a board-level packaging system A, comprising at least one board-level packaging structure 100 as described above. The specific structural features of the board-level packaging structure 100 have been described in detail above and will not be repeated here.

[0086] When the board-level packaging system A includes a plurality of board-level packaging structures 100 , the plurality of board-level packaging structures 100 are electrically connected via a connection module.

[0087] In one embodiment, multiple board-level packaging structures 100 can be electrically connected through cables 36 of connectors 34 to form Fig.16 Board-level packaging system A is shown.

[0088] In another embodiment, multiple board-level packaging structures A can be electrically connected through the optical fiber 40 of the photoelectric conversion chip 38 to form Fig.16 Board-level packaging system A is shown.

[0089] It should be noted that, in this embodiment, there is no specific limitation on the electrical connection method between the multiple board-level packaging structures 100, and it can be selected according to actual needs.

[0090] It should be further explained that there is no specific requirement for the number of board-level packaging structures 100 in the board-level packaging system A, and the number can be selected according to the size of the board-level packaging structure.

[0091] The board-level packaging system of the disclosed embodiment includes at least one board-level packaging structure as described above. The board-level packaging structure adopts a large-area square panel, which significantly improves the chip capacity, area utilization and I / O density, and significantly improves the system performance, thereby solving the problem of limited performance of a single SoW system and achieving high computing power integration; the chip computing layer achieves high-density interconnection with the help of multiple bridge chips, and no longer needs to rely on building a fine circuit structure in the RDL.

[0092] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the embodiments of the present disclosure, but the embodiments of the present disclosure are not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the embodiments of the present disclosure, and these modifications and improvements are also considered to be within the protection scope of the embodiments of the present disclosure.

Claims

1. A board-level packaging structure, characterized in that: include: Square panels; A plurality of bridge chips are arranged on the surface of the square panel; A plastic packaging layer, disposed on the surface of the square panel and wrapping the plurality of bridge chips; A redistribution layer is disposed on a surface of the plastic packaging layer away from the square panel and a bump surface of the bridge chip, and is electrically connected to the bridge chip; The chip operation layer and the connection module are both arranged on the redistribution layer and electrically connected to the redistribution layer.

2. The board-level packaging structure according to claim 1, characterized in that: It also includes a plurality of data relay chips, which are arranged on the surface of the square panel and wrapped in the plastic sealing layer.

3. The board-level packaging structure according to claim 1, characterized in that: The square panel is a glass panel.

4. The board-level packaging structure according to any one of claims 1 to 3, characterized in that: The connection module includes a plurality of connectors arranged on the redistribution layer and cables arranged on the connectors.

5. The board-level packaging structure according to any one of claims 1 to 3, characterized in that: The connection module further includes a plurality of photoelectric conversion chips arranged on the redistribution layer and optical fibers arranged on the photoelectric conversion chips.

6. A board-level packaging method, characterized in that: The packaging method comprises: Available in square panels; Mounting a plurality of bridge chips on the surface of the square panel; Forming a plastic encapsulation layer on the surface of the square panel to wrap the plurality of bridge chips, and thinning the plastic encapsulation layer to expose the bumps of the bridge chip; forming a redistribution layer on the surface of the plastic packaging layer away from the square panel and the surface of the bump; The chip operation layer and the connection module are mounted on the rewiring layer.

7. The board-level packaging method according to claim 6, characterized in that: When mounting a plurality of bridge chips on the surface of the square panel, the method further comprises: A plurality of data relay chips are mounted on the surface of the square panel.

8. The board-level packaging method according to claim 6, characterized in that: Mounting the connection module on the redistribution layer includes: Mounting a plurality of connectors provided with cables on the redistribution layer; or, A plurality of photoelectric conversion chips provided with optical fibers are mounted on the redistribution layer.

9. The board-level packaging method according to any one of claims 6 to 8, characterized in that: The square panel is a glass panel.

10. A board-level packaging system, characterized in that: Comprising at least one board-level packaging structure according to any one of claims 1 to 5; wherein, When the board-level packaging system includes a plurality of board-level packaging structures, the plurality of board-level packaging structures are electrically connected through the connection module.

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