A board level package structure and package system

Abstract

The embodiment of the present disclosure provides a board-level packaging structure and a packaging system. The board-level packaging structure comprises a plurality of board-level packaging units which are electrically connected to each other. Each board-level packaging unit comprises a square panel, a plastic packaging layer, a plurality of bridge chips, a chip operation module, a first connection module, a power management module and a second connection module. The square panel is provided with a first vertical interconnection structure penetrating through the thickness of the square panel. The plastic packaging layer is arranged on the first surface of the square panel. The plastic packaging layer is provided with a second vertical interconnection structure penetrating through the thickness of the plastic packaging layer and electrically connected to the first vertical interconnection structure. The bridge chips are arranged on the first surface of the square panel and wrapped in the plastic packaging layer. The chip operation module and the first connection module are arranged on the side of the plastic packaging layer away from the square panel. The power management module and the second connection module are arranged on the second surface of the square panel. The structure adopts a square panel, significantly improves the system performance, realizes high computing power integration, realizes back vertical power supply through a double-sided connection structure, and effectively shortens the transmission path.

Description

TECHNICAL FIELD

[0001] The embodiment of the present disclosure belongs to the technical field of semiconductor packaging, and particularly relates to a board-level packaging structure and a packaging system. BACKGROUND

[0002] SoW (System on wafer) is to integrate a certain number of computing chips onto a whole wafer as a whole to form a HPC (High Performance Computing) chip system.

[0003] SoW is to reconfigure computing chips into a wafer by using FO technology with a glass carrier as a carrier, to complete interconnection between chips through plastic packaging and re-wiring, to peel off the carrier, and to form the whole SoW system by interconnecting power devices with computing chips in a flip-chip manner on the reconfigured wafer.

[0004] Due to the limitation of wafer size, the overall performance of a single SoW system is limited.

[0005] In view of the above problems, it is necessary to provide a board-level packaging structure and a packaging system which are reasonable in design and effective in solving the above problems. SUMMARY

[0006] The embodiment of the present disclosure aims to at least solve one of the technical problems existing in the prior art, and provides a board-level packaging structure and a packaging system.

[0007] The embodiment of the present disclosure provides a board-level packaging structure, comprising:

[0008] a square panel, which is provided with a plurality of first vertical interconnection structures penetrating through the thickness thereof;

[0009] a plastic packaging layer, which is arranged on the first surface of the square panel, and is provided with a plurality of second vertical interconnection structures penetrating through the thickness thereof and electrically connected with the first vertical interconnection structures;

[0010] a plurality of bridge chips, which are arranged on the first surface of the square panel and wrapped in the plastic packaging layer;

[0011] a chip operation module and a first connection module, which are arranged on the side of the plastic packaging layer away from the square panel, and are electrically connected with the bridge chips and the second vertical interconnection structures, respectively;

[0012] a power management module and a second connection module, which are arranged on the second surface of the square panel and are electrically connected with the first vertical interconnection structures.

[0013] Optionally, the chip operation module comprises a first re-wiring layer and a chip operation layer.

[0014] The first redistribution layer is arranged on a surface of the plastic package layer away from the square panel and is electrically connected with the bridge chip and the second vertical interconnection structure respectively.

[0015] The chip operation layer is arranged on the first redistribution layer and is electrically connected with the first redistribution layer.

[0016] Optionally, the chip operation layer includes a plurality of computing chips, or the chip operation layer includes a plurality of computing chips and a plurality of storage chips.

[0017] Optionally, the first connection module includes a plurality of first connectors arranged on the first redistribution layer and a first cable arranged on the first connectors.

[0018] Optionally, the first connection module further includes a plurality of optoelectronic conversion chips arranged on the first redistribution layer and an optical fiber arranged on the optoelectronic conversion chips.

[0019] Optionally, the power management module includes a second redistribution layer and a power management chip.

[0020] The second redistribution layer is arranged on a second surface of the square panel and is electrically connected with the first vertical interconnection structure.

[0021] The power management chip is arranged on the second redistribution layer and is electrically connected with the second redistribution layer.

[0022] Optionally, the second connection module is arranged on the second redistribution layer and is electrically connected with the second redistribution layer.

[0023] Optionally, the second connection module includes a plurality of second connectors arranged on the second redistribution layer and a second cable arranged on the second connectors.

[0024] Optionally, the square panel is a glass panel.

[0025] Another aspect of the embodiments of the present disclosure provides a board-level packaging system including at least one board-level packaging structure as described above.

[0026] When the board-level packaging system includes a plurality of board-level packaging structures, the plurality of board-level packaging structures are electrically connected through the first connection module and the second connection module respectively.

[0027] The board-level packaging structure and packaging system of the embodiments of the present disclosure, the board-level packaging structure adopts a large-area square panel, significantly improves the chip capacity, area utilization rate and I / O density, significantly improves the system performance, thereby solving the problem of limited performance of a single SoW system, and realizing high-computing power integration; the chip computing module realizes high-density interconnection with the aid of multiple bridge chips, and no longer needs to rely on constructing a fine line structure in the RDL; the first surface of the square panel is provided with the chip computing module and the first connecting module, the second surface of the square panel is provided with the power management module and the second connecting module, and the back surface of the square panel is vertically powered through the first vertical interconnection structure and the second vertical interconnection structure, thereby effectively shortening the transmission path. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 A cross-sectional view of a board-level packaging structure according to an embodiment of the present disclosure;

[0029] Figure 2 A cross-sectional view of a board-level packaging structure according to another embodiment of the present disclosure;

[0030] Figure 3 A plan view of a board-level packaging structure according to another embodiment of the present disclosure;

[0031] Figure 4 A structural schematic diagram of a board-level packaging system according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] In order for those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, the embodiments of the present disclosure are further described in detail below with reference to the drawings and specific embodiments.

[0033] As shown in the drawings, Figures 1 to 3 The embodiments of the present disclosure provide a board-level packaging structure 100, which includes a square panel 22, multiple bridge chips 24, a plastic encapsulation layer 26, a chip computing module, a first connecting module, a power management module and a second connecting module.

[0034] The square panel 22 is provided with multiple first vertical interconnection structures 46 penetrating the thickness thereof.

[0035] Specifically, preferably, in the present embodiment, the square panel 22 adopts a glass panel. In the prior art, the carrier plate is stripped in the packaging process, and the final packaging structure does not contain the carrier plate. However, the board-level packaging structure of the embodiments of the present disclosure retains the square glass panel, effectively controls the warping of the board-level packaging structure by using the rigidity of the glass panel, solves the problem of mismatch between large-area EMC and chip CTE, and improves the reliability of the board-level packaging structure.

[0036] That is, in the embodiment, the first vertical interconnection structure 46 can be a TGV via, through which electrical connection of the components on both sides of the square panel 22 can be achieved.

[0037] The plastic package layer 26 is arranged on the first surface of the square panel 22, and the plastic package layer 26 is provided with a plurality of second vertical interconnection structures 48 penetrating through the thickness thereof and electrically connected with the first vertical interconnection structure 46.

[0038] Specifically, as shown in Figure 1 and Figure 2 , the plastic package layer 26 is arranged on the top surface of the square panel 22. In the embodiment, the second vertical interconnection structure 48 can be a TMV via. Through the TMV via, electrical connection of the components on both sides of the plastic package layer 26 can be achieved.

[0039] The plurality of bridge chips 24 are arranged on the first surface of the square panel 22 and wrapped in the plastic package layer 26. Specifically, as shown in Figure 1 and Figure 2 , the plurality of bridge chips 24 are arranged on the top surface of the square panel 22 and wrapped in the plastic package layer 26.

[0040] The chip computing module and the first connection module are arranged on the side of the plastic package layer 26 away from the square panel 22, and are electrically connected with the bridge chip 24 and the second vertical interconnection structure 48, respectively.

[0041] The power management module and the second connection module are arranged on the second surface of the square panel 22 and are electrically connected with the first vertical interconnection structure 46. Specifically, as shown in Figure 2 and Figure 3 , the power management module and the second connection module are arranged on the bottom surface of the square panel 22 and are electrically connected with the first vertical interconnection structure 46.

[0042] It should be noted that the first connection module and the second connection module are used for electrical connection between a plurality of board-level package structures.

[0043] The board-level package structure of the embodiment of the present disclosure adopts a large-area square panel, significantly improves the chip capacity, area utilization rate and I / O density, significantly improves the system performance, thereby solving the problem of limited performance of a single SoW system, and realizing high-computing power integration; the chip computing module realizes high-density interconnection with the aid of a plurality of bridge chips, and no longer needs to rely on constructing fine line structures in the RDL; the first surface of the square panel is provided with the chip computing module and the first connection module, the second surface of the square panel is provided with the power management module and the second connection module, and the back surface of the square panel is vertically powered through the first vertical interconnection structure and the second vertical interconnection structure, effectively shortening the transmission path.

[0044] For example, as shown in Figures 1 to 3As shown in

[0045] As shown in Figure 1 and Figure 2 The chip operation module includes a first rewiring layer and a chip operation layer 32.

[0046] The first rewiring layer is arranged on the surface of the encapsulation layer 26 away from the square panel 22 and is electrically connected with the bridge chip 24 and the second vertical interconnection structure 48 respectively.

[0047] The chip operation layer 32 is arranged on the first rewiring layer and is electrically connected with the first rewiring layer.

[0048] In the embodiment, the chip operation layer 32 can include only a plurality of computing chips, or the chip operation layer 32 can include a plurality of computing chips and a plurality of storage chips. Of course, the chip operation layer 32 can also adopt other types of chips. The chips in the chip operation layer 32 are electrically interconnected through the first rewiring layer and the bridge chip 24. According to the area of the square panel 22, the chip operation layer 32 is distributed in a matrix, which can significantly improve the chip capacity, area utilization and I / O density of the entire packaging structure.

[0049] It should be noted that the type and number of the chip operation layer 32 are not specifically limited and can be selected according to actual needs.

[0050] As shown in Figure 1 and Figure 2 The first rewiring layer includes a first dielectric layer 28 and a first metal layer 30. The first dielectric layer 28 is arranged on the surface of the encapsulation layer 26 away from the square panel 22, the functional surface of the bridge chip 24 and the surface of the second vertical interconnection structure 48 away from the square panel 22. The first dielectric layer 28 is provided with a plurality of first openings, and the first metal layer 30 is arranged in the first openings. The first metal layer 30 is electrically connected with the bridge chip 24 and the second vertical interconnection structure 48 respectively. In the embodiment, the first dielectric layer 28 can adopt a PI layer, and the first metal layer 30 can adopt a copper metal layer.

[0051] In the embodiment, by arranging the first rewiring layer, high-density interconnection of the chip operation layer can be realized.

[0052] As shown in Figure 1 In an embodiment, the first connection module includes a plurality of first connectors 34 arranged on the first rewiring layer and a first cable 36 arranged on the first connector 34.

[0053] Specifically, as shown in Figure 1 a plurality of first connectors 34 are arranged on the first metal layer 30 of the edge region of the square panel 22, and each first connector 34 is arranged with a first cable 36.

[0054] It should be noted that the number of first connectors 34 is not specifically limited in this embodiment, and can be selected according to actual needs.

[0055] Exemplarily, as shown in Figure 2 in another embodiment, the first connection module further includes a plurality of photoelectric conversion chips 38 arranged on the first redistribution layer and optical fibers 40 arranged on the photoelectric conversion chips 38.

[0056] Specifically, as shown in Figure 2 a plurality of photoelectric conversion chips 38 are arranged on the first metal layer 30 of the edge region of the square panel 22, and each photoelectric conversion chip 38 is arranged with an optical fiber 40.

[0057] It should be noted that the number of photoelectric conversion chips 38 is not specifically limited, and can be selected according to actual needs.

[0058] It should be further noted that the specific type of the first connection module is not specifically limited, and can be selected according to actual needs.

[0059] Exemplarily, as shown in Figure 1 and Figure 2 the power management module includes a second redistribution layer and a power management chip 56. The second redistribution layer is arranged on the second surface of the square panel 22 and is electrically connected with the first vertical interconnection structure 46. The power management chip 56 is arranged on the second redistribution layer and is electrically connected with the second redistribution layer.

[0060] In this embodiment, the second redistribution layer can realize high-density interconnection of the power management chip, and the plurality of power management chips arranged on the second surface of the square panel can realize back vertical power supply of the square panel, effectively shortening the transmission path.

[0061] Exemplarily, as shown in Figure 1 and Figure 2 the second redistribution layer includes a second dielectric layer 52 and a second metal layer 53. The second dielectric layer 52 is arranged on the second surface of the square panel 22 and the surface of the first vertical interconnection structure 46 facing the power management chip 56. Among them, the second dielectric layer 52 is arranged with a plurality of second openings, and the second metal layer 54 is arranged in the second openings. In this embodiment, the second dielectric layer 52 can adopt a PI layer, and the second metal layer 54 can adopt a copper metal layer.

[0062] Exemplarily, as shown in Figure 1 and Figure 2 The second connection module is arranged on the second redistribution layer and is electrically connected with the second redistribution layer. Specifically, the second connection module is arranged on the second metal layer 54 and is electrically connected with the second metal layer 54.

[0063] Exemplarily, as shown in Figure 1 and Figure 2 The second connection module includes a plurality of second connectors 34' arranged on the second redistribution layer and a second cable 36' arranged on the second connectors 34'.

[0064] It should be noted that, as shown in Figure 1 and Figure 2 In this embodiment, the plurality of second connectors 34' can be distributed apart from the power management chip 56, of course, the plurality of second connectors 34' can be arranged on the edge region of the second surface of the square panel 22. The number and distribution mode of the second connectors 34' are not limited in this embodiment, and can be selected according to actual needs.

[0065] Exemplarily, in this embodiment, the square panel 22 can be a glass panel.

[0066] In the prior art, the carrier plate is peeled off in the packaging process, and the final packaging structure does not contain the carrier plate. The board-level packaging structure of the embodiment of the present disclosure retains the square glass panel, effectively controls the warping of the board-level packaging structure by the rigidity of the glass panel, solves the problem of mismatching between the large-area EMC and the chip CTE in the prior art, and improves the reliability of the board-level packaging structure. In addition, a plurality of first vertical interconnection structures are arranged on the retained square panel, realizing vertical interconnection of the packaging structure and effectively shortening the transmission path.

[0067] As shown in Figure 4 Another aspect of the embodiment of the present disclosure provides a board-level packaging system A, which includes at least one board-level packaging structure 100 described above. Wherein, the specific structural features of the board-level packaging structure 100 have been described in detail above, and will not be repeated here.

[0068] Wherein, when the board-level packaging system A includes a plurality of board-level packaging structures 100, the plurality of board-level packaging structures 100 are respectively electrically connected through the first connection module and the second connection module.

[0069] As shown in Figure 1 In an embodiment, the plurality of board-level packaging structures 100 are respectively electrically connected through the first cable 36 and the second cable 36', forming the board-level packaging system A as shown in Figure 4

[0070] As shown in Figure 2 ​As shown, in another embodiment, the plurality of board-level packaging structures 100 are respectively electrically connected through the optical fiber 40 and the second cable 36' to form Figure 4 The board-level packaging system A is shown.

[0071] It should be noted that in this embodiment, the electrical connection mode between the plurality of board-level packaging structures 100 is not specifically limited and can be selected as needed.

[0072] It should be further noted that the number of board-level packaging structures 100 in the board-level packaging system A is not specifically required and can be selected according to the size of the board-level packaging structure.

[0073] The board-level packaging system of the embodiments of the present disclosure includes at least one board-level packaging structure as described above, which uses a large-area square panel to significantly improve the chip capacity, area utilization rate, and I / O density, significantly improve the system performance, thereby solving the problem of limited performance of a single SoW system and realizing high computing power integration. The chip computing layer realizes high-density interconnection with the aid of a plurality of bridge chips, and no longer needs to rely on constructing a fine line structure in the RDL. The first surface of the square panel is provided with a chip computing module and a first connection module, and the second surface of the square panel is provided with a power management module and a second connection module, and the back of the square panel is vertically powered through the first vertical interconnection structure and the second vertical interconnection structure, effectively shortening the transmission path.

[0074] It can be understood that the above embodiments are only exemplary embodiments adopted to illustrate the principles of the embodiments of the present disclosure, but the embodiments of the present disclosure are not limited thereto. Various modifications and improvements can be made by those of ordinary skill in the art without departing from the spirit and essence of the embodiments of the present disclosure, and these modifications and improvements are also considered within the protection scope of the embodiments of the present disclosure.

Claims

1. A board-level packaging structure, characterized in that, The application relates to a square panel provided with a plurality of first vertical interconnection structures penetrating through the thickness of the square panel; a plastic sealing layer provided on the first surface of the square panel, the plastic sealing layer being provided with a plurality of second vertical interconnection structures penetrating through the thickness of the plastic sealing layer and electrically connected with the first vertical interconnection structures; a plurality of bridge chips provided on the first surface of the square panel and wrapped in the plastic sealing layer; a chip operation module and a first connecting module provided on the side of the plastic sealing layer away from the square panel and electrically connected with the bridge chips and the second vertical interconnection structures respectively; wherein the chip operation module comprises a first rewiring layer and a chip operation layer; the first rewiring layer is provided on the surface of the plastic sealing layer away from the square panel and is electrically connected with the bridge chips and the second vertical interconnection structures respectively; the chip operation layer is provided on the first rewiring layer and is electrically connected with the first rewiring layer; the chip operation layer comprises a plurality of computing chips or a plurality of computing chips and a plurality of storage chips; the first connecting module comprises a plurality of first connectors provided on the first rewiring layer and a first cable provided on the first connectors; and / or the first connecting module further comprises a plurality of photoelectric conversion chips provided on the first rewiring layer and an optical fiber provided on the photoelectric conversion chips; a power management module and a second connecting module are provided on the second surface of the square panel and are electrically connected with the first vertical interconnection structures; wherein the power management module comprises a second rewiring layer and a power management chip; the second rewiring layer is provided on the second surface of the square panel and is electrically connected with the first vertical interconnection structures; the power management chip is provided on the second rewiring layer and is electrically connected with the second rewiring layer; the second connecting module is provided on the second rewiring layer and is electrically connected with the second rewiring layer; the second connecting module comprises a plurality of second connectors provided on the second rewiring layer and a second cable provided on the second connectors, wherein the second connectors are distributed at intervals from the power management chip. The square panel is made of a glass panel. The first vertical interconnection structures are TGV through holes. The second vertical interconnection structures are TMV through holes. The chip operation module is arranged in the central region of the plastic sealing layer, and the first connecting module is arranged in the edge region of the plastic sealing layer. The first rewiring layer comprises a first dielectric layer and a first metal layer. The first dielectric layer is arranged on the surface of the plastic sealing layer away from the square panel, the functional surface of the bridge chip and the surface of the second vertical interconnection structure away from the square panel. The first dielectric layer is provided with a plurality of first openings, and the first metal layer is arranged in the first openings; wherein the first metal layer is electrically connected with the bridge chips and the second vertical interconnection structures respectively. The second rewiring layer comprises a second dielectric layer and a second metal layer.

2. The package-on-board structure of claim 1, wherein, The second dielectric layer is arranged on the second surface of the square panel and the surface of the first vertical interconnection structure facing the power management chip.

3. The package-on-board structure of claim 1, wherein, ​ 4. The package-on-package structure of claim 1, wherein, ​ 5. The package-on-board structure of claim 1, wherein, ​ 6. The package-on-package structure of claim 1, wherein, ​ ​ ​ 7. The package-on-package structure of claim 1, wherein, ​ ​ The second dielectric layer is provided with a plurality of second openings, and the second metal layer is arranged in the second openings.

8. A system for a board level package, comprising: The board-level package structure comprises at least one board-level package structure according to any one of claims 1 to 7; wherein, When the board-level package system comprises a plurality of board-level package structures, the first connection module and the second connection module are respectively arranged between the plurality of board-level package structures for electrical connection.

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