Semiconductor device and method for measuring positional deviation of semiconductor device

Abstract

The invention provides a semiconductor device capable of easily measuring position deviation of two kinds of flip-chip connected chips. The semiconductor device includes a first substrate and a second substrate mounted on top of each other, the first substrate including a plurality of conductive first pads, a plurality of conductive second pads, and a conductive member, the second substrate including a plurality of conductive third pads, and a plurality of conductive fourth pads, the first substrate further including a first measurement pad, a second measurement pad, and a second measurement pad. A measurement unit which is connected to at least one of the plurality of third pads and measures whether the third pads are electrically connected to the fourth pads via the first pads, the conductive member, and the second pads; and a second measurement pad connected to at least one of the plurality of fourth pads and configured to confirm whether the third pad is electrically connected to the fourth pads via the first pad, the conductive member, and the second pad.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for measuring position deviation of the semiconductor device. Background Art

[0002] In the past, there is a known process of overlapping two chips. Patent document 1 discloses a plurality of substrates for flip chip connection. In order to improve the yield rate of flip chip connection, the plurality of substrates have two or more cross-shaped alignment marks (see Patent document 1). Figure 5 ).

[0003] When metal wiring is formed on each of a plurality of substrates, an alignment mark is formed on each substrate as a TEG (Test Elementary Group) pattern simultaneously with the metal wiring. Therefore, the alignment mark formed on each substrate determines the relative positional relationship with the metal wiring. In order to measure the relative positional deviation (hereinafter, positional deviation) between the alignment mark of one substrate and the alignment mark of another substrate, a laser microscope is generally used.

[0004] Patent Document 1: Japanese Patent Application Laid-Open No. 09-321086

[0005] However, in the prior art, a laser microscope is used to measure the position deviation of the alignment mark, which requires the setting and maintenance of the laser microscope, and thus sometimes cannot meet the demand for further shortening the manufacturing time of semiconductor devices. Thus, there is room for improvement in measuring the position deviation of two chips (substrates) connected by flip-chip. Summary of the invention

[0006] In view of the above circumstances, an object of the present disclosure is to provide a semiconductor device capable of easily measuring the positional deviation of two chips connected by flip-chip connection, and a method for measuring the positional deviation of the semiconductor device.

[0007] In order to solve the above-mentioned problems, the semiconductor device disclosed in the present invention is a semiconductor device comprising a first substrate and a second substrate which are mounted in an overlapping manner, wherein the first substrate comprises: a plurality of conductive first pads which are arranged on the substrate surface in a first direction parallel to the substrate surface of the first substrate when the first substrate is viewed from a specific direction, and are separated from each other; a plurality of conductive second pads which are arranged on the substrate surface in a second direction which is different from the first direction and is parallel to the substrate surface when the first substrate is viewed from the specific direction, and are separated from each other; and a conductive component which is arranged on the substrate surface and electrically connects the plurality of the first pads and the second pads, and the second substrate comprises: a plurality of conductive third pads which are arranged on the substrate surface in a second direction which is different from the first direction and is parallel to the substrate surface when the first substrate is viewed from the specific direction. when the second substrate is looked down upon from the above-mentioned specific direction, the second substrate is arranged on an opposite surface thereof which is opposite to the first substrate and is separated from each other in the above-mentioned first direction; a plurality of conductive fourth pads are arranged on the opposite surface and are separated from each other in the above-mentioned second direction when the second substrate is looked down upon from the above-mentioned specific direction; a first measuring pad is connected to at least one of the plurality of the third pads, and measures whether the third pad is electrically connected to the fourth pad via the first pad, the conductive component and the second pad; and a second measuring pad is connected to at least one of the plurality of the fourth pads, and is used to confirm whether the third pad is electrically connected to the fourth pad via the first pad, the conductive component and the second pad.

[0008] In the position deviation measurement method of the semiconductor device disclosed in the present invention, the semiconductor device comprises a first substrate and a second substrate which are mounted in an overlapping manner, the first substrate comprising: a plurality of conductive first pads which are arranged on the substrate surface in a first direction parallel to the substrate surface of the first substrate when the first substrate is viewed from a specific direction; a plurality of conductive second pads which are arranged on the substrate surface in a second direction which is different from the first direction and parallel to the substrate surface when the first substrate is viewed from the specific direction; and a conductive component which is provided on the substrate surface and electrically connects the plurality of the first pads and the second pads, the second substrate comprising: a plurality of conductive third pads which are arranged on a surface of the second substrate which is opposite to the first substrate in the first direction when the second substrate is viewed from the specific direction; a plurality of conductive fourth pads which are arranged on the surface of the second substrate which is opposite to the first substrate in the second direction when the second substrate is viewed from the specific direction; a first measurement pad which is arranged on the plurality of the third pads The method for measuring the position deviation of the semiconductor device comprises: a step of determining whether any one of the plurality of third pads is conductive with any one of the plurality of fourth pads by using a measuring device connected to the first measurement pad and the second measurement pad; and a step of determining, when any one of the plurality of third pads is not conductive with any one of the plurality of fourth pads, determining that the deviation amount between the first chip formed on the first substrate and the second chip formed on the second substrate is within a specific range, and when any one of the plurality of third pads is conductive with any one of the plurality of fourth pads, determining that the position deviation amount between the first chip and the second chip is outside the specific range.

[0009] According to the present disclosure, it is possible to provide a semiconductor device capable of easily measuring the positional deviation of two chips connected by flip-chip connection, and a method for measuring the positional deviation of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is a diagram showing the structure of a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 2 It is a diagram showing the structure of a semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 3 Is magnification Figure 1 A diagram near the bump shown.

[0013] Figure 4 It is a figure which shows an example of an alignment mark.

[0014] Figure 5 It is a diagram showing a structural example of a measurement structure.

[0015] Figure 6 This is a flowchart for explaining the method for measuring position deviation of a semiconductor device according to the present disclosure.

[0016] Figure 7 It is a diagram for explaining the method of measuring the positional deviation of the semiconductor device of the present disclosure.

[0017] Figure 8 It is a diagram for explaining the method of measuring the position deviation of the semiconductor device of the present disclosure.

[0018] Fig. 9 It is a diagram for explaining the method of measuring the positional deviation of the semiconductor device of the present disclosure.

[0019] Fig.10 This is a block diagram showing the hardware configuration of the position deviation measuring device.

[0020] Fig.11 It is a diagram showing the functional blocks of the position deviation measuring device.

[0021] Description of Reference Numerals

[0022] 10…first substrate; 10a…opposing surface; 11…first pad; 12A…measurement procedure; 12…second pad; 13…conductive component; 13A…storage unit; 13a…first extension unit; 13b…second extension unit; 14…display; 15…input device; 16…memory; 18…bus; 20…second substrate; 20a…opposing surface; 21…third pad; 22…fourth pad; 23…first measurement pad; 24…second measurement pad; 30…bump; 40…measurement structure; 50…alignment mark; 51…first alignment mark; 51a…center; 52…second alignment mark; 52a…center; 100…semiconductor device; 200…measurement device; 201…input unit; 202…conduction determination unit; 203…deviation determination unit DETAILED DESCRIPTION

[0023] Hereinafter, the embodiments will be described based on the drawings. In addition, the same or similar reference numerals are attached to the same functions and structures, and the description thereof will be appropriately omitted.

[0024] (Implementation Method)

[0025] Figure 1 and Figure 2 It is a diagram showing a configuration example of a semiconductor device according to an embodiment of the present disclosure. Figure 1 A cross-sectional view showing the semiconductor device 100 is shown. Figure 2 The appearance of the semiconductor device 100 is shown.

[0026] like Figure 1 As shown, the semiconductor device 100 may include a first substrate 10 and a second substrate 20 which are stacked and mounted in a vertical manner. The first substrate 10 may be interpreted as a first chip substrate. The second substrate 20 may be interpreted as a second chip substrate. Up and down may be interpreted as a relative positional relationship in a direction D which is a specific direction.

[0027] In the process, the first substrate 10 and the second substrate 20 are closely connected by the bumps 30 arranged in an array. Specifically, after the first substrate 10 on which a specific integrated circuit (e.g., a SEED chip) as a first chip is mounted is reversed (flipped) 180 degrees, when it is overlapped with the second substrate 20 on which another integrated circuit (e.g., a POT chip) as a second chip is mounted, the first substrate 10 and the second substrate 20 are closely connected by the bumps 30 arranged in an array. In this way, the two chips can be electrically connected.

[0028] The bump 30 may be interpreted as a protruding electrode. A plurality of bumps 30 may be arranged in a direction D1. The direction D1 may be interpreted as a direction orthogonal to the direction D. Furthermore, a plurality of bumps 30 may be arranged in a direction D2. The direction D2 may be interpreted as a direction orthogonal to both the direction D and the direction D1.

[0029] The semiconductor device 100 may include a measurement structure 40 and an alignment mark 50 . The measurement structure 40 and the alignment mark 50 may be provided between the first substrate 10 and the second substrate 20 .

[0030] The alignment mark 50 may include a first alignment mark and a second alignment mark.

[0031] The first alignment mark may be provided on the substrate surface of the first substrate 10. The substrate surface of the first substrate 10 may be interpreted as the opposite surface 10a of the first substrate 10 that is opposite to the second substrate 20 (see Figure 2 ).

[0032] The second alignment mark may be provided on the substrate surface of the second substrate 20. The substrate surface of the second substrate 20 may be interpreted as the opposite surface 20a of the second substrate 20 that is opposite to the first substrate 10 (see Figure 2 ). Specific examples of the first alignment mark and the second alignment mark will be described later.

[0033] Figure 3 Is magnification Figure 1It is assumed that by overlapping the first substrate 10 and the second substrate 20, the first substrate 10 is slightly deviated from a specific position of the second substrate 20 in one or both of the directions D1 and D2. Figure 3 The diagram shows a state where a plurality of electrodes respectively provided on the first substrate 10 and the second substrate 20 are slightly offset. The electrodes may include conductors respectively provided on the first substrate 10 and the second substrate 20 and the above-mentioned bumps 30.

[0034] In this way, even in the case of positional deviation of the electrodes, as long as the positional deviation of the electrodes is within a specific range, the conduction between the chip of the first substrate 10 and the chip of the second substrate 20 can be ensured. On the other hand, if the positional deviation of the electrodes is outside the specific range, there is a high possibility that the conduction between the chip of the first substrate 10 and the chip of the second substrate 20 cannot be ensured. Therefore, the yield rate of the flip-chip connection may be reduced. In the prior art, in order to suppress the reduction in the yield rate of the flip-chip connection, the positional deviation of the first alignment mark relative to the second alignment mark is measured using a laser microscope.

[0035] Figure 4 2 is a diagram showing an example of an alignment mark. Figure 4 The measurement structure 40 and the alignment mark 50 are shown on the upper side. In the direction D, when the substrates are viewed from the first substrate 10 toward the second substrate 20, the measurement structure 40 and the alignment mark 50 are arranged between the first substrate 10 and the second substrate 20. The alignment mark 50 can be arranged near the measurement structure 40. Figure 4 The lower side is enlarged to show Figure 4 The alignment mark 50 is shown on the upper side.

[0036] The alignment mark 50 may include a first alignment mark 51 and a second alignment mark 52 in a cross shape. When metal wiring is formed on the substrate, these marks are formed as TEG patterns simultaneously with the metal wiring, so that the relative positional relationship with the metal wiring can be determined. In order to measure the positional deviation of the first alignment mark 51 relative to the second alignment mark 52, a laser microscope is generally used in the prior art.

[0037] The semiconductor device 100 of the present disclosure includes a measurement structure 40, and the presence or absence of positional deviation of electrodes or two substrates, the amount of positional deviation, etc. can be measured by changing the conduction state of a plurality of conductive components constituting the measurement structure 40, that is, changing the electrical connection state of the components. In other words, the presence or absence of positional deviation of electrodes or substrates, the amount of positional deviation, etc. can be measured without using a laser microscope.

[0038] The following reference Figure 5 The structure of the measurement structure 40 will be described specifically. Figure 5is a diagram showing an example of a measurement structure. Figure 5 , the measurement structure 40 is shown when the first substrate 10 is viewed from above. Specifically, the measurement structure 40 is shown when the first substrate 10 is viewed from above toward the second substrate 20 in the direction D. The measurement structure 40 may be provided between the first substrate 10 and the second substrate 20. The measurement structure 40 may be composed of a plurality of conductive components provided on the first substrate 10 and the second substrate 20, respectively.

[0039] (First Substrate 10)

[0040] The first substrate 10 may include a plurality of first pads 11, a plurality of second pads 12, a conductive member 13 having a specific shape, and a first alignment mark 51. The specific shape may be interpreted as an L-shape.

[0041] (First pad 11)

[0042] Each of the plurality of first pads 11 may be interpreted as a conductive terminal, wiring or electrode. The plurality of first pads 11 may be provided on the first extension portion 13a of the conductive component 13. Specifically, the plurality of first pads 11 may be provided on the surface of the first extension portion 13a of the conductive component 13 on the side opposite to the first substrate 10 side. The surface on the side opposite to the first substrate 10 side may be interpreted as the surface of the first extension portion 13a facing the second substrate 20. It may be electrically connected to the first extension portion 13a. The detailed structure of the conductive component 13 will be described later.

[0043] The plurality of first pads 11 may be arranged on the substrate surface of the first substrate 10 (the surface of the first extension portion 13a facing the second substrate 20) separated from each other in the direction D1. The direction D1 may be interpreted as a first direction on an imaginary plane parallel to the substrate surface of the first substrate 10 when the first substrate 10 is viewed from above. The substrate surface of the first substrate 10 may be interpreted as the opposing surface 10a of the first substrate 10 facing the second substrate 20 (see Figure 2 ).

[0044] The plurality of first pads 11 may be arranged on a first imaginary line extending in the direction D1. The first imaginary line may be interpreted as an imaginary line passing through the vicinity of the center of each of the plurality of first pads 11 in the direction D2 and parallel to the arrangement direction of the pads. The first imaginary line may be interpreted as passing through the center portion 51a of the first alignment mark 51 (see Figure 4 ) or a line near the center portion 51a.

[0045] The interval between two adjacent specific first pads 11 may be set to gradually increase from the first pad 11 closest to the virtual reference point P toward the first pad 11 farthest from the reference point P.

[0046] The reference point P can be interpreted as the first alignment mark 51 and the center portion 51a (refer to Figure 4 The central portion 51a of the first alignment mark 51 may be interpreted as the portion where the center of the first alignment mark 51 in the direction D1 overlaps with the center of the first alignment mark 51 in the direction D2.

[0047] The center portion 51 a of the first alignment mark 51 can be interpreted as a position where the first imaginary line described above and a second imaginary line described later intersect.

[0048] In order to make the positional deviation of the first chip formed on the first substrate 10 and the second chip formed on the second substrate 20 within a specific range, the spacing distance between the first pad 11 and the third pad 21 in the direction D1 can be set to the following values. That is, the arrangement positions of the first pad 11 and the third pad 21 in the direction D1 can be set to ensure these distances.

[0049] Distance Y1 = 2 μm

[0050] Distance Y2 = 4 μm

[0051] Distance Y3 = 6 μm

[0052] Distance Y4 = 8 μm

[0053] (Second pad 12)

[0054] Each of the plurality of second pads 12 may be interpreted as a conductive terminal, wiring or electrode. The plurality of second pads 12 may be provided on the second extension portion 13b of the conductive component 13. Specifically, the plurality of second pads 12 may be provided on the surface of the second extension portion 13b of the conductive component 13 on the side opposite to the first substrate 10 side. The surface on the side opposite to the first substrate 10 side may be interpreted as the surface of the second extension portion 13b facing the second substrate 20. The plurality of second pads 12 may be electrically connected to the second extension portion 13b of the conductive component 13.

[0055] The plurality of second pads 12 may be arranged on the substrate surface of the first substrate 10 (the surface of the second extension portion 13b opposite to the second substrate 20) separated from each other in the direction D2. The direction D2 may be interpreted as a second direction different from the first direction on an imaginary plane parallel to the substrate surface of the first substrate 10 when looking down at the first substrate 10. Specifically, the second direction may be interpreted as a direction orthogonal to the first direction on the imaginary plane, or may be interpreted as a direction other than the direction orthogonal to the first direction.

[0056] The plurality of second pads 12 may be arranged on a second imaginary line extending in the direction D2. The second imaginary line may be interpreted as an imaginary line passing through the vicinity of the center of each of the plurality of second pads 12 in the direction D1 and parallel to the arrangement direction of the pads. The second imaginary line may be interpreted as passing through the center portion 51a of the first alignment mark 51 (see Figure 4 ) or a line near the center portion 51a.

[0057] The interval between two adjacent specific second solder pads 12 can be set to gradually widen from the second solder pad 12 at the position closest to the imaginary reference point P (or center portion 51a) toward the second solder pad 12 at the position farthest from the reference point P (or center portion 51a).

[0058] In order to make the positional deviation of the first chip and the second chip within a specific range, the spacing distance between the second pad 12 and the fourth pad 22 in the direction D2 can be set to the following values. That is, the arrangement positions of the second pad 12 and the fourth pad 22 in the direction D2 can be set to ensure these distances.

[0059] Distance X1 = 2 μm

[0060] Distance X2 = 4 μm

[0061] Distance X3 = 6 μm

[0062] Distance X4 = 8 μm

[0063] (Conductive member 13)

[0064] The conductive component 13 can be interpreted as a conductive terminal, wiring or electrode that electrically connects the plurality of first pads 11 and the second pads 12. The conductive component 13 can also be interpreted as a component for electrically connecting the first measurement pad 23 and the second measurement pad 24. The conductive component 13 can be provided on the substrate surface of the first substrate 10. Specifically, the conductive component 13 can be provided on the opposite surface 10a of the first substrate 10 that is opposite to the second substrate 20 (see Figure 2 ).

[0065] The conductive member 13 may include a first extending portion 13 a extending in a first direction (direction D1 ), and a second extending portion 13 b extending from an end of the first extending portion 13 a toward a second direction (direction D2 ).

[0066] (First Extension 13a)

[0067] The first extension portion 13 a may have a shape extending from the reference point P to a position separated by a certain distance in the first direction. A plurality of first pads 11 may be provided at the first extension portion 13 a.

[0068] (Second Extension 13b)

[0069] The second extension portion 13 b may have a shape extending from the reference point P to a position separated by a certain distance in the second direction. A plurality of second pads 12 may be provided at the second extension portion 13 b.

[0070] (Second Substrate 20)

[0071] The second substrate 20 may include a plurality of third pads 21 , a plurality of fourth pads 22 , a first measurement pad 23 , a second measurement pad 24 , and a second alignment mark 52 .

[0072] (Third pad 21)

[0073] Each of the plurality of third pads 21 may be interpreted as a conductive terminal, wiring or electrode. The plurality of third pads 21 may be provided on the substrate surface of the second substrate 20. The plurality of third pads 21 may be arranged on the substrate surface of the second substrate 10 separated from each other in the direction D1. The plurality of third pads 21 may be arranged to overlap the first extension portion 13a of the conductive component 13 from the reference point P to a position separated by a certain distance in the first direction. The substrate surface of the second substrate 10 may be interpreted as the opposing surface 20a of the second substrate 20 that is opposite to the first substrate 10 (see Figure 2 ).

[0074] Each of the plurality of third pads 21 may be formed to be in non-electrical contact with the first extension portion 13a of the conductive component 13. Specifically, the thickness of each of the plurality of third pads 21 in the direction D may be thicker than the thickness of each of the plurality of first pads 11 in the direction D. In addition, an insulating film may be provided in a partial area (e.g., between adjacent first pads 11) within the surface of the first extension portion 13a of the conductive component 13. Thus, it is possible to prevent the third pads 21 from being in electrical contact with the first extension portion 13a of the conductive component 13 when the first substrate 10 and the second substrate 20 are overlapped.

[0075] The plurality of third pads 21 may be arranged on a third imaginary line extending in the direction D1. The third imaginary line may be interpreted as an imaginary line passing through the vicinity of the center of each of the plurality of third pads 21 in the direction D2 and parallel to the arrangement direction of the pads. The third imaginary line may be interpreted as passing through the center portion 52a of the second alignment mark 52 (refer to Figure 4 ) or a line near the center portion 52a.

[0076] The center portion 52 a of the second alignment mark 52 can be interpreted as a position where the third imaginary line described above and a fourth imaginary line described later intersect.

[0077] The interval between two adjacent specific third pads 21 can be set to gradually widen from the third pad 21 located closest to the center portion 52a of the second alignment mark 52 toward the third pad 21 located farthest from the center portion 52a of the second alignment mark 52.

[0078] (Fourth pad 22)

[0079] Each of the plurality of fourth pads 22 may be interpreted as a conductive terminal, wiring or electrode. The plurality of fourth pads 22 may be disposed on the substrate surface of the second substrate 20. The plurality of fourth pads 22 may be arranged on the substrate surface of the second substrate 20 separated from each other in the direction D2. The plurality of fourth pads 22 may be configured to overlap with the second extension portion 13b of the conductive component 13 from the reference point P to a position separated by a certain distance in the second direction.

[0080] Each of the plurality of fourth pads 22 may be formed to be in non-electrical contact with the second extension portion 13b of the conductive component 13. Specifically, the thickness of each of the plurality of fourth pads 22 in the direction D may be thicker than the thickness of each of the plurality of second pads 12 in the direction D. In addition, an insulating film may be provided in a partial area (e.g., between adjacent second pads 12) within the surface of the second extension portion 13b of the conductive component 13. Thus, it is possible to prevent the fourth pads 22 from being in electrical contact with the second extension portion 13b of the conductive component 13 when the first substrate 10 and the second substrate 20 are overlapped.

[0081] The plurality of fourth pads 22 may be arranged on a fourth imaginary line extending in the direction D2. The fourth imaginary line may be interpreted as an imaginary line passing through the vicinity of the center of each of the plurality of fourth pads 22 in the direction D1 and parallel to the arrangement direction of the pads. The fourth imaginary line may be interpreted as passing through the center portion 52a of the second alignment mark 52 (see Figure 4 ) or a line near the center portion 52a.

[0082] The interval between two adjacent specific fourth pads 22 can be set to gradually widen from the fourth pad 22 located closest to the center portion 52a of the second alignment mark 52 toward the fourth pad 22 located farthest from the center portion 52a of the second alignment mark 52.

[0083] (First measurement pad 23)

[0084] Each of the plurality of first measurement pads 23 may be interpreted as a pad for measuring whether the third pad 21 is in conduction with the fourth pad 22 via the first pad 11, the conductive member 13, and the second pad 12. Each of the plurality of first measurement pads 23 may be interpreted as a conductive terminal, wiring, or electrode.

[0085] The plurality of first measurement pads 23 may be disposed on the opposite surface 20a of the second substrate 20 that is opposite to the first substrate 10 (see Figure 2 ). The plurality of first measurement pads 23 may be arranged on the substrate surface (opposing surface 20a) of the second substrate 20 in a direction D1 and separated from each other. Each of the plurality of first measurement pads 23 may be electrically connected to at least one of the plurality of third pads 21. The positions of the plurality of first measurement pads 23 are not particularly limited, as long as they are positions that are easily connected to wiring, connectors, etc. extending from the measurement device 200.

[0086] (Second measurement pad 24)

[0087] Each of the plurality of second measurement pads 24 may be interpreted as a pad for measuring whether the third pad 21 is in conduction with the fourth pad 22 via the first pad 11, the conductive component 13 and the second pad 12. Each of the plurality of second measurement pads 24 may be interpreted as a conductive terminal, wiring or electrode.

[0088] The plurality of second measurement pads 24 may be disposed on the opposite surface 20a of the second substrate 20 that is opposite to the first substrate 10 (see Figure 2 ). The plurality of second measurement pads 24 may be arranged on the substrate surface (opposing surface 20a) of the second substrate 20 in a direction D2 separated from each other. Each of the plurality of second measurement pads 24 may be electrically connected to at least one of the plurality of fourth pads 22. The positions of the plurality of second measurement pads 24 are not particularly limited, as long as they are positions that are easily connected to wiring, connectors, etc. extending from the measurement device 200.

[0089] The measurement device 200 can be connected to the first measurement pad 23 and the second measurement pad 24. The detailed structure of the measurement device 200 will be described later.

[0090] In addition, it is preferred that the first measurement pads 23 are respectively provided on the plurality of third pads 21. In addition, it is preferred that the second measurement pads 24 are respectively provided on the plurality of fourth pads 22. Thus, a plurality of current paths can be provided. That is, a plurality of paths electrically connecting the first measurement pad 23 and the second measurement pad 24 can be provided. By providing a plurality of current paths, the flow rate of the current changes compared to the case where there is only one current path, so the measuring device 200 can estimate the positional deviation of the electrode etc. based on the current. Specifically, the measuring device 200 can calculate the positional deviation corresponding to the value of the current flowing from the first measurement pad 23 to the second measurement pad 24 by using table information that establishes a correspondence between the value of the current and the positional deviation of the electrode etc.

[0091] Next, refer to Figure 6 to Figure 9 A method for measuring the positional deviation of the semiconductor device 100 will be described. Figure 6This is a flowchart for explaining the method for measuring position deviation of a semiconductor device according to the present disclosure. Figure 7 , Figure 8 as well as Fig. 9 It is a diagram for explaining the method of measuring the position deviation of the semiconductor device of the present disclosure.

[0092] exist Figure 7 2 shows a first substrate 10 and a second substrate 20 which are mounted one on top of another so that the amount of positional deviation falls within a specific range. Figure 7 The state of the first substrate 10 and the second substrate 20 shown is similar to Figure 5 The first substrate 10 and the second substrate 20 shown in FIG. Figure 8 as well as Fig. 9 2 shows the first substrate 10 and the second substrate 20 which are mounted one on top of another so that the amount of positional deviation is outside a specific range.

[0093] The method for measuring the positional deviation of the semiconductor device 100 may include a conduction determination process for performing a conduction determination and a positional deviation amount determination process for determining the presence or absence of the positional deviation and the amount of the positional deviation.

[0094] exist Figure 6 In step S1 shown, in the conduction determination process, the current flowing through the first measurement pad 23 and the second measurement pad 24, the voltage applied to the first measurement pad 23 and the second measurement pad 24, etc. can be measured (step S1).

[0095] Next, in step S2, in the conduction determination process, it can be determined whether any one of the plurality of third pads 21 and any one of the plurality of fourth pads 22 is in a non-conducting state or a conducting state based on the measured current, etc. In other words, it can be determined whether any one of the plurality of first measurement pads 23 and any one of the plurality of second measurement pads 24 is in a non-conducting state or a conducting state.

[0096] like Figure 7 As shown, the non-conductive state may be interpreted as a situation where any of the plurality of third pads 21 is not in contact with any of the plurality of first pads 11 , or a situation where any of the plurality of fourth pads 22 is not in contact with any of the plurality of second pads 12 .

[0097] like Figure 8 as well as Fig. 9 As shown, the conduction state can be interpreted as the situation where any one of the plurality of third pads 21 contacts with any one of the plurality of first pads 11 and any one of the plurality of fourth pads 22 contacts with any one of the plurality of second pads 12. Figure 8As shown, in the case where the two third pads 21 are in contact with the two first pads 11 and the two second pads 12 are in contact with the two fourth pads 22 , two current paths A are formed.

[0098] like Figure 7 As shown, in the non-conducting state (step S2, yes), in step S3, in the position deviation determination process, it can be determined that the position deviation of the first chip formed on the first substrate 10 and the second chip formed on the second substrate 20 is within a specific range.

[0099] like Figure 8 as well as Fig. 9 As shown, in the case of the on state (step S2, No), in step S4, in the positional deviation amount determination process, it can be determined that the positional deviation amount is outside the specific range.

[0100] In the positional deviation determination process, when one or two current paths A are formed, it may be determined that the positional deviation between the first chip formed on the first substrate 10 and the second chip formed on the second substrate 20 is within a specific range. In the positional deviation determination process, when three or more current paths A are formed, it may be determined that the positional deviation is outside the specific range.

[0101] In the positional deviation determination process, it may be determined that when two current paths A are formed, the positional deviation is a specific value X (μm), when three current paths A are formed, the positional deviation is a specific value Y (μm) greater than X, and when four current paths A are formed, the positional deviation is a specific value Z (μm) greater than Y. In the positional deviation determination process, when one current path A is formed, it may be determined that the positional deviation is a specific value M (μm) less than X.

[0102] Fig.10 2 is a block diagram showing the hardware structure of the position deviation measuring device. The position deviation measuring device 200 includes a CPU (Central Processing Unit) 11, a storage unit 13A as a non-volatile memory, a display 14 such as a liquid crystal display, an input device 15, a memory 16 as a temporary storage area, and a network I / F (Interface) 17. The CPU 11, the storage unit 13A, the display 14, the input device 15, the memory 16, and the network I / F 17 are connected to a bus 18.

[0103] The CPU 11 can be interpreted as a processor. The input device 15 can include a keyboard, a mouse, and other pointing devices. The storage unit 13A can be implemented by a HDD (Hard Disk Drive), an SSD (Solid State Drive), a flash memory, and the like. The position deviation measurement program 12A is stored in the storage unit 13A. The CPU 11 can read the position deviation measurement program 12A from the storage unit 13A and expand it in the memory 16, and execute the expanded position deviation measurement program 12A.

[0104] Next, refer to Fig.11 The function of the position deviation measuring device 200 will be described. Fig.11 2 is a diagram showing the functional blocks of the position deviation measuring device. The position deviation measuring device 200 may include an input unit 201, a conduction determination unit 202, and a position deviation amount determination unit 203. The input unit 201, the conduction determination unit 202, and the position deviation amount determination unit 203 may be configured by Fig.10 This is achieved by the CPU 11 shown executing the position deviation measurement program 12A.

[0105] (Input unit 201)

[0106] The input unit 201 can input information indicating the current flowing through the first measurement pad 23 and the second measurement pad 24 , the voltage applied to these pads, and the like.

[0107] (Conduction Determination Section 202)

[0108] The conduction determination unit 202 can determine whether any one of the third pads 21 is conductively connected to any one of the fourth pads 22 based on the value of the current or the value of the voltage flowing through the first measurement pad 23 and the second measurement pad 24 .

[0109] (Position Deviation Amount Determination Unit 203)

[0110] The position deviation determination unit 203 can determine whether the position deviation between the first chip formed on the first substrate 10 and the second chip formed on the second substrate 20 is within a specific range or outside the specific range, and transmit information indicating the determination result to the display 14. The display 14 has a display control unit, and the display control unit can display the presence or absence of position deviation, the position deviation amount, etc. based on the information.

[0111] (Function, Effect)

[0112] In the semiconductor device 100 of the present disclosure, the first substrate 10 includes a plurality of first pads 11, a plurality of second pads 12, and a conductive member 13, and the second substrate 20 includes a plurality of third pads 21, a plurality of fourth pads 22, a first measurement pad 23, and a second measurement pad 24. Thus, the presence or absence of positional deviation of the chips of the first substrate 10 and the second substrate 20 mounted in an overlapping manner, the amount of positional deviation, etc. can be measured by the change in the electrical connection state of these plurality of conductive members. Therefore, the amount of positional deviation, etc. can be easily measured without using a laser microscope.

[0113] Furthermore, since a laser microscope is not required, the time associated with setting up and maintaining the laser microscope can be reduced, and the manufacturing time of the semiconductor device 100 can be further shortened. The manufacturing cost of the semiconductor device 100 can also be reduced.

[0114] In addition, regarding the above description, the following supplementary notes are disclosed.

[0115] (Supplementary Note 1) A semiconductor device comprising a first substrate and a second substrate mounted in an overlapping manner,

[0116] The first substrate comprises:

[0117] A plurality of conductive first pads are arranged on the substrate surface separated from each other in a first direction parallel to the substrate surface of the first substrate when the first substrate is viewed from a specific direction;

[0118] a plurality of conductive second pads arranged on the substrate surface separated from each other in a second direction different from the first direction and parallel to the substrate surface when the first substrate is viewed from the specific direction; and

[0119] The conductive component is disposed on the substrate surface and electrically connects the plurality of first pads and the second pads.

[0120] The second substrate comprises:

[0121] a plurality of third conductive pads arranged on a surface of the second substrate facing the first substrate and spaced apart from each other in the first direction when the second substrate is viewed from the specific direction;

[0122] A plurality of conductive fourth pads are arranged on the opposing surface in a manner separated from each other in the second direction when the second substrate is viewed from the specific direction;

[0123] a first measurement pad connected to at least one of the plurality of third pads, and measuring whether the third pad is electrically connected to the fourth pad via the first pad, the conductive component, and the second pad; and

[0124] The second measurement pad is connected to at least one of the plurality of fourth pads and is used to confirm whether the third pad is electrically connected to the fourth pad via the first pad, the conductive component and the second pad.

[0125] (Supplementary Note 2) The semiconductor device according to Supplementary Note 1, wherein:

[0126] The conductive component includes: a first extending portion extending along the first direction, and a second extending portion extending from an end of the first extending portion along the second direction.

[0127] The plurality of first pads are disposed on the first extension portion.

[0128] The plurality of second pads are disposed on the second extension portion.

[0129] The first measurement pads are respectively provided on the plurality of the third pads.

[0130] The second measurement pads are respectively provided on the plurality of fourth pads.

[0131] (Supplementary Note 3) A method for measuring position deviation of a semiconductor device,

[0132] The semiconductor device comprises a first substrate and a second substrate which are mounted in an overlapping manner.

[0133] The first substrate comprises:

[0134] A plurality of conductive first pads are arranged on the substrate surface separated from each other in a first direction parallel to the substrate surface of the first substrate when the first substrate is viewed from a specific direction;

[0135] a plurality of conductive second pads arranged on the substrate surface separated from each other in a second direction different from the first direction and parallel to the substrate surface when the first substrate is viewed from the specific direction; and

[0136] The conductive component is disposed on the substrate surface and electrically connects the plurality of first pads and the second pads.

[0137] The second substrate comprises:

[0138] a plurality of third conductive pads arranged on a surface of the second substrate facing the first substrate and spaced apart from each other in the first direction when the second substrate is viewed from the specific direction;

[0139] A plurality of conductive fourth pads are arranged on the opposing surface in a manner separated from each other in the second direction when the second substrate is viewed from the specific direction;

[0140] a first measuring pad connected to at least one of the plurality of third pads, and measuring whether the third pad is electrically connected to the fourth pad via the first pad, the conductive component and the second pad; and

[0141] The second measuring pad is connected to at least one of the plurality of fourth pads and is used to confirm whether the third pad is conductively connected to the fourth pad via the first pad, the conductive component and the second pad.

[0142] The method for measuring the position deviation of the semiconductor device comprises:

[0143] A step of using a measuring device connected to the first measuring pad and the second measuring pad to determine whether any one of the plurality of third pads is conductively connected to any one of the plurality of fourth pads; and

[0144] The step of determining that the position deviation amount between the first chip formed on the first substrate and the second chip formed on the second substrate is within a specific range when any one of the plurality of the third solder pads is not electrically connected to any one of the plurality of the fourth solder pads, and determining that the position deviation amount between the first chip and the second chip is outside the specific range when any one of the plurality of the third solder pads is electrically connected to any one of the plurality of the fourth solder pads.

Claims

1. A semiconductor device comprising a first substrate and a second substrate mounted in an overlapping manner, The first substrate comprises: A plurality of conductive first pads are arranged on the substrate surface separated from each other in a first direction parallel to the substrate surface of the first substrate when the first substrate is viewed from a specific direction; a plurality of conductive second pads arranged on the substrate surface separated from each other in a second direction different from the first direction and parallel to the substrate surface when the first substrate is viewed from the specific direction; and A conductive component is disposed on the substrate surface and electrically connects the plurality of first pads and the second pads. The second substrate comprises: a plurality of third conductive pads arranged on a surface of the second substrate facing the first substrate and spaced apart from each other in the first direction when the second substrate is viewed from the specific direction; A plurality of conductive fourth pads are arranged on the opposing surface separated from each other in the second direction when the second substrate is viewed from the specific direction; a first measurement pad connected to at least one of the plurality of third pads, and measuring whether the third pad is electrically connected to the fourth pad via the first pad, the conductive component, and the second pad; and The second measurement pad is connected to at least one of the plurality of fourth pads and is used to confirm whether the third pad is electrically connected to the fourth pad via the first pad, the conductive component and the second pad.

2. The semiconductor device according to claim 1, wherein The conductive component includes: a first extending portion extending along the first direction, and a second extending portion extending from an end of the first extending portion along the second direction. The plurality of first pads are disposed on the first extension portion. The plurality of second pads are disposed on the second extension portion. The first measurement pads are respectively provided on the plurality of the third pads. The second measurement pads are respectively provided on the plurality of fourth pads.

3. A method for measuring position deviation of a semiconductor device, The semiconductor device comprises a first substrate and a second substrate which are mounted in an overlapping manner. The first substrate comprises: A plurality of conductive first pads are arranged on the substrate surface separated from each other in a first direction parallel to the substrate surface of the first substrate when the first substrate is viewed from a specific direction; a plurality of conductive second pads arranged on the substrate surface separated from each other in a second direction different from the first direction and parallel to the substrate surface when the first substrate is viewed from the specific direction; and A conductive component is disposed on the substrate surface and electrically connects the plurality of first pads and the second pads. The second substrate comprises: a plurality of third conductive pads arranged on a surface of the second substrate facing the first substrate and spaced apart from each other in the first direction when the second substrate is viewed from the specific direction; A plurality of conductive fourth pads are arranged on the opposing surface separated from each other in the second direction when the second substrate is viewed from the specific direction; a first measurement pad connected to at least one of the plurality of third pads, and measuring whether the third pad is electrically connected to the fourth pad via the first pad, the conductive component, and the second pad; and The second measuring pad is connected to at least one of the plurality of fourth pads and is used to confirm whether the third pad is conductively connected to the fourth pad via the first pad, the conductive component and the second pad. The method for measuring the position deviation of the semiconductor device comprises: A step of using a measuring device connected to the first measuring pad and the second measuring pad to determine whether any one of the plurality of third pads is conductively connected to any one of the plurality of fourth pads; and The step of determining that the deviation amount between the first chip formed on the first substrate and the second chip formed on the second substrate is within a specific range when any one of the plurality of third solder pads is not electrically connected to any one of the plurality of fourth solder pads, and determining that the position deviation amount between the first chip and the second chip is outside the specific range when any one of the plurality of third solder pads is electrically connected to any one of the plurality of fourth solder pads.

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