Chip packaging structure, manufacturing method thereof and electronic equipment

Abstract

The embodiment of the invention discloses a chip packaging structure, a manufacturing method thereof and electronic equipment, relates to the technical field of semiconductors, and mainly aims to solve the problem that a glass core plate in the chip packaging structure is easy to break. In the chip packaging structure, a glass core plate is provided with a metalized through hole. The first wiring layer is arranged on the first side of the glass core plate and electrically connected with the metalized via holes. The first chip is arranged on the side, away from the glass core plate, of the first wiring layer and electrically connected with the first wiring layer. The first coating layer is arranged on the second side of the glass core plate and provided with a first conductive column arranged in a penetrating mode, and the first conductive column is electrically connected with the first wiring layer through the metalized via hole. The second chip is wrapped in the first wrapping layer and is electrically connected to the first wiring layer through the metalized via hole. The first coating layer can increase the overall structural flexibility of the chip packaging structure, improve the mechanical strength of the chip packaging structure, relieve the stress on the glass core plate, and reduce the fracture risk of the glass core plate.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a chip packaging structure and a manufacturing method thereof and an electronic device. Background Art

[0002] The chip packaging technology based on the glass core board is to use the glass substrate as the core board, encapsulate the chip on the glass core board or inside the glass core board to form a chip packaging structure. This chip packaging structure has the advantages of good electrical performance and low manufacturing cost. This is because the size of the metallized through hole (Through Glass Via, TGV) made on the glass core board and the size of the metal line in the wiring layer made on both sides of the glass core board can be well adapted to the size of the metal line on the PCB board, so there is no need to set an additional interconnect substrate between the chip packaging structure and the PCB.

[0003] However, glass core boards are prone to breakage, which limits the widespread application of chip packaging technology based on glass core boards. Summary of the invention

[0004] The embodiments of the present application provide a chip packaging structure, a method for manufacturing the chip packaging structure, and an electronic device including the chip packaging structure, the main purpose of which is to solve the problem that a glass core board is prone to breakage in a chip packaging structure based on a glass core board.

[0005] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0006] In the first aspect, a chip packaging structure is provided, which includes: a glass core board, a first wiring layer, a first chip, a first cladding layer, and a second chip. The glass core board has a metallized via. The first wiring layer is arranged on the first side of the glass core board and is electrically connected to the metallized via. The first chip is arranged on the side of the first wiring layer away from the glass core board and is electrically connected to the first wiring layer. The first cladding layer is arranged on the second side of the glass core board and has a first conductive column arranged through it, and the first conductive column is electrically connected to the first wiring layer through the metallized via. The second chip is wrapped in the first cladding layer and is electrically connected to the first wiring layer through the metallized via.

[0007] As can be seen from the above, a first coating layer is provided on the back of the glass core board. On the one hand, since the first coating layer is composed of organic materials, it itself has good structural flexibility, thereby increasing the overall structural flexibility of the chip packaging structure, improving the mechanical strength of the chip packaging structure, and avoiding the fracture problem caused by the small thickness of the glass core board. Moreover, when the chip packaging structure is installed on the PCB, the first coating layer can effectively relieve the stress on the glass core board, thereby avoiding the fracture of the glass core board due to excessive stress. On the other hand, by burying the second chip (or other components) and the first conductive column for electrical connection inside the first coating layer, the integration of the chip packaging structure is improved while avoiding the opening of a deep cavity on the glass core board, thereby avoiding damage to the overall structure of the glass core board and avoiding the process difficulty problem faced by opening a deep cavity on the glass core board.

[0008] In combination with the first aspect, in a possible implementation of the first aspect, the chip packaging structure further includes a second wiring layer, which is arranged on a side of the first cladding layer away from the glass core board and is electrically connected to the first conductive column. In these embodiments, the second wiring layer may have one or more layers of metal circuits, and the metal circuits between different layers are electrically interconnected. Optionally, the size of the metal circuit in the second wiring layer is greater than the size of the metal circuit in the first wiring layer; the wiring density of the metal circuit in the second wiring layer is less than the wiring density of the metal circuit in the first wiring layer. In this implementation, a second wiring layer is provided on a side of the first cladding layer away from the glass core board. On the one hand, the presence of the second wiring layer can improve the metal circuit density and device integration of the chip packaging structure; on the other hand, in an application scenario such as directly mounting the chip packaging structure on a PCB, since the size of the metal circuit in the second wiring layer is greater than the size of the metal circuit in the first wiring layer, the second wiring layer can serve as a transition between other circuits in the chip packaging structure and the circuit on the PCB, thereby improving the feasibility of directly mounting the chip packaging structure on the PCB, so that the chip packaging structure can be adapted to PCBs of more specifications.

[0009] In combination with the first aspect, in a possible implementation of the first aspect, the chip packaging structure further includes a packaging substrate, which is arranged on a side of the second wiring layer away from the first cladding layer; the first conductive column is electrically connected to the metal circuit in the packaging substrate through the second wiring layer. Optionally, the size of the metal circuit in the packaging substrate is larger than the size of the metal circuit in the second wiring layer, and the wiring density of the metal circuit in the packaging substrate is smaller than the wiring density of the metal circuit in the second wiring layer. In this implementation, a packaging substrate is also arranged on a side of the second wiring layer away from the first cladding layer. Since the size of the metal circuit in the packaging substrate is larger than the size of the metal circuit in the second wiring layer, and the wiring density of the metal circuit in the packaging substrate is smaller than the wiring density of the metal circuit in the second wiring layer, it can serve as a transition between the chip packaging structure and the circuit on the PCB, thereby improving the feasibility of directly installing the chip packaging structure on the PCB.

[0010] In combination with the first aspect, in a possible implementation of the first aspect, the chip packaging structure further includes a packaging substrate, and the second wiring layer includes a layer of metal wiring. The presence of the packaging substrate can reduce the number of layers of metal wiring in the second wiring layer.

[0011] In combination with the first aspect, in a possible implementation of the first aspect, the chip packaging structure further includes a solder ball array or a copper pillar bump array, which can be arranged on a side of the second wiring layer away from the first cladding layer, and electrically connected to the first conductive pillar through the second wiring layer. Wherein, in the case where the above-mentioned packaging substrate does not exist in the chip packaging structure, the chip packaging structure can be electrically connected to the circuit outside the chip packaging structure through the solder ball array or the copper pillar bump array, and in the case where the above-mentioned packaging substrate exists in the chip packaging structure, the electrical connection between the second wiring layer and the packaging substrate can be achieved through the solder ball array or the copper pillar bump array.

[0012] In combination with the first aspect, in a possible implementation of the first aspect, when the above-mentioned packaging substrate exists in the chip packaging structure, a solder ball array and a copper pillar bump array are provided on the side of the packaging substrate away from the second wiring layer, which are used to realize the electrical connection between the chip packaging structure and the external circuit, for example, to realize the electrical connection between the chip packaging structure and the PCB board.

[0013] In combination with the first aspect, in a possible implementation of the first aspect, the chip packaging structure further includes a third wiring layer, the third wiring layer is disposed between the first cladding layer and the glass core board; the third wiring layer is electrically connected to the first wiring layer through a metallized via, and the first conductive column is electrically connected to the metallized via through the third wiring layer. The third wiring layer has a solder ball on a surface on one side close to the first cladding layer, and the second chip is electrically connected to the solder ball.

[0014] In combination with the first aspect, in a possible implementation of the first aspect, the chip packaging structure also includes an encapsulation layer composed of a plastic encapsulation material, and the encapsulation layer is arranged on the side of the first wiring layer away from the glass core board; the first chip can be completely or partially wrapped in the encapsulation layer. Among them, the situation where the first chip is partially wrapped in the encapsulation layer is, for example, that the front side (active side) of the chip is exposed outside the encapsulation layer to facilitate the heat dissipation of the chip. In this implementation, on the one hand, the plastic encapsulation material wraps the first chip to protect the first chip from damage. On the other hand, the presence of the encapsulation layer can further improve the mechanical strength and fracture toughness of the chip packaging structure, further reduce the risk of fracture of the glass core board, and further reduce the thickness of the glass core board, and the size of the TGV can be further reduced.

[0015] In combination with the first aspect, in a possible implementation of the first aspect, the chip packaging structure further includes a second coating layer, which is made of an organic material, is disposed between the glass core board and the first wiring layer, and has a second conductive column disposed therethrough; the metallized via is electrically connected to the first wiring layer through the second conductive column. In this implementation, by disposing the second coating layer between the glass core board and the first wiring layer, the mechanical strength and fracture toughness of the chip packaging structure can be further improved, the risk of fracture of the glass core board can be further reduced, and the thickness of the glass core board can be further reduced, and the size of the TGV can be further reduced.

[0016] In combination with the first aspect, in a possible implementation of the first aspect, the chip packaging structure further includes a third chip, the third chip is wrapped in the second cladding layer and electrically connected to the first wiring layer. By burying the third chip in the second cladding layer, the integration of the chip packaging structure is further improved.

[0017] In combination with the first aspect, in a possible implementation of the first aspect, the glass core board has a first groove on a surface of one side close to the first wiring layer; the chip packaging structure also includes a third chip, which is disposed in the first groove and electrically connected to the first wiring layer. In this implementation, by providing a groove on the first side surface of the glass core board and installing a chip or other device, the integration of the chip packaging structure is further improved.

[0018] In combination with the first aspect, in a possible implementation of the first aspect, the third chip is an electrical interconnection structure, which is wrapped in the second coating layer or located in a groove on the first side surface of the glass core board. There are multiple first chips, and different first chips are electrically connected through the electrical interconnection structure. In the case where the interconnection line density between different first chips is high, by burying the electrical interconnection structure in the second coating layer, or setting the electrical interconnection structure in the groove on the first side surface of the glass core board, the requirements for the interconnection line density between different first chips can be met, and the signal quality between different first chips can be guaranteed. At the same time, the volume of the chip packaging structure is reduced, which is conducive to the integration of more chips and components.

[0019] In combination with the first aspect, in a possible implementation of the first aspect, the depth of the first groove on the first side of the glass core board is less than 150 μm. In this way, on the one hand, the risk of increasing the glass core board breakage due to the groove being too deep can be avoided, and on the other hand, the process difficulty of forming the groove can be reduced.

[0020] In combination with the first aspect, in a possible implementation of the first aspect, the electrical interconnection structure includes: a substrate and a wiring layer arranged on one side of the substrate. For example, the line width of the metal line in the wiring layer is usually less than or equal to 2μm, and the line spacing is usually less than or equal to 2μm. The line width and line spacing of the metal lines in the usual wiring layer are generally greater than 2um. In other words, the density of the metal lines in the electrical interconnection structure is much greater than the density of the metal lines in the wiring layer. Furthermore, the electrical interconnection structure can support the requirements for the interconnection line density between different first chips, which is conducive to the miniaturization and high integration of the chip packaging structure.

[0021] In combination with the first aspect, in a possible implementation of the first aspect, the electrical interconnection structure further includes a through silicon via penetrating the substrate; the metallized via is electrically connected to the first wiring layer through the through silicon via. In this way, the length of the line between the metallized via and the first wiring layer can be shortened, and signal loss can be reduced. For example, the loss of the current signal can be reduced.

[0022] In combination with the first aspect, in a possible implementation of the first aspect, the thickness of the glass core board in the direction from the first wiring layer to the first cladding layer is 50um-2000um. For example, when the chip packaging structure includes a packaging substrate, the thickness of the glass core board can be 50um-200um. When the chip packaging structure does not include a packaging substrate and is used to be directly installed on a PCB board, the thickness of the glass core board can be 200um-2000um. This is because, when the chip packaging structure is installed on a PCB board, if the chip packaging structure includes a packaging substrate, the packaging substrate can alleviate the stress on the glass core board, and then the thickness of the glass substrate can be further reduced to achieve a smaller TGV without increasing the risk of fracture of the glass core board. On the contrary, if the chip packaging structure does not include a packaging substrate, the thickness and fracture risk of the glass substrate must be taken into account.

[0023] In the second aspect, an embodiment of the present application provides a method for manufacturing a chip packaging structure, the method comprising: preparing a metallized via on a glass core board; forming a first wiring layer on a first side of the glass core board, and installing a first chip on the first wiring layer; the first wiring layer is electrically connected to the metallized via; installing a second chip on a second side of the glass core board, and forming a first cladding layer; the first cladding layer wraps the second chip and has a first conductive column arranged therethrough, and the first conductive column is electrically connected to the first wiring layer through the metallized via.

[0024] In combination with the second aspect, in a possible implementation manner of the second aspect, the method further includes: forming a second wiring layer on a side of the first cladding layer away from the glass core board, the second wiring layer being electrically connected to the first conductive column.

[0025] In combination with the second aspect, in a possible implementation of the second aspect, before installing the second chip on the second side of the glass core board, it also includes: forming a third wiring layer on the second side of the glass core board, and forming a solder ball on the surface of the third wiring layer on one side close to the first cladding layer; the third wiring layer is electrically connected to the first wiring layer through the metallized via, and the first conductive column is electrically connected to the metallized via through the third wiring layer; installing the second chip on the second side of the glass core board specifically includes: soldering the second chip to the solder ball.

[0026] In combination with the second aspect, in a possible implementation of the second aspect, before forming the first wiring layer on the first side of the glass core board, it also includes: forming a second coating layer on the first side of the glass core board, the second coating layer having a second conductive column arranged therethrough; the metallized via is electrically connected to the first wiring layer through the second conductive column.

[0027] In combination with the second aspect, in a possible implementation of the second aspect, before forming the second coating layer on the first side of the glass core board, it also includes: installing a third chip on the first side of the glass core board, the second coating layer wrapping the third chip; the third chip is electrically connected to the first wiring layer.

[0028] In combination with the second aspect, in a possible implementation of the second aspect, before forming the first wiring layer on the first side of the glass core board, the manufacturing method also includes: making a first groove on the first side surface of the glass core board; installing a third chip in the first groove; and electrically connecting the third chip to the first wiring layer.

[0029] In combination with the second aspect, in a possible implementation manner of the second aspect, there are multiple first chips; the third chip is an electrical interconnection structure, and different first chips are electrically connected through the electrical interconnection structure.

[0030] In a third aspect, an embodiment of the present application further provides an electronic device, comprising: a main board and any one of the above-mentioned chip packaging structures, wherein the main board is arranged on a side of the glass core board in the chip packaging structure where the first coating layer is arranged, and is electrically connected to the chip packaging structure.

[0031] Among them, the technical effects brought about by any design method in the second aspect to the third aspect can refer to the technical effects brought about by different design methods in the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A schematic structural diagram of a glass core board provided in an embodiment of the present application;

[0033] Figure 2 A three-dimensional diagram of an electronic device according to an embodiment of the present application;

[0034] Figure 3 An exploded view of an electronic device according to an embodiment of the present application;

[0035] Figure 4 This is a schematic diagram of the structure of a chip packaging structure and a mainboard in an electronic device according to an embodiment of the present application;

[0036] Figure 5 A schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0037] Figure 6 A schematic diagram of an interconnection bridge chip provided in an embodiment of the present application;

[0038] Figure 7 A schematic diagram of another chip packaging structure provided in an embodiment of the present application;

[0039] Figure 8 A schematic diagram of another chip packaging structure provided in an embodiment of the present application;

[0040] Fig. 9 A schematic diagram of another chip packaging structure provided in an embodiment of the present application;

[0041] Fig.10 A schematic diagram of another chip packaging structure provided in an embodiment of the present application;

[0042] Fig.11 A schematic diagram of another chip packaging structure provided in an embodiment of the present application;

[0043] Fig.12 A partial exploded schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0044] Fig.13 A partial exploded schematic diagram of another chip packaging structure provided in an embodiment of the present application;

[0045] Fig.14 A schematic diagram of another chip packaging structure provided in an embodiment of the present application;

[0046] Fig.15 A flow chart of a method for manufacturing a chip packaging structure provided in an embodiment of the present application;

[0047] Fig.16 A schematic diagram of a manufacturing process of a chip packaging structure provided in an embodiment of the present application;

[0048] Fig.17 A schematic diagram of a manufacturing process of another chip packaging structure provided in an embodiment of the present application;

[0049] Fig.18 A schematic diagram of a manufacturing process of another chip packaging structure provided in an embodiment of the present application;

[0050] Fig.19 A schematic diagram of the manufacturing process of another chip packaging structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0051] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0052] In the following, the terms "first", "second", etc. are used only for descriptive purposes to distinguish between identical or similar items with substantially identical functions and effects, and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", etc. may explicitly or implicitly include one or more of the features.

[0053] Also, in the description of the present application, unless otherwise specified, “plurality” means two or more than two.

[0054] In addition, in this application, directional terms such as "upper", "lower", "left", "right", "horizontal" and "vertical" are defined relative to the positions of the components in the drawings. It should be understood that these directional terms are relative concepts. They are used for relative description and clarification, and they can change accordingly according to the changes in the positions of the components in the drawings. Unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium.

[0055] Meanwhile, in the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a concrete manner for ease of understanding.

[0056] In addition, the network architecture and business scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Ordinary technicians in this field can know that with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0057] The chip packaging technology based on the glass core board is to use the glass substrate as the core board, encapsulate the chip on the glass core board or inside the glass core board to form a chip packaging structure. This chip packaging structure has the advantages of good electrical performance and low manufacturing cost. This is because the size of the metallized through hole (Through Glass Via, TGV) made on the glass core board and the size of the metal line in the wiring layer made on both sides of the glass core board can be well adapted to the size of the metal line on the PCB board, so there is no need to set an additional interconnect substrate between the chip packaging structure and the PCB.

[0058] However, this glass core board-based chip packaging technology has obvious limitations.

[0059] First, in order to meet the high electrical interconnection density, the size of the TGV in the glass core board is required to be as small as possible. Since the thicker the glass core board, the more difficult it is to make a small-sized TGV, the thickness of the glass core board has to be reduced to achieve the production of a small-sized TGV. However, if the thickness of the glass core board is not enough, it will lead to insufficient mechanical strength and easy fracture after being stressed. Especially when the glass core board is large in size and is directly assembled to the PCB, the fracture of the glass core board becomes a technical problem that needs to be solved urgently.

[0060] Second, if Figure 1 As shown, due to the demand for integration and performance, it is also necessary to open a deep cavity on the back of the glass core board and bury chips or components. Among them, the back of the glass core board can be understood as the side of the glass core board where the chip is not installed, and the side where the chip is installed can be called the front. This process of burying chips or components inside the glass core board is very complicated, and the obtained cavity depth consistency is poor, which is not conducive to the subsequent installation of multiple chips or components of the same size. In addition, when it is necessary to bury multiple chips or components of different sizes, it is difficult to make multiple cavities of different depths on the glass core board. At the same time, opening a deep cavity on the back of the glass core board destroys the structural integrity of the glass core board and further increases the risk of breakage of the glass core board. The above two problems exist at the same time, which limits the widespread application of chip packaging technology based on glass core boards.

[0061] In view of this, the embodiments of the present application provide a chip packaging structure and an electronic device including the chip packaging structure. In some application scenarios, the chip packaging structure can be a chip obtained by packaging a bare chip, or a semiconductor structure obtained by packaging multiple chips, such as a multi-chip module (MCM) or a SIP package (System In a Package) structure. The chip packaging structure has high mechanical strength while meeting the requirements of high electrical interconnection density and device integration, reducing the risk of glass core board fracture.

[0062] The above-mentioned electronic devices include, but are not limited to, electronic devices in the fields of information technology (IT) and communication technology (CT), such as supercomputing equipment, artificial intelligence equipment, servers, optical communication equipment, mobile phones, tablet computers (tablet personal computer), laptop computers (laptop computer), personal digital assistants (personal digital assistant, PDA), cameras, personal computers, notebook computers, vehicle-mounted equipment, wearable devices, augmented reality (augmented reality, AR) glasses, AR helmets, virtual reality (virtual reality, VR) glasses or VR helmets and other devices that need to process / store / transmit and receive data. The embodiments of the present application do not impose any special restrictions on the specific form of the above-mentioned electronic devices. For the convenience of explanation below, the electronic device is taken as an example. Figure 2 The mobile phone shown is used as an example for illustration.

[0063] Figure 2 A three-dimensional diagram of an electronic device provided in some embodiments of the present application, Figure 3 for Figure 2 Exploded view of the electronic device shown. Figure 2 and Figure 3 , the electronic device 1000 is a mobile phone. The electronic device 1000 may include Figure 3 The screen 100 , the middle frame 200 , the rear cover 300 and the mainboard 400 fixed on the middle frame 200 are shown.

[0064] Understandably, Figure 2 and Figure 3 Some components included in the electronic device 1000 are shown only as examples, and the actual shapes, actual sizes, actual positions, and actual structures of these components are not subject to any restriction. Figure 2 and Figure 3 For example, in some other examples, the electronic device 1000 may not include the screen 100. Alternatively, the electronic device 1000 may also include Figure 3 Camera 500 is shown.

[0065] In the embodiment of the present application, the electronic device 1000 further includes: Figure 4 The chip packaging structure 600 shown in the figure. The chip packaging structure mentioned in the embodiment of the present application can also be referred to as an integrated circuit. Figure 4As shown, the chip package structure 600 is disposed on the mainboard 400 and is electrically connected to the mainboard 400. For example, the chip package structure 600 can be electrically connected to the mainboard 400 through a ball grid array (BGA) or a plurality of copper pillar bumps (CPB) arranged in an array, so that the chip package structure 600 can realize signal transmission with other devices or device stacking structures on the mainboard 400.

[0066] It should be noted that the mainboard 400 may be a printed circuit board (PCB). The number of the chip packaging structures 600 on the mainboard 400 may be one, two, or more than two, which is not limited in the present application.

[0067] For the convenience of the following description, some drawings of the embodiments of the present application show a three-dimensional space coordinate system, namely, an X, Y, and Z coordinate system. Figure 4 , the plane where the main board 400 is located is the XY plane. Figure 4 Taking the main board 400 shown in the figure as a rectangle as an example, the X-axis may be the length direction of the main board 400, the Y-axis may be the width direction of the main board 400, and the Z-axis may be a direction perpendicular to or approximately perpendicular to the main board 400 within a manufacturing tolerance range. It can be understood that the width dimension of the main board 400 is smaller than the length dimension of the main board 400.

[0068] It should be noted that Figures 2 to 4 This is only an example of the application scenario of the chip packaging structure provided in the embodiment of the present application, which specifically shows the application mode of the chip packaging structure integrated in an electronic device. In fact, the chip packaging structure provided in the embodiment of the present application can also be used as an independent electronic device, and the specific implementation method will be described in detail below.

[0069] Please refer to Figure 5 The chip packaging structure 600 includes a glass core board 1, a first wiring layer 2, a first chip 3, a first cladding layer 4, a second chip 5, and a solder ball array 6 (or a copper column bump). The glass core board has a metallized via 101. The first wiring layer 2 is arranged on the first side of the glass core board 1 and is electrically connected to the metallized via 101. The first chip 3 is arranged on the side of the first wiring layer 2 away from the glass core board 1 and is electrically connected to the first wiring layer 2. The first cladding layer 4 is arranged on the second side of the glass core board 1 and has a first conductive column 401 that is arranged through it. The first conductive column 401 is electrically connected to the first wiring layer 2 through the metallized via 101. The second chip 5 is wrapped in the first cladding layer 4 and is electrically connected to the first wiring layer 2 through the metallized via 101. The solder ball array 6 is arranged on the side of the first cladding layer 4 away from the glass core board 1 and is electrically connected to the first conductive column 401.

[0070] In some embodiments, the chip package structure 600 may not include the solder ball array 6 .

[0071] In some embodiments, for the convenience of description, the first side of the glass core board 1 is also referred to as the front side of the glass core board 1 , and the second side of the glass core board 1 is also referred to as the back side of the glass core board 1 .

[0072] exist Figure 5 In the chip packaging structure 600 shown, a first coating layer 4 is provided on the back of the glass core board 1. On the one hand, since the first coating layer 4 is made of organic material, it has good structural flexibility, thereby increasing the overall structural flexibility of the chip packaging structure 600, improving the mechanical strength of the chip packaging structure 600, and avoiding the problem of fracture caused by the small thickness of the glass core board 1. Moreover, when the chip packaging structure 600 is installed on the PCB, the first coating layer 4 can effectively relieve the stress on the glass core board 1, thereby avoiding the fracture of the glass core board 1 due to excessive stress. On the other hand, by burying the second chip 5 (or other components) and the first conductive column 401 for electrical connection inside the first coating layer 4, the integration of the chip packaging structure 600 is improved while avoiding the opening of a deep cavity on the glass core board 1, thereby avoiding damage to the overall structure of the glass core board 1 and avoiding the process difficulty problem faced by opening a deep cavity on the glass core board 1.

[0073] In the embodiment of the present application, the above-mentioned chip (including the first chip 3 and the second chip 5) can be a processing chip with a data processing function, such as a central processing unit (CPU), a system on chip (SOC) or a graphics processing unit (GPU) and other chips that can process data. The above-mentioned memory can be a random access memory (RAM) or a read-only memory (ROM). The chip can be a bare chip (i.e., a single die) or a chip stacking structure (i.e., multiple bare dies are stacked).

[0074] The present application does not limit the number of the first chip 3 and the second chip 5 in the chip packaging structure 600. The number of the first chip 3 and the second chip 5 in the chip packaging structure 600 can be one or more. However, for an MCM component, the number of chips is usually two or more. For example, multiple first chips 3 can be stacked in a direction perpendicular to the mainboard 400 / glass core board 1, or can be arranged in parallel in a direction parallel to the mainboard 400 / glass core board 1, that is, Figure 5The second chips 5 can be stacked in a direction perpendicular to the main board 400 / glass core board 1, or arranged in parallel in a direction parallel to the main board 400 / glass core board 1. Figure 5 The manner shown is provided in the first coating layer 4 .

[0075] In some embodiments, the glass core board 1 may be made of glass materials such as quartz glass or high-silica glass.

[0076] In some embodiments, the organic material may be an organic polymer material. The organic material wraps the second chip. The organic material may also be referred to as a molding compound, including but not limited to epoxy molding compound (EMC), silicone resin, etc. The epoxy molding compound (EMC), also known as epoxy resin molding compound, epoxy molding compound, etc., is a powdered molding compound made of epoxy resin as a base resin, high-performance phenolic resin as a curing agent, silicon micropowder as a filler, and a variety of additives.

[0077] In some embodiments, Figure 5 As shown, there is at least one wiring layer on the second side surface of the glass core board 1. For the convenience of explanation and to distinguish it from the first wiring layer, the wiring layer is referred to as the second metal layer 7. In other embodiments, the wiring layer can also be referred to as the third wiring layer. The second metal layer 7 includes metal lines, BGA and / or CPB. The TGV in the glass core board 1 is electrically connected to the second metal layer 7 on the second side surface of the glass core board 1. Using chip packaging technology, the second chip 5 can be mechanically and electrically connected to the second metal layer 7 on the second side surface of the glass core board 1, and the first chip 3 can also be mechanically and electrically connected to the first wiring layer 2. Chip packaging technologies such as wire bonding (WB), flip chip bonding (FC), etc.

[0078] In a possible implementation, the above-mentioned chip (including the first chip 3 and the second chip 5) can be the processing chip with data processing function mentioned above, or it can be a chip (bridgedie) with electrical interconnection function. In some examples of the present application, such a chip with electrical interconnection function can also be called an electrical interconnection structure or an interconnection bridge chip. It should be understood that the interconnection bridge chip includes but is not limited to such a chip with electrical interconnection function.

[0079] Figure 6 FIG. 1 is an exemplary interconnection bridge chip. Figure 6As shown in A and B, the interconnection bridge chip generally includes a substrate (such as a wafer or a silicon chip) and a circuit layer arranged on one side of the substrate. The circuit layer includes one or more layers of metal circuits. The metal circuits between different layers realize high-density interconnection. Through silicon vias can be arranged in the substrate and interconnected with the circuit layer, such as Figure 6 As shown in A in the figure. The substrate may also not be provided with a through silicon via, such as Figure 6 As shown in B. The line width of the metal line in the interconnection bridge chip is usually less than or equal to 2μm, and the line spacing is usually less than or equal to 2μm. The line width and line spacing of the metal line in the usual wiring layer are generally greater than 2um. In other words, the density of the metal line in the electrical interconnection structure is much greater than the density of the metal line in the wiring layer. Since the interconnection bridge chip itself has a high wiring density, setting it in the chip packaging structure can meet the requirements for high interconnection density between different chips in the chip packaging structure, reduce the volume of the chip packaging structure, and facilitate the integration of more chips and components.

[0080] In some embodiments, Figure 7 As shown, the chip packaging structure 600 also includes a second wiring layer 8, which is arranged on the side of the first cladding layer 4 away from the glass core board 1, and the second wiring layer 8 is electrically connected to the first conductive column 401. In these embodiments, the second wiring layer 8 can have one or more layers of metal lines, and the metal lines between different layers are electrically interconnected. The solder ball array 6 is arranged on the side of the second wiring layer 8 away from the first cladding layer 4. The solder ball array 6 is electrically connected to the first conductive column 401 through the metal lines in the second wiring layer 8.

[0081] In a possible implementation, the size of the metal circuit in the second wiring layer 8 is greater than the size of the metal circuit in the first wiring layer 2 and the second metal layer 7 .

[0082] exist Figure 7In the chip packaging structure 600 shown, a second wiring layer 8 is provided on the side of the first cladding layer 4 away from the glass core board 1. On the one hand, the presence of the second wiring layer 8 can improve the metal line density and device integration of the chip packaging structure 600; on the other hand, in the application scenario where the chip packaging structure 600 is directly mounted on a PCB, since the size of the metal line in the second wiring layer 8 is larger than the size of the metal line in the first wiring layer 4 and the second metal layer 7, the second wiring layer 8 can be used as a transition between other lines in the chip packaging structure 600 and the lines on the PCB, thereby improving the feasibility of the chip packaging structure 600 being directly mounted on the PCB, so that the chip packaging structure 600 can be adapted to PCBs of more specifications. It should be noted that the "chip packaging structure is directly mounted on the PCB" here means that no additional packaging substrate or wiring layer is provided between the chip packaging structure 600 and the PCB, and the solder ball array 6 on the chip packaging structure 600 is directly soldered on the PCB board, thereby being electrically connected to the circuit on the PCB board.

[0083] In some embodiments, Figure 8 As shown, the chip packaging structure 600 further includes a packaging layer 9 made of a plastic packaging material, and the packaging layer 9 is arranged on a side of the first wiring layer 2 away from the glass core board 1. Figure 8 As shown in the figure, the first chip 3 can be partially wrapped in the packaging layer 9, and the front side (active side) of the first chip 3 is exposed outside the packaging layer, which can be beneficial to the heat dissipation of the chip. On the one hand, the plastic encapsulation material wraps the first chip 3 to protect the first chip 3 from damage. On the other hand, the presence of the packaging layer 9 can further improve the mechanical strength and fracture toughness of the chip packaging structure 600, further reduce the risk of fracture of the glass core board 1, and further reduce the thickness of the glass core board 1, and the size of the TGV can be further reduced. In addition, the plastic encapsulation material can also be used to fill the connection between the first chip 3 and the first wiring layer 2 to ensure the installation stability of the first chip 3 and the mechanical strength of the chip packaging structure, and will not adversely affect the heat dissipation of the device.

[0084] In some embodiments, Fig. 9As shown, the chip packaging structure 600 also includes a second cladding layer 10 made of an organic material, which is arranged between the glass core board 1 and the first wiring layer 2 and has a second conductive column 1001 arranged therethrough. In these embodiments, the metallized via 101 is electrically connected to the first wiring layer 2 through the second conductive column 1001. Optionally, there is at least one wiring layer on the first side surface of the glass core board 1. For the convenience of description and to distinguish it from the first wiring layer, the second wiring layer and the third wiring layer, the wiring layer is referred to as the first metal layer 11. In other embodiments, the wiring layer can also be referred to as the fourth wiring layer. The first metal layer 11 includes a metal line. The TGV in the glass core board 1 is electrically connected to the first metal layer 11 on the first side surface of the glass core board 1. The second cladding layer 10 is electrically connected to the TGV in the glass core board 1 through the first metal layer 11. In these embodiments, by providing a second coating layer 10 between the glass core board 1 and the first wiring layer 2, the mechanical strength and fracture toughness of the chip packaging structure 600 can be further improved, the risk of fracture of the glass core board 1 can be further reduced, the thickness of the glass core board 1 can be further reduced, and the size of the TGV can be further reduced.

[0085] In some embodiments, Fig. 9 As shown in FIG. 6 , the chip packaging structure 600 further includes a third chip 12 . The third chip 12 is wrapped in the second encapsulation layer 10 . The third chip 12 is electrically connected to the first wiring layer 2 .

[0086] In some embodiments, the pin pitch of the first chip 3 is smaller than the pin pitch of the second chip 5, which means that the first chip 3 has higher requirements on the interconnection line density than the second chip 5. For example, the first chip 3 can be a processor or a memory, and the second chip 5 can be a DTC chip, a passive component, etc.

[0087] Based on this, in a possible implementation, Fig.10 and Fig.11 As shown in FIG. 1 , the third chip 12 is, for example, Figure 6 The interconnection bridge chip shown in the figure. The interconnection bridge chip is wrapped in the second coating layer 10. High-density electrical interconnection is achieved between different first chips 3 on the first wiring layer 2 through the interconnection bridge chip. For example, different first chips 3 on the first wiring layer 2 can be processors (such as CPU, GPU) and memories, respectively. In a more specific implementation, the first wiring layer 2 has a solder ball array on one side close to the second coating layer 10, and the front side of the interconnection bridge chip (the side with high-density routing) is electrically connected to the metal lines in the first wiring layer through the solder balls in the solder ball array, thereby achieving high-density interconnection between different first chips 3 on the first wiring layer.

[0088] The third chip 12, i.e., the interconnection bridge chip, may have a through silicon via or may not have a through silicon via. Fig.10 and Fig.11 For example, Fig.10 The third chip 12 is as follows Figure 6 The interconnection bridge chip A shown in FIG. 1 does not have a through silicon via. The front side of the third chip 12 is directly connected to the first wiring layer 2, and the back side of the third chip 12 is connected to the first wiring layer 2. Fig. 9 The adhesive layer 13 shown in FIG. 1 is adhered to the first metal layer 11 . Fig.11 The third chip 12 is as follows Figure 6 The interconnection bridge chip B is shown in FIG. , that is, it has a through silicon via. The front side of the third chip 12 is connected to the first wiring layer 2 by welding, and the back side of the third chip 12 is connected to the second metal layer 11 by welding.

[0089] In one possible implementation, Fig.10 As shown, the metallized vias in the glass core board 1 can be electrically connected to the first wiring layer through the silicon vias in the interconnection bridge chip. In this way, the length of the line between the metallized vias and the first wiring layer can be shortened, and the signal loss can be reduced. For example, the loss of the current signal can be reduced.

[0090] In other embodiments, Fig.12 As shown, the first side surface of the glass core board 1 close to the first wiring layer 2 has a first groove 102. The third chip 12 is arranged in the first groove 102 and is electrically connected to the first wiring layer 2. In these embodiments, by opening a groove on the first side surface of the glass core board 1 and installing a chip or other device, the integration of the chip packaging structure is further improved.

[0091] In a possible implementation, the depth of the first groove 102 on the first side of the glass core board is less than 150 μm, for example, 100 μm. This can avoid the risk of increasing the glass core board breakage due to the groove being too deep, and can reduce the difficulty of the groove process.

[0092] It should be noted that Fig.12 The specific implementation of the third chip 12 can also be Figure 6 The interconnection bridge chip shown in FIG. 1 is used to realize high-density interconnection between different first chips 3 on the first wiring layer. Fig.11 and Fig.10 The implementation shown is similar, Fig.12 The third chip 12 may have a through silicon via for realizing electrical connection between the metallized via in the glass core board 1 and the first wiring layer, or may not have a through silicon via. Fig.12 For a detailed introduction to this implementation method, please refer to Fig.11 and Fig.10 The contents of the illustrated embodiment will not be described in detail here.

[0093] In a possible implementation, the metallized via 101 in the glass core board 1 is opened in the first groove 102 , so that the metallized via 101 is electrically connected to the first wiring layer 2 through the third chip 12 .

[0094] In some embodiments, Fig.13 As shown, the chip packaging structure also includes a packaging substrate 14, which is arranged on the side of the second wiring layer 8 away from the first cladding layer 4; the first conductive column 401 is soldered to the packaging substrate 14 through the solder ball array on the second wiring layer 8 to be electrically connected to the metal circuit in the packaging substrate 14. Optionally, a plastic encapsulation material is also provided at the welding point between the second wiring layer 8 and the packaging substrate 14 to ensure the stability of the connection between the two. Optionally, the size of the metal circuit in the packaging substrate 14 is larger than the size of the metal circuit in the second wiring layer 8, and the wiring density of the metal circuit in the packaging substrate 14 is smaller than the wiring density of the metal circuit in the second wiring layer 8. In this implementation, a packaging substrate is also provided on the side of the second wiring layer away from the first cladding layer. Since the size of the metal circuit in the packaging substrate is larger than the size of the metal circuit in the second wiring layer, and the wiring density of the metal circuit in the packaging substrate is smaller than the wiring density of the metal circuit in the second wiring layer, it can be used as a transition between the chip packaging structure and the circuit on the PCB, thereby improving the feasibility of directly mounting the chip packaging structure on the PCB.

[0095] exist Fig.13 In the illustrated embodiment, the second wiring layer includes a layer of metal circuits. The presence of the packaging substrate can reduce the number of layers of metal circuits in the second wiring layer.

[0096] In the above embodiment, the thickness of the glass core board in the direction from the first wiring layer to the first cladding layer is 50um-2000um. For example, when the chip packaging structure includes a packaging substrate, the thickness of the glass core board can be 50um-200um. When the chip packaging structure does not include a packaging substrate and is used to be directly installed on a PCB board, the thickness of the glass core board can be 200um-2000um. This is because, when the chip packaging structure is installed on a PCB board, if the chip packaging structure includes a packaging substrate, then the packaging substrate can alleviate the stress on the glass core board, and then the thickness of the glass substrate can be further reduced to achieve a smaller TGV without increasing the risk of fracture of the glass core board. On the contrary, if the chip packaging structure does not include a packaging substrate, the thickness and fracture risk of the glass substrate must be taken into account.

[0097] In some embodiments, Fig.14As shown in, when the chip packaging structure is implemented as an independent electronic device, in the chip packaging structure 600, a heat sink 15 is also provided on the side of the packaging layer 9 away from the glass core board 1, which is used to dissipate heat for the chip packaging structure. An electrical connector 16 is also provided on the side of the second wiring layer 10 away from the glass core board 1, one end of the electrical connector 16 is electrically connected to the second wiring layer 8, and the other end is used to connect to an external circuit, thereby realizing an electrical connection between the chip packaging structure and the external circuit, so that the chip packaging structure is realized as an independent electronic device. For example, the electrical connector 16 includes a power supply module for supplying power to the devices in the chip packaging structure, and may also include an interconnection module for realizing the transmission of signals between the chip packaging structure and the external circuit.

[0098] Fig.15 A method for manufacturing a chip packaging structure provided in an embodiment of the present application is given, such as Fig.15 As shown, the manufacturing method may include the following steps.

[0099] S100, preparing metallized vias on a glass core board.

[0100] S200 , forming a first wiring layer on a first side of the glass core board, and mounting a first chip on the first wiring layer; the first wiring layer is electrically connected to the metallized via.

[0101] S300, installing a second chip on the second side of the glass core board and forming a first cladding layer; the first cladding layer wraps the second chip and has a first conductive column arranged therethrough, and the first conductive column is electrically connected to the first wiring layer through a metallized via.

[0102] S400 , forming a solder ball array on a side of the first cladding layer away from the glass core board, wherein the solder ball array is electrically connected to the first wiring layer through metallized vias.

[0103] It should be noted that Fig.15 The manufacturing method flow shown does not constitute a limitation on the order of executing the steps of the manufacturing method provided in the embodiment of the present application. For example, S300 may be executed first, and then S200, or S200 may be executed first, and then S100, etc. In addition, Fig.15 The further refinement steps of each step shown in the above-mentioned steps may be executed alternately. For example, the refinement step of S100 may be executed alternately with the refinement step of S200.

[0104] In some embodiments, the manufacturing method of the chip packaging structure further includes: S500, forming a second wiring layer on a side of the first cladding layer away from the glass core board, wherein the second wiring layer is electrically connected to the first conductive column.

[0105] In some embodiments, before executing S300, the manufacturing method of the chip packaging structure also includes: forming a third wiring layer on the second side of the glass core board and forming solder balls on the third wiring layer; in S300, installing a second chip on the second side of the glass core board, specifically including: soldering the second chip to the solder balls.

[0106] In some embodiments, before executing S200, the manufacturing method of the chip packaging structure further includes: S600, forming a second cladding layer on the first side of the glass core board, the second cladding layer having a second conductive column arranged therethrough. In these embodiments, the metallized via is electrically connected to the first wiring layer through the second conductive column.

[0107] In some embodiments, before executing S600, the chip packaging structure manufacturing method further includes: S700, installing a third chip on the first side of the glass core board. In these embodiments, the second cladding layer wraps the third chip; and the third chip is electrically connected to the first wiring layer.

[0108] In some embodiments, before executing S600, the chip packaging structure manufacturing method further includes: S800, installing an electrical interconnection structure on the first side of the glass core board. In these embodiments, the second coating layer wraps the electrical interconnection structure, and the metallized via is electrically connected to the first wiring layer through the electrical interconnection structure.

[0109] In some embodiments, before executing S200, the method for manufacturing the chip packaging structure further includes: S900, manufacturing a first groove on a first side surface of the glass core board; installing a third chip in the first groove; and electrically connecting the third chip to the first wiring layer.

[0110] In some embodiments, before executing S300, the method for manufacturing the chip packaging structure further includes: S1000, manufacturing a second groove on the second side surface of the glass core board; installing a third chip in the second groove; and electrically connecting the third chip to the first wiring layer.

[0111] The following describes in detail the manufacturing method of the chip packaging structure provided by the embodiment of the present application through a plurality of different embodiments. For the convenience of description, the first side surface of the glass core board is called the front side, and the second side surface is called the back side.

[0112] In one example, following Fig.16 The process shown is to manufacture the chip packaging structure provided in the embodiment of the present application:

[0113] S161, etching through holes on the glass core board, and metalizing the through holes to form metalized vias.

[0114] In a specific implementation, the above metallization process may be depositing a metal layer, such as a copper layer.

[0115] S162, forming a first wiring layer on the front side of the glass core board; the metallized vias in the glass core board are electrically connected to the lines in the first wiring layer.

[0116] S163, forming a metal layer (ie, the second metal layer mentioned in the above embodiment) on the back side of the glass core board, and preparing a first conductive column on the metal layer; the metallized via in the glass core board is electrically connected to the first conductive column through the metal layer.

[0117] S164, installing a chip (ie, the second chip mentioned in the above embodiment) on the second metal layer on the back side of the glass core board.

[0118] S165. Use a plastic encapsulation material to form a first cladding layer on the back side of the glass core board, so that the first cladding layer wraps the first conductive column and the chip on the back side, and one end of the first conductive column away from the glass core board is exposed to the outer surface of the first cladding layer.

[0119] S166. Form a second wiring layer on a surface of the first cladding layer away from the glass core board, wherein the second wiring layer is electrically connected to the first conductive column.

[0120] S167 . Install a chip (ie, the first chip mentioned in the above embodiment) on a side of the first wiring layer away from the glass core board.

[0121] S168, forming a solder ball array on a surface of the second wiring layer on a side away from the first cladding layer.

[0122] Through the above S161-S168, the following is produced: Figure 7 The chip packaging structure shown.

[0123] In another example, following Fig.17 The process shown is to manufacture the chip packaging structure provided in the embodiment of the present application:

[0124] S171, etching through holes on the glass core board, and metalizing the through holes to form metalized vias.

[0125] In a specific implementation, the above metallization process may be depositing a metal layer, such as a copper layer.

[0126] S172, forming a metal layer (ie, the second metal layer mentioned in the above embodiment) on the back side of the glass core board, and preparing a first conductive column on the metal layer; the metallized via in the glass core board is electrically connected to the first conductive column through the metal layer.

[0127] S173, installing a chip (ie, the second chip mentioned in the above embodiment) on the second metal layer on the back side of the glass core board.

[0128] S174. Use a plastic encapsulation material to form a first cladding layer on the back side of the glass core board, so that the first cladding layer wraps the first conductive column and the chip on the back side, and one end of the first conductive column away from the glass core board is exposed to the outer surface of the first cladding layer.

[0129] S175, forming a second wiring layer on a surface of the first cladding layer away from the glass core board, wherein the second wiring layer is electrically connected to the first conductive column.

[0130] S176, forming a first wiring layer on the front side of the glass core board; the metallized vias in the glass core board are electrically connected to the lines in the first wiring layer.

[0131] S177 . Install a chip (ie, the first chip mentioned in the above embodiment) on a side of the first wiring layer away from the glass core board.

[0132] S178, forming a solder ball array on a surface of the second wiring layer on a side away from the first cladding layer.

[0133] Through the above S171-S178, the following is produced: Figure 7 The chip packaging structure shown.

[0134] In another example, following Fig.18 The process shown is to manufacture the chip packaging structure provided in the embodiment of the present application:

[0135] S181, etching blind holes on the glass core board in a direction from the front side to the back side of the glass core board, and metalizing the blind holes to form metalized blind holes.

[0136] In a specific implementation, the above metallization process may be depositing a metal layer, such as a copper layer.

[0137] S182, forming a first wiring layer on the front side of the glass core board; the metallized blind holes in the glass core board are electrically connected to the lines in the first wiring layer.

[0138] Optionally, a carrier may be bonded to the side of the glass core board where the first wiring layer is formed, to facilitate subsequent operations.

[0139] S183, grinding and polishing the back side of the glass core board until the metal layer of the hole in the glass core board is exposed, so that the metallized blind hole becomes a metallized through hole.

[0140] S184, forming a metal layer (ie, the second metal layer mentioned in the above embodiment) on the back side of the glass core board, and preparing a first conductive column on the metal layer; the metallized via in the glass core board is electrically connected to the first conductive column through the metal layer.

[0141] S185. Install a chip (ie, the second chip mentioned in the above embodiment) on the second metal layer on the back side of the glass core board.

[0142] S186. Use a plastic encapsulation material to form a first cladding layer on the back side of the glass core board, so that the first cladding layer wraps the first conductive column and the chip on the back side, and one end of the first conductive column away from the glass core board is exposed to the outer surface of the first cladding layer.

[0143] S187. Form a second wiring layer on a surface of the first cladding layer away from the glass core board, wherein the second wiring layer is electrically connected to the first conductive column.

[0144] S188. Install a chip (ie, the first chip mentioned in the above embodiment) on a side of the first wiring layer away from the glass core board.

[0145] S189, forming a solder ball array on a surface of the second wiring layer on a side away from the first cladding layer.

[0146] Through the above S181-S189, the following is produced: Figure 7 The chip packaging structure shown.

[0147] In another example, according to Fig.19 The process shown is to manufacture the chip packaging structure provided in the embodiment of the present application:

[0148] S191. Etching blind holes on the glass core board in a direction from the back side to the front side of the glass core board, and metalizing the blind holes to form metalized blind holes.

[0149] S192, forming a metal layer (ie, the second metal layer mentioned in the above embodiment) on the back side of the glass core board, and preparing a first conductive column on the metal layer; the metallized blind hole in the glass core board is electrically connected to the first conductive column through the metal layer.

[0150] S193, installing a chip (ie, the second chip mentioned in the above embodiment) on the second metal layer on the back side of the glass core board.

[0151] S194. Use a plastic encapsulation material to form a first cladding layer on the back side of the glass core board, so that the first cladding layer wraps the first conductive column and the chip on the back side, and one end of the first conductive column away from the glass core board is exposed to the outer surface of the first cladding layer.

[0152] S195, forming a second wiring layer on a surface of the first cladding layer away from the glass core board, wherein the second wiring layer is electrically connected to the first conductive column.

[0153] S196. Grind and polish the front side of the glass core board until the metal layer of the hole in the glass core board is exposed, so that the metallized blind hole becomes a metallized through hole.

[0154] S197, forming a first wiring layer on the front side of the glass core board; the metallized vias in the glass core board are electrically connected to the lines in the first wiring layer.

[0155] S198. Install a chip (ie, the first chip mentioned in the above embodiment) on a side of the first wiring layer away from the glass core board.

[0156] S199, forming a solder ball array on a surface of the second wiring layer on a side away from the first cladding layer.

[0157] Through the above S181-S189, the following is produced: Figure 7 The chip packaging structure shown.

[0158] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0159] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A chip packaging structure, characterized in that: include: Glass core board with metallized vias; A first wiring layer, disposed on one side of the glass core board and electrically connected to the metallized via; A first chip is arranged on a side of the first wiring layer away from the glass core board and is electrically connected to the first wiring layer; A first cladding layer, made of an organic material, is disposed on the other side of the glass core board, and has a first conductive column disposed therethrough, wherein the first conductive column is electrically connected to the first wiring layer through the metallized via hole; The second chip is wrapped in the first covering layer and electrically connected to the first wiring layer through the metallized vias.

2. The chip packaging structure according to claim 1, characterized in that: The chip packaging structure further includes: The second wiring layer is arranged on a side of the first cladding layer away from the glass core board and is electrically connected to the first conductive column.

3. The chip packaging structure according to claim 2, characterized in that: The chip packaging structure further includes: A packaging substrate, arranged on a side of the second wiring layer away from the first cladding layer; The first conductive column is electrically connected to a metal line in the packaging substrate through the second wiring layer.

4. The chip packaging structure according to claim 2 or 3, characterized in that: The second wiring layer includes a layer of metal lines.

5. The chip packaging structure according to any one of claims 1 to 4, characterized in that: The chip packaging structure further includes: A third wiring layer is arranged between the first cladding layer and the glass core board; the third wiring layer is electrically connected to the first wiring layer through the metallized vias, a solder ball is provided on a side of the third wiring layer close to the first cladding layer, and the second chip is electrically connected to the solder ball; The first conductive column is electrically connected to the metallized via through the third wiring layer.

6. The chip packaging structure according to any one of claims 1 to 5, characterized in that: The chip packaging structure further includes: The packaging layer is arranged on a side of the first wiring layer away from the glass core board; the first chip is located in the packaging layer.

7. The chip packaging structure according to claim 6, characterized in that: The packaging layer is made of a plastic packaging material, and the first chip is completely or partially wrapped in the plastic packaging material.

8. The chip packaging structure according to any one of claims 1 to 7, characterized in that: The chip packaging structure further includes: The second cladding layer is made of an organic material, is disposed between the glass core board and the first wiring layer, and has a second conductive column disposed therethrough; the metallized via is electrically connected to the first wiring layer through the second conductive column.

9. The chip packaging structure according to claim 8, characterized in that: The chip packaging structure further includes: The third chip is wrapped in the second covering layer and electrically connected to the first wiring layer.

10. The chip packaging structure according to any one of claims 1 to 7, characterized in that: The glass core board has a first groove on its surface on one side close to the first wiring layer; the chip packaging structure further includes: A third chip is disposed in the first groove and is electrically connected to the first wiring layer.

11. The chip packaging structure according to claim 9 or 10, characterized in that: The number of the first chips is multiple; The third chip is an electrical interconnection structure, and different first chips are electrically connected via the electrical interconnection structure.

12. The chip packaging structure according to claim 11, characterized in that: The electrical interconnection structure includes: a substrate and a wiring layer arranged on one side of the substrate.

13. The chip packaging structure according to claim 11 or 12, characterized in that: The electrical interconnection structure further includes a through silicon via penetrating the substrate; the metallized via is electrically connected to the first wiring layer through the through silicon via and the wiring layer.

14. The chip packaging structure according to claim 10, characterized in that: The depth of the first groove is less than 150 um.

15. The chip packaging structure according to any one of claims 1 to 14, characterized in that: The thickness of the glass core board in the direction from the first wiring layer to the first cladding layer is 50um-2000um.

16. The chip packaging structure according to any one of claims 1 to 15, characterized in that: A solder ball array and a copper pillar bump array are arranged on a side of the second wiring layer away from the first cladding layer.

17. A method for manufacturing a chip packaging structure, characterized in that: The method comprises: Prepare metallized vias on the glass core board; forming a first wiring layer on a first side of the glass core board, and mounting a first chip on the first wiring layer; the first wiring layer is electrically connected to the metallized via; A second chip is mounted on the second side of the glass core board, and a first cladding layer is formed; the first cladding layer wraps the second chip and has a first conductive column arranged therethrough, and the first conductive column is electrically connected to the first wiring layer through the metallized via.

18. The manufacturing method according to claim 17, characterized in that: The method further comprises: A second wiring layer is formed on a side of the first cladding layer away from the glass core board, and the second wiring layer is electrically connected to the first conductive column.

19. The manufacturing method according to claim 18, characterized in that: Before the second chip is installed on the second side of the glass core board, the method further includes: A third wiring layer is formed on the second side of the glass core board, and a solder ball is formed on the surface of the third wiring layer on one side close to the first cladding layer; the third wiring layer is electrically connected to the first wiring layer through the metallized via hole, and the first conductive column is electrically connected to the metallized via hole through the third wiring layer; The step of installing a second chip on the second side of the glass core board comprises: The second chip is soldered to the solder balls.

20. The method according to any one of claims 17 to 19, characterized in that: Before forming the first wiring layer on the first side of the glass core board, the method further includes: A second cladding layer is formed on the first side of the glass core board, wherein the second cladding layer has a second conductive column disposed therethrough; and the metallized via is electrically connected to the first wiring layer through the second conductive column.

21. The manufacturing method according to claim 20, characterized in that: Before forming the second cladding layer on the first side of the glass core board, the method further comprises: A third chip is mounted on the first side of the glass core board, and the second cladding layer wraps the third chip; the third chip is electrically connected to the first wiring layer.

22. The method according to any one of claims 17 to 19, characterized in that: Before forming the first wiring layer on the first side of the glass core board, the manufacturing method further includes: Making a first groove on a first side surface of the glass core board; A third chip is mounted in the first groove; the third chip is electrically connected to the first wiring layer.

23. The method according to claim 21 or 22, characterized in that: The number of the first chips is multiple; The third chip is an electrical interconnection structure, and different first chips are electrically connected via the electrical interconnection structure.

24. An electronic device, characterized in that: include: Motherboard; According to the chip packaging structure as described in any one of claims 1-16, the main board is arranged on a side of the glass core board in the chip packaging structure where the first cladding layer is arranged, and is electrically connected to the chip packaging structure.

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