A method, apparatus, equipment, and medium for optimal range control of a phase shifter.

Abstract

This invention relates to the field of control technology for flexible AC circuits, and particularly to a method, apparatus, device, and medium for optimal control of a phase shifter. The method includes: setting a reference power and calculating real-time active power; entering a closed-loop control mode and inputting the deviation between the real-time active power and the reference power into a PI controller to generate a continuous range signal; converting the continuous range signal into a discrete range signal and selecting the signal closest to the reference power; driving the phase shifter to adjust the taps of the parallel transformer to regulate the real-time active power of the line; if the deviation exceeds a preset threshold, maintaining the closed-loop control mode for adjustment; if the deviation is within the threshold, entering a range trial mode to determine the power change trend; if the trend is opposite, switching to an open-loop mode and clearing the PI controller error, saving the current range as the reference range; adjusting the reference range to record the deviation value, selecting the range with the smallest deviation as the optimal range, completing the optimization control, and improving line transmission efficiency.

Description

Technical Field

[0001] This invention relates to the field of control technology for flexible AC, and in particular to a method, apparatus, equipment and medium for optimal control of the gear position of a phase shifter. Background Technology

[0002] Currently, as my country's power grid continues to expand, the operational efficiency of power grids in densely loaded areas is becoming increasingly apparent, and local transmission bottlenecks are hindering the improvement of regional power supply capacity. Due to the scarcity of land resources in densely loaded areas, the difficulty of power grid construction is constantly increasing, and traditional power flow control methods such as generation regulation and load transfer are slow and ineffective.

[0003] A phase shifter is a new type of power flow control device and a special type of transformer. It controls the active power of a line by changing the voltage phase angle at the connection point. Due to its economic and compact characteristics, it has broad application prospects in densely loaded areas and renewable energy consumption scenarios.

[0004] As a key component in electrical systems for adjusting phase and optimizing power transmission, the control performance of phase shifters directly affects the overall efficiency and stability of the system. Since phase shifters are discrete power flow control devices, the dual-loop control methods commonly used in unified power flow controllers and other equipment are not applicable to their control. How to achieve optimal control of phase shifters and realize the power flow control target of the power grid is the key issue for phase shifters to play their regulatory role.

[0005] The information disclosed in this background section is intended only to enhance the understanding of the general background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0006] This invention provides a method, apparatus, device, and medium for optimal control of the gear position of a phase shifter, thereby effectively solving the problems in the background art.

[0007] To achieve the above objectives, the technical solution adopted by this invention is: a phase shifter gear optimization control method, which is implemented based on a gear optimization controller and a line power flow calculator. The gear optimization controller includes a PI controller, an analog-to-digital converter, and a drive trigger. The method includes the following steps:

[0008] S10: Set the reference power, which is determined according to the requirements and objectives of system power flow control;

[0009] S20: The real-time voltage and current signals of the line where the phase shifter is located are collected by the line power flow calculator, and the real-time active power is calculated.

[0010] S30: Enter closed-loop control mode, input the deviation between the real-time active power and the reference power to the PI controller, and generate a continuous gear signal;

[0011] S40: The continuous gear signal is converted into a discrete gear signal by the analog-to-digital converter, and the discrete gear signal that is closest to the reference power is selected.

[0012] S50: Input the discrete tap signal to the drive trigger to drive the phase shifter to adjust the tap connection position of the parallel transformer in order to adjust the real-time active power of the line.

[0013] S60: Obtain the adjusted real-time active power through the line power flow calculator, and calculate the deviation between the real-time active power and the reference power; if the deviation exceeds the preset threshold, maintain the closed-loop control mode and return to step S30 to continue adjustment; if the deviation is within the preset threshold, enter the gear probing mode.

[0014] S70: In gear probing mode, determine whether the real-time active power in closed-loop control mode has an opposite trend. If so, end the closed-loop control mode and enter open-loop control mode. At the same time, clear the error of the PI controller and retain the current output gear as the reference gear.

[0015] S80: Based on the current reference gear, sequentially perform the increase or decrease operation of the reference gear to form multiple adjustment gears, and record the deviation between the real-time active power and the reference power under each adjustment gear.

[0016] S90: Compare the deviations between the real-time active power and the reference power under multiple adjustment gears, select the gear with the smallest deviation as the optimal gear, and control the phase shifter to operate at the optimal gear to complete the gear optimization control.

[0017] Further, in step S20, the real-time voltage and current signals of the line where the phase shifter is located are acquired by the line power flow calculator, and the real-time active power is calculated. The calculation model for the real-time active power includes:

[0018]

[0019] In the formula, P is the real-time active power, and u d u q To express the three-phase voltage u in the abc coordinate system a u b u c The voltage in the dq coordinate system is obtained by performing the Park transformation, i d 、i q To convert the three-phase current i in the abc coordinate systema 、i b 、i c The Park transformation is performed to obtain the current in the dq coordinate system.

[0020] Furthermore, the PI controller includes a proportional control element and an integral control element. The PI controller receives the deviation between the active power calculated in real time by the line power flow calculator and the reference power as a deviation signal, and generates an adjustment signal based on the deviation signal; wherein:

[0021] The proportional control loop processes the deviation signal in real time to generate an adjustment signal that is proportional to the magnitude of the deviation. When the system detects a deviation, the proportional control loop responds quickly to the deviation signal to reduce the dynamic deviation in a timely manner.

[0022] The integral control loop accumulates the deviation signal to generate an integral signal for correcting the steady-state error; the integral control loop generates a correction signal by accumulating the deviation signal over a long period of time to gradually eliminate the steady-state error of the system.

[0023] Further, the analog-to-digital converter includes a zero-step hold and an amplitude limiter. In step S40, the continuous gear signal is converted into a discrete gear signal by the analog-to-digital converter, and the discrete gear signal closest to the reference power is selected. The steps include:

[0024] S41: The continuous gear signal output by the PI controller is transformed into a discrete gear signal through Z-transformation, generating a stepped discrete signal; the Z-transformation is used to perform time discretization processing on the continuous signal, decomposing the continuous signal into a stepped signal with fixed intervals.

[0025] S42: The amplitude of the discrete gear signal is limited by an amplitude limiter to ensure that the output signal operates within the physical limits of the phase shifter; the amplitude limiter presets the maximum and minimum amplitudes according to the gear range of the phase shifter;

[0026] S43: The discrete gear signal after amplitude limitation is input to the gear selection module and compared with the reference power; the discrete gear signal closest to the reference power is selected as the basis for gear adjustment, and the phase shifter is driven to adjust the gear to achieve optimized matching between the output power and the reference power.

[0027] Furthermore, in step S41, the continuous gear position signal output by the PI controller is transformed into a discrete gear position signal through Z-transformation, generating a stepped discrete signal. The stepped discrete gear position signal is then input to a 0-step hold for processing. The 0-step hold keeps the signal output value constant in each sampling period to ensure the consistency of the signal in the time domain and provide a stable input signal for the subsequent gear selection module.

[0028] Furthermore, in step S42, the amplitude limiter dynamically sets the minimum and maximum range of the output signal based on the actual number of taps on the secondary side of the parallel transformer of the phase shifter and the system operating parameters. The amplitude limiter can output discrete voltage signals with positive or negative polarity.

[0029] When the output discrete range signal of the 0-step hold is lower than the minimum value, the amplitude limiter will limit the output discrete range signal to the minimum value;

[0030] When the output discrete range signal of the 0-step hold is higher than the maximum value, the amplitude limiter will limit the output discrete range signal to the maximum value;

[0031] When the output discrete range signal of the 0-step hold is within the range of maximum and minimum values, the amplitude limiter keeps the original output value of the discrete range signal unchanged;

[0032] The output signal of the amplitude limiter is transmitted as an input signal to the gear selection module to select the gear signal that is closest to the reference power, thereby achieving precise control of the optimal gear.

[0033] Furthermore, in step S70, in gear probing mode, the following steps are used to determine whether the closed-loop control mode is complete, and then switch to open-loop control mode:

[0034] S71: In closed-loop control mode, detect the real-time trend of active power change;

[0035] S72: If the trend of real-time active power changes in the opposite direction, and the deviation between the real-time active power and the reference power is within the preset acceptable range, then the closed-loop control is determined to be completed, the closed-loop control mode is ended and the open-loop control mode is switched.

[0036] S73: After switching to open-loop control mode, the accumulated error value of the PI controller is cleared to zero, eliminating the error accumulation that may occur during closed-loop control, and providing unbiased initial conditions for the open-loop control mode.

[0037] S74: Save the current output gear as the reference gear, and use the reference gear for subsequent exploration and selection of the optimal gear;

[0038] S75: If the deviation between the real-time active power and the reference power does not reach the preset range, the closed-loop control mode is maintained, and the adjustment continues until the deviation enters an acceptable range, and then the gear trial mode is switched.

[0039] Further, in step S80, based on the current reference gear, the reference gear is sequentially increased or decreased to form multiple adjustment gears, and the deviation between the real-time active power and the reference power at each adjustment gear is recorded. The steps include:

[0040] S81: Keep the reference gear unchanged, record the deviation between the real-time active power and the reference power at this time, as deviation 1;

[0041] S82: Adjust the gear down one level from the reference gear, i.e., reference gear -1, hold for a preset time, and record the deviation between the real-time active power and the reference power at this time as deviation 2.

[0042] S83: Adjust the gear from the reference gear up by one gear, i.e., reference gear + 1, hold for a preset time, and record the deviation between the real-time active power and the reference power at this time as deviation 3.

[0043] S84: Compare the deviation 1, the deviation 2 and the deviation 3, select the gear with the smallest deviation as the optimal gear, and save it as the adjustment reference for the phase shifter.

[0044] The present invention also includes a phase shifter gear optimization control device, using the method described above, comprising:

[0045] A reference power setting unit is used to set a reference power, which is determined according to the requirements and objectives of system power flow control;

[0046] The real-time active power calculation unit is used to collect the real-time voltage and current signals of the line where the phase shifter is located through the line power flow calculator, and calculate the real-time active power.

[0047] The closed-loop control unit is used to enter the closed-loop control mode, input the deviation between the real-time active power and the reference power to the PI controller, and generate a continuous gear signal.

[0048] The discrete gear signal conversion and selection unit is used to convert the continuous gear signal into a discrete gear signal through the analog-to-digital converter, and select the discrete gear signal that is closest to the reference power.

[0049] The tap adjustment drive unit is used to input the discrete tap signal to the drive trigger and drive the phase shifter to adjust the tap connection position of the parallel transformer in order to adjust the real-time active power of the line.

[0050] The deviation calculation and closed-loop adjustment unit is used to obtain the adjusted real-time active power through the line power flow calculator and calculate the deviation between the real-time active power and the reference power; if the deviation exceeds a preset threshold, the closed-loop control mode is maintained and the adjustment continues; if the deviation is within the preset threshold, the gear trial mode is entered.

[0051] The gear testing unit is used to determine whether the real-time active power in the closed-loop control mode has an opposite trend in the gear testing mode. If so, the closed-loop control mode is terminated and the open-loop control mode is entered. At the same time, the error of the PI controller is cleared and the current output gear is retained as the reference gear.

[0052] The reference gear adjustment unit is used to sequentially increase or decrease the reference gear based on the current reference gear to form multiple adjustment gears, and to record the deviation between the real-time active power and the reference power at each adjustment gear.

[0053] The optimal gear selection unit is used to compare the deviation between the real-time active power and the reference power under multiple adjustment gears, select the gear with the smallest deviation as the optimal gear, and control the phase shifter to operate at the optimal gear to complete the gear optimization control.

[0054] The present invention also includes a computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, implements the method as described above.

[0055] The present invention also includes a storage medium having a computer program stored thereon, which, when executed by a processor, implements the method as described above.

[0056] The beneficial effects of this invention are as follows:

[0057] The proportional control element in the PI controller rapidly reduces the deviation between the current system state and the target state, achieving initial rapid adjustment. The integral control element effectively eliminates any potential steady-state errors. Then, the continuous signal output by the PI controller is transformed into a discrete signal through Z-transformation. The signal is then input to a zero-step hold circuit to ensure that the output signal value remains constant within each sampling period. A preliminary power level is calculated using a power closed-loop control algorithm. Based on this preliminary power level, the power level is increased or decreased to further determine if there is a power level closer to the target power setting. The optimal power level is then selected, thereby making the line power as close as possible to the set power and improving the transmission efficiency of the line. Attached Figure Description

[0058] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0059] Figure 1 This is the circuit diagram for the phase shifter;

[0060] Figure 2 Flowchart of the range optimization control method for a phase shifter;

[0061] Figure 3 Algorithm diagram for finding the optimal gear position for a phase shifter;

[0062] Figure 4 Waveform diagram of the gear optimization control process;

[0063] Figure 5 A schematic diagram of the gear optimization control device for a phase shifter;

[0064] Figure 6 A schematic diagram of the structure of a computer device. Detailed Implementation

[0065] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0066] The circuit diagram of the phase shifter designed in this invention is as follows: Figure 1 As shown, the phase shifter includes a main circuit and a control circuit. The main circuit includes an adjustable-range transformer, and the control circuit includes a range optimization controller and a line power flow calculator, which together form a closed-loop feedback regulation system. The neutral point of the power supply at the sending end is grounded, and the output terminal of the stator winding is connected to the second line impedance. The adjustable-range transformer has four interfaces: the first interface of the adjustable-range transformer for phase a is connected to phase a, the second interface of the adjustable-range transformer for phase a is connected to phase a, the third interface of the adjustable-range transformer for phase a is connected to phase b, and the adjustable-range transformer for phase a... The fourth interface of the adjustable-span transformer is connected to phase b. The first interface of the adjustable-span transformer of phase b is connected to phase b. The second interface of the adjustable-span transformer of phase b is connected to phase b. The third interface of the adjustable-span transformer of phase b is connected to phase c. The fourth interface of the adjustable-span transformer of phase b is connected to phase c. The first interface of the adjustable-span transformer of phase c is connected to phase c. The second interface of the adjustable-span transformer of phase c is connected to phase c. The third interface of the adjustable-span transformer of phase c is connected to phase a. The fourth interface of the adjustable-span transformer of phase c is connected to phase a. The second line impedance is connected to the receiving end power supply.

[0067] like Figures 2 to 3 The diagram illustrates a method for optimal gear selection control of a phase shifter. This method is implemented using a gear selection controller and a line power flow calculator. The gear selection controller includes a PI controller, an analog-to-digital converter, and a drive trigger. The method includes the following steps:

[0068] S10: Set the reference power. The reference power is determined according to the needs and objectives of the system power flow control and serves as a reference standard for gear optimization control.

[0069] S20: The real-time voltage and current signals of the line where the phase shifter is located are collected by the line power flow calculator, and the real-time active power is calculated.

[0070] S30: Enter closed-loop control mode, input the deviation between real-time active power and reference power to the PI controller, and generate continuous gear signals;

[0071] S40: Converts continuous gear signals into discrete gear signals using an analog-to-digital converter, and selects the discrete gear signal that is closest to the reference power.

[0072] S50: Input the discrete tap signal to the drive trigger to drive the phase shifter to adjust the tap connection position of the parallel transformer in order to regulate the real-time active power of the line.

[0073] S60: Obtain the adjusted real-time active power through the line power flow calculator and calculate the deviation between the real-time active power and the reference power; if the deviation exceeds the preset threshold, maintain the closed-loop control mode and return to step S30 to continue adjustment; if the deviation is within the preset threshold, enter the gear trial mode.

[0074] S70: In gear probing mode, determine whether the real-time active power in closed-loop control mode has the opposite trend. If so, end the closed-loop control mode and enter the open-loop control mode. At the same time, clear the error of the PI controller and retain the current output gear as the reference gear.

[0075] S80: Based on the current reference gear, the reference gear is increased or decreased sequentially to form multiple adjustment gears, and the deviation between the real-time active power and the reference power is recorded for each adjustment gear.

[0076] S90: Compare the deviations between the real-time active power and the reference power under multiple adjustment gears, select the gear with the smallest deviation as the optimal gear, and control the phase shifter to operate at the optimal gear, thus completing the gear optimization control.

[0077] Based on the actual needs or preset conditions of the system, a reference power is set. The reference power is set by comprehensively considering the system's operation optimization goals and power flow constraints. The reference power is the input value of the gear optimization controller and is the reference standard for finding the optimal gear. During the operation of the closed-loop control system, the deviation between the actual output power and the preset reference value is used as the basis for adjustment.

[0078] By acquiring the voltage and current signals of the line in real time and combining them with the reference power for precise power calculation and closed-loop regulation, the system output power is ensured to be as close as possible to the set reference power, thereby improving the accuracy of power regulation. A PI controller is introduced to continuously adjust the real-time active power deviation, and a discrete signal output is achieved through an analog-to-digital converter, ensuring the flexibility of the range adjustment and the speed of dynamic response, which significantly improves the dynamic response performance of the system. Through optimal range selection, the phase shifter is made to operate in the best state close to the target power, thereby optimizing the line power transmission efficiency and reducing system transmission loss.

[0079] By combining a gear-trial mode with closed-loop and open-loop control, and recording deviation data at multiple gears to select the optimal gear, the method effectively overcomes the slow dynamic response of traditional phase shifters. The analog-to-digital converter performs stepwise processing on the continuous signal and sets discrete gear signals, avoiding system oscillations caused by signal abrupt changes and ensuring the stability of the control process. In addition, by setting a deviation threshold, the method effectively prevents the impact of over-adjustment on the system. In the gear-trial mode, the optimal gear is quickly locked by increasing or decreasing the preset reference gear, simplifying complex control logic, reducing adjustment time, and improving system operating efficiency. Through real-time data acquisition and dynamic adjustment, this method is not only applicable to phase shifters but can also be extended to other power control scenarios requiring gear adjustment, demonstrating strong adaptability.

[0080] In this embodiment, in step S20, the real-time voltage and current signals of the line where the phase shifter is located are collected by the line power flow calculator, and the real-time active power is calculated. The calculation model for the real-time active power includes:

[0081]

[0082] In the formula, P is the real-time active power, and u d u q To express the three-phase voltage u in the abc coordinate system a u b u c The voltage in the dq coordinate system is obtained by performing the Park transformation, i d 、i q To convert the three-phase current i in the abc coordinate system a 、i b 、ic The Park transformation is performed to obtain the current in the dq coordinate system.

[0083] Specifically, the line power flow calculator uses the three-phase voltage and three-phase current of the line where the phase shifter is located as input values, and then calculates the three-phase voltage u in the abc coordinate system. a u b u c and three-phase current i a 、i b 、i c Performing the Park transformation yields the voltage u in the dq coordinate system. d u q and current i d 、i q Then, the active power of the line flow is calculated in real time, and the real-time active power is transmitted to the tap optimization controller, which effectively simplifies the calculation process of complex signals, avoids the accumulation of errors caused by phase angle changes, and thus significantly improves the accuracy of active power calculation.

[0084] The PI controller includes a proportional control element and an integral control element. The PI controller receives the deviation between the active power calculated in real-time by the line power flow calculator and the reference power as a deviation signal, and generates an adjustment signal based on the deviation signal; wherein:

[0085] The proportional control loop processes the deviation signal in real time and generates an adjustment signal that is proportional to the magnitude of the deviation. When the system detects a deviation, the proportional control loop responds quickly to the deviation signal to reduce the dynamic deviation in a timely manner, thereby improving the system's response speed and dynamic stability.

[0086] The integral control loop accumulates the deviation signal to generate an integral signal for correcting the steady-state error. By accumulating the deviation signal over a long period, the integral control loop generates a correction signal to gradually eliminate the steady-state error of the system, thereby improving the system's control accuracy and steady-state performance.

[0087] The proportional control stage can respond quickly to real-time deviation signals, significantly reducing dynamic deviations and avoiding system instability caused by power fluctuations. The improved dynamic response allows the phase shifter to quickly adjust its range to adapt to rapid changes in system load. The integral control stage can gradually correct the steady-state error of the system by accumulating long-term deviation signals, making the system output power highly consistent with the reference power. Improving steady-state performance helps optimize the long-term operating efficiency of the system and reduce losses caused by power deviations. The synergistic effect ensures that the phase shifter can maintain high efficiency and reliability in both dynamic adjustment and steady-state operation.

[0088] As a preferred embodiment of the above, the analog-to-digital converter includes a 0-step hold and an amplitude limiter. In step S40, the continuous gear signal is converted into a discrete gear signal by the analog-to-digital converter, and the discrete gear signal closest to the reference power is selected. The steps include:

[0089] S41: The Z-transform transforms the continuous gear signal output by the PI controller into a discrete gear signal, generating a stepped discrete signal. The Z-transform is used to discretize the continuous signal in time, decomposing the continuous signal into a stepped signal with fixed intervals, thereby reducing the impact of signal abrupt changes on the system, smoothing gear signal changes, and reducing system oscillations that may be caused by signal fluctuations.

[0090] S42: The amplitude limiter limits the amplitude of discrete range signals to ensure that the output signal operates within the physical limits of the phase shifter; the amplitude limiter presets the maximum and minimum amplitudes according to the range of the phase shifter to limit the signal from exceeding the allowable range and prevent excessively large or small signal amplitudes from causing system instability or equipment damage.

[0091] S43: Input the discrete gear position signal after amplitude limitation to the gear position selection module and compare it with the reference power; select the discrete gear position signal that is closest to the reference power as the basis for gear position adjustment, and drive the phase shifter to adjust the gear position, so as to achieve optimized matching between the output power and the reference power and improve the line power transmission efficiency.

[0092] The proportional control element in the PI controller rapidly reduces the deviation between the current system state and the target state, achieving initial rapid adjustment. The integral control element effectively eliminates any potential steady-state errors. Then, the continuous signal output by the PI controller is transformed into a discrete signal through Z-transformation. The signal is then input to a zero-step hold circuit to ensure that the output signal value remains constant within each sampling period. A preliminary power level is calculated using a power closed-loop control algorithm. Based on this preliminary power level, the power level is increased or decreased to further determine if there is a power level closer to the target power setting. The optimal power level is then selected, thereby making the line power as close as possible to the set power and improving the transmission efficiency of the line.

[0093] As a preferred embodiment of the above, in step S41, the continuous gear signal output by the PI controller is transformed into a discrete gear signal by Z-transformation, generating a stepped discrete signal. The stepped discrete gear signal is then input to a 0-step hold for processing. The 0-step hold keeps the signal output value constant in each sampling period to ensure the consistency of the signal in the time domain, providing a stable input signal for the subsequent gear selection module and reducing adjustment errors caused by signal fluctuations.

[0094] The Z-transform discretizes the continuous gear position signal, generating a stepped discrete signal with a fixed sampling time interval, eliminating the impact of high-frequency fluctuations and abrupt changes in the continuous signal on the system; the stepped processing smooths the signal changes and avoids system instability caused by drastic signal fluctuations; the 0-step hold keeps the signal value constant in each sampling period, ensuring the consistency of the discrete signal in the time domain; it eliminates the interference of signal jumps or jitter on gear selection, providing a stable signal input for subsequent processing.

[0095] In step S42, the amplitude limiter dynamically sets the minimum and maximum range of the output signal based on the actual number of taps on the secondary side of the parallel transformer of the phase shifter and the system operating parameters. The amplitude limiter can output discrete voltage signals with positive or negative polarity.

[0096] When the output discrete range signal of the 0-step hold is lower than the minimum value, the amplitude limiter will limit the output discrete range signal to the minimum value;

[0097] When the output discrete range signal of the 0-step hold is higher than the maximum value, the amplitude limiter will limit the output discrete range signal to the maximum value;

[0098] When the output discrete range signal of the 0-step hold is within the range of the maximum and minimum values, the amplitude limiter keeps the original output value of the discrete range signal unchanged;

[0099] The output signal of the amplitude limiter is transmitted as an input signal to the gear selection module to select the gear signal that is closest to the reference power, so as to achieve precise control of the optimal gear. The limiting logic of the amplitude limiter ensures that the discrete gear signal conforms to the physical operating range of the phase shifter, avoiding system instability or equipment damage caused by the signal exceeding the range, and improving the safety and reliability of system operation.

[0100] In this embodiment, the amplitude limiter is set based on the actual number of taps on the secondary side of the parallel transformer of the phase shifter. Each phase shifter contains nine secondary taps and can output voltages of both positive and negative polarities. Therefore, the maximum and minimum amplitude limits set by the amplitude limiter are 9 and -9, respectively. When the output discrete range signal of the 0th order hold is lower than -9, the output discrete range signal of the amplitude limiter will be forced to -9. When the output discrete range signal of the 0th order hold is higher than 9, the output discrete range signal of the amplitude limiter will be forced to -9.

[0101] The amplitude limiter ensures that the output signal complies with the physical limits of the secondary tap of the parallel transformer by dynamically setting the minimum and maximum value range of the signal. This avoids equipment overload or hardware damage caused by the signal exceeding the range, and forcibly limits out-of-range signals (such as signals below -9 or above 9) to a safe range (-9 to 9). This effectively avoids the risk of operational runaway caused by abnormal signals and improves the operational safety of the system.

[0102] In this embodiment, in step S70, under the gear probing mode, the following steps are used to determine whether the closed-loop control mode is complete, and then switch to the open-loop control mode:

[0103] S71: In closed-loop control mode, detect the trend of real-time active power change; if the trend of real-time active power change relative to the reference power changes from decreasing to increasing in the opposite direction, it indicates that the actual power is close to the reference power.

[0104] S72: If the trend of real-time active power changes in the opposite direction, and the deviation between real-time active power and reference power is within the preset acceptable range, then the closed-loop control is determined to be completed, the closed-loop control mode ends and the open-loop control mode is switched.

[0105] S73: After switching to open-loop control mode, the accumulated error value of the PI controller is cleared to zero, eliminating the error accumulation that may occur during closed-loop control and providing unbiased initial conditions for open-loop control mode.

[0106] S74: Save the current output gear as the reference gear and use the reference gear for subsequent exploration and selection of the optimal gear;

[0107] S75: If the deviation between the real-time active power and the reference power does not reach the preset range, the closed-loop control mode will be maintained and the adjustment will continue until the deviation enters an acceptable range before switching to the gear probing mode.

[0108] By adjusting in reverse according to the real-time active power change trend, the system ensures that it only switches to open-loop control mode when the actual power is close to the reference power, reducing erroneous adjustments caused by unclear switching conditions. By clearing the accumulated error of the PI controller, it provides a deviation-free initial condition for open-loop control, avoiding interference from historical errors in subsequent gear adjustments and improving the accuracy of open-loop control. The reference gear is saved to provide a reliable reference for subsequent gear trials, reducing adjustment errors during the trial process and ensuring that the final selected gear is optimal. By detecting the deviation range and change trend in real time, unnecessary closed-loop adjustments are avoided, and the system quickly enters the open-loop control and gear trial stage, shortening the adjustment time. Switching to open-loop control within a controllable power deviation range avoids frequent closed-loop adjustments and reduces the impact of system power fluctuations on transmission efficiency.

[0109] As a preferred embodiment of the above, in step S80, based on the current reference gear, the reference gear is sequentially increased or decreased to form multiple adjustment gears, and the deviation between the real-time active power and the reference power at each adjustment gear is recorded. The steps include:

[0110] S81: Keep the reference gear unchanged, record the deviation between the real-time active power and the reference power at this time, and use it as deviation 1;

[0111] S82: Adjust the gear down one level from the reference gear, i.e., reference gear -1, hold for a preset time, and record the deviation between the real-time active power and the reference power at this time as deviation 2.

[0112] S83: Adjust the gear from the reference gear up by one gear, i.e., reference gear + 1, hold for a preset time, and record the deviation between the real-time active power and the reference power at this time as deviation 3.

[0113] S84: Compare deviation 1, deviation 2 and deviation 3, select the gear with the smallest deviation as the optimal gear, and save it as the adjustment reference for the phase shifter.

[0114] By probing and adjusting step by step (base level, adjusting down one level, adjusting up one level) and recording the deviation under each adjustment, it is ensured that the optimal level can minimize the deviation between the real-time active power of the system and the base power, thus achieving the purpose of precise matching. By probing and comparing the deviations of different levels, the blindness of traditional level selection based solely on a single theoretical value or model calculation is avoided, thereby improving the actual effect of level selection.

[0115] Figure 4The waveform diagram shows the process of range optimization using the phase shifter range optimization control method. The voltage level of the line where the phase shifter is located is 220kV, the maximum output range of the phase shifter is 9 ranges, and the initial control target of the line power flow is 2250MW. At 20s, the power flow control target is adjusted from 2250MW to 1750MW. The discrete range signal corresponding to the purple line in the figure is the range control signal output by the range optimization controller. The red line reflects the change of the reference power setting of the line power flow regulation. The green line is the change of the actual output active power of the line where the phase shifter is located. Initially, the phase shifter operates in a steady state. The base power of the line where the phase shifter is located is 2250MW. Due to the discrete output of the phase shifter, the actual output active power is 2261MW, which is closest to the base power. At 20 seconds, due to the power flow control requirement, the base power of the phase shifter needs to be adjusted from 2250MW to 1750MW. The phase shifter enters a brief gear optimization phase: the system first enters the closed-loop control phase, as shown in the blue dashed box in the figure. It can be seen that the discrete gear signal decreases rapidly, and then several small fluctuations occur in a very short time, eventually stabilizing at gear 6. At the same time, the active power of the line where the phase shifter is located also fluctuates according to the adjustment of the gear signal, eventually changing slowly around 1730MW. The gear at this time is not necessarily the optimal gear, so the system continues to perform gear optimization and enters the gear trial phase. The final stable setting of position 6 during the closed-loop control phase is recorded as the baseline setting. This setting is maintained for two seconds, and the difference between the line's output active power and the baseline power is recorded as difference 1. Next, the setting is adjusted down one position from the current baseline setting (baseline setting minus 1), and this process is repeated for two seconds. At this point, it is clearly visible that the line's output active power is lower than the given baseline power value, with a relatively large deviation. This difference is recorded as difference 2. Subsequently, the system adjusts the setting again, increasing it up one position from the baseline setting (baseline setting plus 1), and this process is repeated for two seconds. During this process, the line's output active power is higher than the given baseline power value, with a large deviation. This difference is recorded as difference 3. Comparing difference 1, difference 2, and difference 3, difference 1 is found to be the smallest. Therefore, the initial baseline setting is determined to be the optimal setting for a line with a control target of 1730MW.

[0116] This invention includes a phase shifter gear optimization control device, using the method described above, such as... Figure 5 Shown, including:

[0117] The reference power setting unit is used to set the reference power, which is determined according to the requirements and objectives of the system power flow control.

[0118] The real-time active power calculation unit is used to collect the real-time voltage and current signals of the line where the phase shifter is located through the line power flow calculator, and calculate the real-time active power.

[0119] The closed-loop control unit is used to enter the closed-loop control mode, input the deviation between the real-time active power and the reference power to the PI controller, and generate a continuous gear signal.

[0120] Discrete gear signal conversion and selection unit is used to convert continuous gear signals into discrete gear signals through analog-to-digital converter, and select the discrete gear signal that is closest to the reference power.

[0121] The tap adjustment drive unit is used to input discrete tap signals to the drive trigger, drive the phase shifter to adjust the tap connection position of the parallel transformer, so as to regulate the real-time active power of the line.

[0122] The deviation calculation and closed-loop adjustment unit is used to obtain the adjusted real-time active power through the line power flow calculator and calculate the deviation between the real-time active power and the reference power. If the deviation exceeds the preset threshold, the closed-loop control mode is maintained and the adjustment continues. If the deviation is within the preset threshold, the gear trial mode is entered.

[0123] The gear testing unit is used to determine whether the real-time active power in the closed-loop control mode has an opposite trend in the gear testing mode. If so, the closed-loop control mode is ended and the open-loop control mode is entered. At the same time, the error of the PI controller is cleared and the current output gear is retained as the reference gear.

[0124] The reference gear adjustment unit is used to sequentially increase or decrease the reference gear based on the current reference gear, forming multiple adjustment gears, and recording the deviation between the real-time active power and the reference power at each adjustment gear.

[0125] The optimal gear selection unit is used to compare the deviation between the real-time active power and the reference power under multiple adjustment gears, select the gear with the smallest deviation as the optimal gear, and control the phase shifter to operate at the optimal gear, thus completing the gear optimization control.

[0126] Please see Figure 6 The diagram shows a structural schematic of a computer device provided in an embodiment of this application. An embodiment of this application provides a computer device 400, including a processor 410 and a memory 420. The memory 420 stores a computer program executable by the processor 410. When the computer program is executed by the processor 410, it performs the method described above.

[0127] This application embodiment also provides a storage medium 430, on which a computer program is stored, and the computer program is executed by a processor 410 to perform the above method.

[0128] The storage medium 430 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read Only Memory (EPROM), Programmable Red-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0129] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. "A plurality of" means two or more, unless otherwise explicitly specified.

[0130] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0131] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0132] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process, and the scope of the preferred embodiments of the invention includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as will be understood by those skilled in the art to which embodiments of the invention pertain.

[0133] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0134] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0135] Those skilled in the art will understand that all or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.

[0136] The storage medium mentioned above can be a read-only memory, a disk, or an optical disk, etc. Although embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention.

Claims

1. A method for optimal range selection control of a phase shifter, characterized in that, This control method is implemented based on a gear optimization controller and a line power flow calculator. The gear optimization controller includes a PI controller, an analog-to-digital converter, and a drive trigger. The method includes the following steps: S10: Set the reference power, which is determined according to the requirements and objectives of system power flow control; S20: The real-time voltage and current signals of the line where the phase shifter is located are collected by the line power flow calculator, and the real-time active power is calculated. S30: Enter closed-loop control mode, input the deviation between the real-time active power and the reference power to the PI controller, and generate a continuous gear signal; The PI controller includes a proportional control element and an integral control element. The PI controller receives the deviation between the active power calculated in real-time by the line power flow calculator and the reference power as a deviation signal, and generates an adjustment signal based on the deviation signal; wherein: The proportional control loop processes the deviation signal in real time to generate an adjustment signal that is proportional to the magnitude of the deviation. When the system detects a deviation, the proportional control loop responds quickly to the deviation signal to reduce the dynamic deviation in a timely manner. The integral control loop accumulates the deviation signal to generate an integral signal for correcting the steady-state error; the integral control loop generates a correction signal by accumulating the deviation signal over a long period of time to gradually eliminate the steady-state error of the system. S40: The continuous gear signal is converted into a discrete gear signal by the analog-to-digital converter, and the discrete gear signal that is closest to the reference power is selected. S50: Input the discrete tap signal to the drive trigger to drive the phase shifter to adjust the tap connection position of the parallel transformer in order to adjust the real-time active power of the line. S60: Obtain the adjusted real-time active power through the line power flow calculator, and calculate the deviation between the real-time active power and the reference power; if the deviation exceeds the preset threshold, maintain the closed-loop control mode and return to step S30 to continue adjustment; if the deviation is within the preset threshold, enter the gear probing mode. S70: In gear probing mode, determine whether the real-time active power in closed-loop control mode has an opposite trend. If so, end the closed-loop control mode and enter open-loop control mode. At the same time, clear the error of the PI controller and retain the current output gear as the reference gear. S80: Based on the current reference gear, sequentially perform the increase or decrease operation of the reference gear to form multiple adjustment gears, and record the deviation between the real-time active power and the reference power under each adjustment gear. S90: Compare the deviations between the real-time active power and the reference power under multiple adjustment gears, select the gear with the smallest deviation as the optimal gear, and control the phase shifter to operate at the optimal gear to complete the gear optimization control.

2. The phase shifter gear optimization control method according to claim 1, characterized in that, In step S20, the real-time voltage and current signals of the line where the phase shifter is located are acquired by the line power flow calculator, and the real-time active power is calculated. The calculation model for the real-time active power includes: In the formula, P is the real-time active power, and u d u q To convert the three-phase voltage u in the abc coordinate system a u b u c The voltage in the dq coordinate system is obtained by performing the Park transformation, i d i q To convert the three-phase current i in the abc coordinate system a i b i c The Park transformation is performed to obtain the current in the dq coordinate system.

3. The phase shifter range optimization control method according to claim 1, characterized in that, The analog-to-digital converter includes a zero-step hold and an amplitude limiter. In step S40, the continuous gear signal is converted into a discrete gear signal by the analog-to-digital converter, and the discrete gear signal closest to the reference power is selected. The steps include: S41: The continuous gear signal output by the PI controller is transformed into a discrete gear signal through Z-transformation, generating a stepped discrete signal; the Z-transformation is used to perform time discretization processing on the continuous signal, decomposing the continuous signal into a stepped signal with fixed intervals. S42: The amplitude of the discrete gear signal is limited by an amplitude limiter to ensure that the output signal operates within the physical limits of the phase shifter; the amplitude limiter presets the maximum and minimum amplitudes according to the gear range of the phase shifter; S43: The discrete gear signal after amplitude limitation is input to the gear selection module and compared with the reference power; the discrete gear signal closest to the reference power is selected as the basis for gear adjustment, and the phase shifter is driven to adjust the gear to achieve optimized matching between the output power and the reference power.

4. The phase shifter range optimization control method according to claim 3, characterized in that, In step S41, the continuous gear signal output by the PI controller is transformed into a discrete gear signal through Z-transformation, generating a stepped discrete signal. The stepped discrete gear signal is then input to a 0-step hold for processing. The 0-step hold keeps the signal output value constant in each sampling period to ensure the consistency of the signal in the time domain and provide a stable input signal for the subsequent gear selection module.

5. The phase shifter gear optimization control method according to claim 3, characterized in that, In step S42, the amplitude limiter dynamically sets the minimum and maximum range of the output signal based on the actual number of taps on the secondary side of the parallel transformer of the phase shifter and the system operating parameters. The amplitude limiter can output discrete voltage signals with positive or negative polarity. When the output discrete range signal of the 0-step hold is lower than the minimum value, the amplitude limiter will limit the output discrete range signal to the minimum value; When the output discrete range signal of the 0-step hold is higher than the maximum value, the amplitude limiter will limit the output discrete range signal to the maximum value; When the output discrete range signal of the 0-step hold is within the range of maximum and minimum values, the amplitude limiter keeps the original output value of the discrete range signal unchanged; The output signal of the amplitude limiter is transmitted as an input signal to the gear selection module to select the gear signal that is closest to the reference power, thereby achieving precise control of the optimal gear.

6. The method for optimal gear selection control of a phase shifter according to claim 1, characterized in that, In step S70, in gear probing mode, the following steps are used to determine whether the closed-loop control mode is complete, and then switch to open-loop control mode: S71: In closed-loop control mode, detect the real-time trend of active power change; S72: If the trend of real-time active power changes in the opposite direction, and the deviation between the real-time active power and the reference power is within the preset acceptable range, then the closed-loop control is determined to be completed, the closed-loop control mode is ended and the open-loop control mode is switched. S73: After switching to open-loop control mode, the accumulated error value of the PI controller is cleared to zero, eliminating the error accumulation that may occur during closed-loop control, and providing unbiased initial conditions for the open-loop control mode. S74: Save the current output gear as the reference gear, and use the reference gear for subsequent exploration and selection of the optimal gear; S75: If the deviation between the real-time active power and the reference power does not reach the preset range, the closed-loop control mode is maintained, and the adjustment continues until the deviation enters an acceptable range, and then the gear trial mode is switched.

7. The phase shifter range optimization control method according to claim 1, characterized in that, In step S80, based on the current reference gear, the reference gear is sequentially increased or decreased to form multiple adjustment gears, and the deviation between the real-time active power and the reference power at each adjustment gear is recorded. The steps include: S81: Keep the reference gear unchanged, record the deviation between the real-time active power and the reference power at this time, as deviation 1; S82: Adjust the gear down one level from the reference gear, i.e., reference gear -1, hold for a preset time, and record the deviation between the real-time active power and the reference power at this time as deviation 2. S83: Adjust the gear from the reference gear up by one gear, i.e., reference gear + 1, hold for a preset time, and record the deviation between the real-time active power and the reference power at this time as deviation 3. S84: Compare the deviation 1, the deviation 2 and the deviation 3, select the gear with the smallest deviation as the optimal gear, and save it as the adjustment reference for the phase shifter.

8. A phase shifter gear optimization control device, characterized in that, Using the method as described in any one of claims 1 to 7, comprising: A reference power setting unit is used to set a reference power, which is determined according to the requirements and objectives of system power flow control; The real-time active power calculation unit is used to collect the real-time voltage and current signals of the line where the phase shifter is located through the line power flow calculator, and calculate the real-time active power. The closed-loop control unit is used to enter the closed-loop control mode, input the deviation between the real-time active power and the reference power to the PI controller, and generate a continuous gear signal. The discrete gear signal conversion and selection unit is used to convert the continuous gear signal into a discrete gear signal through the analog-to-digital converter, and select the discrete gear signal that is closest to the reference power. The tap adjustment drive unit is used to input the discrete tap signal to the drive trigger and drive the phase shifter to adjust the tap connection position of the parallel transformer in order to adjust the real-time active power of the line. The deviation calculation and closed-loop adjustment unit is used to obtain the adjusted real-time active power through the line power flow calculator and calculate the deviation between the real-time active power and the reference power; if the deviation exceeds a preset threshold, the closed-loop control mode is maintained and the adjustment continues; if the deviation is within the preset threshold, the gear trial mode is entered. The gear testing unit is used to determine whether the real-time active power in the closed-loop control mode has an opposite trend in the gear testing mode. If so, the closed-loop control mode is terminated and the open-loop control mode is entered. At the same time, the error of the PI controller is cleared and the current output gear is retained as the reference gear. The reference gear adjustment unit is used to sequentially increase or decrease the reference gear based on the current reference gear to form multiple adjustment gears, and to record the deviation between the real-time active power and the reference power under each adjustment gear. The optimal gear selection unit is used to compare the deviation between the real-time active power and the reference power under multiple adjustment gears, select the gear with the smallest deviation as the optimal gear, and control the phase shifter to operate at the optimal gear to complete the gear optimization control.

9. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the method as described in any one of claims 1-7.

10. A storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the method as described in any one of claims 1-7.

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