Mode control circuit of power factor correction circuit

Abstract

The invention relates to the technical field of circuit control, and discloses a mode control circuit of a power factor correction circuit, comprising: a power factor correction circuit comprising a power grid voltage port, a DC voltage port and a waveform input port; the frequency coefficient determination unit is connected with the power grid voltage port and the direct current voltage port, and generates a frequency coefficient and an average current based on the power grid voltage and the direct current voltage; the mode frequency determining unit is connected with the power grid voltage port, the direct-current voltage port and the frequency coefficient determining unit, and generates a mode frequency based on the power grid voltage, the direct-current voltage and the average current; the working frequency determination unit is connected with the frequency coefficient determination unit and the mode frequency determination unit, and determines the working frequency based on the frequency coefficient and the mode frequency; and the waveform output unit is connected with the working frequency determination unit and the waveform input port and is used for carrying out discontinuous and critical mode control on the power factor correction circuit based on the working frequency. According to the invention, the loss of the switching device in the power factor correction circuit is reduced.

Description

Technical Field

[0001] The present application relates to the technical field of circuit control, and in particular to a mode control circuit of a power factor correction circuit. Background Art

[0002] With the rapid development of power factor correction circuits, power factor correction circuits are being used more and more frequently in various fields, and higher requirements are also being placed on the mode control circuits of power factor correction circuits.

[0003] The mode control circuit of the traditional power factor correction circuit directly and continuously controls the circuit in the critical current mode. This mode control circuit of the power factor correction circuit has a great defect, because it continuously works in the critical current mode, and there is a phenomenon that the operating frequency of PFC (Power Factor Correction) is higher near the zero point of AC (alternating current voltage), and it works at a higher operating frequency under light load conditions (when the inductor current is small). Therefore, the mode control circuit of this power factor correction circuit will have a problem of high operating frequency due to continuous operation in the critical current mode, which will cause greater losses in the switching devices in the power factor correction circuit. Summary of the invention

[0004] The main purpose of the present application is to propose a mode control circuit for a power factor correction circuit, aiming to solve the technical problem of large loss of switching devices in the power factor correction circuit.

[0005] To achieve the above object, the present application provides a mode control circuit of a power factor correction circuit, the mode control circuit of the power factor correction circuit comprising:

[0006] A power factor correction circuit, the power factor correction circuit comprising a grid voltage port, a DC voltage port and a waveform input port;

[0007] a frequency coefficient determination unit, wherein an input end of the frequency coefficient determination unit is connected to the grid voltage port and the DC voltage port, and the frequency coefficient determination unit is used to generate a frequency coefficient and an average current based on a grid voltage of the grid voltage port and a DC voltage of the DC voltage port;

[0008] a mode frequency determination unit, wherein an input end of the mode frequency determination unit is connected to the grid voltage port, the DC voltage port and the first output end of the frequency coefficient determination unit, and the mode frequency determination unit is used to generate a mode frequency based on the grid voltage of the grid voltage port, the DC voltage of the DC voltage port and the average current;

[0009] an operating frequency determination unit, wherein an input end of the operating frequency determination unit is connected to the second output end of the frequency coefficient determination unit and the output end of the mode frequency determination unit, and the operating frequency determination unit is used to determine the operating frequency based on the frequency coefficient and the mode frequency;

[0010] A waveform output unit, wherein the input end of the waveform output unit is connected to the output end of the operating frequency determination unit, the output end of the waveform output unit is connected to the waveform input port, and the waveform output unit is used to perform intermittent and critical mode control on the power factor correction circuit based on the operating frequency.

[0011] In one embodiment, the frequency coefficient determination unit includes an average current output circuit, a frequency coefficient processing circuit and a frequency coefficient output circuit, the frequency coefficient processing circuit is connected to the DC voltage port, the average current output circuit and the frequency coefficient output circuit, the average current output circuit is connected to the grid voltage port, the frequency coefficient output circuit, the input end of the mode frequency determination unit and the input end of the working frequency determination unit, and the frequency coefficient processing circuit includes:

[0012] A zero-order holder, wherein an input end of the zero-order holder is connected to the DC voltage port;

[0013] A first sampling processing chip, wherein a first input terminal of the first sampling processing chip is connected to an output terminal of the zero-order holder, and a second input terminal of the first sampling processing chip is connected to a voltage sampling port;

[0014] A proportional-integral chip, wherein an input end of the proportional-integral chip is connected to an output end of the first sampling and processing chip, and an output end of the proportional-integral chip is connected to the frequency coefficient output circuit;

[0015] A first multiplication device, wherein a first input terminal of the first multiplication device is connected to an output terminal of the proportional-integral chip, a first input terminal of the first multiplication device is connected to a current sampling port, and an output terminal of the first multiplication device is connected to the average current output circuit.

[0016] In one embodiment, the average current output circuit includes:

[0017] A first amplifier, wherein an input terminal of the first amplifier is connected to the grid voltage port;

[0018] a first absolute value device, wherein an input terminal of the first absolute value device is connected to an output terminal of the first amplifier;

[0019] a second multiplication device, wherein a first input terminal of the second multiplication device is connected to an output terminal of the first absolute value device, and a second input terminal of the second multiplication device is connected to an output terminal of the first multiplication device;

[0020] a second amplifier, wherein an input terminal of the second amplifier is connected to an output terminal of the second multiplication device;

[0021] A third multiplication device, wherein a first input terminal of the third multiplication device is connected to an output terminal of the second amplifier, a second input terminal of the third multiplication device is connected to input terminals of the frequency coefficient output circuit and the operating frequency determination unit, and an output terminal of the third multiplication device is connected to an input terminal of the mode frequency determination unit.

[0022] In one embodiment, the frequency coefficient output circuit includes:

[0023] A third amplifier, wherein an input end of the third amplifier is connected to an output end of the proportional-integral chip;

[0024] a second sampling processing chip, wherein a first input terminal of the second sampling processing chip is connected to the output terminal of the third amplifier, and a second input terminal of the second sampling processing chip is connected to the frequency sampling port;

[0025] A first limiting device, wherein the input end of the first limiting device is connected to the output end of the second sampling processing chip, and the output end of the first limiting device is connected to the input end of the operating frequency determination unit and the third multiplication device in the average current output circuit.

[0026] In one embodiment, the mode frequency determination unit includes a first processing circuit and a second processing circuit, the second processing circuit is connected to the first processing circuit, the first output end of the frequency coefficient determination unit and the input end of the operating frequency determination unit, the first processing circuit is connected to the grid voltage port and the DC voltage port, and the second processing circuit includes:

[0027] a second limiting device, wherein an input terminal of the second limiting device is connected to an output terminal of a third multiplication device in the frequency coefficient determination unit;

[0028] a fourth multiplying device, wherein a first input terminal of the fourth multiplying device is connected to the output terminal of the second limiting device, and a second input terminal of the fourth multiplying device is connected to the inductance input port;

[0029] a first dividing device, wherein a first input terminal of the first dividing device is connected to an output terminal of the fourth multiplying device, and a second input terminal of the first dividing device is connected to the first processing circuit;

[0030] A third limiting device, wherein the input end of the third limiting device is connected to the output end of the first dividing device, and the output end of the third limiting device is connected to the input end of the operating frequency determining unit.

[0031] In one embodiment, the first processing circuit includes:

[0032] A second absolute value device, wherein an input terminal of the second absolute value device is connected to the grid voltage port;

[0033] a third sampling processing chip, wherein a first input terminal of the third sampling processing chip is connected to an output terminal of the second absolute value device, and a second input terminal of the third sampling processing chip is connected to the DC voltage port;

[0034] a second dividing device, wherein a first input terminal of the second dividing device is connected to the DC voltage port, and a second input terminal of the second dividing device is connected to an output terminal of the third sampling processing chip;

[0035] A fifth multiplication device, wherein a first input terminal of the fifth multiplication device is connected to an output terminal of the second division device, a second input terminal of the fifth multiplication device is connected to the grid voltage port, and an output terminal of the fifth multiplication device is connected to a second input terminal of the first division device.

[0036] In one embodiment, the operating frequency determination unit includes:

[0037] a third dividing device, wherein a first input terminal of the third dividing device is connected to an output terminal of a third limiting device in the mode frequency determining unit, and a second input terminal of the third dividing device is connected to a second input terminal of a third multiplying device in the frequency coefficient determining unit;

[0038] A fourth limiting device, wherein the input end of the fourth limiting device is connected to the output end of the third dividing device, and the output end of the fourth limiting device is connected to the input end of the waveform output unit.

[0039] In one embodiment, the waveform output unit includes:

[0040] an integrator, wherein an input end of the integrator is connected to an output end of a fourth limiting device in the operating frequency determining unit;

[0041] A first comparator, wherein an input terminal of the first comparator is connected to an output terminal of the integrator, and an output terminal of the first comparator is connected to a reset terminal of the integrator;

[0042] An SR trigger, wherein the set end of the SR trigger is connected to the output end of the first comparator, and the output end of the SR trigger is connected to the waveform input port.

[0043] In one embodiment, the power factor correction circuit is connected to the positive pole of the power grid and the negative pole of the power grid, a first voltage collector is connected between the positive pole of the power grid and the negative pole of the power grid, an output end of the first voltage collector serves as the power grid voltage port, and the power factor correction circuit includes:

[0044] a first diode, wherein an anode of the first diode is connected to a positive electrode of the power grid;

[0045] a second diode, wherein a cathode of the second diode is connected to an anode of the first diode;

[0046] a third diode, wherein an anode of the third diode is connected to a negative electrode of the power grid, and a cathode of the third diode is connected to a cathode of the first diode;

[0047] a fourth diode, wherein a cathode of the fourth diode is connected to an anode of the third diode, and an anode of the fourth diode is connected to an anode of the second diode;

[0048] a first resistor, wherein a first end of the first resistor is connected to a cathode of the third diode;

[0049] a fifth diode, wherein an anode of the fifth diode is connected to the second end of the first resistor;

[0050] an inductor, a first end of the inductor being connected to a cathode of the third diode;

[0051] a second resistor, a first end of the second resistor being connected to a second end of the inductor;

[0052] A switch tube, wherein the drain of the switch tube is connected to the second end of the second resistor, the source of the switch tube is connected to the anode of the fourth diode, and the gate of the switch tube serves as the waveform input port, wherein a current collector is further connected between the anode of the second diode and the source of the switch tube, and the output end of the current collector serves as the inductor current port;

[0053] a sixth diode, wherein an anode of the sixth diode is connected to the second end of the second resistor, and a cathode of the sixth diode is connected to a cathode of the fifth diode;

[0054] A capacitor, a second end of the capacitor being connected to a cathode of the sixth diode;

[0055] A third resistor, wherein the second end of the third resistor is connected to the first end of the capacitor, and the first end of the third resistor is connected to the source of the switch tube, wherein a second voltage collector is connected between the second end of the capacitor and the first end of the third resistor, and the output end of the second voltage collector serves as the DC voltage port.

[0056] In one embodiment, the power factor correction circuit further includes an inductor current port, and the mode control circuit of the power factor correction circuit further includes:

[0057] A second comparator, wherein a first input terminal of the second comparator is connected to the inductor current port, and a second input terminal of the second comparator is connected to an output terminal of a third multiplication device in the frequency coefficient determination unit;

[0058] An upper edge trigger device, wherein the input end of the upper edge trigger device is connected to the output end of the second comparator, and the output end of the upper edge trigger device is connected to the reset end of the SR trigger in the waveform output unit.

[0059] The present application provides a mode control circuit of a power factor correction circuit, wherein the mode control circuit of the power factor correction circuit includes a power factor correction circuit, wherein the power factor correction circuit includes a grid voltage port, a DC voltage port, and a waveform input port; a frequency coefficient determination unit, wherein the input end of the frequency coefficient determination unit is connected to the grid voltage port and the DC voltage port, and the frequency coefficient determination unit is used to generate a frequency coefficient and an average current based on the grid voltage of the grid voltage port and the DC voltage of the DC voltage port; a mode frequency determination unit, wherein the input end of the mode frequency determination unit is connected to the grid voltage port, the DC voltage port, and a first output end of the frequency coefficient determination unit, and the mode frequency determination unit is used to generate a frequency coefficient and an average current based on the grid voltage of the grid voltage port and the DC voltage of the DC voltage port. A frequency determination unit is used to generate a mode frequency based on the grid voltage of the grid voltage port, the DC voltage of the DC voltage port and the average current; an operating frequency determination unit, the input end of the operating frequency determination unit is connected to the second output end of the frequency coefficient determination unit and the output end of the mode frequency determination unit, and the operating frequency determination unit is used to determine the operating frequency based on the frequency coefficient and the mode frequency; a waveform output unit, the input end of the waveform output unit is connected to the output end of the operating frequency determination unit, the output end of the waveform output unit is connected to the waveform input port, and the waveform output unit is used to perform intermittent and critical mode control on the power factor correction circuit based on the operating frequency.

[0060] The frequency coefficient determination unit generates a frequency coefficient and an average current based on the grid voltage collected at the grid voltage port and the DC voltage collected at the DC voltage port, and the mode frequency determination unit generates a mode frequency based on the grid voltage collected at the grid voltage port, the DC voltage collected at the DC voltage port, and the average current, and finally inputs the mode frequency and the frequency coefficient into the working frequency determination unit, so as to determine the corresponding working frequency based on the working frequency determination unit, and then the waveform output unit controls the power factor correction circuit to work in the discontinuous or critical mode based on the working frequency. Thus, the phenomenon that the working frequency of the PFC is higher near the AC zero point and works at a higher working frequency under light load conditions (when the inductor current is small) is avoided in the prior art because of continuous operation in the critical current mode. The grid voltage of the grid voltage port and the DC voltage of the DC voltage port are processed by the frequency coefficient determination unit, the frequency coefficient determination unit, and the mode frequency determination unit to obtain the working frequency, and finally the discontinuous (which can reduce the loss of the switching device) and critical mode control can be performed in the waveform output unit based on the working frequency to avoid the defect of always using the critical current mode, thereby reducing the loss of the switching device in the power factor correction circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0062] Figure 1 A schematic diagram of the structure of a mode control circuit of a power factor correction circuit of the present application;

[0063] Figure 2 This is a connection diagram of a commonly used power factor correction circuit;

[0064] Figure 3 A waveform diagram of a commonly used power factor correction circuit;

[0065] Figure 4 It is another waveform schematic diagram of a mode control circuit of a commonly used power factor correction circuit;

[0066] Figure 5 A waveform diagram of a mode control circuit of the power factor correction circuit of the present application;

[0067] Figure 6 A circuit connection diagram of a frequency coefficient processing circuit in a mode control circuit of a power factor correction circuit of the present application;

[0068] Figure 7 A circuit connection diagram of an average current output circuit in a mode control circuit of a power factor correction circuit of the present application;

[0069] Figure 8 A circuit connection diagram of a frequency coefficient output circuit in a mode control circuit of a power factor correction circuit of the present application;

[0070] Fig. 9 A schematic diagram of a module of a frequency coefficient determination unit in a mode control circuit of a power factor correction circuit of the present application;

[0071] Fig.10 A circuit connection diagram of a second processing circuit in a mode control circuit of the power factor correction circuit of the present application;

[0072] Fig.11 A circuit connection diagram of a first processing circuit in a mode control circuit of a power factor correction circuit of the present application;

[0073] Fig.12 A schematic diagram of a module of a mode frequency determination unit in a mode control circuit of a power factor correction circuit of the present application;

[0074] Fig.13 A circuit connection diagram of a working frequency determination unit in a mode control circuit of a power factor correction circuit of the present application;

[0075] Fig.14 A circuit connection diagram of a waveform output unit in a mode control circuit of a power factor correction circuit of the present application;

[0076] Fig.15 A circuit connection diagram of a power factor correction circuit in a mode control circuit of the power factor correction circuit of the present application;

[0077] Fig.16 A schematic diagram of an overall circuit connection of a mode control circuit of the power factor correction circuit of the present application;

[0078] Fig.17 A waveform diagram of a first embodiment of a mode control circuit of a power factor correction circuit of the present application;

[0079] Fig.18 A waveform diagram of a second embodiment of a mode control circuit of a power factor correction circuit of the present application;

[0080] Fig.19 It is a waveform diagram of the third embodiment of the mode control circuit of the power factor correction circuit of the present application.

[0081] Description of Figure Numbers:

[0082] 10. Power factor correction circuit; 11. Grid voltage port; 12. DC voltage port; 13. Waveform input port; 20. Frequency coefficient determination unit; 30. Mode frequency determination unit; 40. Working frequency determination unit; 50. Waveform output unit; 21. Frequency coefficient processing circuit; 22. Average current output circuit; 23. Frequency coefficient output circuit; 31. First processing circuit; 32. Second processing circuit; Z. Zero-order holder; Y1. Voltage sampling port; E1. First sampling processing chip; B. Proportional integral chip; Y2. Current sampling port; X1. First multiplication device; F1. First amplifier; U1. First absolute value device; X2. Second multiplication device; F2. Second amplifier; X3. Third multiplication device; F3. Third amplifier; Y3. Frequency sampling port; E2. Second sampling Processing chip; Z1, the first limiting device; Z2, the second limiting device; Y4, the inductance input port; X4, the fourth multiplication device; M1, the first division device; Z3, the third limiting device; E3, the third sampling processing chip; U2, the second absolute value device; M2, the second division device; X5, the fifth multiplication device; M3, the third division device; Z4, the fourth limiting device; J, integrator; A1, the first comparator; S1, the SR trigger; D1-D6, the first diode-the sixth diode; V1, the first voltage collector; VAC, the grid voltage; A, the current collector; IAC, the inductor current; Q1, the switch tube; L, the inductor; V2, the second voltage collector; VO, the DC voltage; R1-R3, the first resistor-the third resistor; C, the capacitor; A2, the second comparator; N, the upper edge trigger device.

[0083] The purpose, features and advantages of this application will be further described in conjunction with the embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0084] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0085] It should be noted that if the embodiments of the present application involve directional indications (such as up, down, left, right, front, back...), the directional indications are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0086] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present application, the descriptions of "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or suggesting their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0087] The present application provides a mode control circuit of a power factor correction circuit, referring to Figure 1 A schematic diagram of the structure of a mode control circuit of a power factor correction circuit, wherein the mode control circuit of the power factor correction circuit comprises:

[0088] A power factor correction circuit 10, wherein the power factor correction circuit 10 comprises a grid voltage port 11, a DC voltage port 12 and a waveform input port 13;

[0089] A frequency coefficient determination unit 20, wherein an input end of the frequency coefficient determination unit 20 is connected to the grid voltage port 11 and the DC voltage port 12, and the frequency coefficient determination unit 20 is used to generate a frequency coefficient and an average current based on the grid voltage VAC of the grid voltage port 11 and the DC voltage VO of the DC voltage port 12;

[0090] a mode frequency determination unit 30, wherein an input end of the mode frequency determination unit 30 is connected to the grid voltage port 11, the DC voltage port 12 and the first output end of the frequency coefficient determination unit 20, and the mode frequency determination unit 30 is used to generate a mode frequency based on the grid voltage VAC of the grid voltage port 11, the DC voltage VO of the DC voltage port 12 and the average current;

[0091] an operating frequency determination unit 40, wherein an input end of the operating frequency determination unit 40 is connected to the second output end of the frequency coefficient determination unit 20 and the output end of the mode frequency determination unit 30, and the operating frequency determination unit 40 is used to determine the operating frequency based on the frequency coefficient and the mode frequency;

[0092] A waveform output unit 50, wherein the input end of the waveform output unit 50 is connected to the output end of the operating frequency determination unit 40, and the output end of the waveform output unit 50 is connected to the waveform input port 13, and the waveform output unit 50 is used to perform intermittent and critical mode control on the power factor correction circuit 10 based on the operating frequency.

[0093] For example, refer to Figure 2 , Figure 2 This is a connection diagram of a commonly used power factor correction circuit. The figure shows a schematic diagram of the current flow in the power factor correction circuit. The commonly used power factor correction circuit usually uses a BOOST converter. In realizing the function of power factor correction, in actual use, the BOOSTB converter usually works in: CRM (Critical Conduction Mode) and DCM (Discontinuous Conduction Mode). For the critical current mode, it makes the PFC circuit have the advantages of high efficiency and simple control. It is often used in small-power AC-DC power factor correction circuits below 500 watts. The so-called critical mode is to control the inductor current to return to zero point in each switching cycle through PWM (Pulse Width Modulation), and then the inductor current starts from zero point each time it is turned on, so it is called the critical current working mode. Please refer to Figure 3 , Figure 3 A waveform diagram of the mode control circuit of a commonly used power factor correction circuit. Ton in the figure represents the switch-on voltage. Because the input AC voltage (Vac) changes in a sinusoidal pattern, in order to achieve different voltage instantaneous values, it operates in critical current mode. Because the system's operating switching frequency (fSW) is not fixed, but changes inversely to the waveform of the grid's sinusoidal wave. This will make the PFC's operating frequency higher near the AC zero point, and will also work at a higher operating frequency under light load conditions (when the inductor current is small), that is, the PFC's operating frequency reaches its highest when Vac is 0. Further, refer to Figure 4 , Figure 4 This is another waveform diagram of the mode control circuit of a commonly used power factor correction circuit. The figure shows the working waveform of the critical mode PFC. ISW (the same as the inductor current and the diode current) is the current waveform flowing through the switching device when the switch is turned on. Then the current drops to zero in the inductor current off stage. ILPK is the average inductor current. From the analysis of the above figure, it can be seen that the higher switching frequency in the critical current mode will increase the switching loss of the switching device and the magnetic loss of the magnetic device. Overall, in order to ensure the critical current mode operation under light load, the benefits are not obvious. On the contrary, when entering the discontinuous current mode under light load, reducing the switching frequency can actually improve the system working efficiency. Therefore, the mode control circuit of the power factor correction circuit of this application is proposed to control the power factor correction circuit 10 to switch between discontinuous and critical modes.

[0094] Based on the above analysis, from the perspective of the instantaneous value of the PFC inductor current waveform, the difference between CRM and DCM operation lies in the relationship between the equivalent cycle average value and the peak value, which can be referred to Figure 5 , Figure 5 This is a waveform diagram of the mode control circuit of the power factor correction circuit of the present application. When CRM is working, the cycle average current ILavg=ipk / 2, and when DCM is working, because the inductor current has reached zero in advance in the TOFF stage, there will also be a time area with no current in the entire switching cycle, which is named td here. Therefore, the average current value of DCM operation needs to consider the zero current time td. When DCM is working, ILavg=ipk / 2*((ton+toff) / (ton+toff+td)), where ton is the switch on time and toff is the switch off time. Then, the relationship between the zero current time td and the switching frequency is derived, and a k coefficient is established to link the cycle ratio of TDCM / TCRM. Then, according to the input and output voltages, inductance, and peak current, the cycle of CRM operation at this time can be calculated. The cycle of DCM is longer than that of CRM, so the cycle relationship coefficient k can be introduced. When k is greater than 1, the BOOSTPFC power stage will work in DCM; when it is equal to 1, it will work completely according to CRM. Therefore, the DCM / CRM working area conversion can be achieved by adjusting the k coefficient. In order to achieve the light load efficiency of PFC operation, the k coefficient can be changed under light load conditions to make the system work in the DCM area. Under heavy load, the k coefficient can be reduced to 1 to make the system work in the CRM. The frequency coefficient k can be used to adjust and control the system working mode. The calculation formula is as follows:

[0095] Tdcm=ton+toff+td

[0096] Tcrm=ton+toff

[0097]

[0098]

[0099]

[0100] ipk=Iavg*k*2

[0101] Among them, Tdcm is the period of DCM, Tcrm is the period of CRM, k is a determined coefficient, vac is the grid voltage, vo is the DC voltage, Lf is the inductance, ipk is the peak current in the circuit, Iavg is the average current, ILavg is the average current of the inductor, and the above parameters can be collected based on various acquisition instruments and are not limited here. At this time, the td time introduced by the discontinuous mode is equivalent to reducing the cycle average value of DCM. In order to make the cycle average value of the inductor current in the two working modes of DCM / CRM consistent, it is also necessary to compensate the peak current according to td, and the coefficient of td compensation is the inverse relationship of the frequency coefficient k. Therefore, it can be deduced that the average value of different DCM / CRM working modes can be uniformly compensated according to the frequency coefficient k: ipk=iLavg*2*k. In DCM, k is greater than 1, and the average current is compensated by increasing the peak current. In CRM, k=1, and the average current and peak current do not need to be compensated according to theoretical calculations. The calculation formula is as follows:

[0102]

[0103]

[0104]

[0105] ipk=ILavg*2*k

[0106] Therefore, based on the above control, the power factor correction circuit 10 is controlled to work in the intermittent and critical modes to avoid the working defects of the critical mode.

[0107] In this embodiment, the power factor correction circuit 10 includes a grid voltage port 11, a DC voltage port 12 and a waveform input port 13, that is, three pieces of information in the power factor correction circuit 10 need to be used respectively: the grid voltage VAC of the grid voltage port 11, the DC voltage VO of the DC voltage port 12, and the inductor current IAC of the inductor current port. Then, the grid voltage VAC of the grid voltage port 11 and the DC voltage VO of the DC voltage port 12 are determined in the frequency coefficient determination unit 20 to generate the frequency coefficient and the average current, that is, the above coefficient k and the average current Iavg, and then the mode frequency corresponding to the grid voltage VAC of the grid voltage port 11, the DC voltage VO of the DC voltage port 12 and the average current is determined in the mode frequency determination unit 30, that is, the frequency of the control PWM at this time, and finally the working frequency of the switch tube can be controlled based on the mode frequency, so as to realize the intermittent and critical mode control of the power factor correction circuit 10 by the working frequency determined by the working frequency determination unit 40, the working frequency refers to the frequency of the PWM wave, that is, the duration of the high and low levels, so as to finally control the switch tube based on the duration of the high and low levels, so that the power factor correction circuit 10 works in the intermittent mode or the critical mode according to the actual situation, so as to avoid the defect of always using the critical current mode, thereby reducing the loss of the switching device in the power factor correction circuit. It is worth noting that the above methods of determining the working frequency based on the mode frequency and determining the mode frequency based on the frequency coefficient are all implemented by the following circuits, and can also be implemented in other ways, which are not limited here.

[0108] The present embodiment provides a mode control circuit of a power factor correction circuit, wherein the mode control circuit of the power factor correction circuit includes a power factor correction circuit, wherein the power factor correction circuit includes a grid voltage port, a DC voltage port, and a waveform input port; a frequency coefficient determination unit, wherein an input end of the frequency coefficient determination unit is connected to the grid voltage port and the DC voltage port, and the frequency coefficient determination unit is used to generate a frequency coefficient and an average current based on a grid voltage of the grid voltage port and a DC voltage of the DC voltage port; and a mode frequency determination unit, wherein an input end of the mode frequency determination unit is connected to the grid voltage port, the DC voltage port, and a first output end of the frequency coefficient determination unit, and the frequency coefficient determination unit is used to generate a frequency coefficient and an average current based on a grid voltage of the grid voltage port and a DC voltage of the DC voltage port. The mode frequency determination unit is used to generate the mode frequency based on the grid voltage of the grid voltage port, the DC voltage of the DC voltage port and the average current; the working frequency determination unit, the input end of the working frequency determination unit is connected to the second output end of the frequency coefficient determination unit and the output end of the mode frequency determination unit, and the working frequency determination unit is used to determine the working frequency based on the frequency coefficient and the mode frequency; the waveform output unit, the input end of the waveform output unit is connected to the output end of the working frequency determination unit, the output end of the waveform output unit is connected to the waveform input port, and the waveform output unit is used to perform intermittent and critical mode control on the power factor correction circuit based on the working frequency. The frequency coefficient determination unit generates the frequency coefficient and the average current based on the grid voltage collected by the grid voltage port and the DC voltage collected by the DC voltage port, so that the mode frequency determination unit generates the mode frequency based on the grid voltage collected by the grid voltage port, the DC voltage collected by the DC voltage port and the average current, and finally the mode frequency and the frequency coefficient are input to the working frequency determination unit, so that the corresponding working frequency is determined based on the working frequency determination unit, and then the waveform output unit controls the power factor correction circuit to work in the intermittent or critical mode based on the working frequency. This avoids the phenomenon in the prior art that the PFC operating frequency is higher near the AC zero point due to continuous operation in the critical current mode, and operates at a higher operating frequency under light load conditions (when the inductor current is small). The grid voltage at the grid voltage port and the DC voltage at the DC voltage port are processed by the frequency coefficient determination unit, the frequency coefficient determination unit, and the mode frequency determination unit to obtain the operating frequency. Finally, intermittent (which can reduce the loss of the switching device) and critical mode control can be performed in the waveform output unit based on the operating frequency to avoid the defect of always using the critical current mode, thereby reducing the loss of the switching device in the power factor correction circuit.

[0109] Further, in another embodiment of the mode control circuit of the power factor correction circuit of the present application, referring to Figure 6 , Figure 6This is a circuit connection diagram of a frequency coefficient processing circuit in a mode control circuit of a power factor correction circuit of the present application. The frequency coefficient determination unit 20 includes an average current output circuit 22, a frequency coefficient processing circuit 21 and a frequency coefficient output circuit 23. The frequency coefficient processing circuit 21 is connected to the DC voltage port 12, the average current output circuit 22 and the frequency coefficient output circuit 23. The average current output circuit 22 is connected to the grid voltage port 11, the frequency coefficient output circuit 23, the input end of the mode frequency determination unit 30 and the input end of the working frequency determination unit 40. The frequency coefficient processing circuit 21 includes:

[0110] A zero-order holder Z, wherein an input end of the zero-order holder Z is connected to the DC voltage port 12;

[0111] A first sampling processing chip E1, wherein a first input terminal of the first sampling processing chip E1 is connected to the output terminal of the zero-order holder Z, and a second input terminal of the first sampling processing chip E1 is connected to the voltage sampling port Y1;

[0112] A proportional-integral chip B, wherein the input end of the proportional-integral chip B is connected to the output end of the first sampling processing chip E1, and the output end of the proportional-integral chip B is connected to the frequency coefficient output circuit 23;

[0113] A first multiplication device X1, wherein a first input terminal of the first multiplication device X1 is connected to an output terminal of the proportional-integral chip B, a first input terminal of the first multiplication device X1 is connected to a current sampling port Y2, and an output terminal of the first multiplication device X1 is connected to the average current output circuit 21.

[0114] In this embodiment, the frequency coefficient determination unit 20 includes an average current output circuit 22, a frequency coefficient processing circuit 21 and a frequency coefficient output circuit 23. The connection relationship between the frequency coefficient processing circuit 21 and each unit circuit is as follows: Figure 6 As shown, the frequency coefficient processing circuit 21 includes a zero-order holder Z, a first sampling processing chip E1, a proportional integral chip B and a first multiplication device X1. The zero-order holder Z is used to ensure that the input sampling points are interpolated and converted into continuous signals. The voltage sampling port Y1 is a port for collecting DC voltage, which can actually collect 400 DC voltages in a certain state and then calculate the average value. The current sampling port Y2 is used to collect the average current, which can actually collect 8 average currents in a certain state and then calculate the average value. Finally, the product of the two is output to the average current output circuit 22, and the sampled DC current is output to the frequency coefficient output circuit 23.

[0115] Further, refer to Figure 7 , Figure 7This is a circuit connection diagram of an average current output circuit in a mode control circuit of a power factor correction circuit of the present application. The average current output circuit 22 includes:

[0116] A first amplifier F1, wherein an input end of the first amplifier F1 is connected to the grid voltage port 11;

[0117] A first absolute value device U1, wherein an input terminal of the first absolute value device U1 is connected to an output terminal of the first amplifier F1;

[0118] a second multiplication device X2, wherein a first input terminal of the second multiplication device X2 is connected to an output terminal of the first absolute value device U1, and a second input terminal of the second multiplication device X2 is connected to an output terminal of the first multiplication device X1;

[0119] a second amplifier F2, wherein an input terminal of the second amplifier F2 is connected to an output terminal of the second multiplication device X2;

[0120] A third multiplication device X3, a first input end of the third multiplication device X3 is connected to the output end of the second amplifier F2, a second input end of the third multiplication device X3 is connected to the frequency coefficient output circuit 23 and the input end of the operating frequency determination unit 40, and an output end of the third multiplication device X3 is connected to the input end of the mode frequency determination unit 30.

[0121] Specifically, refer to Figure 8 , Figure 8 This is a circuit connection diagram of a frequency coefficient output circuit in a mode control circuit of the power factor correction circuit of the present application. The frequency coefficient output circuit 23 includes:

[0122] A third amplifier F3, wherein the input end of the third amplifier F3 is connected to the output end of the proportional-integral chip B;

[0123] A second sampling processing chip E2, wherein a first input terminal of the second sampling processing chip E2 is connected to an output terminal of the third amplifier F3, and a second input terminal of the second sampling processing chip E2 is connected to a frequency sampling port Y3;

[0124] A first limiting device Z1, wherein the input end of the first limiting device Z1 is connected to the output end of the second sampling processing chip E2, and the output end of the first limiting device Z1 is connected to the input end of the working frequency determination unit 40 and the third multiplication device X3 in the average current output circuit 22.

[0125] In this embodiment, the average current output circuit 22 includes a first amplifier F1, a first absolute value device U1, a second multiplication device X2, a second amplifier F2 and a third multiplication device X3. After being amplified by the first amplifier F1, the grid voltage VAC is de-absoluteized and output to the second multiplication device X2. The absolute value of the grid voltage VAC is multiplied by the product of the output of the frequency coefficient processing circuit 21 and then amplified. After being multiplied by the output of the frequency coefficient output circuit 23, the target average current to be used (i.e., the average current determined in the frequency coefficient determination unit 20 in the above embodiment) is obtained. In the frequency coefficient output circuit 23, the frequency coefficient output circuit 23 includes a third amplifier F3, a second sampling processing chip E2 and a first limiting device Z1. The DC current sampled by the frequency coefficient processing circuit 21 is amplified and sampled by the third amplifier F3. Finally, the output value is limited based on the first limiting device Z1, such as 0-1 limitation, etc., and finally the frequency coefficient determined by the frequency coefficient determination unit 20 is obtained, wherein the frequency sampling port Y3 sets the minimum operating frequency for light load operation. Please refer to Fig. 9 , Fig. 9 This is a module schematic diagram of a frequency coefficient determination unit in the mode control circuit of the power factor correction circuit of the present application. The entire frequency coefficient and average current can also be determined using other currents, and the circuit composition is not limited here.

[0126] Further, in another embodiment of the mode control circuit of the power factor correction circuit of the present application, referring to Fig.10 , Fig.10 This is a circuit connection diagram of the second processing circuit in the mode control circuit of the power factor correction circuit of the present application. The mode frequency determination unit 30 includes a first processing circuit 31 and a second processing circuit 32. The second processing circuit 32 is connected to the first processing circuit 31, the first output end of the frequency coefficient determination unit 10 and the input end of the working frequency determination unit 40. The first processing circuit 31 is connected to the grid voltage port 11 and the DC voltage port 12. The second processing circuit 32 includes:

[0127] a second limiting device Z2, wherein an input terminal of the second limiting device Z2 is connected to an output terminal of a third multiplication device X3 in the frequency coefficient determination unit 10;

[0128] A fourth multiplication device X4, wherein a first input terminal of the fourth multiplication device X4 is connected to the output terminal of the second limiting device Z2, and a second input terminal of the fourth multiplication device X4 is connected to the inductance input port Y4;

[0129] a first dividing device M1, wherein a first input terminal of the first dividing device M1 is connected to an output terminal of the fourth multiplying device X4, and a second input terminal of the first dividing device M3 is connected to the first processing circuit 31;

[0130] A third limiting device Z3 , wherein the input end of the third limiting device Z3 is connected to the output end of the first dividing device M1 , and the output end of the third limiting device Z3 is connected to the input end of the operating frequency determining unit 40 .

[0131] Exemplarily, the mode frequency determination unit 30 includes a first processing circuit 31 and a second processing circuit 32. The connection between the mode frequency determination unit 30 and other unit circuits is shown in FIG. Fig.10 The second processing circuit 32 includes a second limiting device Z2, a fourth multiplication device X4, a first division device M1 and a third limiting device Z3. The average current output by the third multiplication device X3 is limited by the second limiting device Z2, and the average current after limitation is multiplied by the inductance value in the inductance input port Y4. The inductance value in the inductance input port Y4 can be the inductance value in the power factor correction circuit 10 input by the user, and the product of the multiplication of the two is divided by the output result of the first processing circuit 31, and the result is limited to obtain the mode frequency determined by the mode frequency determination unit 30 based on the average current, the grid voltage VAC of the grid voltage port 11 and the DC voltage VO of the DC voltage port 12, so as to facilitate subsequent processing by the working frequency determination unit 40.

[0132] Further, see Fig.11 , Fig.11 This is a circuit connection diagram of a first processing circuit in a mode control circuit of a power factor correction circuit of the present application. The first processing circuit 31 includes:

[0133] A second absolute value device U2, wherein an input end of the second absolute value device U2 is connected to the grid voltage port 11;

[0134] A third sampling and processing chip E3, wherein a first input terminal of the third sampling and processing chip E3 is connected to the output terminal of the second absolute value device U2, and a second input terminal of the third sampling and processing chip E3 is connected to the DC voltage port 12;

[0135] A second dividing device M2, wherein a first input terminal of the second dividing device M2 is connected to the DC voltage port 12, and a second input terminal of the second dividing device M2 is connected to an output terminal of the third sampling processing chip E3;

[0136] A fifth multiplier device X5, wherein a first input terminal of the fifth multiplier device X5 is connected to an output terminal of the second divider device M2, a second input terminal of the fifth multiplier device X5 is connected to the grid voltage port 11, and an output terminal of the fifth multiplier device X5 is connected to a second input terminal of the first divider device M1.

[0137] In this embodiment, the first processing circuit 31 includes a second absolute value device U2, a third sampling processing chip E3 (the sampling processing chip in this application is used to subtract the input, such as the third sampling processing chip E3 subtracts the value of the second input port from the value of the first input port), a second division device M2 and a fifth multiplication device X5. The second absolute value device U2 performs absolute value processing on the grid voltage VAC, and the processed grid voltage VAC is sampled with the DC voltage VO to obtain a sampled voltage. The sampled voltage is first divided by the grid voltage VAC to obtain a division value, and then the division value is multiplied with the DC voltage VO to obtain a value that needs to be input into the second processing circuit 32. Further, reference may be made to Fig.12 , Fig.12 This is a module schematic diagram of a mode frequency determination unit in the mode control circuit of the power factor correction circuit of the present application. The entire mode frequency can also be determined using other currents, and the circuit composition is not limited here.

[0138] In one embodiment, the entire control process is as follows: the inductor current enters the freewheeling discharge mode, and the inductor current decreases. At this time, the control algorithm calculates in real time, and calculates the CRM frequency in the current state according to the input grid voltage VAC, the output DC voltage VO, the peak current given by the current sampling port Y2, and the inductance given by the frequency sampling port Y3, and then calculates the operating frequency under the current working condition according to the frequency coefficient k calculated according to the load level. Finally, the set value of the operating frequency is input to the integrator or digital counter in the operating frequency determination unit 40 to realize the timing and control of the operating frequency. When the output of the integrator reaches the set cycle length, a set signal is sent to the main PWM trigger to start a new cycle PWM. Among them, the frequency coefficient output circuit 23 can use the PFC voltage regulator loop using PI or other types of controllers, and the output of the voltage outer loop is calibrated to a range of 0-1.0 to represent 100% output power. At the same time, the output of the voltage outer loop is used for switching frequency foldback control. The input value Max_k of the frequency sampling port Y3 is used to subtract the output of the third amplifier F3 voltage loop to achieve operation near Max_k when the load is light. Max_k is used to set the minimum operating frequency for light load operation. When the load is added to the heavy load, the k coefficient will drop to a position close to 1.0 to achieve heavy load operation at CRM. In addition, the frequency variable k coefficient is clamped at the lower limit to prevent the loop from calculating a value less than 1.0, allowing the system to enter DCM mode.

[0139] Further, in another embodiment of the mode control circuit of the power factor correction circuit of the present application, referring to Fig.13 , Fig.13 This is a circuit connection diagram of a working frequency determination unit in the mode control circuit of the power factor correction circuit of the present application. The working frequency determination unit 40 includes:

[0140] a third dividing device M3, wherein a first input terminal of the third dividing device M3 is connected to an output terminal of a third limiting device Z3 in the mode frequency determining unit 30, and a second input terminal of the third dividing device M3 is connected to a second input terminal of a third multiplying device X3 in the frequency coefficient determining unit 10;

[0141] A fourth limiting device Z4 , wherein the input end of the fourth limiting device Z4 is connected to the output end of the third dividing device M3 , and the output end of the fourth limiting device X4 is connected to the input end of the waveform output unit 50 .

[0142] In this embodiment, after the mode frequency is determined, the operating frequency will be obtained based on the operating frequency determination unit 40. The operating frequency determination unit 40 includes a third division device M3 and a fourth limiting device Z4. The main function is to process the values ​​of the frequency coefficient determination unit 20 and the mode frequency determination unit 30 to obtain the final required operating frequency, that is, to perform a division operation.

[0143] Further, in another embodiment of the mode control circuit of the power factor correction circuit of the present application, referring to Fig.14 , Fig.14 This is a circuit connection diagram of a waveform output unit in the mode control circuit of the power factor correction circuit of the present application. The waveform output unit 50 includes:

[0144] an integrator J, wherein an input end of the integrator J is connected to an output end of a fourth limiting device Z4 in the operating frequency determining unit 40;

[0145] a first comparator A1, wherein an input terminal of the first comparator A1 is connected to an output terminal of the integrator J, and an output terminal of the first comparator A1 is connected to a reset terminal of the integrator J;

[0146] SR trigger S1, the set end of the SR trigger S1 is connected to the output end of the first comparator A1, and the output end of the SR trigger S1 is connected to the waveform input port 13.

[0147] In this embodiment, after the operating frequency is obtained, PWM is driven based on the operating frequency, and comparison is performed based on the first comparator A1 to determine which mode the operation is in. Because the parameters for calculating k can be known by determining the driving PWM, the size of k can be determined to achieve intermittent and critical mode control.

[0148] Further, in another embodiment of the mode control circuit of the power factor correction circuit of the present application, referring to Fig.15 , Fig.15 This is a circuit connection diagram of a power factor correction circuit in a mode control circuit of the power factor correction circuit of the present application. The power factor correction circuit 10 is connected to the positive pole of the power grid and the negative pole of the power grid. A first voltage collector V1 is connected between the positive pole of the power grid and the negative pole of the power grid. The output end of the first voltage collector V1 serves as the power grid voltage port 11. The power factor correction circuit 10 includes:

[0149] A first diode D1, wherein an anode of the first diode D1 is connected to a positive electrode of the power grid;

[0150] a second diode D2, wherein a cathode of the second diode D2 is connected to an anode of the first diode D1;

[0151] a third diode D3, wherein an anode of the third diode D3 is connected to a negative electrode of the power grid, and a cathode of the third diode D3 is connected to a cathode of the first diode D1;

[0152] a fourth diode D4, wherein a cathode of the fourth diode D4 is connected to an anode of the third diode D3, and an anode of the fourth diode D4 is connected to an anode of the second diode D2;

[0153] a first resistor R1, wherein a first end of the first resistor R1 is connected to a cathode of the third diode D3;

[0154] a fifth diode D5, wherein an anode of the fifth diode D5 is connected to the second end of the first resistor R1;

[0155] an inductor L, wherein a first end of the inductor L is connected to a cathode of the third diode D3;

[0156] a second resistor R2, wherein a first end of the second resistor R2 is connected to a second end of the inductor L;

[0157] A switch tube Q1, wherein the drain of the switch tube Q1 is connected to the second end of the second resistor R2, the source of the switch tube Q1 is connected to the anode of the fourth diode D4, and the gate of the switch tube Q1 serves as the waveform input port 13, wherein a current collector A is further connected between the anode of the second diode D1 and the source of the switch tube Q1, and the output end of the current collector A serves as the inductor current port;

[0158] a sixth diode D6, wherein an anode of the sixth diode D6 is connected to the second end of the second resistor R2, and a cathode of the sixth diode D6 is connected to a cathode of the fifth diode D5;

[0159] A capacitor C, a second end of the capacitor C is connected to the cathode of the sixth diode D6;

[0160] A third resistor R3, a second end of the third resistor R3 is connected to the first end of the capacitor C, and the first end of the third resistor R3 is connected to the source of the switch tube Q1, wherein a second voltage collector V2 is connected between the second end of the capacitor C and the first end of the third resistor R3, and an output end of the second voltage collector V2 serves as the DC voltage port 12.

[0161] In this embodiment, the power factor correction circuit 10 can be composed of the above circuits or other components, which are not limited here. That is, it is necessary to collect the grid voltage VAC, DC voltage VO and inductor current IAC in the power factor correction circuit 10, which can be set at other equivalent positions for collection, and the specific position is not limited here.

[0162] Further, in another embodiment of the mode control circuit of the power factor correction circuit of the present application, referring to Fig.16 , Fig.16 1 is a schematic diagram of an overall circuit connection of a mode control circuit of a power factor correction circuit of the present application. The power factor correction circuit 10 further includes an inductor current port. The mode control circuit of the power factor correction circuit further includes:

[0163] A second comparator A2, wherein a first input terminal of the second comparator A2 is connected to the inductor current port, and a second input terminal of the second comparator A2 is connected to an output terminal of a third multiplication device X3 in the frequency coefficient determination unit 10;

[0164] An upper edge trigger device N, wherein the input end of the upper edge trigger device N is connected to the output end of the second comparator A2 , and the output end of the upper edge trigger device N is connected to the reset end of the SR trigger S1 in the waveform output unit 50 .

[0165] In this embodiment, the mode control circuit of the power factor correction circuit also includes a second comparator A2 and an upper edge trigger device N, which is mainly used to control the PWM TON shutdown: when the output of the voltage outer loop is multiplied by the sampling of the grid voltage and used as the average value control amount of the PFC inductor current, then the iPK inductor peak current setting value is calculated through the relationship derived above, and the peak current setting and the inductor current sampling value (inductor current IAC) are compared and contrasted in real time using an analog comparator (second comparator A2). When the inductor current IAC is greater than the peak current setting value IPK (it can also be the average current calculated by the frequency coefficient determination unit 20) in the PWM ON stage, a reset signal is sent to the SR trigger to shut down the PWM to achieve the shutdown control of the switch tube. Further, please refer to Fig.17 , Fig.17 This is a waveform diagram of the first embodiment of the mode control circuit of the power factor correction circuit of the present application. By gradually increasing the load current to full load, it can be observed that the operation control of the entire system is achieved by changing the frequency coefficient k. It can be seen that PFC control can be achieved under all load positions. Among them, the six areas from top to bottom are: grid voltage (waveform with larger amplitude) and AC input current, peak current with larger given amplitude) and inductor current instantaneous value sampling, PWM output, frequency control coefficient k, load current, and PWM cycle calculation value; refer to Fig.18 , Fig.18 This is a waveform diagram of the second embodiment of the mode control circuit of the power factor correction circuit of the present application. When the power factor correction circuit works in the critical mode, the three regions from top to bottom are: grid voltage (upper straight line portion) and AC input current, peak current setting (upper straight line portion) and inductor current instantaneous value sampling, PWM output; refer to Fig.19 , Fig.19 This is a waveform diagram of the third embodiment of the mode control circuit of the power factor correction circuit of the present application. When the power factor correction circuit works in the critical mode, the grid voltage (the upper straight line part) and the AC input current, the peak current setting (the upper straight line part) and the instantaneous value sampling of the inductor current, and the PWM output. It can be seen from the above waveforms that the entire control process implements the control of DCM / CRM PFC in a simple and reliable way, with low distortion of the input current in the full working range, high PF, simple implementation, simple principle, good implementation effect, and at the same time reduces the loss of the switching device in the power factor correction circuit.

[0166] The above description is only a preferred embodiment of the present application, and does not limit the patent scope of the present application. All equivalent structural changes made by using the contents of the present application specification and drawings under the application concept of the present application, or directly / indirectly used in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A mode control circuit of a power factor correction circuit, characterized in that: The mode control circuit of the power factor correction circuit comprises: A power factor correction circuit, the power factor correction circuit comprising a grid voltage port, a DC voltage port and a waveform input port; a frequency coefficient determination unit, wherein an input end of the frequency coefficient determination unit is connected to the grid voltage port and the DC voltage port, and the frequency coefficient determination unit is used to generate a frequency coefficient and an average current based on a grid voltage of the grid voltage port and a DC voltage of the DC voltage port; a mode frequency determination unit, wherein an input end of the mode frequency determination unit is connected to the grid voltage port, the DC voltage port and the first output end of the frequency coefficient determination unit, and the mode frequency determination unit is used to generate a mode frequency based on the grid voltage of the grid voltage port, the DC voltage of the DC voltage port and the average current; an operating frequency determination unit, wherein an input end of the operating frequency determination unit is connected to the second output end of the frequency coefficient determination unit and the output end of the mode frequency determination unit, and the operating frequency determination unit is used to determine the operating frequency based on the frequency coefficient and the mode frequency; A waveform output unit, wherein the input end of the waveform output unit is connected to the output end of the operating frequency determination unit, the output end of the waveform output unit is connected to the waveform input port, and the waveform output unit is used to perform intermittent and critical mode control on the power factor correction circuit based on the operating frequency.

2. The mode control circuit of the power factor correction circuit according to claim 1, characterized in that: The frequency coefficient determination unit includes an average current output circuit, a frequency coefficient processing circuit and a frequency coefficient output circuit. The frequency coefficient processing circuit is connected to the DC voltage port, the average current output circuit and the frequency coefficient output circuit. The average current output circuit is connected to the grid voltage port, the frequency coefficient output circuit, the input end of the mode frequency determination unit and the input end of the working frequency determination unit. The frequency coefficient processing circuit includes: A zero-order holder, wherein an input end of the zero-order holder is connected to the DC voltage port; A first sampling processing chip, wherein a first input terminal of the first sampling processing chip is connected to an output terminal of the zero-order holder, and a second input terminal of the first sampling processing chip is connected to a voltage sampling port; A proportional-integral chip, wherein an input end of the proportional-integral chip is connected to an output end of the first sampling and processing chip, and an output end of the proportional-integral chip is connected to the frequency coefficient output circuit; A first multiplication device, wherein a first input terminal of the first multiplication device is connected to an output terminal of the proportional-integral chip, a first input terminal of the first multiplication device is connected to a current sampling port, and an output terminal of the first multiplication device is connected to the average current output circuit.

3. The mode control circuit of the power factor correction circuit according to claim 2, characterized in that: The average current output circuit comprises: A first amplifier, wherein an input terminal of the first amplifier is connected to the grid voltage port; a first absolute value device, wherein an input terminal of the first absolute value device is connected to an output terminal of the first amplifier; a second multiplication device, wherein a first input terminal of the second multiplication device is connected to an output terminal of the first absolute value device, and a second input terminal of the second multiplication device is connected to an output terminal of the first multiplication device; a second amplifier, wherein an input terminal of the second amplifier is connected to an output terminal of the second multiplication device; A third multiplication device, wherein a first input terminal of the third multiplication device is connected to an output terminal of the second amplifier, a second input terminal of the third multiplication device is connected to input terminals of the frequency coefficient output circuit and the operating frequency determination unit, and an output terminal of the third multiplication device is connected to an input terminal of the mode frequency determination unit.

4. The mode control circuit of the power factor correction circuit according to claim 2, characterized in that: The frequency coefficient output circuit comprises: A third amplifier, wherein an input end of the third amplifier is connected to an output end of the proportional-integral chip; a second sampling processing chip, wherein a first input terminal of the second sampling processing chip is connected to the output terminal of the third amplifier, and a second input terminal of the second sampling processing chip is connected to the frequency sampling port; A first limiting device, wherein the input end of the first limiting device is connected to the output end of the second sampling processing chip, and the output end of the first limiting device is connected to the input end of the operating frequency determination unit and the third multiplication device in the average current output circuit.

5. The mode control circuit of the power factor correction circuit according to claim 1, characterized in that: The mode frequency determination unit includes a first processing circuit and a second processing circuit, the second processing circuit is connected to the first processing circuit, the first output terminal of the frequency coefficient determination unit and the input terminal of the working frequency determination unit, the first processing circuit is connected to the grid voltage port and the DC voltage port, and the second processing circuit includes: a second limiting device, wherein an input terminal of the second limiting device is connected to an output terminal of a third multiplication device in the frequency coefficient determination unit; a fourth multiplying device, wherein a first input terminal of the fourth multiplying device is connected to the output terminal of the second limiting device, and a second input terminal of the fourth multiplying device is connected to the inductance input port; a first dividing device, wherein a first input terminal of the first dividing device is connected to an output terminal of the fourth multiplying device, and a second input terminal of the first dividing device is connected to the first processing circuit; A third limiting device, wherein an input end of the third limiting device is connected to an output end of the first dividing device, and an output end of the third limiting device is connected to an input end of the operating frequency determining unit.

6. The mode control circuit of the power factor correction circuit according to claim 5, characterized in that: The first processing circuit comprises: A second absolute value device, wherein an input terminal of the second absolute value device is connected to the grid voltage port; a third sampling processing chip, wherein a first input terminal of the third sampling processing chip is connected to an output terminal of the second absolute value device, and a second input terminal of the third sampling processing chip is connected to the DC voltage port; a second dividing device, wherein a first input terminal of the second dividing device is connected to the DC voltage port, and a second input terminal of the second dividing device is connected to an output terminal of the third sampling processing chip; A fifth multiplication device, wherein a first input terminal of the fifth multiplication device is connected to an output terminal of the second division device, a second input terminal of the fifth multiplication device is connected to the grid voltage port, and an output terminal of the fifth multiplication device is connected to a second input terminal of the first division device.

7. The mode control circuit of the power factor correction circuit according to claim 1, characterized in that: The operating frequency determination unit comprises: a third dividing device, wherein a first input terminal of the third dividing device is connected to an output terminal of a third limiting device in the mode frequency determining unit, and a second input terminal of the third dividing device is connected to a second input terminal of a third multiplying device in the frequency coefficient determining unit; A fourth limiting device, wherein the input end of the fourth limiting device is connected to the output end of the third dividing device, and the output end of the fourth limiting device is connected to the input end of the waveform output unit.

8. The mode control circuit of the power factor correction circuit according to claim 1, characterized in that: The waveform output unit comprises: an integrator, wherein an input end of the integrator is connected to an output end of a fourth limiting device in the operating frequency determining unit; A first comparator, wherein an input terminal of the first comparator is connected to an output terminal of the integrator, and an output terminal of the first comparator is connected to a reset terminal of the integrator; An SR trigger, wherein the set end of the SR trigger is connected to the output end of the first comparator, and the output end of the SR trigger is connected to the waveform input port.

9. The mode control circuit of the power factor correction circuit according to any one of claims 1 to 8, characterized in that: The power factor correction circuit is connected to the positive pole of the power grid and the negative pole of the power grid, a first voltage collector is connected between the positive pole of the power grid and the negative pole of the power grid, and the output end of the first voltage collector serves as the power grid voltage port. The power factor correction circuit includes: a first diode, wherein an anode of the first diode is connected to a positive electrode of the power grid; a second diode, wherein a cathode of the second diode is connected to an anode of the first diode; a third diode, wherein an anode of the third diode is connected to a negative electrode of the power grid, and a cathode of the third diode is connected to a cathode of the first diode; a fourth diode, wherein a cathode of the fourth diode is connected to an anode of the third diode, and an anode of the fourth diode is connected to an anode of the second diode; a first resistor, wherein a first end of the first resistor is connected to a cathode of the third diode; a fifth diode, wherein an anode of the fifth diode is connected to the second end of the first resistor; an inductor, a first end of the inductor being connected to a cathode of the third diode; a second resistor, a first end of the second resistor being connected to a second end of the inductor; A switch tube, wherein the drain of the switch tube is connected to the second end of the second resistor, the source of the switch tube is connected to the anode of the fourth diode, and the gate of the switch tube serves as the waveform input port, wherein a current collector is further connected between the anode of the second diode and the source of the switch tube, and the output end of the current collector serves as the inductor current port; a sixth diode, wherein an anode of the sixth diode is connected to the second end of the second resistor, and a cathode of the sixth diode is connected to a cathode of the fifth diode; A capacitor, a second end of the capacitor being connected to a cathode of the sixth diode; A third resistor, wherein the second end of the third resistor is connected to the first end of the capacitor, and the first end of the third resistor is connected to the source of the switch tube, wherein a second voltage collector is connected between the second end of the capacitor and the first end of the third resistor, and the output end of the second voltage collector serves as the DC voltage port.

10. The mode control circuit of the power factor correction circuit according to any one of claims 1 to 8, characterized in that: The power factor correction circuit further includes an inductor current port, and the mode control circuit of the power factor correction circuit further includes: A second comparator, wherein a first input terminal of the second comparator is connected to the inductor current port, and a second input terminal of the second comparator is connected to an output terminal of a third multiplication device in the frequency coefficient determination unit; An upper edge trigger device, wherein the input end of the upper edge trigger device is connected to the output end of the second comparator, and the output end of the upper edge trigger device is connected to the reset end of the SR trigger in the waveform output unit.

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