Mode control circuit of power factor correction circuit

Abstract

The present application relates to the field of circuit control technology and discloses a mode control circuit for a power factor correction circuit, comprising: a power factor correction circuit including a grid voltage port, a DC voltage port, and a waveform input port; a frequency coefficient determination unit connected to the grid voltage port and the DC voltage port, generating a frequency coefficient and an average current based on the grid voltage and the DC voltage; a mode frequency determination unit connected to the grid voltage port, the DC voltage port, and the frequency coefficient determination unit, generating a mode frequency based on the grid voltage, the DC voltage, and the average current; an operating frequency determination unit connected to the frequency coefficient determination unit and the mode frequency determination unit, determining an operating frequency based on the frequency coefficient and the mode frequency; and a waveform output unit connected to the operating frequency determination unit and the waveform input port, performing discontinuous and critical mode control on the power factor correction circuit based on the operating frequency. The present application reduces the loss of switching devices in the power factor correction circuit.

Description

Technical Field

[0001] The present application relates to the field of circuit control technology, and in particular to a mode control circuit of a power factor correction circuit. Background Art

[0002] With the rapid development of power factor correction circuits, power factor correction circuits are being used more and more frequently in various fields, and at the same time, higher requirements are being placed on the mode control circuits of power factor correction circuits.

[0003] The mode control circuit of a traditional power factor correction circuit directly and continuously controls the circuit in critical current mode. This type of power factor correction circuit has a major flaw. Because it continuously operates in critical current mode, the operating frequency of the PFC (Power Factor Correction) is higher near the zero point of the AC (alternating current voltage), and it also operates at a higher operating frequency under light load conditions (when the inductor current is small). Therefore, the mode control circuit of this power factor correction circuit will have a high operating frequency problem due to continuously operating in critical current mode, which in turn causes large losses in the switching devices in the power factor correction circuit. Summary of the Invention

[0004] The main purpose of this application is to propose a mode control circuit for a power factor correction circuit, aiming to solve the technical problem of large loss of switching devices in the power factor correction circuit.

[0005] To achieve the above objectives, the present application provides a mode control circuit for a power factor correction circuit, the mode control circuit for the power factor correction circuit comprising:

[0006] A power factor correction circuit, the power factor correction circuit comprising a grid voltage port, a DC voltage port and a waveform input port;

[0007] a frequency coefficient determination unit, wherein an input end of the frequency coefficient determination unit is connected to the grid voltage port and the DC voltage port, and the frequency coefficient determination unit is configured to generate a frequency coefficient and an average current based on the grid voltage of the grid voltage port and the DC voltage of the DC voltage port;

[0008] a mode frequency determination unit, wherein an input end of the mode frequency determination unit is connected to the grid voltage port, the DC voltage port, and the first output end of the frequency coefficient determination unit, and the mode frequency determination unit is configured to generate a mode frequency based on the grid voltage of the grid voltage port, the DC voltage of the DC voltage port, and the average current;

[0009] an operating frequency determining unit, wherein an input terminal of the operating frequency determining unit is connected to the second output terminal of the frequency coefficient determining unit and the output terminal of the mode frequency determining unit, and the operating frequency determining unit is configured to determine an operating frequency based on the frequency coefficient and the mode frequency;

[0010] A waveform output unit, wherein the input end of the waveform output unit is connected to the output end of the operating frequency determination unit, the output end of the waveform output unit is connected to the waveform input port, and the waveform output unit is used to perform intermittent and critical mode control on the power factor correction circuit based on the operating frequency.

[0011] In one embodiment, the frequency coefficient determination unit includes an average current output circuit, a frequency coefficient processing circuit, and a frequency coefficient output circuit. The frequency coefficient processing circuit is connected to the DC voltage port, the average current output circuit, and the frequency coefficient output circuit. The average current output circuit is connected to the grid voltage port, the frequency coefficient output circuit, an input terminal of the mode frequency determination unit, and an input terminal of the operating frequency determination unit. The frequency coefficient processing circuit includes:

[0012] A zero-order keeper, wherein an input end of the zero-order keeper is connected to the DC voltage port;

[0013] a first sampling processing chip, wherein a first input terminal of the first sampling processing chip is connected to the output terminal of the zero-order holder, and a second input terminal of the first sampling processing chip is connected to the voltage sampling port;

[0014] a proportional-integral chip, wherein an input end of the proportional-integral chip is connected to an output end of the first sampling and processing chip, and an output end of the proportional-integral chip is connected to the frequency coefficient output circuit;

[0015] A first multiplication device, wherein the first input end of the first multiplication device is connected to the output end of the proportional-integral chip, the first input end of the first multiplication device is connected to the current sampling port, and the output end of the first multiplication device is connected to the average current output circuit.

[0016] In one embodiment, the average current output circuit includes:

[0017] a first amplifier, wherein an input terminal of the first amplifier is connected to the grid voltage port;

[0018] a first absolute value device, wherein an input terminal of the first absolute value device is connected to an output terminal of the first amplifier;

[0019] a second multiplying device, wherein a first input terminal of the second multiplying device is connected to an output terminal of the first absolute value device, and a second input terminal of the second multiplying device is connected to an output terminal of the first multiplying device;

[0020] a second amplifier, wherein an input terminal of the second amplifier is connected to an output terminal of the second multiplication device;

[0021] a third multiplication device, wherein a first input terminal of the third multiplication device is connected to the output terminal of the second amplifier, a second input terminal of the third multiplication device is connected to the input terminals of the frequency coefficient output circuit and the operating frequency determination unit, and an output terminal of the third multiplication device is connected to the input terminal of the mode frequency determination unit.

[0022] In one embodiment, the frequency coefficient output circuit includes:

[0023] a third amplifier, wherein an input end of the third amplifier is connected to an output end of the proportional-integral chip;

[0024] a second sampling processing chip, wherein a first input terminal of the second sampling processing chip is connected to the output terminal of the third amplifier, and a second input terminal of the second sampling processing chip is connected to the frequency sampling port;

[0025] A first limiting device, wherein the input end of the first limiting device is connected to the output end of the second sampling processing chip, and the output end of the first limiting device is connected to the input end of the operating frequency determination unit and the third multiplication device in the average current output circuit.

[0026] In one embodiment, the mode frequency determination unit includes a first processing circuit and a second processing circuit, the second processing circuit being connected to the first processing circuit, the first output terminal of the frequency coefficient determination unit, and the input terminal of the operating frequency determination unit, the first processing circuit being connected to the grid voltage port and the DC voltage port, and the second processing circuit including:

[0027] a second limiting device, wherein an input terminal of the second limiting device is connected to an output terminal of the third multiplication device in the frequency coefficient determination unit;

[0028] a fourth multiplying device, wherein a first input terminal of the fourth multiplying device is connected to the output terminal of the second limiting device, and a second input terminal of the fourth multiplying device is connected to the inductance input port;

[0029] a first dividing device, wherein a first input terminal of the first dividing device is connected to an output terminal of the fourth multiplying device, and a second input terminal of the first dividing device is connected to the first processing circuit;

[0030] A third limiting device, wherein the input end of the third limiting device is connected to the output end of the first dividing device, and the output end of the third limiting device is connected to the input end of the operating frequency determining unit.

[0031] In one embodiment, the first processing circuit includes:

[0032] a second absolute value device, wherein an input terminal of the second absolute value device is connected to the grid voltage port;

[0033] a third sampling and processing chip, wherein a first input terminal of the third sampling and processing chip is connected to the output terminal of the second absolute value device, and a second input terminal of the third sampling and processing chip is connected to the DC voltage port;

[0034] a second dividing device, wherein a first input terminal of the second dividing device is connected to the DC voltage port, and a second input terminal of the second dividing device is connected to an output terminal of the third sampling and processing chip;

[0035] A fifth multiplication device, wherein a first input terminal of the fifth multiplication device is connected to the output terminal of the second division device, a second input terminal of the fifth multiplication device is connected to the grid voltage port, and an output terminal of the fifth multiplication device is connected to the second input terminal of the first division device.

[0036] In one embodiment, the operating frequency determining unit includes:

[0037] a third dividing device, wherein a first input terminal of the third dividing device is connected to an output terminal of the third limiting device in the pattern frequency determining unit, and a second input terminal of the third dividing device is connected to a second input terminal of the third multiplying device in the frequency coefficient determining unit;

[0038] A fourth limiting device, wherein the input end of the fourth limiting device is connected to the output end of the third dividing device, and the output end of the fourth limiting device is connected to the input end of the waveform output unit.

[0039] In one embodiment, the waveform output unit includes:

[0040] an integrator, wherein an input end of the integrator is connected to an output end of a fourth limiting device in the operating frequency determining unit;

[0041] a first comparator, wherein an input terminal of the first comparator is connected to an output terminal of the integrator, and an output terminal of the first comparator is connected to a reset terminal of the integrator;

[0042] An SR trigger, wherein the set end of the SR trigger is connected to the output end of the first comparator, and the output end of the SR trigger is connected to the waveform input port.

[0043] In one embodiment, the power factor correction circuit is connected to the positive pole and the negative pole of the grid, a first voltage collector is connected between the positive pole and the negative pole of the grid, and the output end of the first voltage collector serves as the grid voltage port. The power factor correction circuit includes:

[0044] a first diode, wherein the anode of the first diode is connected to the positive electrode of the power grid;

[0045] a second diode, wherein a cathode of the second diode is connected to an anode of the first diode;

[0046] a third diode, wherein the anode of the third diode is connected to the negative electrode of the power grid, and the cathode of the third diode is connected to the cathode of the first diode;

[0047] a fourth diode, wherein a cathode of the fourth diode is connected to an anode of the third diode, and an anode of the fourth diode is connected to an anode of the second diode;

[0048] a first resistor, wherein a first end of the first resistor is connected to a cathode of the third diode;

[0049] a fifth diode, wherein an anode of the fifth diode is connected to the second end of the first resistor;

[0050] an inductor, a first end of the inductor being connected to the cathode of the third diode;

[0051] a second resistor, a first end of the second resistor being connected to the second end of the inductor;

[0052] a switching tube, wherein the drain of the switching tube is connected to the second end of the second resistor, the source of the switching tube is connected to the anode of the fourth diode, and the gate of the switching tube serves as the waveform input port, wherein a current collector is further connected between the anode of the second diode and the source of the switching tube, and the output end of the current collector serves as the inductor current port;

[0053] a sixth diode, wherein an anode of the sixth diode is connected to the second end of the second resistor, and a cathode of the sixth diode is connected to the cathode of the fifth diode;

[0054] a capacitor, wherein a second end of the capacitor is connected to a cathode of the sixth diode;

[0055] a third resistor, wherein the second end of the third resistor is connected to the first end of the capacitor, and the first end of the third resistor is connected to the source of the switching tube, wherein a second voltage collector is connected between the second end of the capacitor and the first end of the third resistor, and the output end of the second voltage collector serves as the DC voltage port.

[0056] In one embodiment, the power factor correction circuit further includes an inductor current port, and the mode control circuit of the power factor correction circuit further includes:

[0057] a second comparator, wherein a first input terminal of the second comparator is connected to the inductor current port, and a second input terminal of the second comparator is connected to an output terminal of a third multiplication device in the frequency coefficient determination unit;

[0058] An upper edge trigger device, wherein the input end of the upper edge trigger device is connected to the output end of the second comparator, and the output end of the upper edge trigger device is connected to the reset end of the SR trigger in the waveform output unit.

[0059] The present application provides a mode control circuit of a power factor correction circuit, wherein the mode control circuit of the power factor correction circuit includes a power factor correction circuit, wherein the power factor correction circuit includes a grid voltage port, a DC voltage port, and a waveform input port; a frequency coefficient determination unit, wherein the input end of the frequency coefficient determination unit is connected to the grid voltage port and the DC voltage port, and the frequency coefficient determination unit is used to generate a frequency coefficient and an average current based on the grid voltage of the grid voltage port and the DC voltage of the DC voltage port; a mode frequency determination unit, wherein the input end of the mode frequency determination unit is connected to the grid voltage port, the DC voltage port, and a first output end of the frequency coefficient determination unit, and the mode frequency determination unit is used to generate a frequency coefficient and an average current based on the grid voltage of the grid voltage port and the DC voltage of the DC voltage port. A mode frequency determination unit is used to generate a mode frequency based on the grid voltage of the grid voltage port, the DC voltage of the DC voltage port and the average current; an operating frequency determination unit, the input end of the operating frequency determination unit is connected to the second output end of the frequency coefficient determination unit and the output end of the mode frequency determination unit, and the operating frequency determination unit is used to determine the operating frequency based on the frequency coefficient and the mode frequency; a waveform output unit, the input end of the waveform output unit is connected to the output end of the operating frequency determination unit, the output end of the waveform output unit is connected to the waveform input port, and the waveform output unit is used to perform intermittent and critical mode control on the power factor correction circuit based on the operating frequency.

[0060] A frequency coefficient determination unit generates a frequency coefficient and an average current based on the grid voltage collected at the grid voltage port and the DC voltage collected at the DC voltage port. A mode frequency determination unit then generates a mode frequency based on the grid voltage collected at the grid voltage port, the DC voltage collected at the DC voltage port, and the average current. The mode frequency and frequency coefficient are ultimately input into an operating frequency determination unit, which determines the corresponding operating frequency based on the operating frequency determination unit. The waveform output unit then controls the power factor correction circuit to operate in discontinuous or critical mode based on the operating frequency. This avoids the prior art phenomenon of the PFC operating frequency being high near the AC zero point due to continuous operation in critical current mode, and operating at a higher operating frequency under light load conditions (when the inductor current is low). The frequency coefficient determination unit, the frequency coefficient determination unit, and the mode frequency determination unit process the grid voltage at the grid voltage port and the DC voltage at the DC voltage port to obtain the operating frequency. Finally, discontinuous (which can reduce switching device losses) and critical mode control can be performed in the waveform output unit based on the operating frequency, avoiding the drawback of continuous critical current mode operation and thereby reducing switching device losses in the power factor correction circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0062] Figure 1 This is a schematic structural diagram of a mode control circuit of a power factor correction circuit of the present application;

[0063] Figure 2 This is a connection diagram of a commonly used power factor correction circuit;

[0064] Figure 3 This is a waveform diagram of a commonly used power factor correction circuit;

[0065] Figure 4 This is another waveform diagram of a mode control circuit of a commonly used power factor correction circuit;

[0066] Figure 5 A waveform diagram of a mode control circuit of the power factor correction circuit of the present application;

[0067] Figure 6 A circuit connection diagram of a frequency coefficient processing circuit in a mode control circuit of the power factor correction circuit of the present application;

[0068] Figure 7 A circuit connection diagram of an average current output circuit in a mode control circuit of the power factor correction circuit of the present application;

[0069] Figure 8 A circuit connection diagram of a frequency coefficient output circuit in a mode control circuit of the power factor correction circuit of the present application;

[0070] Figure 9 A schematic diagram of a module of a frequency coefficient determination unit in a mode control circuit of a power factor correction circuit of the present application;

[0071] Figure 10 A circuit connection diagram of a second processing circuit in the mode control circuit of the power factor correction circuit of the present application;

[0072] Figure 11 A circuit connection diagram of a first processing circuit in a mode control circuit of the power factor correction circuit of the present application;

[0073] Figure 12 A schematic diagram of a module of a mode frequency determination unit in a mode control circuit of a power factor correction circuit of the present application;

[0074] Figure 13 A circuit connection diagram of an operating frequency determination unit in a mode control circuit of the power factor correction circuit of the present application;

[0075] Figure 14 This is a circuit connection diagram of a waveform output unit in the mode control circuit of the power factor correction circuit of the present application;

[0076] Figure 15 A circuit connection diagram of a power factor correction circuit in a mode control circuit of the power factor correction circuit of the present application;

[0077] Figure 16 A schematic diagram of the overall circuit connection of the mode control circuit of the power factor correction circuit of the present application;

[0078] Figure 17 This is a waveform diagram of the first embodiment of the mode control circuit of the power factor correction circuit of the present application;

[0079] Figure 18 This is a waveform diagram of the second embodiment of the mode control circuit of the power factor correction circuit of the present application;

[0080] Figure 19 This is a waveform diagram of the third embodiment of the mode control circuit of the power factor correction circuit of the present application.

[0081] Description of Figure Numbers:

[0082] 10. Power factor correction circuit; 11. Grid voltage port; 12. DC voltage port; 13. Waveform input port; 20. Frequency coefficient determination unit; 30. Mode frequency determination unit; 40. Operating frequency determination unit; 50. Waveform output unit; 21. Frequency coefficient processing circuit; 22. Average current output circuit; 23. Frequency coefficient output circuit; 31. First processing circuit; 32. Second processing circuit; Z, zero-order hold; Y1, voltage sampling port; E1, first sampling processing chip; B, proportional integral chip; Y2, current sampling port; X1, first multiplication device; F1, first amplifier; U1, first absolute value device; X2, second multiplication device; F2, second amplifier; X3, third multiplication device; F3, third amplifier; Y3, frequency sampling port; E2, second sampling Processing chip; Z1, first limiting device; Z2, second limiting device; Y4, inductance input port; X4, fourth multiplication device; M1, first division device; Z3, third limiting device; E3, third sampling processing chip; U2, second absolute value device; M2, second division device; X5, fifth multiplication device; M3, third division device; Z4, fourth limiting device; J, integrator; A1, first comparator; S1, SR trigger; D1-D6, first diode-sixth diode; V1, first voltage collector; VAC, grid voltage; A, current collector; IAC, inductor current; Q1, switch tube; L, inductor; V2, second voltage collector; VO, DC voltage; R1-R3, first resistor-third resistor; C, capacitor; A2, second comparator; N, upper edge trigger device.

[0083] The purpose, features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0084] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0085] It should be noted that if the embodiments of the present application involve directional indications (such as up, down, left, right, front, back, etc.), such directional indications are only used to explain the relative position relationship, movement status, etc. between the various components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0086] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present application, the descriptions of "first", "second", etc. are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of such features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the fact that they can be implemented by ordinary technicians in this field. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0087] The present application provides a mode control circuit of a power factor correction circuit, referring to Figure 1 A schematic structural diagram of a mode control circuit of a power factor correction circuit is provided. The mode control circuit of the power factor correction circuit includes:

[0088] A power factor correction circuit 10, comprising a grid voltage port 11, a DC voltage port 12 and a waveform input port 13;

[0089] a frequency coefficient determination unit 20, wherein an input end of the frequency coefficient determination unit 20 is connected to the grid voltage port 11 and the DC voltage port 12, and the frequency coefficient determination unit 20 is configured to generate a frequency coefficient and an average current based on the grid voltage VAC of the grid voltage port 11 and the DC voltage VO of the DC voltage port 12;

[0090] a mode frequency determination unit 30, wherein an input end of the mode frequency determination unit 30 is connected to the grid voltage port 11, the DC voltage port 12, and the first output end of the frequency coefficient determination unit 20, and the mode frequency determination unit 30 is configured to generate a mode frequency based on the grid voltage VAC of the grid voltage port 11, the DC voltage VO of the DC voltage port 12, and the average current;

[0091] an operating frequency determining unit 40, wherein an input end of the operating frequency determining unit 40 is connected to the second output end of the frequency coefficient determining unit 20 and the output end of the mode frequency determining unit 30, and the operating frequency determining unit 40 is configured to determine an operating frequency based on the frequency coefficient and the mode frequency;

[0092] The waveform output unit 50 has an input end connected to the output end of the operating frequency determination unit 40, and an output end of the waveform output unit 50 is connected to the waveform input port 13. The waveform output unit 50 is used to perform intermittent and critical mode control on the power factor correction circuit 10 based on the operating frequency.

[0093] For example, refer to Figure 2 , Figure 2 This is a connection diagram of a commonly used power factor correction circuit. The figure shows a schematic diagram of the current flow in the power factor correction circuit. Commonly used power factor correction circuits usually use BOOST converters. In realizing the function of power factor correction, in actual use, the working modes of BOOSTB converters are usually: CRM (Critical Conduction Mode) and DCM (Discontinuous Conduction Mode). For the critical current mode, it makes the PFC circuit have the advantages of high efficiency and simple control. It is often used in power factor correction circuits of small power AC-DC below 500 watts. The so-called critical mode is to control the inductor current to return to zero point in each switching cycle through PWM (Pulse Width Modulation, pulse width modulation), and then the inductor current starts from zero point each time it is turned on, so it is called the critical current working mode. Please refer to Figure 3 , Figure 3 A waveform diagram of the mode control circuit of a commonly used power factor correction circuit. Ton in the figure represents the switch-on voltage. Since the input AC voltage (Vac) varies in a sinusoidal pattern, in order to achieve different voltage instantaneous values, it operates in critical current mode. This is because the system's operating switching frequency (fSW) is not fixed, but changes inversely to the grid's sinusoidal waveform. This will cause the PFC's operating frequency to be higher near the AC zero point, and will also operate at a higher operating frequency under light load conditions (when the inductor current is small), that is, the PFC's operating frequency reaches its highest when Vac is 0. For further information, refer to Figure 4 , Figure 4 This is another waveform diagram of the mode control circuit of a commonly used power factor correction circuit. The figure shows the operating waveform of the critical mode PFC. ISW (the same as the inductor current and diode current) is the current waveform flowing through the switching device when the switch is turned on. The current then drops to zero during the inductor current off phase. ILPK is the average inductor current. As can be seen from the above figure, a higher switching frequency in the critical current mode will increase the switching loss of the switching device and the magnetic loss of the magnetic device. Overall, the benefits of ensuring critical current mode operation under light load are not obvious. On the contrary, when entering the discontinuous current mode under light load, reducing the switching frequency can actually improve the system operating efficiency. Therefore, the mode control circuit of the power factor correction circuit of this application is proposed to control the power factor correction circuit 10 to switch between discontinuous and critical modes.

[0094] Based on the above analysis, from the perspective of the instantaneous value of the PFC inductor current waveform, the difference between CRM and DCM operation lies in the relationship between the equivalent cycle average value and peak value. Figure 5 , Figure 5 This is a waveform diagram of the mode control circuit of the power factor correction circuit of this application. During CRM operation, the cycle-average current ILavg = ipk / 2. However, during DCM operation, the inductor current reaches zero early during the TOFF phase. In addition, there is a period of zero current during the entire switching cycle, designated as td. Therefore, the average current in DCM operation needs to take into account the zero current time td. During DCM operation, ILavg = ipk / 2 * ((ton + toff) / (ton + toff + td)), where ton is the switch on time and toff is the switch off time. The relationship between the zero current time td and the switching frequency is then derived, establishing a k coefficient to relate the TDCM / TCRM cycle ratio. The CRM cycle can then be calculated based on the input and output voltages, inductance, and peak current. Since the DCM cycle is longer than the CRM cycle, a cycle relationship coefficient k is introduced. When k is greater than 1, the BOOST PFC power stage operates in DCM; when it is equal to 1, it operates entirely in CRM. Therefore, the DCM / CRM operating region conversion can be achieved by adjusting the k coefficient. To achieve light-load efficiency of PFC operation, the k coefficient can be changed under light load conditions to make the system operate in the DCM region. Under heavy load, the k coefficient can be reduced to 1 to make the system operate in the CRM region. The frequency coefficient k can be used to adjust and control the system operating mode. Its calculation formula is as follows:

[0095]

[0096] Among them, Tdcm is the DCM cycle, Tcrm is the CRM cycle, k is a certain coefficient, vac is the grid voltage, vo is the DC voltage, Lf is the inductance, ipk is the peak current in the circuit, Iavg is the average current, and ILavg is the inductor average current. The above parameters can be collected based on various acquisition instruments and are not limited here. At this time, the td time introduced by the discontinuous mode is equivalent to reducing the cycle average value of DCM. In order to make the cycle average value of the inductor current consistent in the DCM / CRM operating modes, it is also necessary to compensate the peak current based on td. The coefficient of td compensation is inversely proportional to the frequency coefficient k. Therefore, it can be deduced that the average value of different DCM / CRM operating modes can be uniformly compensated based on the frequency coefficient k: ipk=iLavg*2*k. In DCM, k is greater than 1, and the average current is compensated by increasing the peak current. In CRM, k=1, and the average current and peak current do not need to be compensated according to theoretical calculations. The calculation formula is as follows:

[0097]

[0098] Therefore, based on the above control, the power factor correction circuit 10 is controlled to operate in the discontinuous and critical modes to avoid the working defects of the critical mode.

[0099] In this embodiment, the power factor correction circuit 10 includes a grid voltage port 11, a DC voltage port 12 and a waveform input port 13, that is, three pieces of information in the power factor correction circuit 10 need to be used respectively: the grid voltage VAC of the grid voltage port 11, the DC voltage VO of the DC voltage port 12, and the inductor current IAC of the inductor current port. Then, based on the frequency coefficient determination unit 20, the grid voltage VAC at the grid voltage port 11 and the DC voltage VO at the DC voltage port 12 are determined to generate a frequency coefficient and an average current, namely, the above coefficient k and the average current Iavg. Then, the mode frequency determination unit 30 determines the mode frequency corresponding to the grid voltage VAC at the grid voltage port 11, the DC voltage VO at the DC voltage port 12, and the average current, namely, the frequency of the PWM control at this time. Finally, the operating frequency of the switch tube can be controlled based on the mode frequency, so as to achieve discontinuous and critical mode control of the power factor correction circuit 10 at the operating frequency determined by the operating frequency determination unit 40. The operating frequency refers to the frequency of the PWM wave, namely, the duration of the high and low levels. Based on the duration of the high and low levels, the switch tube is finally switched on and off, so that the power factor correction circuit 10 operates in the discontinuous mode or the critical mode according to the actual situation, thereby avoiding the defect of always using the critical current mode, thereby reducing the loss of the switching device in the power factor correction circuit. It is worth noting that the above methods of determining the operating frequency based on the mode frequency and determining the mode frequency based on the frequency coefficient are both implemented with the following circuits, and can also be implemented in other ways, which are not limited here.

[0100] This embodiment provides a mode control circuit of a power factor correction circuit, wherein the mode control circuit of the power factor correction circuit includes a power factor correction circuit, wherein the power factor correction circuit includes a grid voltage port, a DC voltage port, and a waveform input port; a frequency coefficient determination unit, wherein the input end of the frequency coefficient determination unit is connected to the grid voltage port and the DC voltage port, and the frequency coefficient determination unit is used to generate a frequency coefficient and an average current based on the grid voltage of the grid voltage port and the DC voltage of the DC voltage port; a mode frequency determination unit, wherein the input end of the mode frequency determination unit is connected to the grid voltage port, the DC voltage port, and a first output end of the frequency coefficient determination unit, A mode frequency determination unit is configured to generate a mode frequency based on the grid voltage at the grid voltage port, the DC voltage at the DC voltage port, and the average current; an operating frequency determination unit is configured to have an input connected to the second output of the frequency coefficient determination unit and the output of the mode frequency determination unit, and to determine an operating frequency based on the frequency coefficient and the mode frequency; and a waveform output unit is configured to have an input connected to the output of the operating frequency determination unit and an output connected to the waveform input port, and to control the power factor correction circuit to operate in discontinuous and critical modes based on the operating frequency. The frequency coefficient determination unit generates a frequency coefficient and an average current based on the grid voltage collected at the grid voltage port and the DC voltage collected at the DC voltage port, and the mode frequency determination unit further generates a mode frequency based on the grid voltage collected at the grid voltage port, the DC voltage collected at the DC voltage port, and the average current. The mode frequency and frequency coefficient are ultimately input to the operating frequency determination unit, and the operating frequency determination unit determines a corresponding operating frequency, thereby controlling the power factor correction circuit to operate in discontinuous or critical mode based on the operating frequency. This avoids the phenomenon in the prior art that the PFC operating frequency is higher near the AC zero point due to continuous operation in the critical current mode, and operates at a higher operating frequency under light load conditions (when the inductor current is small). The grid voltage of the grid voltage port and the DC voltage of the DC voltage port are processed by the frequency coefficient determination unit, the frequency coefficient determination unit, and the mode frequency determination unit to obtain the operating frequency. Finally, intermittent (which can reduce the loss of the switching device) and critical mode control can be performed in the waveform output unit based on the operating frequency to avoid the defect of always using the critical current mode, thereby reducing the loss of the switching device in the power factor correction circuit.

[0101] Furthermore, in another embodiment of the mode control circuit of the power factor correction circuit of the present application, referring to Figure 6 , Figure 6This is a circuit connection diagram of the frequency coefficient processing circuit in the mode control circuit of the power factor correction circuit of the present application. The frequency coefficient determination unit 20 includes an average current output circuit 22, a frequency coefficient processing circuit 21, and a frequency coefficient output circuit 23. The frequency coefficient processing circuit 21 is connected to the DC voltage port 12, the average current output circuit 22, and the frequency coefficient output circuit 23. The average current output circuit 22 is connected to the grid voltage port 11, the frequency coefficient output circuit 23, the input end of the mode frequency determination unit 30, and the input end of the operating frequency determination unit 40. The frequency coefficient processing circuit 21 includes:

[0102] A zero-order holder Z, wherein an input end of the zero-order holder Z is connected to the DC voltage port 12;

[0103] a first sampling and processing chip E1, wherein a first input terminal of the first sampling and processing chip E1 is connected to the output terminal of the zero-order holder Z, and a second input terminal of the first sampling and processing chip E1 is connected to the voltage sampling port Y1;

[0104] A proportional-integral chip B, wherein the input end of the proportional-integral chip B is connected to the output end of the first sampling and processing chip E1, and the output end of the proportional-integral chip B is connected to the frequency coefficient output circuit 23;

[0105] A first multiplication device X1, wherein the first input end of the first multiplication device X1 is connected to the output end of the proportional-integral chip B, the first input end of the first multiplication device X1 is connected to the current sampling port Y2, and the output end of the first multiplication device X1 is connected to the average current output circuit 21.

[0106] In this embodiment, the frequency coefficient determination unit 20 includes an average current output circuit 22, a frequency coefficient processing circuit 21 and a frequency coefficient output circuit 23. The connection relationship between the frequency coefficient processing circuit 21 and each unit circuit is as follows: Figure 6 As shown, the frequency coefficient processing circuit 21 includes a zero-order holder Z, a first sampling processing chip E1, a proportional integral chip B and a first multiplication device X1. The zero-order holder Z is used to ensure that the input sampling points are interpolated and converted into continuous signals. The voltage sampling port Y1 is a port for collecting DC voltage. It can actually collect 400 DC voltages in a certain state and then calculate the average value. The current sampling port Y2 is used to collect average current. It can actually collect 8 average currents in a certain state and then calculate the average value. Finally, the product of the two is output to the average current output circuit 22, and the sampled DC current is output to the frequency coefficient output circuit 23.

[0107] Further, refer to Figure 7 , Figure 7FIG. 1 is a circuit connection diagram of an average current output circuit in a mode control circuit of a power factor correction circuit of the present application. The average current output circuit 22 includes:

[0108] a first amplifier F1, wherein an input end of the first amplifier F1 is connected to the grid voltage port 11;

[0109] a first absolute value device U1, wherein an input terminal of the first absolute value device U1 is connected to an output terminal of the first amplifier F1;

[0110] a second multiplication device X2, wherein a first input terminal of the second multiplication device X2 is connected to the output terminal of the first absolute value device U1, and a second input terminal of the second multiplication device X2 is connected to the output terminal of the first multiplication device X1;

[0111] a second amplifier F2, wherein an input terminal of the second amplifier F2 is connected to an output terminal of the second multiplication device X2;

[0112] A third multiplication device X3, a first input end of the third multiplication device X3 is connected to the output end of the second amplifier F2, a second input end of the third multiplication device X3 is connected to the frequency coefficient output circuit 23 and the input end of the operating frequency determination unit 40, and an output end of the third multiplication device X3 is connected to the input end of the mode frequency determination unit 30.

[0113] Specifically, refer to Figure 8 , Figure 8 This is a circuit connection diagram of a frequency coefficient output circuit in the mode control circuit of the power factor correction circuit of the present application. The frequency coefficient output circuit 23 includes:

[0114] a third amplifier F3, wherein the input end of the third amplifier F3 is connected to the output end of the proportional-integral chip B;

[0115] a second sampling processing chip E2, wherein a first input terminal of the second sampling processing chip E2 is connected to the output terminal of the third amplifier F3, and a second input terminal of the second sampling processing chip E2 is connected to the frequency sampling port Y3;

[0116] A first limiting device Z1, wherein the input end of the first limiting device Z1 is connected to the output end of the second sampling processing chip E2, and the output end of the first limiting device Z1 is connected to the input end of the operating frequency determination unit 40 and the third multiplication device X3 in the average current output circuit 22.

[0117] In this embodiment, the average current output circuit 22 includes a first amplifier F1, a first absolute value device U1, a second multiplication device X2, a second amplifier F2, and a third multiplication device X3. After being amplified by the first amplifier F1, the grid voltage VAC is de-absoluteized and output to the second multiplication device X2. The absolute value of the grid voltage VAC is multiplied by the product output by the frequency coefficient processing circuit 21 and then amplified. After being multiplied by the output of the frequency coefficient output circuit 23, the target average current to be used (i.e., the average current determined in the frequency coefficient determination unit 20 in the above embodiment) is obtained. In the frequency coefficient output circuit 23, the frequency coefficient output circuit 23 includes a third amplifier F3, a second sampling processing chip E2, and a first limiting device Z1. The DC current sampled by the frequency coefficient processing circuit 21 is amplified and sampled by the third amplifier F3. Finally, the output value is limited based on the first limiting device Z1, such as 0-1 limiting, to finally obtain the frequency coefficient determined by the frequency coefficient determination unit 20. The frequency sampling port Y3 sets the minimum operating frequency for light load operation. For reference, Figure 9 , Figure 9 This is a module schematic diagram of the frequency coefficient determination unit in the mode control circuit of the power factor correction circuit of this application. The entire frequency coefficient and average current can also be determined using other currents, and the circuit composition is not limited here.

[0118] Furthermore, in another embodiment of the mode control circuit of the power factor correction circuit of the present application, referring to Figure 10 , Figure 10 This is a circuit connection diagram of the second processing circuit in the mode control circuit of the power factor correction circuit of the present application. The mode frequency determination unit 30 includes a first processing circuit 31 and a second processing circuit 32. The second processing circuit 32 is connected to the first processing circuit 31, the first output end of the frequency coefficient determination unit 10, and the input end of the operating frequency determination unit 40. The first processing circuit 31 is connected to the grid voltage port 11 and the DC voltage port 12. The second processing circuit 32 includes:

[0119] a second limiting device Z2, wherein an input end of the second limiting device Z2 is connected to an output end of the third multiplication device X3 in the frequency coefficient determination unit 10;

[0120] a fourth multiplying device X4, wherein a first input terminal of the fourth multiplying device X4 is connected to the output terminal of the second limiting device Z2, and a second input terminal of the fourth multiplying device X4 is connected to the inductance input port Y4;

[0121] a first dividing device M1, wherein a first input terminal of the first dividing device M1 is connected to an output terminal of the fourth multiplying device X4, and a second input terminal of the first dividing device M3 is connected to the first processing circuit 31;

[0122] A third limiting device Z3 , wherein the input end of the third limiting device Z3 is connected to the output end of the first dividing device M1 , and the output end of the third limiting device Z3 is connected to the input end of the operating frequency determining unit 40 .

[0123] Exemplarily, the mode frequency determination unit 30 includes a first processing circuit 31 and a second processing circuit 32. The connection between the mode frequency determination unit 30 and other unit circuits is shown in FIG. Figure 10 The second processing circuit 32 includes a second limiting device Z2, a fourth multiplying device X4, a first dividing device M1, and a third limiting device Z3. The average current output by the third multiplying device X3 is limited by the second limiting device Z2, and the limited average current is multiplied by the inductance value in the inductance input port Y4. The inductance value in the inductance input port Y4 can be the inductance value in the power factor correction circuit 10 input by the user. The product of the multiplication of the two is divided by the output result of the first processing circuit 31, and the result is limited to obtain the mode frequency determined by the mode frequency determination unit 30 based on the average current, the grid voltage VAC of the grid voltage port 11, and the DC voltage VO of the DC voltage port 12, so as to facilitate subsequent processing by the operating frequency determination unit 40.

[0124] Further, refer to Figure 11 , Figure 11 This is a circuit connection diagram of a first processing circuit in a mode control circuit of a power factor correction circuit of the present application. The first processing circuit 31 includes:

[0125] a second absolute value device U2, wherein an input end of the second absolute value device U2 is connected to the grid voltage port 11;

[0126] a third sampling and processing chip E3, wherein a first input terminal of the third sampling and processing chip E3 is connected to the output terminal of the second absolute value device U2, and a second input terminal of the third sampling and processing chip E3 is connected to the DC voltage port 12;

[0127] a second dividing device M2, wherein a first input terminal of the second dividing device M2 is connected to the DC voltage port 12, and a second input terminal of the second dividing device M2 is connected to an output terminal of the third sampling and processing chip E3;

[0128] A fifth multiplication device X5, wherein a first input terminal of the fifth multiplication device X5 is connected to an output terminal of the second division device M2, a second input terminal of the fifth multiplication device X5 is connected to the grid voltage port 11, and an output terminal of the fifth multiplication device X5 is connected to a second input terminal of the first division device M1.

[0129] In this embodiment, the first processing circuit 31 includes a second absolute value device U2, a third sampling processing chip E3 (the sampling processing chip in this application is used to subtract inputs, such as the third sampling processing chip E3 subtracts the value of the first input port from the value of the second input port), a second dividing device M2, and a fifth multiplying device X5. The second absolute value device U2 performs absolute value processing on the grid voltage VAC, and samples the processed grid voltage VAC and the DC voltage VO to obtain a sampled voltage. The sampled voltage is first divided by the grid voltage VAC to obtain a division value, and then the division value is multiplied by the DC voltage VO to obtain a value to be input into the second processing circuit 32. For further information, please refer to Figure 12 , Figure 12 This is a module diagram of a mode frequency determination unit in the mode control circuit of the power factor correction circuit of the present application. The entire mode frequency can also be determined using other currents, and the circuit composition is not limited here.

[0130] In one embodiment, the entire control process is as follows: the inductor current enters the freewheeling discharge mode, and the inductor current decreases. At this point, the control algorithm performs real-time calculations based on the input grid voltage VAC, the output DC voltage VO, the peak current given by the current sampling port Y2, and the inductance given by the frequency sampling port Y3 to calculate the current CRM frequency. The operating frequency under the current operating conditions is then calculated based on the frequency coefficient k calculated based on the load level. The set operating frequency value is ultimately input into an integrator or digital counter within the operating frequency determination unit 40 for timing and control of the operating frequency. When the integrator output reaches the set cycle length, a set signal is sent to the main PWM trigger to initiate a new PWM cycle. The frequency coefficient output circuit 23 can utilize a PFC voltage regulator loop using a PI or other type of controller. The output of the outer voltage loop is calibrated to a range of 0-1.0, representing 100% output power. The output of the outer voltage loop is used for switching frequency foldback control. The output of the third amplifier F3's voltage loop is subtracted from the input value Max_k at the frequency sampling port Y3 to achieve operation near Max_k under light load conditions. Max_k sets the minimum operating frequency for light load operation. When the load increases to a heavier level, the k coefficient drops to near 1.0, achieving CRM operation under heavy loads. Furthermore, a lower limit is applied to the frequency variable k coefficient to prevent the loop from calculating a value less than 1.0, which would cause the system to enter DCM mode.

[0131] Furthermore, in another embodiment of the mode control circuit of the power factor correction circuit of the present application, referring to Figure 13 , Figure 13 FIG. 1 is a circuit connection diagram of an operating frequency determination unit in a mode control circuit of a power factor correction circuit of the present application. The operating frequency determination unit 40 includes:

[0132] a third dividing device M3, wherein a first input terminal of the third dividing device M3 is connected to an output terminal of the third limiting device Z3 in the pattern frequency determining unit 30, and a second input terminal of the third dividing device M3 is connected to a second input terminal of the third multiplying device X3 in the frequency coefficient determining unit 10;

[0133] A fourth limiting device Z4 , wherein the input end of the fourth limiting device Z4 is connected to the output end of the third dividing device M3 , and the output end of the fourth limiting device X4 is connected to the input end of the waveform output unit 50 .

[0134] In this embodiment, after the mode frequency is determined, the operating frequency will be obtained based on the operating frequency determination unit 40. The operating frequency determination unit 40 includes a third division device M3 and a fourth limiting device Z4. It mainly processes the numerical values ​​of the frequency coefficient determination unit 20 and the mode frequency determination unit 30 to obtain the final required operating frequency, that is, performs a division operation.

[0135] Furthermore, in another embodiment of the mode control circuit of the power factor correction circuit of the present application, referring to Figure 14 , Figure 14 FIG. 5 is a circuit connection diagram of a waveform output unit in a mode control circuit of a power factor correction circuit of the present application. The waveform output unit 50 includes:

[0136] an integrator J, wherein an input end of the integrator J is connected to an output end of the fourth limiting device Z4 in the operating frequency determination unit 40;

[0137] a first comparator A1, wherein an input terminal of the first comparator A1 is connected to an output terminal of the integrator J, and an output terminal of the first comparator A1 is connected to a reset terminal of the integrator J;

[0138] SR trigger S1 , the set end of the SR trigger S1 is connected to the output end of the first comparator A1 , and the output end of the SR trigger S1 is connected to the waveform input port 13 .

[0139] In this embodiment, after the operating frequency is obtained, PWM is driven based on the operating frequency. At the same time, comparison is performed based on the first comparator A1 to determine which mode the operation is in. Because the parameters for calculating k can be known by determining the driving PWM, the size of k can be determined to achieve discontinuous and critical mode control.

[0140] Furthermore, in another embodiment of the mode control circuit of the power factor correction circuit of the present application, referring to Figure 15 , Figure 15 This is a circuit connection diagram of a power factor correction circuit in a mode control circuit of the power factor correction circuit of the present application. The power factor correction circuit 10 is connected to the positive pole and the negative pole of the grid. A first voltage collector V1 is connected between the positive pole and the negative pole of the grid. The output end of the first voltage collector V1 serves as the grid voltage port 11. The power factor correction circuit 10 includes:

[0141] a first diode D1, wherein the anode of the first diode D1 is connected to the positive electrode of the power grid;

[0142] a second diode D2, wherein a cathode of the second diode D2 is connected to an anode of the first diode D1;

[0143] a third diode D3, wherein the anode of the third diode D3 is connected to the negative electrode of the grid, and the cathode of the third diode D3 is connected to the cathode of the first diode D1;

[0144] a fourth diode D4, wherein a cathode of the fourth diode D4 is connected to an anode of the third diode D3, and an anode of the fourth diode D4 is connected to an anode of the second diode D2;

[0145] a first resistor R1, wherein a first end of the first resistor R1 is connected to a cathode of the third diode D3;

[0146] a fifth diode D5, wherein an anode of the fifth diode D5 is connected to the second end of the first resistor R1;

[0147] an inductor L, wherein a first end of the inductor L is connected to a cathode of the third diode D3;

[0148] a second resistor R2, wherein a first end of the second resistor R2 is connected to a second end of the inductor L;

[0149] a switching tube Q1, wherein the drain of the switching tube Q1 is connected to the second end of the second resistor R2, the source of the switching tube Q1 is connected to the anode of the fourth diode D4, and the gate of the switching tube Q1 serves as the waveform input port 13. A current collector A is further connected between the anode of the second diode D1 and the source of the switching tube Q1, and the output end of the current collector A serves as the inductor current port;

[0150] a sixth diode D6, wherein an anode of the sixth diode D6 is connected to the second end of the second resistor R2, and a cathode of the sixth diode D6 is connected to the cathode of the fifth diode D5;

[0151] a capacitor C, wherein a second end of the capacitor C is connected to a cathode of the sixth diode D6;

[0152] A third resistor R3, wherein the second end of the third resistor R3 is connected to the first end of the capacitor C, and the first end of the third resistor R3 is connected to the source of the switch tube Q1, wherein a second voltage collector V2 is connected between the second end of the capacitor C and the first end of the third resistor R3, and the output end of the second voltage collector V2 serves as the DC voltage port 12.

[0153] In this embodiment, the power factor correction circuit 10 can be composed of the above circuits or other compositions, which are not limited here. That is, it is necessary to collect the grid voltage VAC, DC voltage VO and inductor current IAC in the power factor correction circuit 10, which can be set at other equivalent positions for collection, and the specific position is not limited here.

[0154] Furthermore, in another embodiment of the mode control circuit of the power factor correction circuit of the present application, referring to Figure 16 , Figure 16 This is a schematic diagram of an overall circuit connection of a mode control circuit of a power factor correction circuit of the present application. The power factor correction circuit 10 further includes an inductor current port. The mode control circuit of the power factor correction circuit further includes:

[0155] a second comparator A2, wherein a first input terminal of the second comparator A2 is connected to the inductor current port, and a second input terminal of the second comparator A2 is connected to an output terminal of the third multiplication device X3 in the frequency coefficient determination unit 10;

[0156] An upper edge trigger device N, wherein the input end of the upper edge trigger device N is connected to the output end of the second comparator A2 , and the output end of the upper edge trigger device N is connected to the reset end of the SR trigger S1 in the waveform output unit 50 .

[0157] In this embodiment, the mode control circuit of the power factor correction circuit further includes a second comparator A2 and an upper edge trigger device N, which are mainly used to control the PWMTON shutdown: when the output of the voltage outer loop is multiplied by the grid voltage sampling and used as the average value control quantity of the PFC inductor current, then the inductor peak current setting value iPK is calculated using the relationship derived above. The peak current setting is compared with the inductor current sampling value (inductor current IAC) in real time using an analog comparator (second comparator A2). When the inductor current IAC is greater than the peak current setting value IPK (which can also be the average current calculated by the frequency coefficient determination unit 20) during the PWMON stage, a reset signal is sent to the SR trigger to shut down the PWM, thereby realizing the shutdown control of the switch tube. For further details, please refer to Figure 17 , Figure 17 This is a waveform diagram of the first embodiment of the mode control circuit of the power factor correction circuit of the present application. By gradually increasing the load current to full load, it can be observed that the operation of the entire system is controlled by changing the frequency coefficient k. It can be seen that PFC control can be achieved under all load conditions. Among them, the six areas from top to bottom are: grid voltage (large amplitude waveform) and AC input current, peak current (given large amplitude waveform) and inductor current instantaneous value sampling, PWM output, frequency control coefficient k, load current, and PWM period calculation value; refer to Figure 18 , Figure 18 This is a waveform diagram of the second embodiment of the mode control circuit of the power factor correction circuit of the present application. When the power factor correction circuit operates in the critical mode, the three regions from top to bottom are: grid voltage (upper straight line portion) and AC input current, peak current setting (upper straight line portion) and inductor current instantaneous value sampling, and PWM output; please refer to Figure 19 , Figure 19 This is a waveform diagram of the third embodiment of the mode control circuit for the power factor correction circuit of the present application. When the power factor correction circuit operates in critical mode, the grid voltage (the upper straight line portion) and AC input current, the peak current setting (the upper straight line portion), and the instantaneous value of the inductor current are sampled and PWM output. As can be seen from the above waveforms, the entire control process achieves DCM / CRMPFC control in a simple and reliable manner, with low input current distortion and high PF across the entire operating range. The implementation is simple, the principle is simple, and the implementation effect is good, while also reducing the losses of the switching devices in the power factor correction circuit.

[0158] The above description is only a preferred embodiment of the present application and does not limit the patent scope of the present application. All equivalent structural transformations made based on the contents of the present application specification and drawings, or direct / indirect application in other related technical fields, are included in the patent protection scope of the present application.

Claims

1. A mode control circuit for a power factor correction circuit, characterized in that: The mode control circuit of the power factor correction circuit includes: A power factor correction circuit, the power factor correction circuit comprising a grid voltage port, a DC voltage port and a waveform input port; a frequency coefficient determination unit, wherein an input end of the frequency coefficient determination unit is connected to the grid voltage port and the DC voltage port, and the frequency coefficient determination unit is configured to generate a frequency coefficient and an average current based on the grid voltage of the grid voltage port and the DC voltage of the DC voltage port; a mode frequency determination unit, wherein an input end of the mode frequency determination unit is connected to the grid voltage port, the DC voltage port, and the first output end of the frequency coefficient determination unit, and the mode frequency determination unit is configured to generate a mode frequency based on the grid voltage of the grid voltage port, the DC voltage of the DC voltage port, and the average current; an operating frequency determining unit, wherein an input terminal of the operating frequency determining unit is connected to the second output terminal of the frequency coefficient determining unit and the output terminal of the mode frequency determining unit, and the operating frequency determining unit is configured to determine an operating frequency based on the frequency coefficient and the mode frequency; A waveform output unit, wherein the input end of the waveform output unit is connected to the output end of the operating frequency determination unit, the output end of the waveform output unit is connected to the waveform input port, and the waveform output unit is used to perform intermittent and critical mode control on the power factor correction circuit based on the operating frequency.

2. The mode control circuit of the power factor correction circuit according to claim 1, wherein: The frequency coefficient determination unit includes an average current output circuit, a frequency coefficient processing circuit, and a frequency coefficient output circuit. The frequency coefficient processing circuit is connected to the DC voltage port, the average current output circuit, and the frequency coefficient output circuit. The average current output circuit is connected to the grid voltage port, the frequency coefficient output circuit, the input end of the mode frequency determination unit, and the input end of the operating frequency determination unit. The frequency coefficient processing circuit includes: A zero-order keeper, wherein an input end of the zero-order keeper is connected to the DC voltage port; a first sampling processing chip, wherein a first input terminal of the first sampling processing chip is connected to the output terminal of the zero-order holder, and a second input terminal of the first sampling processing chip is connected to the voltage sampling port; a proportional-integral chip, wherein an input end of the proportional-integral chip is connected to an output end of the first sampling and processing chip, and an output end of the proportional-integral chip is connected to the frequency coefficient output circuit; A first multiplication device, wherein the first input end of the first multiplication device is connected to the output end of the proportional-integral chip, the first input end of the first multiplication device is connected to the current sampling port, and the output end of the first multiplication device is connected to the average current output circuit.

3. The mode control circuit of the power factor correction circuit according to claim 2, wherein: The average current output circuit includes: a first amplifier, wherein an input terminal of the first amplifier is connected to the grid voltage port; a first absolute value device, wherein an input terminal of the first absolute value device is connected to an output terminal of the first amplifier; a second multiplying device, wherein a first input terminal of the second multiplying device is connected to an output terminal of the first absolute value device, and a second input terminal of the second multiplying device is connected to an output terminal of the first multiplying device; a second amplifier, wherein an input terminal of the second amplifier is connected to an output terminal of the second multiplication device; a third multiplication device, wherein a first input terminal of the third multiplication device is connected to the output terminal of the second amplifier, a second input terminal of the third multiplication device is connected to the input terminals of the frequency coefficient output circuit and the operating frequency determination unit, and an output terminal of the third multiplication device is connected to the input terminal of the mode frequency determination unit.

4. The mode control circuit of the power factor correction circuit according to claim 2, wherein: The frequency coefficient output circuit includes: a third amplifier, wherein an input end of the third amplifier is connected to an output end of the proportional-integral chip; a second sampling processing chip, wherein a first input terminal of the second sampling processing chip is connected to the output terminal of the third amplifier, and a second input terminal of the second sampling processing chip is connected to the frequency sampling port; A first limiting device, wherein the input end of the first limiting device is connected to the output end of the second sampling processing chip, and the output end of the first limiting device is connected to the input end of the operating frequency determination unit and the third multiplication device in the average current output circuit.

5. The mode control circuit of the power factor correction circuit according to claim 1, wherein: The mode frequency determination unit includes a first processing circuit and a second processing circuit, the second processing circuit being connected to the first processing circuit, the first output terminal of the frequency coefficient determination unit, and the input terminal of the operating frequency determination unit, the first processing circuit being connected to the grid voltage port and the DC voltage port, and the second processing circuit including: a second limiting device, wherein an input terminal of the second limiting device is connected to an output terminal of the third multiplication device in the frequency coefficient determination unit; a fourth multiplying device, wherein a first input terminal of the fourth multiplying device is connected to the output terminal of the second limiting device, and a second input terminal of the fourth multiplying device is connected to the inductance input port; a first dividing device, wherein a first input terminal of the first dividing device is connected to an output terminal of the fourth multiplying device, and a second input terminal of the first dividing device is connected to the first processing circuit; A third limiting device, wherein the input end of the third limiting device is connected to the output end of the first dividing device, and the output end of the third limiting device is connected to the input end of the operating frequency determining unit.

6. The mode control circuit of the power factor correction circuit according to claim 5, wherein: The first processing circuit includes: a second absolute value device, wherein an input terminal of the second absolute value device is connected to the grid voltage port; a third sampling and processing chip, wherein a first input terminal of the third sampling and processing chip is connected to the output terminal of the second absolute value device, and a second input terminal of the third sampling and processing chip is connected to the DC voltage port; a second dividing device, wherein a first input terminal of the second dividing device is connected to the DC voltage port, and a second input terminal of the second dividing device is connected to an output terminal of the third sampling and processing chip; A fifth multiplication device, wherein a first input terminal of the fifth multiplication device is connected to the output terminal of the second division device, a second input terminal of the fifth multiplication device is connected to the grid voltage port, and an output terminal of the fifth multiplication device is connected to the second input terminal of the first division device.

7. The mode control circuit of the power factor correction circuit according to claim 1, wherein: The operating frequency determining unit includes: a third dividing device, wherein a first input terminal of the third dividing device is connected to an output terminal of the third limiting device in the pattern frequency determining unit, and a second input terminal of the third dividing device is connected to a second input terminal of the third multiplying device in the frequency coefficient determining unit; A fourth limiting device, wherein the input end of the fourth limiting device is connected to the output end of the third dividing device, and the output end of the fourth limiting device is connected to the input end of the waveform output unit.

8. The mode control circuit of the power factor correction circuit according to claim 1, wherein: The waveform output unit includes: an integrator, wherein an input end of the integrator is connected to an output end of a fourth limiting device in the operating frequency determining unit; a first comparator, wherein an input terminal of the first comparator is connected to an output terminal of the integrator, and an output terminal of the first comparator is connected to a reset terminal of the integrator; An SR trigger, wherein the set end of the SR trigger is connected to the output end of the first comparator, and the output end of the SR trigger is connected to the waveform input port.

9. The mode control circuit of the power factor correction circuit according to any one of claims 1 to 8, wherein: The power factor correction circuit is connected to the positive pole and the negative pole of the grid, a first voltage collector is connected between the positive pole and the negative pole of the grid, and an output end of the first voltage collector serves as the grid voltage port. The power factor correction circuit includes: a first diode, wherein the anode of the first diode is connected to the positive electrode of the power grid; a second diode, wherein a cathode of the second diode is connected to an anode of the first diode; a third diode, wherein the anode of the third diode is connected to the negative electrode of the power grid, and the cathode of the third diode is connected to the cathode of the first diode; a fourth diode, wherein a cathode of the fourth diode is connected to an anode of the third diode, and an anode of the fourth diode is connected to an anode of the second diode; a first resistor, wherein a first end of the first resistor is connected to a cathode of the third diode; a fifth diode, wherein an anode of the fifth diode is connected to the second end of the first resistor; an inductor, a first end of the inductor being connected to the cathode of the third diode; a second resistor, a first end of the second resistor being connected to the second end of the inductor; a switching tube, wherein the drain of the switching tube is connected to the second end of the second resistor, the source of the switching tube is connected to the anode of the fourth diode, and the gate of the switching tube serves as the waveform input port, wherein a current collector is further connected between the anode of the second diode and the source of the switching tube, and the output end of the current collector serves as the inductor current port; a sixth diode, wherein an anode of the sixth diode is connected to the second end of the second resistor, and a cathode of the sixth diode is connected to the cathode of the fifth diode; a capacitor, wherein a second end of the capacitor is connected to a cathode of the sixth diode; a third resistor, wherein the second end of the third resistor is connected to the first end of the capacitor, and the first end of the third resistor is connected to the source of the switching tube, wherein a second voltage collector is connected between the second end of the capacitor and the first end of the third resistor, and the output end of the second voltage collector serves as the DC voltage port.

10. The mode control circuit of the power factor correction circuit according to any one of claims 1 to 8, characterized in that: The power factor correction circuit further includes an inductor current port, and the mode control circuit of the power factor correction circuit further includes: a second comparator, wherein a first input terminal of the second comparator is connected to the inductor current port, and a second input terminal of the second comparator is connected to an output terminal of a third multiplication device in the frequency coefficient determination unit; An upper edge trigger device, wherein the input end of the upper edge trigger device is connected to the output end of the second comparator, and the output end of the upper edge trigger device is connected to the reset end of the SR trigger in the waveform output unit.

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