Charge pump ripple regulation circuit and method for charge pump ripple regulation

Abstract

The invention relates to the technical field of memories, and discloses a charge pump ripple adjusting circuit, which comprises a charge pump unit comprising N charge pumps connected in parallel, the control signal of each charge pump corresponds to a sub-clock signal; the comparator is connected with the output end of the charge pump unit and used for comparing the reference voltage with the output voltage of the charge pump unit; the delay unit is connected with the output end of the charge pump unit, the output end of the comparator and a clock signal; the control unit is used for detecting the change rate of the output voltage of the charge pump unit and generating a plurality of sub-clock signals which are sequentially delayed for a preset duration by using a clock signal so as to control the number of the charge pumps in a working state; wherein the preset duration depends on the change rate of the output voltage of the charge pump unit, and the output signal of the comparator is used for controlling the on-off state of the charge pump. The circuit dynamically adjusts the driving capability of the charge pump unit based on the load condition, reduces ripples and ensures the working efficiency. The invention also discloses a method for charge pump ripple regulation.

Description

Technical Field

[0001] The present application relates to the field of memory technology, for example, to a charge pump ripple regulation circuit and a method for charge pump ripple regulation. Background Art

[0002] The requirements for ripple when reading, writing and erasing the memory are getting higher and higher. It is very challenging to design the charge pump loop control structure to achieve controllable ripple under light and heavy loads and to keep the ripple small under light loads.

[0003] A charge pump circuit is disclosed in the related technology, and the charge pump circuit includes: a charge pump array, including N sub-charge pumps, the sub-output ends of the N sub-charge pumps are connected to form the output end of the charge pump circuit to output voltage, wherein N is greater than 1; a clock circuit, used to provide a clock for each sub-charge pump, and the clock provided to two adjacent sub-charge pumps has a delay.

[0004] In the process of implementing the embodiments of the present disclosure, it is found that there are at least the following problems in the related art:

[0005] The related technology achieves the purpose of lower ripple by turning on the charge pumps in sequence. The clock signal of each charge pump is delayed before being passed to the charge pump. The delay is a fixed delay size determined by the CMOS process. Different PVT (Process-Voltage-Voltage) results in different delay times, and the changes are random. Since the delay time is fixed, the dynamic adjustment capability is weak. For example: under relatively stable conditions, when light load switches to heavy load, the target voltage cannot rise to the specified potential immediately due to the fixed delay time, which ultimately leads to a low output voltage mean. Summary of the invention

[0006] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical components or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0007] The embodiments of the present disclosure provide a charge pump ripple regulation circuit and a charge pump ripple regulation method, so as to ensure the working efficiency of the charge pump while regulating the output ripple.

[0008] In some embodiments, the charge pump ripple regulation circuit includes:

[0009] A charge pump unit includes N parallel charge pumps for outputting voltage; the control signal of each charge pump is a corresponding sub-clock signal; a comparator is connected to the output end of the charge pump unit and is used to compare a reference voltage and the output voltage of the charge pump unit; a delay unit is connected to the output end of the charge pump unit, the output end of the comparator, and the clock signal; it is used to detect the rate of change of the output voltage of the charge pump unit, and use the clock signal to generate multiple sub-clock signals that are delayed in sequence by preset time lengths to control the number of charge pumps in working state; wherein the preset time length depends on the rate of change of the output voltage of the charge pump unit, and the output signal of the comparator is used to control the switching state of the charge pump.

[0010] In some embodiments, the method for charge pump ripple regulation includes: sampling the output voltage of the charge pump unit; when the output voltage is less than the target voltage, adjusting the preset duration of the delay unit according to the rate of change of the output voltage to adjust the number of charge pumps in the working state in the charge pump unit.

[0011] The charge pump ripple regulation circuit and the charge pump ripple regulation method provided by the embodiments of the present disclosure can achieve the following technical effects:

[0012] The delay module generates a control signal of the charge pump unit, i.e., a sub-clock signal, based on the comparison result of the clock signal and the comparator. At the same time, the delay duration, i.e., the preset duration, between each sub-clock signal is determined according to the change rate of the output voltage of the charge pump unit. Among them, the change rate of the output voltage can reflect the load condition. In this way, the delay duration is determined based on the load condition, the driving capacity of the charge pump unit is dynamically adjusted, the ripple is reduced, and the working efficiency is guaranteed. And the circuit structure is simple.

[0013] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:

[0015] Figure 1 is a structural schematic diagram of a charge pump ripple regulation circuit provided by an embodiment of the present disclosure;

[0016] Figure 2 is a schematic diagram of the structure of a delay unit in a circuit provided by an embodiment of the present disclosure;

[0017] Figure 3 is a structural schematic diagram of another charge pump ripple regulation circuit provided by an embodiment of the present disclosure;

[0018] Figure 4 is a structural schematic diagram of another charge pump ripple regulation circuit provided by an embodiment of the present disclosure;

[0019] Figure 5 is a schematic diagram of the output voltage and sub-clock signal under heavy load and light load provided by the embodiment of the present disclosure;

[0020] Figure 6 It is a schematic diagram of a method for charge pump ripple regulation provided by an embodiment of the present disclosure.

[0021] Reference numerals:

[0022] 201: charge pump unit; 202: comparator; 203: delay unit; 204: voltage divider unit; 231: detection module; 232: delay module. DETAILED DESCRIPTION

[0023] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0024] The terms "first", "second", etc. in the specification and claims of the embodiments of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so that the embodiments of the embodiments of the present disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0025] In the embodiments of the present disclosure, the terms "upper", "lower", "inside", "middle", "outside", "front", "back" and the like indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings. These terms are mainly intended to better describe the embodiments of the present disclosure and their embodiments, and are not intended to limit the indicated devices, elements or components to have a specific direction, or to be constructed and operated in a specific direction. Moreover, in addition to being used to indicate directions or positional relationships, some of the above terms may also be used to indicate other meanings. For example, the term "upper" may also be used to indicate a certain dependency or connection relationship in certain circumstances. For those of ordinary skill in the art, the specific meanings of these terms in the embodiments of the present disclosure can be understood according to specific circumstances.

[0026] In addition, the terms "disposed", "connected", and "fixed" should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be an internal connection between two devices, elements, or components. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present disclosure can be understood according to specific circumstances.

[0027] Unless otherwise stated, the term "plurality" means two or more.

[0028] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B indicates: A or B.

[0029] The term "and / or" is a description of the association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B.

[0030] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other.

[0031] Combination Figure 1 As shown, an embodiment of the present disclosure provides a charge pump ripple regulation circuit, comprising a charge pump unit 201, a comparator 202 and a delay unit 203 connected in sequence.

[0032] The charge pump unit 201 includes N parallel charge pumps for outputting voltage; the control signal of each charge pump is a corresponding sub-clock signal. The comparator 202 is connected to the output end of the charge pump unit 201 and is used to compare the reference voltage and the output voltage of the charge pump unit. The delay unit 203 is connected to the output end of the charge pump unit 201, the output end of the comparator 202 and the clock signal CLK. The delay unit 203 is used to detect the rate of change of the output voltage of the charge pump unit 201, and use the clock signal CLK to generate multiple sub-clock signals that are sequentially delayed by a preset time length to control the number of charge pumps in the working state. Among them, the preset time length depends on the rate of change of the output voltage of the charge pump unit 201, and the output signal of the comparator 202 is used to control the switching state of the charge pump.

[0033] Here, the charge pump unit includes a plurality of charge pumps connected in parallel to generate the required high voltage. The driving capability of each charge pump is the same, and each charge pump is controlled by a corresponding sub-clock signal, where N is greater than 1. As an example, the charge pump unit includes four charge pumps, namely charge pump A, charge pump B, charge pump C, and charge pump D, and the corresponding sub-clock signals are CLK_A, CLK_B, CLK_C, and CLK_D.

[0034] The comparator compares the reference voltage and the output voltage of the charge pump unit to determine whether the output voltage of the charge pump unit reaches the target voltage based on the comparison result. Wherein, when the comparator is directly connected to the output voltage of the charge pump unit, the reference voltage is the target voltage. When sampling the output voltage of the charge pump unit, the comparator compares the sampled voltage and the reference voltage. At this time, the magnitude of the reference voltage is determined based on the ratio of the sampled voltage to the output voltage. In addition, the connection of the two input signals of the comparator can select an adaptive connection method based on demand. As an example, the non-inverting input terminal of the comparator is connected to the output voltage of the charge pump unit, the inverting input terminal is connected to the reference voltage, and the output signal OPO at the output terminal is the comparison result. In this way, when the output voltage of the charge pump unit does not reach the target voltage, the output signal OPO is 0; the charge pump unit works under the control of the sub-clock signal. When the output voltage of the charge pump unit reaches the target voltage, the output signal OPO is 1. At this time, the sub-clock signal is pulled low, so that the charge pump unit is turned off.

[0035] The input signal of the delay unit includes the output voltage of the charge pump unit, the clock signal and the comparison result of the comparator. Among them, the comparison result and the clock signal are used to generate sequentially delayed sub-clock signals. The output voltage of the charge pump unit is used to obtain the rate of change of the output voltage, and the delay unit controls the delay time between each sub-clock signal, that is, the length of the preset time, based on the rate of change of the output voltage. It can be understood that the rate of change of the output voltage is different when the charge pump unit works under heavy load and light load. When the load is heavy, the voltage change rate is relatively fast. At this time, in order to make the output voltage of the charge pump unit rise to the target voltage quickly, the preset time is shortened, that is, the delay time between each sub-clock signal is shortened to ensure work efficiency. When the load is light, the voltage change rate is relatively slow. In this case, in order to avoid excessive ripple output by the charge pump unit, extending the preset time reduces the number of charge pumps in the working state. In this way, the ripple of the charge pump output voltage can be reduced and the stability of the charge pump output voltage can be improved. In this way, the delay time, that is, the preset time, is defined based on the voltage change rate. Compared with the prior art, the delay duration of the embodiment of the present disclosure can be dynamically adjusted based on the load conditions, thereby achieving dynamic adjustment of the driving capability of the charge pump unit, reducing ripple and ensuring working efficiency.

[0036] In addition, taking the above four parallel charge pumps as an example, a plurality of sub-clock signals delayed sequentially by a preset time length are described. Wherein, the preset time length is Ts, and after the first sub-clock signal CLK_A works at time T0, the second sub-clock signal CLK_B works at time T0+Ts, and the third sub-clock signal CLK_C works at time T0+2×Ts, and so on.

[0037] The charge pump ripple regulation circuit provided by the embodiment of the present disclosure generates a control signal, i.e., a sub-clock signal, of the charge pump unit based on the comparison result of the clock signal and the comparator. At the same time, the delay duration, i.e., the preset duration, between each sub-clock signal is determined according to the rate of change of the output voltage of the charge pump unit. The rate of change of the output voltage can reflect the load condition. In this way, the delay duration is determined based on the load condition, the driving capability of the charge pump unit is dynamically adjusted, the ripple is reduced, and the working efficiency is ensured. The circuit structure is simple.

[0038] Combination Figure 2 As shown, optionally, the delay unit 203 includes a detection module 231 and a delay module 232. The detection module 231 includes a detection capacitor Cc and a pull-down current mirror; one end of the detection capacitor Cc is connected to the output voltage of the charge pump unit, the other end is connected to the pull-down current mirror, and the other end outputs a coupling voltage. The delay module 232, the input end of which is connected to the clock signal CLK and the output signal OPO of the comparator 202, is controlled by the coupling voltage to adjust the preset time length between the output sub-clock signals; the output signal of the comparator 202 controls the output state of the sub-clock signal.

[0039] Here, the delay unit includes two parts, one of which is a detection module for the output voltage of the charge pump unit. The other part is a delay module, which sequentially outputs sub-clock signals with the same delay time (i.e., preset time); and the adjustment of the preset time between each sub-clock signal is controlled by the detection result of the detection module. Among them, the detection module includes a detection capacitor and a pull-down current mirror. One end of the detection capacitor is connected to the output voltage of the charge pump unit (i.e., connected to the voltage signal to be detected), and the other end is connected to the pull-down current mirror. The pull-down current mirror provides a relatively stable pull-down current to pull down the node voltage at the other end of the detection capacitor (i.e., the voltage at point X in the figure). In detail, when the charge pump unit works in heavy load mode, the output voltage changes quickly, and the coupling voltage of the detection capacitor at point X is large. Therefore, the pull-down current provided by the pull-down current mirror is not enough to pull down point X, and the coupling voltage is high. When the charge pump unit works in light load mode, the output voltage changes slowly, and the coupling voltage of the detection capacitor at point X is small. Therefore, the voltage at point X is pulled to a low level by the pull-down current.

[0040] The high and low coupling voltages at point X make the preset durations different. Specifically, when the coupling voltage at point X is at a high level, the delay module is adjusted to shorten the preset duration. When the coupling voltage at point X is at a low level, the delay module is adjusted to extend the preset duration. More specifically, the delay module includes a plurality of inverters connected in series, and some inverters (the inverters have a delay function) are controlled by switches, and the switches are controlled to connect the inverters to the circuit or short-circuit the inverters. After these inverters are connected to the circuit, the preset duration is extended. After these inverters are short-circuited, the preset duration is shortened. In this way, the delay unit dynamically adjusts the preset duration according to the rate of change of the output voltage to reduce the output ripple in the light load mode.

[0041] In addition, in some embodiments, the detection module 231 further includes a NOT gate, which is used to flip the coupling voltage at point X to obtain a control voltage Vcontrol. When the coupling voltage at point X is large, the control voltage Vcontrol controls the switch to be disconnected. When the coupling voltage at point X is small, the control voltage Vcontrol controls the switch to be closed.

[0042] Optionally, the delay module 232 includes an inverter string, a control switch, and a logic gate. The inverter string includes M groups, and the control switch and the logic gate each include M pieces.

[0043] M groups of inverter strings, including multiple inverters connected in series, are used to delay the clock signal; the delayed clock signal output by the i-th group of inverter strings is used as the input signal of the i+1-th group of inverters to generate the i+1-th sub-clock signal; the input signal of the 1st group of inverter strings is the first sub-clock signal after the output signal of the comparator and the clock signal are logically operated. M control switches are set in each group of inverter strings, and the signals controlled by the coupling voltage short-circuit some inverters in each group of inverter strings. M logic gates, one input end is connected to the delayed clock signal of the corresponding inverter string, the other input end is connected to the output signal of the comparator, and the output end outputs the corresponding sub-clock signal.

[0044] Here, the structure of the delay module is described in detail. The delay module includes M groups of identical structures, each of which includes an inverter string, a control switch, and a logic gate. Each structure outputs a sub-clock signal and delays the sub-clock signal to make it later than the sub-clock signal corresponding to the input delayed clock signal. Figure 2, the structure of the delay module is described in detail. The input signal of the first group of inverter strings is the first sub-clock signal CLK_A, which is delayed by the inverter string and outputs the first delayed clock signal CLK_AB. The first delayed clock signal CLK_AB and the output signal OPO of the comparator are logically operated by the logic gate to output a signal, and the output signal is the second sub-clock signal CLK_B. At the same time, the first delayed clock signal CLK_AB is used as the input signal of the second group of inverter strings to delay the first delayed clock signal CLK_AB. By analogy, a plurality of sequentially delayed sub-clock signals are obtained. In this way, each sub-clock signal is sequentially delayed by a preset time length. In addition, the first sub-clock signal CLK_A is obtained by logical operation of the output signal OPO of the comparator and the clock signal CLK. In order to enable the output signal OPO of the comparator to control the state of the charge pump, the output signal OPO of the comparator and the clock signal CLK are operated by the NOR gate to obtain the first sub-clock signal. Thus, when the output signal OPO is at a high level, the first sub-clock signal is pulled down.

[0045] Still taking the first group of inverter strings as an example, the preset duration control is explained. The first group of inverter strings includes L inverters connected in series, and Q (Q < L) of the inverters connected in series are connected in parallel with the control switch. When the control switch is disconnected, the Q inverters connected in series are connected to the inverter string. In this way, the number of effective inverters in the inverter string is all inverters, so that the delay duration of the input sub-clock signal is increased. When the control switch is turned on, the Q inverters connected in series are short-circuited. In this way, the number of effective inverters in the inverter string is reduced, so that the delay duration of the input sub-clock signal is shortened.

[0046] In addition, the signal output by the inverter string is logically operated with the output signal of the comparator in order to realize the control of the state of the charge pump unit by the output signal of the comparator. That is, the output signal of the comparator is used to lock or release the signal at the output end of the delay unit. When the output signal of the comparator locks a certain output of the delay module, the corresponding sub-clock signal and the subsequent sub-clock signal are set to a low level, and the corresponding charge pump does not work. When the output signal of the comparator releases the output of the delay module, the corresponding sub-clock signal is a normal pulse signal to control the operation of the corresponding charge pump.

[0047] In addition, it should be noted that since the delay time between adjacent sub-clock signals is the same, the structures of the delay modules are exactly the same (ie, the number of inverter strings, the number of inverters controlled by the control switches, etc. are the same), thereby ensuring that the preset time length is the same.

[0048] Optionally, the number of inverters in each inverter string is L=2n. Here, the number of inverter strings is an even number, so that the delayed clock signal output by the inverter string is consistent with the corresponding input clock signal waveform. In this way, multiple sub-clock signals are the same, and the only difference is that there is a preset delay between adjacent sub-clock signals.

[0049] Optionally, M is less than N. That is, the number of inverter strings is less than the number of charge pumps, and NM=1. This is because the first sub-clock signal is only controlled by the output signal of the comparator without delay control. Subsequent sub-clock signals are controlled by the output signal of the comparator and the delay time length control, so the delay module includes M groups of structures.

[0050] Optionally, the control switch comprises a MOS tube, the gate of the MOS tube is connected to the coupling voltage of the detection module, the drain and the source are connected to the inverter string, and part of the inverters connected between the drain and the source are short-circuited by the controlled coupling voltage.

[0051] Here, the control switch is a MOS tube, the gate of the MOS tube is connected to the coupling voltage of the detection module, and the drain and source are connected to the inverter string. When the MOS tube is turned on, the multiple inverters connected in series between the drain and source of the MOS tube are short-circuited. When the MOS tube is turned off, the multiple inverters connected in series between the drain and source of the MOS tube are connected to the circuit. In this way, the effectiveness of some inverters is controlled by the switch state of the MOS tube.

[0052] Optionally, the MOS tube is a PMOS tube, and a NOT gate is provided at the output end of the MOS tube and the detection module. When the MOS tube is a PMOS tube, the source of the PMOS is connected to one end of the front inverter in the inverter string, and the drain is connected to one end of the back inverter in the inverter string. Among them, the front or back inverter is based on the signal input end of the inverter string, that is, the inverter close to the signal input end is the front. When the X-point coupling voltage of the detection module is high, after the NOT gate logic operation, the gate voltage Vcontrol of the PMOS tube is low. The absolute value of the gate-source voltage difference is greater than the absolute value of the threshold voltage, and the PMOS tube is turned on, so that the inverter connected in series between the source and drain is short-circuited. In this way, when the gate voltage Vcontrol of the PMOS tube is low, some inverters in the inverter string are short-circuited, thereby shortening the preset time. When the X-point coupling voltage of the detection module is low, after the NOT gate logic operation, the gate voltage Vcontrol of the PMOS tube is high. The absolute value of the gate-source voltage difference is smaller than the absolute value of the threshold voltage, so the PMOS tube is turned off, so that the inverter connected in series between the source and drain is connected in series to the inverter string, thereby extending the preset time.

[0053] Optionally, the logic gate comprises a NOR gate, one input end of the NOR gate is connected to the delayed clock signal output by the inverter string, the other output end is connected to the output signal of the comparator, and the output end outputs the sub-clock signal.

[0054] Here, the logic gate is a NOR gate. When the output signal of the comparator is high, the NOR gate outputs a low level (at this time, the delayed clock signal does not affect the output result). In this way, the sub-clock signal output from the output end of the delay module is always low, and the delay time is long. When the load is light, the output signal of the comparator is high for a long time, so when the load is light, the number of charge pumps in the working state in the charge pump unit is adjusted. When the load is heavy, the output signal of the comparator is low for a long time, the delay time is short, and the charge pump unit has more charge pumps in the working state. The output voltage of the charge pump unit quickly reaches the target voltage to ensure work efficiency.

[0055] Combination Figure 2 Optionally, the pull-down current mirror includes a pull-down current source and a pair of MOS tubes. The pull-down current source is used to provide a bias current. The pair of MOS tubes, the drain and gate of the first MOS tube are connected to the pull-down current source, and the source is grounded; the drain of the second MOS tube is connected to the other end of the detection capacitor Cc, the gate is connected to the gate of the first MOS tube, and the source is grounded.

[0056] Here, a pair of MOS tubes constitute a current mirror, which is used to copy the current of the branch where the pull-down current source is located to the branch where the detection capacitor is located. In this way, one end of the detection capacitor is the output voltage of the charge pump unit, and the other end is the current of the pull-down current source. Since the output voltage of the charge pump unit has different slopes when working under heavy load and light load, under the action of the output voltage and the pull-down current source, there is a difference in the voltage coupled at point X through the detection capacitor. In light load mode, the coupling voltage at point X is small, and the voltage at point X is quickly pulled to 0 by the pull-down current. In heavy load mode, the voltage changes quickly, then the coupling voltage at point X is large, the pull-down current is not enough to pull down the voltage at point X, and the voltage at point X is high. In this way, the adjustment of the preset duration control signal of the delay module is realized. In addition, in the embodiment of the present disclosure, a pair of MOS tubes are NMOS tubes.

[0057] Combination Figure 4 Optionally, the circuit further includes a voltage divider unit 204. The input end of the voltage divider unit 204 is connected to the output end of the charge pump unit 201 for sampling the output voltage of the charge pump unit 201; the output end is connected to an input end of the comparator 202 for the comparator 101 to compare the sampled voltage with the reference voltage.

[0058] Here, when judging whether the output voltage of the charge pump unit reaches the target voltage, the output voltage of the charge pump unit is sampled by the voltage divider unit. The sampled voltage VDET is compared with the corresponding reference voltage VREF to judge whether the sampled voltage reaches the reference voltage. The voltage is sampled by the voltage divider unit, so that the obtained sampled voltage has high accuracy and strong anti-interference ability, which helps to improve the accuracy of the judgment. In addition, in the embodiment of the present disclosure, the voltage divider unit includes a voltage divider resistor, etc., but the structure of the voltage divider unit is not limited to a resistor.

[0059] Based on the above charge pump ripple regulation circuit, combined with Figure 6 , the present disclosure provides a method for charge pump ripple regulation, comprising:

[0060] S101, the regulating circuit samples the output voltage of the charge pump unit.

[0061] S102, when the output voltage is less than the target voltage, the regulating circuit adjusts the preset duration of the delay unit according to the rate of change of the output voltage to adjust the number of charge pumps in the working state in the charge pump unit.

[0062] Here, in the process of using the charge pump unit to generate the required high voltage, the output voltage of the charge pump unit is sampled, and it is determined whether the output voltage reaches the target voltage. When the output voltage is less than the target voltage, the charge pump unit is in a working state. Therefore, based on the change rate of the sampled output voltage, the delay time between each sub-clock signal in the charge pump unit is adjusted, that is, the preset time is adjusted. Figure 5 It can be seen that the output voltage of the charge pump unit changes differently when it is lightly loaded and heavily loaded. Therefore, based on the rate of change of the output voltage, the load condition of the charge pump unit can be determined. Then, based on the load condition, the preset duration is adjusted. The adjusted preset duration can change the number of charge pumps in the charge pump unit that are in working state.

[0063] Specifically, when the load is light, the preset time is extended to reduce the number of charge pumps in the working state. Figure 5 When the load is light, the preset time between adjacent sub-clock signals is longer, and the number of charge pumps in the working state is one. When the load is heavy, the preset time is shortened and the number of charge pumps in the working state is increased. As shown in Figure 5, when the load is heavy, the preset time between adjacent sub-clock signals is shorter, and the number of charge pumps in the working state is two or three. In addition, since the sub-clock signal is obtained by logical operation with the output signal OPO of the comparator, when OPO=1, the output sub-clock signal will be pulled down. That is, the signal in the dotted part of the figure is the signal pulled down by the output signal OPO.

[0064] Optionally, in step S102, the regulating circuit adjusts the preset duration of the delay unit according to the rate of change of the output voltage, including:

[0065] When the rate of change of the output voltage indicates that the charge pump unit operates in a light load mode, the regulating circuit regulates the control switch so that all the inverters of the inverter string are connected to the circuit to extend the preset time.

[0066] When the rate of change of the output voltage indicates that the charge pump unit operates in a heavy load mode, the regulating circuit regulates the control switch to short-circuit some inverters in the inverter string to shorten the preset time.

[0067] Here, the working mode of the charge pump unit is determined based on the rate of change of the output voltage, that is, it is determined whether the charge pump unit is in a light load mode or a heavy load mode. As an example, a change rate threshold can be set, and when the rate of change of the output voltage is greater than or equal to the change rate threshold, it is characterized that the charge pump unit works in a heavy load mode. When the rate of change of the output voltage is less than the change rate threshold, it is characterized that the charge pump unit works in a light load mode. After determining the working mode of the charge pump unit, based on the working mode, the state of the control switch is controlled to adjust the number of effective inverters in the inverter string. It can be understood that the more effective inverters there are, the more delayed the output clock signal is. The smaller the number of effective inverters, the faster the output clock signal is. Therefore, by controlling the state of the switch, some inverters are connected to the circuit or some inverters are short-circuited, and the number of effective inverters is adjusted to achieve an extension or shortening of the preset duration. In this way, the operation of the charge pump unit is dynamically adjusted based on the load condition. This enables the charge pump unit to effectively reduce the ripple when it is lightly loaded. When it is heavily loaded, the working efficiency can be guaranteed.

[0068] The above description and the accompanying drawings sufficiently illustrate the embodiments of the present disclosure to enable those skilled in the art to practice them. Other embodiments may include structural and other changes. The embodiments represent only possible variations. Unless explicitly required, individual components and functions are optional, and the order of operations may vary. Portions and features of some embodiments may be included in or replace portions and features of other embodiments. The embodiments of the present disclosure are not limited to the structures described above and shown in the accompanying drawings, and various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A charge pump ripple regulation circuit, characterized in that: include: A charge pump unit, comprising N charge pumps connected in parallel, for outputting voltage; a control signal of each charge pump is a corresponding sub-clock signal; a comparator connected to the output terminal of the charge pump unit and used for comparing a reference voltage with the output voltage of the charge pump unit; A delay unit connected to the output end of the charge pump unit, the output end of the comparator and the clock signal; Used to detect the rate of change of the output voltage of the charge pump unit, and use the clock signal to generate a plurality of sub-clock signals which are sequentially delayed by a preset time length, so as to control the number of charge pumps in a working state; The preset time duration depends on the rate of change of the output voltage of the charge pump unit, and the output signal of the comparator is used to control the switching state of the charge pump.

2. The circuit according to claim 1, characterized in that The delay unit comprises: A detection module, comprising a detection capacitor and a pull-down current mirror; one end of the detection capacitor is connected to the output voltage of the charge pump unit, the other end is connected to the pull-down current mirror, and the other end outputs a coupling voltage; A delay module, whose input end is connected to the clock signal and the output signal of the comparator, is controlled by the coupling voltage to adjust the preset time length between the output sub-clock signals; the output signal of the comparator controls the output state of the sub-clock signal.

3. The circuit according to claim 2, characterized in that The delay module comprises: M groups of inverter strings, including a plurality of inverters connected in series, are used to delay a clock signal; the delayed clock signal output by the i-th group of inverter strings is used as an input signal of the i+1-th group of inverters to generate an i+1-th sub-clock signal; the input signal of the first group of inverter strings is a first sub-clock signal after a logic operation of the output signal of the comparator and the clock signal; M control switches are arranged in each inverter string, and are controlled by the coupling voltage signal to short-circuit some inverters in each inverter string; M logic gates, one input end is connected to the delayed clock signal of the corresponding inverter string, the other input end is connected to the output signal of the comparator, and the output end outputs the corresponding sub-clock signal.

4. The circuit according to claim 3, characterized in that The M groups of inverter strings have the same structure, and the number of inverters connected in parallel with the control switch is the same.

5. The circuit according to claim 3, characterized in that The control switch comprises: The MOS tube has a gate connected to the coupling voltage of the detection module, a drain and a source connected to the inverter string, and a part of the inverters connected between the drain and the source are short-circuited by the controlled coupling voltage.

6. The circuit according to claim 2, characterized in that The logic gates include: The NOR gate has one input end connected to the delayed clock signal output by the inverter string, another output end connected to the output signal of the comparator, and an output end outputting a sub-clock signal.

7. The circuit according to claim 2, characterized in that The pull-down current mirror comprises: A pull-down current source for providing a bias current; A pair of MOS tubes, the drain and gate of the first MOS tube are connected to the pull-down current source, and the source is grounded; the drain of the second MOS tube is connected to the other end of the detection capacitor, the gate is connected to the gate of the first MOS tube, and the source is grounded.

8. The circuit according to any one of claims 1 to 7, characterized in that: The circuit further comprises: The voltage divider unit has an input end connected to the output end of the charge pump unit for sampling the output voltage of the charge pump unit; and an output end connected to an input end of the comparator for the comparator to compare the sampled voltage with a reference voltage.

9. A method for charge pump ripple regulation, characterized in that: The charge pump ripple regulation circuit according to any one of claims 1 to 7, comprising: sampling the output voltage of the charge pump unit; When the output voltage is less than the target voltage, the preset duration of the delay unit is adjusted according to the rate of change of the output voltage to adjust the number of charge pumps in the working state in the charge pump unit.

10. The method according to claim 9, characterized in that The step of adjusting the preset duration of the delay unit according to the rate of change of the output voltage comprises: When the rate of change of the output voltage indicates that the charge pump unit is operating in a light load mode, adjusting the control switch so that all the inverters of the inverter string are connected to the circuit to extend the preset time; When the rate of change of the output voltage indicates that the charge pump unit operates in a heavy load mode, the control switch is adjusted to short-circuit some inverters in the inverter string to shorten the preset time.

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