Slew rate controllable system for powering electric machine

Abstract

A slew rate controllable system for powering an electrical machine. The system may include a plurality of power switches operable to convert a direct current (DC) input to an alternating current (AC) output suitable for powering an electrical machine. The system may include a gate drive system operable to control a slew rate associated with transitioning the switch between open and closed states.

Description

[0001] introduce

[0002] The present disclosure relates to systems configured for providing electrical power to an electric machine, such as, but not necessarily limited to, a slewrate controllable system configured for managing transitions of a power switch that operates to provide electrical power to a traction motor of an electric vehicle.

[0003] In the power inversion process, pulse width modulation, pulse density modulation, delta-sigma modulation, pulse frequency modulation or other binary (on / off) switching control signals suitable for the application can be used to facilitate the transition of switches between different states for the purpose of powering the electric machine. For example, the control signal can alternate the conduction state of the switch to generate electric power with an AC voltage waveform. Some of the more common switches used in higher power applications, such as those used to power the traction motors of electric vehicles, can be controlled by voltage and / or current between states. Wide bandgap (WBG), GaN, SiC and other semiconductors, such as metal oxide field effect transistors (MOSFET) and insulated gate bipolar transistors (IGBT) semiconductors, can form a class of switches that can support a wide variety of switching events. The rate, speed, timing, etc. of the switching event or more specifically, the transition of the switch between the on and off or open and closed states can be characterized as a slew rate. Depending on the type of electric machine being powered, such as, for example, when powering a traction motor used to propel an electric vehicle, the ability to finely select and control the slew rate can be beneficial in minimizing second order effects such as overvoltage spikes, electromagnetic interference (EMI) carrying current, voltage overshoot, etc. Summary of the invention

[0004] One non-limiting aspect of the present disclosure relates to a slew rate controllable system configured for fine selection and control of slew rates of switches used in powering an electric machine. The slew rate controllable system may be particularly beneficial in accurately controlling the slew rates of power switches, transistors, and the like used in facilitating powering traction motors of the type typically used to propel electric vehicles. The slew rate controllable system may dynamically adjust and precisely control slew rates based on a wide variety of operational and performance and considerations to provide different switching speeds capable of balancing high switching slew rates relative to performance benefits and operating environment.

[0005] One non-limiting aspect of the present disclosure relates to a slew rate controllable system for powering an electric machine. The slew rate controllable system may include a plurality of power switches operable to convert a direct current (DC) input into an alternating current (AC) output suitable for powering the electric machine, wherein the power switches are operable between an open state and a closed state to facilitate generating the AC output. The slew rate controllable system may further include a gate drive system operable to control the slew rate associated with transitioning the power switch between the open and closed states. The gate drive system may include a plurality of gate drive circuits individually connected to a gate terminal of an associated one of the power switches. The gate drive circuit may include a plurality of available resistor combinations connectable to a gate terminal of an associated one of the power switches, such that a selected resistor combination in the resistor combination may be used to set the slew rate of the switch associated therewith.

[0006] The gate drive system may include a gate controller operable to determine, for each power switch, a selected resistor combination to optimize slew rate.

[0007] The gate drive system may include a gate driver operable to provide a control signal to the gate drive circuit, the control signal being suitable for implementing the selected resistor combination and controlling the power switch to generate an AC output.

[0008] The control signal may be operable to direct the gate drive circuit to control a gate-source voltage (Vgs) between a gate terminal and a source terminal of a switch associated therewith, Vgs controlling the power switch between open and closed states.

[0009] The gate drive circuit may include resistors such that the amount of resistors for each gate drive circuit is equal to K, wherein K / 2 amount of resistors corresponds to an upper resistor and K / 2 amount of resistors corresponds to a lower resistor, optionally wherein the upper resistor is connected in series with the lower resistor, wherein the gate terminal associated therewith is connected between each of the upper and lower resistors.

[0010] The resistors for each gate driving circuit may be arranged into K / 2 number of branches, wherein each branch includes one of the upper resistors and one of the lower resistors.

[0011] The gate drive system may singularly comprise an upper voltage source and a lower voltage source for each branch.

[0012] The gate driving system may include an upper voltage source and a lower voltage source for each branch, respectively.

[0013] The branch may include an upper gate switch and a lower gate switch, wherein the upper gate switch is connected in series between one of the upper voltage sources and one of the upper resistors, and the lower gate switch is connected in series between one of the lower voltage sources and one of the lower resistors.

[0014] The gate drive circuit may provide a gate voltage to a gate terminal connected thereto that is proportional to a voltage difference between the resistance of a selected combination of upper and lower voltage sources and a resistor.

[0015] The control signal may be configured to selectively control the upper and lower gate switches between open and closed states, and thereby control a selected combination of resistors.

[0016] The control signal may be a pulse width modulation (PWM) signal operable between a high voltage, when received, to turn the upper or lower gate switch to an open state, and a low voltage, when received, to turn the upper or lower switch to a closed state.

[0017] The slew rate controllable system may include a DC link capacitor connected between the power switch and a DC source providing the DC input, optionally wherein the gate controller selects a control signal to optimize a discharge rate of the DC link capacitor to avoid or minimize voltage overshoot of the power switch when transitioning between open and closed states.

[0018] The gate controller may be configured to select the control signal based on one or more of: a DC voltage of the DC source, a temperature of the DC link capacitor, a current of one or more of the AC outputs and a junction temperature of one or more of the power switches, a maximum discharge time, a drain-source voltage (Vds), or a voltage threshold (Vth).

[0019] One non-limiting aspect of the present disclosure relates to a method for controlling a slew rate of a power inverter module operable to power an electric machine. The power inverter module may include a plurality of power switches operable to convert a DC input into an AC output suitable for powering the electric machine. The method may include determining a plurality of resistor combinations available for a plurality of gate drive circuits individually connected to a gate terminal of an associated one of the power switches, determining a selected slew rate for the power switch, determining a selected resistor combination of resistor combinations suitable for achieving the selected slew rate, and generating a control signal for the gate drive circuit to achieve the selected resistor combination and control the conversion of the DC input to the AC output.

[0020] The method may include selecting a desired slew rate based on one or more of: a DC voltage of a DC source providing the DC input, a temperature of a DC link capacitor connected to the DC input, a current of the AC output and a junction temperature of one or more of the power switches, a maximum discharge time, a drain-source voltage (Vds), or a voltage threshold (Vth).

[0021] The method may include an amount of resistors for each gate drive circuit equal to K, wherein K / 2 amount of resistors corresponds to an upper resistor and K / 2 amount of resistors corresponds to a lower resistor, optionally wherein the upper resistor is connected in series with the lower resistor and a gate terminal associated therewith is connected between each of the upper and lower resistors.

[0022] A non-limiting aspect of the present disclosure relates to a power inverter module with a controllable slew rate. The power inverter module may include a plurality of power switches operable to convert a direct current (DC) input into an alternating current (AC) output suitable for powering a traction motor of a vehicle, wherein the power switch is operable between an open state and a closed state to facilitate generating the AC output. The power inverter module may further include a gate drive system operable to control a slew rate associated with transitioning the power switch between an open and closed state. The gate drive system may include a plurality of gate drive circuits individually connected to a gate terminal of an associated one of the power switches. The gate drive circuit may include a plurality of available resistor combinations connectable to a gate terminal of an associated one of the power switches, wherein a selected resistor combination in the resistor combination sets a slew rate for the switch associated therewith.

[0023] The gate drive system can generate a pulse width modulation (PWM) signal for controlling multiple gate switches of the gate drive circuit to control the slew rate and AC output, optionally wherein the PWM signal is operable between a high voltage for transitioning the gate switch to an open state when it is received and a low voltage for transitioning the gate switch to a closed state when it is received.

[0024] The power inverter module may include an amount of resistors equal to K forming a resistor combination for each gate drive circuit, wherein K / 2 amount of resistors corresponds to an upper resistor and K / 2 amount of resistors corresponds to a lower resistor, optionally wherein the upper resistor is connected to an upper voltage source via one of the gate switches, the lower resistor is connected to the lower voltage source via another of the gate switches, and the upper resistor is connected in series with the lower resistor with the gate terminals associated therewith connected therebetween.

[0025] One non-limiting aspect of the present disclosure relates to a slew-rate controllable system for powering an electric machine, comprising: a plurality of power switches operable to convert a direct current (DC) input into an alternating current (AC) output suitable for powering the electric machine, the power switches operable between an open state and a closed state to facilitate generating the AC output; and a gate drive system operable to control a slew rate associated with transitioning the power switches between the open and closed states, the gate drive system comprising a plurality of gate drive circuits individually connected to a gate terminal of an associated one of the power switches, the gate drive circuit comprising an available plurality of resistor combinations connectable to the gate terminal of an associated one of the power switches, wherein a selected one of the resistor combinations sets a slew rate for the switch associated therewith.

[0026] The gate drive system includes a gate controller operable to determine a selected resistor combination for each power switch to optimize slew rate.

[0027] The gate drive system includes a gate driver operable to provide a control signal to the gate drive circuit, the control signal being suitable for achieving the selected resistor combination and controlling the power switch to generate an AC output.

[0028] The control signal is operable to direct the gate drive circuit to control a gate-source voltage (Vgs) between a gate terminal and a source terminal of a switch associated therewith, Vgs controlling the power switch between open and closed states.

[0029] The amount of resistors used for each gate drive circuit is equal to K, where K / 2 amount of resistors corresponds to an upper resistor and K / 2 amount of resistors corresponds to a lower resistor, the upper resistor is connected in series with the lower resistor, and the gate terminal associated therewith is connected between each of the upper and lower resistors.

[0030] The resistors for each gate driving circuit are arranged into K / 2 number of branches, each branch including one of the upper resistors and one of the lower resistors.

[0031] The gate drive system comprises in particular an upper voltage source and a lower voltage source for each branch.

[0032] The gate driving system includes an upper voltage source and a lower voltage source for each branch, respectively.

[0033] Each branch includes an upper gate switch connected in series between one of the upper voltage sources and an upper resistor, and a lower gate switch connected in series between one of the lower voltage sources and one of the lower resistors.

[0034] The gate drive circuit provides a gate voltage to a gate terminal connected thereto, the gate voltage being proportional to the resistance of the selected combination of resistors and the voltage difference between the upper and lower voltage sources.

[0035] The control signal is configured to selectively control the upper and lower gate switches between open and closed states and thereby control a selected combination of resistors.

[0036] The control signal is a pulse width modulation (PWM) signal operable between a high voltage and a low voltage, the high voltage when received turns the upper or lower gate switch to an open state and the low voltage when received turns the upper or lower switch to a closed state.

[0037] A DC link capacitor is connected between the power switch and a DC source providing the DC input, and the gate controller selects a control signal to optimize the discharge rate of the DC link capacitor to avoid or minimize voltage overshoot when the power switch transitions between open and closed states.

[0038] The gate controller is configured to select the control signal based on one or more of: a DC voltage of the DC source, a temperature of the DC link capacitor, one or more currents in the AC output and a junction temperature of one or more of the power switches, a maximum discharge time, a drain-source voltage (Vds), or a voltage threshold (Vth).

[0039] One non-limiting aspect of the present disclosure relates to a method for controlling a slew rate of a power inverter module operable to power an electric machine, the power inverter module including a plurality of power switches operable to convert a DC input into an AC output suitable for powering the electric machine, the method comprising: determining a plurality of resistor combinations available for a plurality of gate drive circuits, the plurality of gate drive circuits individually connected to a gate terminal of an associated one of the power switches; determining a selected slew rate for the power switch; determining a selected resistor combination of resistor combinations suitable for achieving the selected slew rate; and generating a control signal for the gate drive circuit to achieve the selected resistor combination and control conversion of the DC input to the AC output.

[0040] The selected slew rate is determined based on one or more of: a DC voltage of a DC source providing the DC input, a temperature of a DC link capacitor connected to the DC input, a current of the AC output and a junction temperature of one or more of the power switches, a maximum discharge time, a drain-source voltage (Vds), or a voltage threshold (Vth).

[0041] Wherein the amount of resistors used for each gate drive circuit is equal to K, wherein K / 2 amount of resistors corresponds to an upper resistor and K / 2 amount of resistors corresponds to a lower resistor, the upper resistor being connected in series with the lower resistor, wherein the gate terminal associated therewith is connected between each of the upper and lower resistors.

[0042] One non-limiting aspect of the present disclosure relates to a power inverter module with controllable slew rate, comprising: a plurality of power switches operable to convert a direct current (DC) input into an alternating current (AC) output suitable for powering a traction motor of a vehicle, the power switches operable between an open state and a closed state to facilitate generating the AC output; and a gate drive system operable to control a slew rate associated with transitioning the power switches between the open and closed states, the gate drive system comprising a plurality of gate drive circuits individually connected to a gate terminal of an associated one of the power switches, the gate drive circuit comprising a plurality of resistor combinations connectable to a gate terminal of an associated one of the power switches, wherein a selected one of the resistor combinations is set for a slew rate of the power switch with which it is associated.

[0043] The gate drive system generates a pulse width modulation (PWM) signal for controlling multiple gate switches of the gate drive circuit to control the slew rate and AC output, the PWM signal being operable between a high voltage and a low voltage, the high voltage turning the gate switch to an open state when received and the low voltage turning the gate switch to a closed state when received.

[0044] The amount of resistors forming the resistor combination for each gate drive circuit is equal to K, where K / 2 amount of resistors corresponds to an upper resistor and K / 2 amount of resistors corresponds to a lower resistor, the upper resistor is connected to an upper voltage source via one of the gate switches, the lower resistor is connected to the lower voltage source via another of the gate switches, the upper resistor is connected in series with the lower resistor, with the gate terminals associated therewith connected therebetween.

[0045] When considered in conjunction with the accompanying drawings, these features and advantages together with other features and advantages of the present teachings can be readily apparent from the following detailed description of the mode of implementing the present teachings. It should be understood that even though the following figures and embodiments may be described separately, their individual features may be combined into additional embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The accompanying drawings, which may be incorporated in and constitute a part of this specification, illustrate implementations of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0047] Figure 1 A partial schematic view of a slew rate controllable system according to one non-limiting aspect of the present disclosure is illustrated.

[0048] Figure 2 A partial schematic view of a gate drive circuit according to one non-limiting aspect of the present disclosure is illustrated.

[0049] Figure 3 A graph illustrating controller slew rates according to one non-limiting aspect of the present disclosure is illustrated.

[0050] Figure 4 A flow chart illustrating a method of controlling slew rate according to one non-limiting aspect of the present disclosure is illustrated. DETAILED DESCRIPTION

[0051] As required, detailed embodiments of the present disclosure may be disclosed herein; however, it is understood that the disclosed embodiments may be merely examples of the present disclosure, which may be embodied in various and alternative forms. The figures may not necessarily be to scale; some features may be enlarged or minimized to show details of particular components. Therefore, the specific structural and functional details disclosed herein may not need to be interpreted as limiting, but merely as a representative basis for teaching those skilled in the art to adopt the present disclosure in different ways.

[0052] Figure 1 A partial schematic view of a slew rate controllable system 10 according to one non-limiting aspect of the present disclosure is illustrated. The system 10 may include a gate drive system 16 operable to power an electric machine 14, which for exemplary purposes is primarily described as an electric motor 14, commonly referred to as a traction motor 14. The traction motor 14 may be of the type employed in a vehicle such as an electric vehicle to provide mechanical traction operable to propel the vehicle or otherwise perform work. As described in more detail below, the gate drive system 12 may be operable to finely select and control the slew rate of a portion of a plurality of power switches, transistors, etc. S1, S2, ... S6 used as a power inverter module (PIM) 16 to facilitate powering the electric machine 14. The system 12 may dynamically adjust and precisely control the slew rate based on a wide variety of operational and performance considerations to provide different switching speeds capable of balancing high switching slew rates relative to performance benefits and operating environment. Although primarily described with respect to selectively controlling the slew rates of power switches S1, S2, ... S6 for use in electric vehicles, those skilled in the art will readily recognize that the capabilities of system 12 are advantageous in facilitating powering other types of electric machines 14 which would similarly benefit from minimizing second order effects such as overvoltage spikes, electromagnetic interference (EMI) carrying currents, voltage overshoots, and the like.

[0053] The vehicle may include a rechargeable energy storage system (RESS) 20 for storing and supplying electrical power for various systems included on the vehicle. The RESS 20 may be a battery or other energy storage device that is capable of selectively supplying electrical power to and receiving electrical power from the electric machine 14 via the PIM 16. When powering the electric machine 14, the RESS 20 may be configured as a source for providing a direct current (DC) input 22 to the PIM 16. A DC link capacitor 24 may be disposed therebetween to smooth, filter, and otherwise process the DC input 22 for use with the PIM 16. The illustrated PIM 16 includes six power transistors / power switches S1, S2, ... S6, each having a gate terminal G, a drain terminal D, and a source terminal S. Each of the gate terminals G of each switch S1, S2, ... S6 may be separately and independently connected to one of a plurality of gate drive circuits 26. The power switches S1, S2, ... S6 may correspond to a wide range of power switches S1, S2, ... S6, including wide bandgap (WBG), GaN, SiC and other similar semiconductors, such as metal oxide field effect transistors (MOSFETs) and insulated gate bipolar transistors (IGBT) semiconductors. The gate drive system 12 may include a gate controller 30 operable to individually and specifically control the gate drive circuit 26 to control the rate, speed, timing, etc. of switching events of the power switches S1, S2, ... S6, i.e., control the transition of the power switches S1, S2, ... S6 between on and off or open and closed states. The transition of the power switches S1, S2, ... S6 between states may be characterized as a slew rate, wherein the gate drive circuit 26 is operable to individually select the slew rate for each power switch S1, S2, ... S6 according to a corresponding control signal 32 provided from the gate controller 30. One non-limiting aspect of the present disclosure contemplates that the gate drive circuit 26 is operable to provide a gate voltage and / or a gate current to a gate terminal G associated therewith, wherein the corresponding gate voltage or gate current is operable to transition the associated switches S1, S2, ... S6 between open and closed states, i.e., to control whether the corresponding switches S1, S2, ... S6 are active or inactive.

[0054] The gate controller 30 may include a gate driver 34 configured to provide a control signal 32 to each gate drive circuit 26 individually. The gate driver 34 may be used in this manner to facilitate switching events for the power switches S1, S2, ... S6, whereby the DC input 22 may be converted to an alternating current (AC) output 38. The AC output 38 may be generated in the illustrated manner to provide a multi-phase output having a plurality of AC signals 40, 42, 44 suitable for use in powering the electric machine 14, which is illustrated for non-limiting purposes as corresponding to a three-phase implementation, wherein the three-phase AC output 38 is provided to an AC bus or winding of the electric machine 14, such as via corresponding input terminals of the associated AC input. As noted above, the use of the gate drive system 12 to facilitate a controllable slew rate-based approach for controlling switching events, and thereby converting the DC input 22 to an AC output 38 suitable for powering the electric machine 14 is presented for non-limiting purposes, as the present disclosure fully contemplates that the gate drive system 12 is operable in other environments and for other purposes. As such, in addition to the illustrated use case in which the power switches S1, S2, ... S6 can be configured to operate as unidirectional or bidirectional DC / AC converters, the present disclosure fully contemplates the use of the gate drive system 12 to control the slew rate for the power switches S1, S2, ... S6 or other devices.

[0055] The gate controller 30 may include a non-transitory computer-readable storage medium having a plurality of non-transitory instructions stored thereon, which, when executed with associated one or more processors, may operate in accordance with the present disclosure to facilitate generating control signals 32 in a manner that provides a desired slew rate while also managing the AC output required for proper powering of the electric machine 14. Although not separately shown in detail, a plurality of sensors or other features may be employed to facilitate measuring or otherwise determining the DC voltage of the DC source 20, the temperature of the DC link capacitor 24, the current of one or more of the AC outputs 38, and the junction temperature, maximum discharge time, drain-source voltage (Vds), voltage threshold (Vth) of one or more of the switch / power transistors S1, S2, ... S6. The gate controller 30 may process the sensor measurements, metrics, etc. to determine the desired slew rate for each power switch S1, S2, ... S6, which may include selecting the control signal 32 to optimize the discharge speed of the DC link capacitor 24 to avoid or minimize voltage overshoot of the power switches S1, S2, ... S6 when transitioning between the open and closed states. The gate controller 30 may be used in this manner to vary the slew rates of the power switches S1 , S2 , . . . S6 in real time within and between switching events, and optionally in an isolated manner to alter the slew rate to be selected based on operating conditions, desired performance, etc.

[0056] Figure 2 A partial schematic view of one of the gate drive circuits 26 according to one non-limiting aspect of the present disclosure is illustrated. Although the connection will be repeated for each switch S1, S2, ... S6, respectively, for exemplary purposes, the gate drive circuit 26 is shown as being connected to the gate terminal G of the switch S1. Since the switch S1 is configured as a voltage and / or current controlled type switch S1, the gate drive circuit 26 is shown in this manner as being connectable to the gate terminal G, whereby the gate voltage and / or gate current provided to the gate terminal G can be used to transform the switch S1 between the open and closed states, i.e., control the switching event. In the case where the switch S1 adopts an alternative configuration, the gate drive circuit 26 can be similarly adapted to provide a voltage and / or current to the corresponding terminal. The gate drive circuit 26 may include a plurality of branches B, each of which includes an upper gate switch 46, an upper resistor 48, a lower resistor 50, and a lower gate switch 52. The upper gate switch 46 can be connected to an upper voltage source 58, and the lower gate switch 52 can be connected to a lower voltage source 60, optionally, wherein each branch B is specifically connected to the same upper and lower voltage sources 58, 60, or each branch is each connected to its own dedicated or separate set of upper and lower voltage sources 58, 60, i.e., each branch B can include a separate set of upper and lower voltage sources 58, 60, which in turn can be individually controlled with the gate controller 30 to provide the same or different voltage levels. The upper gate switch 46 is shown as being connected in series with the upper voltage source 58, the upper resistor 46, the lower resistor 48, and the lower voltage source 60, wherein the upper gate switch 46 is connected between the upper voltage source 58 and the upper side of the upper resistor 46, the gate terminal G is connected between the lower side of the upper resistor 46 and the upper side of the lower resistor 48, the upper side of the lower resistor 50 is connected to the lower side of the upper resistor 46, and the lower gate switch 52 is connected between the lower voltage source 60 and the lower side of the lower resistor 50.

[0057] The gate driver 34 can be configured to generate a control signal 32 having separate control signals 62, 64, suitable for selectively opening and closing the upper and lower gate switches 46, 52, and thereby controlling the gate voltage and / or current provided to the gate terminal G. The control signals 62, 64 can correspond to a pulse width modulation (PWM) signal operable between a high voltage H and a low voltage L to correspondingly control the associated upper or lower gate switch 46, 52 to be in a closed state and an open state. The duty cycle of the control signal 32 can be varied to finely adjust the gate voltage and / or current at a precise level depending on the desired slew rate, for example, to facilitate real-time adjustment of the slew rate according to the desired operation of the electric machine 14. PWM duty cycle control can be used to change the output current of the gate G (capacitor) in and out of the switch. Due to hysteresis and energy considerations, the fastest gate speed and slew rate may be preferred for switching. The method of controlling the PWM duty cycle can be based on the DC bus voltage and current to allow for optimal efficiency and reliability. For example, for a 400-800V system, the present disclosure may be used to adapt the PIM 16 to each bus. In the illustrated configuration, the control signals 62, 64 may be operable to direct the gate drive circuit 26 to control the gate-source voltage (Vgs) between the gate terminal G and the source terminal of the switch S1, where Vgs controls the power transistor between an open and closed state, and / or the control signals 62, 64 may be operable to direct the gate drive circuit 26 to control the gate current (Ig) to the gate terminal G, where Ig controls the power transistor between an open and closed state. The Vgs and Ig provided to the gate terminal G may be proportional to the resistance of the upper and lower voltage sources 48, 50 and the voltage difference between the upper and lower voltage sources 58, 60.

[0058] The gate driver 34 can be configured to provide different control signals 32 to the upper and lower gate switches 46, 52, such as in the illustrated manner, whereby the control signals 62, 64 can have different duty cycles. This ability to individually vary the duty cycle or other aspects of the control signals 32 used to transition the upper and lower gate switches 46, 52 between states can be beneficial in enabling the gate controller 30 to control Vgs and / or Ig at a very fine and precise level of granularity, wherein the resulting voltage and current are set based on the resistivity of the upper and lower voltage sources 58, 60 and the upper or lower resistors 48, 50. The gate controller 30 can optionally control the voltage provided to each of the upper and lower voltage sources 58, 60 to further enhance its ability to finely select the voltage and / or current provided to the gate terminal G. For example, in some cases, the control signal 32 can be used to selectively open or deactivate any of the upper and lower gate switches 46, 52, optionally in conjunction with changing the voltage of the upper and lower voltage sources 58, 60, thereby even further increasing the specificity of selecting and achieving a desired slew rate. The gate drive circuit 26 can include K amount of upper and lower resistors 48, 50, such as by including K / 2 amount of upper resistors 48 and K / 2 amount of lower resistors 50. The resistivity or resistance value of each of the K amount of upper and lower resistors 48, 50 can be equal or different, and are individually selected before insulation and / or controllable after installation, thereby providing a plurality of resistor combinations depending on whether the upper and / or lower gate switches 46, 52 associated therewith are used for corresponding control of the open or closed state.

[0059] Resistor combinations may be individually arbitrated and used by the gate controller 30 in this manner to selectively control the slew rate of the power switches S1, S2, ... S6 connected to each gate drive circuit 26. For example, the gate controller 30 may be configured to evaluate the available resistor combinations and determine a selected resistor combination from the available resistor combinations for each control circuit 26 based on desired operating performance, environment, sensor readings, etc. The gate controller 30 may include a lookup table or other logic structure capable of monitoring a variety of input conditions for use in determining the selected resistor combination for the gate drive circuit 26. For example, the gate drive controller 30 may vary the selectively resistor combination for one or more power switches S1, S2, ... S6, optionally in concert with the selectively varying voltages of the upper and lower voltage sources 58, 60 of the corresponding branch B, thereby finely controlling the slew rate and DC-to-AC conversion process of the PIM 16. The ability to adjust the slew rate in this manner customizes the operation of the power switches S1, S2, ... S6, or more specifically the slew rate of switching events of the power switches S1, S2, ... S6 to account for the effects of the electric machine 14 and the desired AC input thereto, wear, and other factors.

[0060] Figure 3A diagram 70 of a method for controlling slew rate by changing a selected combination of resistors according to one non-limiting aspect of the present disclosure is illustrated. Diagram 70 is shown as including a vertical axis 72 for voltage and current and a horizontal axis 74 for time. A first waveform 78 represents a voltage (Vds) between drain and source terminals, a second waveform 80 represents a current (Id) through the drain terminal, a third waveform 82 represents Vgs, a fourth waveform 84 represents Ig, a fifth waveform 86 represents a voltage (Vdg) between gate and drain terminals, and a sixth waveform 88 represents an exemplary maximum Vgs (Vgs, max). Diagram 70 illustrates an exemplary scenario whereby the slew rate of switch S1, i.e., dV / dt and / or dI / dt, can be selectively controlled based on the transition properties of switch S1. The period occurring before time T0 may correspond to switch S1 being turned off or activated, after which at time T0, the gate drive circuit 26 begins to power the gate terminal G at an initial slew rate. From time T0 to time T1, as Id increases, the initial slew rate may be maintained. At approximately time T1, or later, as the slope of Vgs decreases and / or as Vds drops, the D drive circuit can begin to power the gate terminal G at an intermediate slew rate, which can be useful for controlling the slope or rate of the corresponding decrease in Vds. At approximately time T2, or once Vds reaches or approaches its minimum value, a larger slew rate can be achieved, optionally with additional slew rate adjustments at T3 and / or T4. The ability to selectively control Vgs and / or Ig during the transition of switch S1 can be beneficial in maximizing performance, or more particularly slew rate, as switch S1 continues to progress through various states associated with transitioning from an open state to a closed state. The method can be performed in this manner, whereby the slew rate for the drive circuit 26 and the accompanying transitions of the switches S1, S2, ... S6 connected thereto can be achieved to control the DC to AC conversion required to power the electric machine 14.

[0061] Figure 4A flow chart of a method for controlling the slew rate of a PIM 16 or other device according to one non-limiting aspect of the present disclosure is illustrated. Block 94 relates to a combination process for determining a plurality of resistor combinations that can be used for a gate drive circuit. The combination process may include access to the resistivity of each of the K-quantity gate resistors 48, 50 and / or the ability of the gate controller 30 to set the resistivity for each of the gate resistors 48, 50 on a per-gate circuit basis, and the available connections that can be established between the gate resistors 48, 50, the branch B, and the upper and lower voltage sources 58, 60. The combination process may be predefined in a lookup table or otherwise determined by the gate controller 30 or otherwise indexed in the following manner: the gate resistors 48, 50 may be connectable to each other depending on the configuration of the corresponding gate drive circuit 26, i.e., based on the resistor combinations available therefor. The combination process may be particularly useful in identifying each available manner in which the gate terminal G of each power switch S1, S2, ... S6 may be driven depending on the selected combination of resistors.

[0062] Box 96 involves a slew rate process for determining the selected slew rate for each power switch S1, S2, ... S6. The slew rate process may include evaluating one or more of the following: the DC voltage of the DC source 20, the temperature of the DC link capacitor 24, the current of one or more of the AC outputs 38, and the junction temperature, maximum discharge time, drain-source voltage (Vds) or voltage threshold (Vth) of one or more of the power switches S1, S2, ... S6. The gate controller 30 may include a lookup table or other method for determining the slew rate that should be used or expected. Box 98 involves a selection process for determining a selected resistor combination in a resistor combination suitable for achieving the selected slew rate. The selection process may occur on a per-gate drive circuit basis so that the selected resistor combination may be individually customized for each gate drive circuit 26 and for the desired slew rate thereof. In the case where the resistor combination available for a particular gate drive circuit 26 may not achieve the preferred slew rate, the selected combination of resistors for it may be selected to correspond to the resistor combination that provides the closest match. Block 100 involves a control process for generating a control signal 32 for the gate drive circuit 26 to achieve a selected resistor combination and control conversion of a DC input to an AC output at a selected slew rate.

[0063] As supported above, the present disclosure relates to a system and method to achieve real-time slew rate (SR) control of power transistors of inverters and converters by paralleling and / or serializing gate charging and discharging subcircuits of gate drive circuits to change the slew rate in real time, maximizing the number of slew rates through external resistor design. Different Vgs plus duty cycle controls can be used to overcome the drop in dynamic response of gate charging and discharging when Vgs is maintained within limits. Feed-forward control can be utilized using a lookup table (LUT) to change the slew rate based on operating conditions, i.e., Vdc, current, Vth, and junction temperature, which can include control based on operating conditions, transistor signal sensing, and part-to-part variations and degradation, and tuning the gate resistor and gate current source of each ON and OFF branch for these conditions. Slew rate control can be operable to compensate for transistor / switch part-to-part variations - i.e., Vth, gate resistors, stray inductance, and in particular, use parallel / serialized control to control slew rate to achieve capacitor discharge while managing I / V overshoot, and tuning the gate resistance or current of each gate resistor branch or gate current branch to attenuate current ripple and higher order harmonics associated with motor losses. The present disclosure can include a minimum amount of hardware as a voltage / current source and low voltage switch, using pulse modulation to control the gate current to achieve a variety of slew rates. This can equivalently transform the gate drive circuit into a charge pump for the gate capacitor, enabling an advantageous method of control through a variable speed gate drive circuit, allowing fine tuning of switching performance to optimize between losses, overshoot, EMI and carrying current. In this way, the gate drive circuit can be operable to turn on / off the power switch to convert electrical power between DC and AC, optionally with faster switching, minimal switching losses and improved maximum power capability, thereby limiting the effects of electrical stress on the power switch, ringing, conducted and radiated EMI, and motor terminal voltage overshoot (PDIV) and carrying current.

[0064] The terms "comprise", "include" and "have" are inclusive and therefore specify the presence of the features, steps, operations, elements or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements or components. When possible, the order of steps, processes and operations can be changed, and additional or alternative steps can be adopted. As used in this specification, the term "or" includes any and all combinations of the associated listed items. The term "any of which" is understood to include any possible combination of the referenced items, including "any one" of the referenced items. "One", "an", "the", "at least one" and "one or more" are used interchangeably to indicate that at least one of the items exists. Unless the context clearly indicates otherwise, there may be multiple such items. Unless clearly or clearly indicated in view of the context including the attached claims, all values ​​of the parameter (e.g., amount or condition) will be understood to be modified by the term "approximately" in all instances, regardless of whether "approximately" actually appears before the value. The component that is "configured to" perform the specified function is able to perform the specified function without change, rather than just having the potential to perform the specified function after further modification. In other words, the described hardware, when expressly configured to perform the specified functions, is specifically selected, created, implemented, utilized, programmed, and / or designed for the purpose of performing the specified functions.

[0065] Although various embodiments have been described, the description is intended to be exemplary rather than restrictive, and it will be clear to those of ordinary skill in the art that many more embodiments and implementations are possible within the scope of the embodiments. Unless specifically limited, any feature of any embodiment may be used in combination with or in place of any other feature or element in any other embodiment. Therefore, the embodiments are not limited except in accordance with the appended claims and their equivalents. In addition, various modifications and changes may be made within the scope of the appended claims. Although several modes for implementing many aspects of this teaching have been described in detail, those skilled in the art who are familiar with the fields to which these teachings are related will recognize various alternative aspects for practicing this teaching within the scope of the appended claims. It is intended that all content contained in the above description or shown in the accompanying drawings should be interpreted as illustrative and exemplary of the entire scope of alternative embodiments, and those of ordinary skill will recognize that these alternative embodiments are implied by the included content, structurally and / or functionally equivalent to the included content, or otherwise become clear based on the included content, and are not limited to those embodiments that are explicitly depicted and / or described.

Claims

1. A slew rate controllable system for supplying power to an electric machine, comprising: a plurality of power switches operable to convert a direct current (DC) input into an alternating current (AC) output suitable for powering an electrical machine, the power switches being operable between an open state and a closed state to facilitate generating the AC output; and A gate drive system operable to control a slew rate associated with transitioning a power switch between open and closed states, the gate drive system comprising a plurality of gate drive circuits individually connected to a gate terminal of an associated one of the power switches, the gate drive circuits comprising an available plurality of resistor combinations connectable to the gate terminal of an associated one of the power switches, wherein a selected one of the resistor combinations sets a slew rate for the switch associated therewith.

2. The slew rate controllable system according to claim 1, wherein: The gate drive system includes a gate controller operable to determine a selected resistor combination for each power switch to optimize slew rate.

3. The slew rate controllable system according to claim 2, wherein: The gate drive system includes a gate driver operable to provide a control signal to the gate drive circuit, the control signal being suitable for achieving the selected resistor combination and controlling the power switch to generate an AC output.

4. The slew rate controllable system according to claim 3, wherein: The control signal is operable to direct the gate drive circuit to control a gate-source voltage (Vgs) between a gate terminal and a source terminal of a switch associated therewith, Vgs controlling the power switch between open and closed states.

5. The slew rate controllable system according to claim 4, wherein: The amount of resistors used for each gate drive circuit is equal to K, where K / 2 amount of resistors corresponds to an upper resistor and K / 2 amount of resistors corresponds to a lower resistor, the upper resistor is connected in series with the lower resistor, and the gate terminal associated therewith is connected between each of the upper and lower resistors.

6. The slew rate controllable system according to claim 5, wherein: The resistors for each gate driving circuit are arranged into K / 2 number of branches, each branch including one of the upper resistors and one of the lower resistors.

7. The slew rate controllable system according to claim 6, wherein: The gate drive system comprises in particular an upper voltage source and a lower voltage source for each branch.

8. The slew rate controllable system according to claim 6, wherein: The gate driving system includes an upper voltage source and a lower voltage source for each branch, respectively.

9. The slew rate controllable system according to claim 8, wherein: Each branch includes an upper gate switch connected in series between one of the upper voltage sources and an upper resistor, and a lower gate switch connected in series between one of the lower voltage sources and one of the lower resistors.

10. The slew rate controllable system according to claim 9, wherein: The gate drive circuit provides a gate voltage to a gate terminal connected thereto, the gate voltage being proportional to the resistance of the selected combination of resistors and the voltage difference between the upper and lower voltage sources.

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