High-frequency current harmonic suppression method for modularized double-winding permanent magnet synchronous motor

Abstract

The invention discloses a high-frequency current harmonic suppression method for a modularized double-winding permanent magnet synchronous motor, and relates to the field of double-winding permanent magnet synchronous motor control. The problems that the cost is increased and energy conversion is not considered due to the fact that multiple inverters are adopted in an existing control strategy are solved. The method comprises the following steps: constructing a double-winding permanent magnet synchronous motor control system, wherein the power supply topology of the double-winding permanent magnet synchronous motor control system is an isolated interleaved parallel topology; obtaining a motor rotor position angle and a rotating speed signal, and calculating a difference value between a rotating speed given signal and a rotating speed feedback signal to obtain d-axis and q-axis current given values of two sets of windings; 6-phase current values are obtained, actual values of d-axis current and q-axis current of the two sets of windings are obtained according to the coordinate transformation matrix, and the difference value of the d-axis current and the q-axis current is solved to serve as input of a current loop PI controller; performing coordinate transformation on the output of the current loop PI controller, and calculating a voltage modulation ratio; and selecting a proper voltage modulation strategy and a carrier phase shift angle to carry out high-frequency current harmonic suppression. The method is applied to the high-frequency current harmonic suppression field.

Description

Technical Field

[0001] The invention relates to the technical field of dual-winding permanent magnet synchronous motor control, and in particular to a method for suppressing high-frequency current harmonics of a modular dual-winding permanent magnet synchronous motor. Background Art

[0002] The dual-winding permanent magnet synchronous motor has the advantages of low-voltage, large-capacity operation and high reliability. However, when the inductance of the motor is small, the high-frequency current harmonic content caused by the voltage modulation process is large. At the same time, in some high-power applications, the switching frequency of the power switching device is limited, which will further increase the high-frequency harmonic current content in the system. The presence of high-frequency harmonic current will increase the high-frequency loss of the system and cause large high-frequency noise in the system.

[0003] In order to suppress high-frequency harmonic currents, some scholars have proposed a control strategy that uses an isolated interleaved parallel topology combined with carrier phase shifting technology. In order to suppress high-frequency current harmonics near 1 times the switching frequency and 2 times the switching frequency as much as possible, three three-phase inverters are required. Therefore, this technology has the following defects:

[0004] Only improving the power supply topology, such as adding more inverters, can improve current harmonics to a certain extent, but it fails to fundamentally solve the complexity and hardware cost problems of the control system. Due to the use of multiple inverters (such as 3 three-phase inverters), the hardware requirements of the control system increase significantly, which will lead to an increase in system costs.

[0005] At the same time, the improvement of the power supply topology has only enhanced the hardware structure, but has not effectively considered the issue of energy conversion efficiency. Although the introduction of multiple inverters may help suppress some harmonics, the increased number and complexity of inverters may lead to reduced energy conversion efficiency of the system. Especially in multi-inverter systems, losses in the power conversion process, heat dissipation problems, and frequency control problems may affect the overall efficiency, especially when running at high load or for a long time. Summary of the invention

[0006] The present invention aims at the problem that the existing control strategy using isolated interleaved parallel topology combined with carrier phase shifting technology uses multiple inverters, which increases the cost and does not consider energy conversion, thus affecting the efficiency. A method for suppressing high-frequency current harmonics of a modular dual-winding permanent magnet synchronous motor is proposed. The method includes:

[0007] S1: construct a dual-winding permanent magnet synchronous motor control system, in which the power supply topology is an isolated interleaved parallel topology, including two sets of three-phase inverters and three common-mode inductors;

[0008] S2: Obtain the motor rotor position angle and speed signal according to the rotary transformer, calculate the difference between the speed setting and the speed feedback signal as the input of the speed loop PI controller, and obtain the current setting values ​​of the two sets of windings d-axis and q-axis;

[0009] S3: Obtain the 6-phase current values ​​through the current sensor, obtain the actual values ​​of the d-axis and q-axis currents of the two sets of windings according to the coordinate transformation matrix, and solve the difference between the given value and the actual value of the d-axis and q-axis currents as the input of the current loop PI controller;

[0010] S4: Perform coordinate transformation on the output of the current loop PI controller to obtain a given voltage value in the α-β coordinate system, and calculate the voltage modulation ratio M according to the control system;

[0011] S5: Select an appropriate voltage modulation strategy and carrier phase shift angle according to the voltage modulation ratio M to suppress high-frequency current harmonics of the dual-winding permanent magnet synchronous motor.

[0012] Furthermore, a preferred method is proposed, in which step S4 comprises:

[0013]

[0014] Where M is the voltage modulation ratio, V dc is the bus voltage, u d1 is the d-axis current inner loop output, u q1 It is the q-axis current inner loop output.

[0015] Furthermore, a preferred manner is proposed, in which the voltage modulation strategy in step S5 includes a space vector voltage modulation strategy SVPWM and a dual switch sequence voltage modulation strategy DSPWM.

[0016] Furthermore, a preferred method is proposed, in which the matching principle between the voltage modulation ratio M, the voltage modulation strategy and the carrier phase shift angle is:

[0017] Calculate the relationship between high-frequency voltage harmonic content and voltage modulation ratio M;

[0018] Calculate the relationship between current harmonic content and voltage modulation ratio M;

[0019] Harmonic analysis is performed using an isolated interleaved parallel topology based on two three-phase inverters;

[0020] According to the high-frequency current harmonic distribution characteristics when using space vector voltage modulation strategy SVPWM and dual switch sequence voltage modulation strategy DSPWM, the carrier phase shift angle and voltage modulation strategy are selected.

[0021] Furthermore, a preferred method is proposed, wherein the relationship between the high-frequency voltage harmonic content and the voltage modulation ratio M is calculated, including:

[0022]

[0023] Among them, A mn Represents the real part of the harmonic voltage amplitude, B mn It represents the imaginary part of the harmonic voltage amplitude, j represents the imaginary unit, m represents the harmonic order of the carrier, n represents the harmonic order of the fundamental wave, i represents the sector number, y represents the imaginary unit, and s (i) represents the lower limit of the interval of the i-th sector, y e (i) represents the upper limit of the interval of the i-th sector; x r (i) represents the carrier phase corresponding to the rising edge of the voltage waveform in the i-th sector, x f (i) represents the carrier phase corresponding to the falling edge of the voltage waveform in the i-th sector, V dc Indicates the bus voltage.

[0024] Furthermore, a preferred method is proposed, wherein the relationship between the current harmonic content and the voltage modulation ratio M is calculated, including:

[0025]

[0026] Among them, I m-rms Indicates the harmonic current distortion value of m times the switching frequency, L is the motor phase inductance; h = 0, 1, 2, 3..., f c represents the carrier frequency, and f0 represents the fundamental frequency of the motor.

[0027] Furthermore, a preferred method is proposed, wherein the harmonic analysis is performed using an isolated interleaved parallel topology based on two three-phase inverters, including:

[0028] Get the motor phase voltage u represented by the inverter output voltage ao1 :

[0029]

[0030] Where, Z0(ω0) represents the coupled inductor impedance; Z A1 (ω0) represents the impedance of the A1 phase winding; u ag1 、u bg1 and u cg1 represents the output voltage of the first three-phase inverter, u ag2 、u bg2 and u cg2 Indicates the three-phase output voltage of the second three-phase inverter;

[0031] The output voltage of each bridge arm of the inverter is calculated according to the double Fourier decomposition formula;

[0032] Analyze the influencing factors of harmonic voltage content based on the output voltage of each bridge arm of the inverter.

[0033] Furthermore, a preferred method is also proposed. The specific matching principle between the hybrid modulation strategy and the voltage modulation ratio M is as follows:

[0034] When M < 0.41, the space vector pulse width modulation (SVPWM) strategy is adopted and the carrier phase shift angle is set to π / 2.

[0035] When 0.41 < M < 0.84, the dual-switch sequence pulse width modulation (DSPWM) strategy is adopted and the carrier phase shift angle is set to π.

[0036] When 0.84 < M < 0.98, the space vector pulse width modulation (SVPWM) strategy is adopted and the carrier phase shift angle is set to π.

[0037] When M > 0.98, the space vector pulse width modulation (DSPWM) strategy is adopted and the carrier phase shift angle is set to π / 2.

[0038] Based on the same inventive concept, the present invention also provides a computer device, including a memory and a processor. A computer program is stored in the memory. When the processor runs the computer program stored in the memory, the processor executes a method for suppressing high-frequency current harmonics of a modular dual-winding permanent magnet synchronous motor according to any one of the above.

[0039] Based on the same inventive concept, the present invention also provides a computer-readable storage medium. A computer program is stored on the computer-readable storage medium. When the computer program is run by a processor, it executes the steps of a method for suppressing high-frequency current harmonics of a modular dual-winding permanent magnet synchronous motor according to any one of the above.

[0040] The advantages of the present invention are as follows:

[0041] In a traditional isolated interleaved parallel topology, multiple inverters are used to suppress high-frequency current harmonics, which usually leads to a significant increase in hardware costs and requires a complex control system for coordination. The introduction of multiple inverters increases the hardware cost and also the complexity of system debugging, maintenance, and fault troubleshooting. By adopting a power supply topology of a dual-winding permanent magnet synchronous motor combined with two sets of three-phase inverters and an optimized control strategy to suppress high-frequency harmonics, the present invention avoids the use of too many inverters, effectively controls the complexity of the overall system, and relatively reduces the hardware cost.

[0042] In the traditional method, although harmonics are reduced by adding inverters, the efficiency of energy conversion is not particularly considered, which may lead to a decrease in the overall energy conversion efficiency of the system due to factors such as an increase in the number of hardware and increased control difficulty. The present invention can maintain a high energy conversion efficiency while reducing harmonics by optimizing the control system and voltage modulation strategy. For example, the current control of the motor is optimized through an accurate current loop PI controller and a coordinate transformation matrix to ensure that the system runs at a higher efficiency, thereby reducing energy loss.

[0043] Harmonic suppression measures in traditional solutions often only target certain specific frequency ranges, and fail to consider the harmonic control issues of the system under different loads and operating conditions from a global perspective. Some solutions may only rely on improvements in hardware topology without optimizing for specific working environments. The present invention achieves high-frequency current harmonic suppression over a wider spectrum through carrier phase shifting technology and the selection of voltage modulation ratios. It can dynamically select the most appropriate modulation strategy based on the real-time operating conditions of the motor, and can flexibly adapt to changes under different loads and working conditions to achieve a more comprehensive harmonic suppression effect.

[0044] The present invention is applied to the field of high-frequency current harmonic suppression. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 This is a schematic diagram of a dual-winding permanent magnet synchronous motor control system according to the first embodiment;

[0046] Figure 2 This is the isolated staggered parallel topological structure diagram described in the first embodiment;

[0047] Figure 3 The switching sequence diagram of the SVPWM and DSPWM modulation strategies of the I sector described in the eleventh embodiment;

[0048] Figure 4 This is a schematic diagram of sector division according to the eleventh embodiment;

[0049] Figure 5 It is a schematic diagram of theoretical calculation and simulation results of harmonic voltage amplitude under DSPWM modulation according to the eleventh embodiment;

[0050] Figure 6 A schematic diagram of theoretical calculation and simulation results of harmonic voltage amplitude under SVPWM modulation according to the eleventh embodiment;

[0051] Figure 7 is the high-order harmonic current distortion value under the SVPWM modulation and DSPWM modulation described in the eleventh embodiment;

[0052] Figure 8 This is a schematic diagram of a circuit network of a motor system according to Embodiment 11;

[0053] Fig. 9 is a schematic diagram of minimum high-order current harmonic content under different modulation strategies described in Implementation 11;

[0054] Fig.10 This is a schematic diagram of the current waveform before inhibition according to the eleventh embodiment;

[0055] Fig.11 This is a schematic diagram of FFT analysis of the uninhibited front current according to the eleventh embodiment;

[0056] Fig.12 This is a schematic diagram of the current waveform after inhibition according to the eleventh embodiment;

[0057] Fig.13 This is a schematic diagram of FFT analysis of the current waveform after inhibition described in Implementation Example 11. DETAILED DESCRIPTION

[0058] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments.

[0059] Implementation method 1, see Figure 1 and Figure 2 This embodiment describes a method for suppressing high-frequency current harmonics of a modular dual-winding permanent magnet synchronous motor, the method comprising:

[0060] S1: construct a dual-winding permanent magnet synchronous motor control system, in which the power supply topology is an isolated interleaved parallel topology, including two sets of three-phase inverters and three common-mode inductors;

[0061] S2: Obtain the motor rotor position angle and speed signal according to the rotary transformer, calculate the difference between the speed setting and the speed feedback signal as the input of the speed loop PI controller, and obtain the current setting values ​​of the two sets of windings d-axis and q-axis;

[0062] S3: Obtain the 6-phase current values ​​through the current sensor, obtain the actual values ​​of the d-axis and q-axis currents of the two sets of windings according to the coordinate transformation matrix, and solve the difference between the given value and the actual value of the d-axis and q-axis currents as the input of the current loop PI controller;

[0063] S4: Perform coordinate transformation on the output of the current loop PI controller to obtain a given voltage value in the α-β coordinate system, and calculate the voltage modulation ratio according to the control system;

[0064] S5: Select an appropriate voltage modulation strategy and carrier phase shift angle according to the voltage modulation ratio M to suppress high-frequency current harmonics of the dual-winding permanent magnet synchronous motor.

[0065] In the traditional isolated staggered parallel topology, multiple inverters are used to suppress high-frequency current harmonics, which usually leads to a significant increase in hardware costs and requires complex control systems for coordination. The introduction of multiple inverters will increase hardware costs and increase the complexity of system debugging, maintenance, and troubleshooting. In this embodiment, a dual-winding permanent magnet synchronous motor is used in combination with a power supply topology of two sets of three-phase inverters, and an optimized control strategy is used to suppress high-frequency harmonics, thereby avoiding the use of too many inverters, effectively controlling the complexity of the overall system, and relatively reducing hardware costs.

[0066] In the traditional method, although harmonics are reduced by adding inverters, the efficiency of energy conversion is not particularly considered, which may lead to a decrease in the overall energy conversion efficiency of the system due to factors such as an increase in the number of hardware and increased control difficulty. In this embodiment, by optimizing the control system and the voltage modulation strategy, it is possible to maintain a high energy conversion efficiency while reducing harmonics. For example, the current control of the motor is optimized through an accurate current loop PI controller and a coordinate transformation matrix to ensure that the system runs at a higher efficiency, thereby reducing energy losses.

[0067] Harmonic suppression measures in traditional solutions often only target certain specific frequency ranges, and fail to consider the harmonic control issues of the system under different loads and operating conditions from a global perspective. Some solutions may only rely on improvements in hardware topology without optimizing for specific working environments. In this implementation, high-frequency current harmonic suppression over a wider spectrum is achieved through carrier phase shifting technology and the selection of voltage modulation ratios. The most appropriate modulation strategy can be dynamically selected based on the real-time operating conditions of the motor, and it can flexibly adapt to changes under different loads and working conditions to achieve a more comprehensive harmonic suppression effect.

[0068] The method proposed in this embodiment can reduce the number of hardware inverters by adopting a modular design and an optimized dual-winding permanent magnet synchronous motor power supply topology, and at the same time suppress harmonics through a relatively simple and efficient control system, thereby reducing the cost and complexity of the overall system.

[0069] In this embodiment, the current is precisely adjusted through an accurate current loop PI controller and coordinate transformation technology, ensuring that the motor can maintain a high energy conversion efficiency at different working points, thereby avoiding energy loss caused by increased hardware redundancy or inaccurate control.

[0070] In this implementation, carrier phase shift technology and adaptive adjustment of the voltage modulation ratio are used to flexibly adjust the suppression effect of high-frequency current harmonics to meet the needs of different loads and operating conditions. This enables the system to provide stable and efficient harmonic control in a wider range of application scenarios.

[0071] Furthermore, since the dual winding design and voltage modulation strategy adopted in this embodiment can optimize the control under different motor operating conditions, the sensitivity of the system to external disturbances and load changes is reduced, thereby improving the robustness of the system. The design of multiple inverters and current control loops can also ensure that the entire system can still maintain high stability and reliability when a problem occurs in a certain component.

[0072] Embodiment 2: This embodiment further limits the method for suppressing high-frequency current harmonics of a modular dual-winding permanent magnet synchronous motor described in embodiment 1. Step S4 includes:

[0073]

[0074] Where M is the voltage modulation ratio, V dc is the bus voltage, u d1 is the d-axis current inner loop output, u q1 It is the q-axis current inner loop output.

[0075] Implementation method three: This implementation method further limits the high-frequency current harmonic suppression method of a modular dual-winding permanent magnet synchronous motor described in implementation method one. The voltage modulation strategy in step S5 includes a space vector voltage modulation strategy SVPWM and a dual switch sequence voltage modulation strategy DSPWM.

[0076] The combination of the two modulation strategies in this embodiment makes the motor control system highly flexible and can automatically select the optimal voltage modulation method according to different loads, speeds and working conditions, so as to adapt to various working environments and requirements under different working conditions. In scenarios with large load changes, the use of SVPWM and DSPWM strategies can automatically adjust the waveforms of voltage and current, effectively avoiding the increase of high-frequency harmonics caused by load fluctuations.

[0077] Embodiment 4: This embodiment further limits the method for suppressing high-frequency current harmonics of a modular dual-winding permanent magnet synchronous motor described in embodiment 3. The matching principle between the voltage modulation ratio M, the voltage modulation strategy and the carrier phase shift angle is:

[0078] Calculate the relationship between high-frequency voltage harmonic content and voltage modulation ratio M;

[0079] Calculate the relationship between current harmonic content and voltage modulation ratio M;

[0080] Harmonic analysis is performed using an isolated interleaved parallel topology based on two three-phase inverters;

[0081] According to the high-frequency current harmonic distribution characteristics when using space vector voltage modulation strategy SVPWM and dual switch sequence voltage modulation strategy DSPWM, the carrier phase shift angle and voltage modulation strategy are selected.

[0082] In this embodiment, by calculating the relationship between the high-frequency voltage harmonic content and the voltage modulation ratio (M), and the relationship between the current harmonic content and the voltage modulation ratio (M), the distribution and amplitude of the harmonics can be accurately evaluated. In this way, the parameters can be optimized in a targeted manner, thereby effectively reducing high-frequency harmonics. Combined with the harmonic content analysis, by comparing the high-frequency current harmonic distribution characteristics under different modulation strategies (such as the space vector voltage modulation strategy SVPWM and the dual switch sequence voltage modulation strategy DSPWM), the appropriate modulation strategy and carrier phase shift angle are selected to further reduce the harmonics.

[0083] The isolated interleaved parallel topology using two three-phase inverters can reduce the generation of harmonics through current distribution and timing control. An important advantage of the interleaved topology is that the current waveforms between the inverters are interleaved, which effectively balances the current waveforms and reduces the impact of high-frequency harmonics. This topology not only reduces the harmonic interference of the motor drive system, but also improves the reliability and efficiency of the system because it achieves smooth and balanced inverter output.

[0084] The use of precise voltage modulation ratio and carrier phase shift angle configuration can actively suppress the generation of high-frequency harmonics. This modulation strategy precisely controls the current waveform of the motor to keep the amplitude of the harmonics at the lowest level in the system, thereby reducing electromagnetic interference (EMI) and energy loss during motor operation. Furthermore, according to the characteristics of different modulation strategies (such as SVPWM and DSPWM), the carrier phase shift angle can be flexibly selected to effectively avoid harmonic overlap by adjusting the carrier frequency phase relationship, making the output waveform closer to a sine wave and reducing the negative impact of harmonics on motor performance.

[0085] In this embodiment, by reducing the content of high-frequency current harmonics, the additional loss of the motor can be reduced, the heating of the motor windings can be alleviated, and the efficiency of the motor can be improved.

[0086] Embodiment 5: This embodiment further limits the method for suppressing high-frequency current harmonics of a modular dual-winding permanent magnet synchronous motor described in Embodiment 4. The relationship between the high-frequency voltage harmonic content and the voltage modulation ratio M is calculated, including:

[0087]

[0088] Among them, A mnRepresents the real part of the harmonic voltage amplitude, B mn It represents the imaginary part of the harmonic voltage amplitude, j represents the imaginary unit, m represents the harmonic order of the carrier, n represents the harmonic order of the fundamental wave, i represents the sector number, y represents the imaginary unit, and s (i) represents the lower limit of the interval of the i-th sector, y e (i) represents the upper limit of the interval of the i-th sector; x r (i) represents the carrier phase corresponding to the rising edge of the voltage waveform in the i-th sector, x f (i) represents the carrier phase corresponding to the falling edge of the voltage waveform in the i-th sector, V dc Indicates the bus voltage.

[0089] Embodiment 6: This embodiment further limits the method for suppressing high-frequency current harmonics of a modular dual-winding permanent magnet synchronous motor described in embodiment 5. The relationship between the calculated current harmonic content and the voltage modulation ratio M includes:

[0090]

[0091] Among them, I m-rms Indicates the harmonic current distortion value of m times the switching frequency, L is the motor phase inductance; h = 0, 1, 2, 3..., f c represents the carrier frequency, and f0 represents the fundamental frequency of the motor.

[0092] Embodiment 7: This embodiment further limits the method for suppressing high-frequency current harmonics of a modular dual-winding permanent magnet synchronous motor described in Embodiment 4. The method adopts an isolated interleaved parallel topology based on two three-phase inverters to perform harmonic analysis, including:

[0093] Get the motor phase voltage u represented by the inverter output voltage ao1 :

[0094]

[0095] Where, Z0(ω0) represents the coupled inductor impedance; Z A1 (ω0) represents the impedance of the A1 phase winding; u ag1 、u bg1 and u cg1 represents the output voltage of the first three-phase inverter, u ag2 、u bg2 and u cg2 Indicates the three-phase output voltage of the second three-phase inverter;

[0096] The output voltage of each bridge arm of the inverter is calculated according to the double Fourier decomposition formula;

[0097] Analyze the influencing factors of harmonic voltage content based on the output voltage of each bridge arm of the inverter.

[0098] In this embodiment, through the double Fourier decomposition formula, the spectrum of the inverter output voltage can be accurately analyzed, and then the content of voltage harmonics can be identified and quantified. This method can not only identify high-frequency harmonic components, but also obtain the source and influencing factors of harmonics, which is crucial for designing more effective harmonic suppression strategies, helps to achieve precise current regulation, and thus reduces the losses and motor vibrations caused by harmonics. The interleaved parallel topology of two three-phase inverters is adopted, so that the working current phases of the two inverters are staggered. In this way, the harmonic interference generated by the simultaneous operation of the two inverters can be effectively reduced. The interleaved parallel topology can make the harmonic phases between the two inverters cancel each other out, thus effectively reducing the harmonic current in the motor windings. This topology improves the harmonic suppression ability of the system and improves the running smoothness and efficiency of the motor.

[0099] During the operation of a permanent magnet synchronous motor, especially under high-speed or high-load conditions, high-frequency harmonic currents may cause motor heating, increased noise, and reduced efficiency. Through this method, the influence of high-frequency current harmonics can be accurately identified and reduced. Combining the interleaved parallel topology and the precise control of the inverter output voltage can suppress these high-frequency current harmonics at the source, thus improving the reliability and stability of the system.

[0100] Furthermore, through the harmonic analysis of the output voltage of each bridge arm of the inverter, the working mode of the inverter can be optimized to make it operate efficiently under the condition of generating lower harmonics. Effective harmonic suppression can not only reduce the energy loss caused by harmonics, but also reduce the electromagnetic interference inside and outside the motor, thereby improving the energy efficiency and stability of the entire drive system.

[0101] Embodiment 8: This embodiment further limits a method for suppressing high-frequency current harmonics of a modular dual-winding permanent magnet synchronous motor described in Embodiment 4. The specific matching principle between the hybrid modulation strategy and the voltage modulation ratio M is as follows:

[0102] When M < 0.41, the space vector voltage modulation strategy SVPWM is adopted and the carrier phase shift angle is set to π / 2;

[0103] When 0.41 < M < 0.84, the dual-switch sequence voltage modulation strategy DSPWM is adopted and the carrier phase shift angle is set to π;

[0104] When 0.84 < M < 0.98, the space vector voltage modulation strategy SVPWM is adopted and the carrier phase shift angle is set to π;

[0105] When M > 0.98, the space vector voltage modulation strategy DSPWM is adopted and the carrier phase shift angle is set to π / 2.

[0106] Embodiment 9. A computer device described in this embodiment includes a memory and a processor, wherein a computer program is stored in the memory. When the processor runs the computer program stored in the memory, the processor executes a method for suppressing high-frequency current harmonics of a modular dual-winding permanent magnet synchronous motor described in any one of embodiments 1 to 7.

[0107] Embodiment 10. A computer-readable storage medium described in this embodiment stores a computer program, and when the computer program is executed by a processor, the steps of a method for suppressing high-frequency current harmonics of a modular dual-winding permanent magnet synchronous motor as described in any one of embodiments 1 to 7 are executed.

[0108] Implementation Method 11: See Figures 3 to 12 This embodiment is a specific example of a method for suppressing high-frequency current harmonics in a modular dual-winding permanent magnet synchronous motor described in the first embodiment, and is also used to explain the second to eighth embodiments, specifically:

[0109] Step 1: According to Figure 1 The control system block diagram shown in the figure builds a dual-winding permanent magnet synchronous motor control system. Its power supply topology is an isolated staggered parallel topology, which includes two sets of three-phase inverters and three common-mode inductors. The topology structure is as follows Figure 2 As shown;

[0110] Step 2: Obtain the motor rotor position angle and speed signal according to the rotary transformer, calculate the difference between the speed setting and the speed feedback signal, and then use the difference as the input of the speed loop PI controller to obtain the current setting values ​​of the two sets of windings d and q axes;

[0111] Step 3: Obtain the 6-phase current values ​​through the current sensor, and then use the coordinate transformation matrix to obtain the actual values ​​of the d-axis and q-axis currents of the two sets of windings. Then, solve the difference between the given value and the actual value of the d-axis and q-axis currents and use it as the input of the current loop PI controller;

[0112] Step 4: Transform the output of the current loop PI controller to obtain the given voltage value in the α-β coordinate system, according to the bus voltage V in the control system dc , current inner loop output u d1 and u q1 Calculate the voltage modulation ratio M; the calculation formula is:

[0113]

[0114] Step 5: Select a suitable voltage modulation strategy and carrier phase shift angle τ according to the voltage modulation ratio M. The voltage modulation strategy includes space vector voltage modulation strategy (SVPWM) and dual switch sequence voltage modulation strategy (DSPWM). The switch switching sequences of the two voltage modulation strategies are as follows: Figure 3 shown.

[0115] The calculation process of the matching principle between the voltage modulation ratio M, the carrier phase shift angle τ and the voltage modulation strategy in step 5 is as follows:

[0116] (1): Calculate the relationship between high-frequency voltage harmonic content and voltage modulation ratio M

[0117] Theoretically calculate the content of harmonic voltage of each multiple switching frequency and its nearby frequencies under different M. Taking the dual-switch sequence voltage modulation strategy as an example, the fundamental voltage and each harmonic voltage component in the modulated voltage can be calculated with the help of the following formula:

[0118]

[0119] In the formula, A mn and B mn Respectively represent the real and imaginary parts of the harmonic voltage amplitude; m represents the harmonic order of the carrier; n represents the harmonic order of the fundamental wave; i represents the number of sectors; y s (i) and y e (i) represents the lower and upper limits of the interval of the i-th sector respectively; x r (i) and x f (i) represents the carrier phase corresponding to the rising edge and falling edge of the voltage waveform in the i-th sector.

[0120] When the dual-switch sequence modulation strategy is adopted, the number of switches in sectors II and V is 2, so the internal integral interval of the formula in sectors II and V has two segments; the number of switches in sectors III and IV is 0, so the integral result of the formula in sectors III and IV is 0. The sector division is as follows: Figure 4 By calculating the intersection of the average voltage in the sector and the carrier, the integration interval of each sector can be obtained, as shown in the following table:

[0121] Substituting the integral interval in the table into the high-frequency voltage harmonic component calculation formula, the amplitude of each high-frequency harmonic voltage under different voltage modulation ratios can be calculated. The calculation formula is:

[0122]

[0123] In V dc =200V, f c =20000π, f0=500π, the frequency f is obtained by theoretical calculation using the above formula c+f0 and 2f c The curve of the harmonic voltage amplitude of +f0 changing with the M value is as follows Figure 5 As shown. The triangle in the figure represents the simulation result obtained by the simulation software under the corresponding M. It can be seen from the figure that the theoretical calculation result of the harmonic voltage amplitude is basically the same as the simulation result. Therefore, the harmonic voltage amplitude of each frequency can be calculated more accurately with the help of the above formula.

[0124] Similarly, it can be calculated that when SVPWM voltage modulation is used, V dc =200V, f c =20000π, f0=500π, the frequency is f c +f0 and 2f c The curve of the harmonic voltage amplitude of +f0 changing with the M value is as follows Figure 6 shown.

[0125] (2): Calculate the relationship between current harmonic content and voltage modulation ratio M

[0126] In order to more clearly see what voltage modulation strategy is adopted under different modulation ratios M and what size of carrier phase shift angle is set to make the high-order harmonic current content in the system smaller, the present embodiment defines the phase winding high-order current harmonic distortion under high-order harmonic voltage excitation, and the calculation formula is:

[0127]

[0128] Where, L is the motor phase inductance; h = 0, 1, 2, 3…

[0129] The above formula is used to calculate the distribution of high-frequency current harmonic content near 1 times the switching frequency and near 2 times the switching frequency when using SVPWM and DSPWM respectively. The calculation results are as follows: Figure 7 In the present invention, the calculation results are standardized, and the reference value is V dc / L.

[0130] (3): System harmonic analysis using an isolated interleaved parallel topology based on two three-phase inverters

[0131] Motor system network such as Figure 8 Taking the A1 phase winding as an example, according to the motor system network diagram, the motor phase voltage u represented by the inverter output voltage can be obtained. ao1 :

[0132]

[0133] Where Z0(ω0) represents the coupled inductor impedance; Z A1 (ω0) represents the impedance of the A1 phase winding; u ag1 、ubg1 and u cg1 They represent the three-phase bridge arm output voltages of the first three-phase inverter; u ag2 、u bg2 and u cg2 They respectively represent the three-phase output voltages of the second three-phase inverter.

[0134] According to the double Fourier decomposition formula, the specific expression of the output voltage of each bridge arm of the inverter can be calculated, taking the A1 phase bridge arm as an example:

[0135]

[0136] In the formula, A 1-00 =V dc , a is the modulation coefficient, ω0 is the motor fundamental angular frequency, ω c is the carrier angular frequency.

[0137] Assume that the initial phase angle of the carrier in the first set of inverters is 0, the initial phase angle of the carrier in the second set of inverters is τ, and the carrier phase difference between the two sets of three-phase inverters is τ.

[0138] When the carrier phase difference is τ, the phase voltage of the A1 phase winding can be further derived:

[0139]

[0140] When n=±3p,p=0,1,2,3L,the corresponding A1 phase voltage u ao1 When m≠0, the harmonic voltage content is 0; when n≠±3p, p=0,1,2,3L, the A1 phase voltage can be simplified to

[0141]

[0142] From the above formula, it can be seen that the harmonic voltage content in the A1 phase voltage is not only related to the carrier phase difference τ, but also to the impedance value of the coupled inductor and the motor impedance value. By reasonably designing the initial carrier phase angle τ of the second inverter, the high-order voltage harmonics in the A1 phase voltage can be suppressed.

[0143] In order to suppress high-frequency current harmonics near 1 times the switching frequency, the carrier phase shift angle τ can be changed so that Z0(ω0)(3+3cos(τ))+Z A1 (ω0) value is the smallest, and 3Z0(ω0)sin(τ)=0, then τ=π can be solved; in order to suppress the high-order current harmonics near 2 times the switching frequency, the carrier phase shift angle τ can be changed to make Z0(ω0)(3+3cos(2τ))+Z A1(ω0) has the minimum value, and at the same time makes 3Z0(ω0)sin(mτ) = 0. At this time, τ = 0.5π can be solved.

[0144] (4): Optimal matching of voltage modulation ratio, carrier phase-shift angle and voltage modulation strategy

[0145] When an isolated interleaved parallel topology is used to supply power to a dual-winding permanent magnet synchronous motor, by reasonably setting the phase-shift angle between the carriers of the two inverters, high-order current harmonics of specific orders can be suppressed. The high-order harmonic components of the motor phase current are mainly concentrated near the switching frequency and its multiple frequencies. When the carrier phase-shift angle is set to π, the current harmonics near the 1-fold switching frequency can be suppressed; when the carrier phase-shift angle is set to π / 2, the current harmonics near the 2-fold switching frequency can be suppressed. For the SVPWM voltage modulation strategy and the DSPWM voltage modulation strategy, as M changes, the high-order harmonic voltage contents at different frequencies will also change, which will in turn cause the high-order current harmonic contents at different frequencies to change. When the SVPWM voltage modulation strategy is adopted, when the value of M is small, the current harmonic content near the 2-fold switching frequency is large; when the value of M is large, the current harmonic content near the 1-fold switching frequency is small. Therefore, when M changes, the carrier phase-shift angle needs to be reasonably set to ensure that the high-order harmonic components in the current are always small. At the same time, when different voltage modulation strategies are adopted, the distribution of the current harmonic contents at each frequency is also different. Since only two sets of three-phase inverters are used in the present invention, changing the carrier phase-shift angle can only suppress the current harmonics near the 1-fold switching frequency or the current harmonics near the 2-fold switching frequency. In order to suppress high-frequency current harmonics as much as possible, it is necessary to reasonably select the size of the carrier phase-shift angle and the voltage modulation strategy according to the high-frequency current harmonic distribution characteristics when using SVPWM and DSPWM, so as to minimize the high-frequency current harmonic content under different voltage modulation ratios M.

[0146] According to the calculation results of (2), the optimal voltage modulation strategy and the size of the carrier phase-shift angle under different voltage modulation ratios M can be obtained. Fig. 9 Shows the minimum high-order current harmonic content of the system under different voltage modulation ratios M when using SVPWM, DSPWM and hybrid modulation. It can be seen from the figure that when using hybrid modulation, the advantages of the two voltage modulation strategies can be fully utilized, so as to ensure the minimum high-order current harmonic content in the system under different voltage modulation ratios M. The specific matching principle of the hybrid modulation strategy and the voltage modulation ratio M is: when M < 0.41, adopt the SVPWM modulation strategy and set the carrier phase-shift angle to π / 2; when 0.41 < M < 0.84, adopt the DSPWM modulation strategy and set the carrier phase-shift angle to π; when 0.84 < M < 0.98, adopt the SVPWM modulation strategy and set the carrier phase-shift angle to π; when M > 0.98, adopt the DSPWM modulation strategy and set the carrier phase-shift angle to π / 2.

[0147] The calculation results are stored in a microprocessor, and in this example, a signal processing chip TMS320F28377D produced by TI is used.

[0148] Step 6: After selecting the appropriate voltage modulation strategy and carrier phase shift angle according to the voltage modulation ratio M, the PWM wave logic in the main control chip needs to be modified in real time (select SVPWM or DSPWM). At the same time, the initial phase angle of the second carrier needs to be changed in real time. In this example, the TBPHS register of the PWM unit of the main control chip needs to be changed.

[0149] The effectiveness of the present invention is verified by experiments as follows:

[0150] The method was verified on a dual-winding permanent magnet synchronous motor drag test platform. The motor's direct-axis inductance is 0.36mH, the quadrature-axis inductance is 0.56mH, the stator resistance is 0.034Ω, the bus voltage is set to 100V, the switching frequency is 10kHz, the speed is set to 300r / min, and the torque is 20. Under this condition, the voltage modulation ratio is 0.4. According to the calculation results of step 2, the SVPWM voltage modulation strategy should be selected and the carrier phase shift angle should be set to π / 2. The experimental results are shown in Fig.10 , 11 , 12 and 13. From the results, when the method of the present invention is not used, the harmonic content of the current near one times the switching frequency is less than the harmonic current near two times the switching frequency when SVPWM voltage modulation is used. Due to the use of two three-phase inverter topologies, the current harmonics near one times the switching frequency and near two times the switching frequency cannot be suppressed at the same time. Under this working condition, the current near two times the switching frequency is suppressed to ensure that the high-frequency current harmonic content of the system is minimized.

[0151] From the above content, it can be seen that the present invention uses only two three-phase inverters to achieve the suppression of high-frequency harmonic currents near 1 times the switching frequency or near 2 times the switching frequency under different voltage modulation ratios M, ensuring that the high-frequency current harmonic content is small under different voltage modulation ratios;

[0152] Since the present invention only uses two three-phase inverters, the system cost is relatively low;

[0153] The present invention makes full use of the distribution characteristics of high-frequency current harmonics when adopting SVPWM and DSPWM modulation strategies, and realizes smaller high-frequency current harmonics under different voltage modulation ratios M through mixed modulation.

[0154] Those skilled in the art will appreciate that the embodiments of the present disclosure may be provided as methods, systems or computer program products. Therefore, the present disclosure may take the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware. Moreover, the present disclosure may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0155] The present disclosure is described with reference to flowcharts and / or block diagrams of methods, devices (systems) and computer program products according to embodiments of the present disclosure. It should be understood that each process and / or block in the flowchart and / or block diagram and the combination of processes and / or blocks in the flowchart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific way, so that the instructions stored in the computer-readable memory produce a product including an instruction device, which implements the functions specified in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0156] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0157] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure rather than to limit its protection scope. Although the present disclosure has been described in detail with reference to the above embodiments, ordinary technicians in the relevant field should understand that after reading the present disclosure, those skilled in the art can still make various changes, modifications or equivalent substitutions to the specific implementation methods of the invention, but these changes, modifications or equivalent substitutions are all within the protection scope of the disclosed claims to be approved.

Claims

1. A method for suppressing high-frequency current harmonics of a modular dual-winding permanent magnet synchronous motor, characterized in that: The method includes: S1: Construct a dual-winding permanent magnet synchronous motor control system. The power supply topology in the dual-winding permanent magnet synchronous motor control system is an isolated interleaved parallel topology, including two sets of three-phase inverters and three common-mode inductors; S2: Obtain the motor rotor position angle and speed signal according to the resolver, calculate the difference between the speed reference and the speed feedback signal as the input of the speed-loop PI controller, and obtain the d-axis and q-axis current reference values of the two windings; S3: Obtain the 6-phase current value through the current sensor, obtain the actual values of the d-axis and q-axis currents of the two windings according to the coordinate transformation matrix, and solve the difference between the d-axis and q-axis current reference values and the actual values as the input of the current-loop PI controller; S4: Perform coordinate transformation on the output of the current-loop PI controller to obtain the reference voltage value in the α-β coordinate system, and calculate the voltage modulation ratio M according to the control system; S5: Select a suitable voltage modulation strategy and carrier phase-shift angle according to the voltage modulation ratio M to suppress the high-frequency current harmonics of the dual-winding permanent magnet synchronous motor.

2. A method for suppressing high-frequency current harmonics of a modular dual-winding permanent magnet synchronous motor according to claim 1, characterized in that: Step S4 includes: Where M is the voltage modulation ratio, V dc is the bus voltage, u d1 is the d-axis current inner loop output, u q1 It is the q-axis current inner loop output.

3. A method for suppressing high-frequency current harmonics of a modular dual-winding permanent magnet synchronous motor according to claim 1, characterized in that: The voltage modulation strategies in step S5 include space vector pulse width modulation strategy SVPWM and dual-switching sequence pulse width modulation strategy DSPWM.

4. A method for suppressing high-frequency current harmonics of a modular dual-winding permanent magnet synchronous motor according to claim 3, characterized in that: The matching principle among the voltage modulation ratio M, the voltage modulation strategy, and the carrier phase-shift angle is: Calculate the relationship between the high-frequency voltage harmonic content and the voltage modulation ratio M; Calculate the relationship between the current harmonic content and the voltage modulation ratio M; Adopt an isolated interleaved parallel topology based on two three-phase inverters for harmonic analysis; According to the high-frequency current harmonic distribution characteristics when adopting the space vector pulse width modulation strategy SVPWM and the dual-switching sequence pulse width modulation strategy DSPWM, select the magnitude of the carrier phase-shift angle and the voltage modulation strategy.

5. A method for suppressing high-frequency current harmonics of a modular dual-winding permanent magnet synchronous motor according to claim 4, characterized in that: The calculation of the relationship between the high-frequency voltage harmonic content and the voltage modulation ratio M includes: Among them, A mn Represents the real part of the harmonic voltage amplitude, B mn It represents the imaginary part of the harmonic voltage amplitude, j represents the imaginary unit, m represents the harmonic order of the carrier, n represents the harmonic order of the fundamental wave, i represents the sector number, y represents the imaginary unit, and s (i) represents the lower limit of the interval of the i-th sector, y e (i) represents the upper limit of the interval of the i-th sector; x r (i) represents the carrier phase corresponding to the rising edge of the voltage waveform in the i-th sector, x f (i) represents the carrier phase corresponding to the falling edge of the voltage waveform in the i-th sector, V dc Indicates the bus voltage.

6. A method for suppressing high-frequency current harmonics of a modular dual-winding permanent magnet synchronous motor according to claim 5, characterized in that: The calculation of the relationship between the current harmonic content and the voltage modulation ratio M includes; Among them, I m-rms It represents the harmonic distortion value of the harmonic current of the m-fold switching frequency, L is the motor phase inductance; h=0,1,2,3…, f c represents the carrier frequency, and f0 represents the fundamental frequency of the motor.

7. A method for suppressing high-frequency current harmonics of a modular dual-winding permanent magnet synchronous motor according to claim 4, characterized in that: The adoption of an isolated interleaved parallel topology based on two three-phase inverters for harmonic analysis includes: Get the motor phase voltage u represented by the inverter output voltage ao1 : Where, Z0(ω0) represents the coupled inductor impedance; Z A1 (ω0) represents the impedance of the A1 phase winding; u ag1 、u bg1 and u cg1 represents the output voltage of the first three-phase inverter, u ag2 、u bg2 and u cg2 Indicates the three-phase output voltage of the second three-phase inverter; Calculate the output voltage of each bridge arm of the inverter according to the double Fourier decomposition formula; Analyze the influencing factors of the harmonic voltage content according to the output voltage of each bridge arm of the inverter.

8. A method for suppressing high-frequency current harmonics of a modular dual-winding permanent magnet synchronous motor according to claim 4, characterized in that: The specific matching principle between the hybrid modulation strategy and the voltage modulation ratio M is: When M < 0.41, adopt the space vector pulse width modulation strategy SVPWM and set the carrier phase-shift angle to π / 2; When 0.41 < M < 0.84, adopt the dual-switching sequence pulse width modulation strategy DSPWM and set the carrier phase-shift angle to π; When 0.84 < M < 0.98, adopt the space vector pulse width modulation strategy SVPWM and set the carrier phase-shift angle to π; When M > 0.98, adopt the space vector pulse width modulation strategy DSPWM and set the carrier phase-shift angle to π / 2.

9. A computer device, characterized in that: It includes a memory and a processor. A computer program is stored in the memory. When the processor runs the computer program stored in the memory, the processor executes a method for suppressing high-frequency current harmonics of a modular dual-winding permanent magnet synchronous motor according to any one of claims 1-7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, which, when executed by a processor, executes the steps of a method for suppressing high-frequency current harmonics of a modular dual-winding permanent magnet synchronous motor as described in any one of claims 1-7.

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