Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, and the method comprises the steps: providing a device substrate, and forming a thin film bulk acoustic wave device and a first metal layer on the device substrate; providing a cap substrate having opposite first and second surfaces; forming an inner groove in the first surface; forming a second metal layer; bonding the device substrate and the cap substrate; wherein before the second metal layer is formed, a first passive device is formed in the inner groove; and / or, after bonding, a second passive device is formed on the second surface, and when the first passive device is formed in the inner groove, the second passive device is electrically connected with the first passive device. The passive device is formed in the cap substrate, the device substrate comprising the film bulk acoustic wave device is bonded with the cap substrate, and impedance matching is directly performed at the film bulk acoustic wave device end, so that the performance of the film bulk acoustic wave device is improved, and the bonded semiconductor device is relatively small in size, relatively high in integration level, simple in process and relatively low in cost.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Film bulk acoustic wave filters have the characteristics of low power loss, good out-of-band suppression, high Q value, and high rectangular coefficient, and are gradually becoming the mainstream of the filter market. Film Bulk Acoustic Resonator (FBAR) chips are generally used with passive components (inductors and capacitors) to improve out-of-band suppression.

[0003] In related technologies, filters and passive components (capacitors and inductors) are typically fixed to a package substrate and electrically connected via wiring. Alternatively, the passive components are fabricated as separate components and then connected to the filter. The former results in larger chip sizes and lower integration, while the latter is complex, difficult, and expensive to manufacture. Summary of the Invention

[0004] The Summary of the Invention introduces a series of simplified concepts that will be further described in the Detailed Description of the Invention. The Summary of the Invention of this application is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0005] In order to solve the existing problems, the present application provides a method for manufacturing a semiconductor device, which comprises:

[0006] Providing a device substrate, on which a thin film bulk acoustic wave device and a first metal layer are formed;

[0007] providing a capping substrate having opposing first and second surfaces;

[0008] forming an inner groove on one side of the first surface of the cap substrate;

[0009] forming a second metal layer covering at least the end surface of the sidewall of the inner groove;

[0010] bonding the device substrate and the cap substrate via the first metal layer and the second metal layer;

[0011] Wherein, before forming the second metal layer, the method further includes: forming a first passive component in the inner groove; and / or,

[0012] After the bonding, a second passive component is formed on the second surface of the cap substrate. When the first passive component is formed in the inner groove, the second passive component is electrically connected to the first passive component.

[0013] In one embodiment, the first passive component is a capacitor, comprising a lower electrode, a capacitor dielectric layer, and an upper electrode, wherein the capacitor dielectric layer is located between the lower electrode and the upper electrode, the lower electrode contacts the bottom surface of the inner groove, and the upper electrode faces away from the lower electrode. After forming the first passive component in the inner groove and before forming the second metal layer, the method includes:

[0014] forming a first insulating layer on the first passive component;

[0015] forming a first opening and a second opening in the first insulating layer, wherein the first opening exposes a portion of the lower electrode, and the second opening exposes a portion of the upper electrode;

[0016] The second metal layer also covers the first passive component and fills the first opening and the second opening.

[0017] In one embodiment, forming a second passive device on the second surface of the cap substrate includes:

[0018] forming a first redistribution layer on the second surface;

[0019] forming a first dielectric layer to cover the first redistribution layer and the second surface, and forming a first contact hole in the first dielectric layer, wherein the first contact hole exposes a portion of the first redistribution layer;

[0020] forming a conductive material to fill the first contact hole to form a first conductive plug and also to cover a portion of the surface of the first dielectric layer to form a second redistribution layer;

[0021] A second dielectric layer is formed to cover the second redistribution layer and the first dielectric layer, and a second contact hole is formed in the second dielectric layer, wherein the second contact hole exposes a portion of the second redistribution layer. The first redistribution layer and the second redistribution layer constitute a second passive device.

[0022] In one embodiment, when the first passive component is formed in the inner groove, a second conductive plug is further formed in the cap substrate, and the second conductive plug is used to electrically connect the second passive component and the first passive component.

[0023] In one embodiment, when the first passive device is formed in the inner groove, the method further includes: forming a through hole in the cap substrate before forming the first redistribution layer, the through hole passing through the cap substrate and exposing a portion of the second metal layer, wherein when the first redistribution layer is formed on the second surface, the first redistribution layer also covers the side walls and bottom of the through hole, so that the second passive device is electrically connected to the first passive device through the second metal layer.

[0024] In another embodiment of the present application, a semiconductor device is provided, comprising:

[0025] a device substrate on which a thin film bulk acoustic wave device and a first metal layer located outside the thin film bulk acoustic wave device are disposed;

[0026] The cap substrate has a first surface and a second surface opposite to each other, and an inner groove is formed on one side of the first surface;

[0027] a second metal layer, covering at least the end surface of the side wall of the inner groove;

[0028] A first passive component is located in the inner groove; and / or

[0029] a second passive component located on the second surface, wherein when the first passive component is formed in the inner groove, the second passive component is electrically connected to the first passive component;

[0030] The side of the cap substrate where the inner groove is formed is opposite to the side of the device substrate where the thin film bulk acoustic wave device is formed, and is bonded to the second metal layer through the first metal layer.

[0031] In one embodiment, the first passive component includes a lower electrode, a capacitor dielectric layer, and an upper electrode that are stacked, and the lower electrode and the upper electrode are electrically connected to different second metal layers, respectively.

[0032] In one embodiment, a first cavity having an opening is formed on one side of the device substrate;

[0033] The thin film bulk acoustic wave device comprises:

[0034] a bottom electrode covering the opening of the first cavity;

[0035] A first conductive structure and a second conductive structure are respectively located on both sides of the bottom electrode;

[0036] a piezoelectric layer located on the device substrate and covering the bottom electrode, the first conductive structure and the second conductive structure, wherein the first metal layer penetrates the piezoelectric layer and is electrically connected to the bottom electrode through the first conductive structure;

[0037] A top electrode is located on the piezoelectric layer, and the first metal layer is electrically connected to the top electrode through the second conductive structure.

[0038] In one embodiment, the second passive component located on the cap substrate includes:

[0039] The second passive component includes:

[0040] At least two redistribution layers, wherein upper and lower adjacent redistribution layers are electrically connected via a conductive plug;

[0041] A dielectric layer covers the second surface of the cap substrate, and the at least two redistribution layers and the conductive plug are arranged in the dielectric layer.

[0042] In one embodiment, when the cap substrate is formed with the first passive device and the second passive device, the semiconductor device further comprises a through hole in the cap substrate, a first redistribution layer is formed on the bottom and inner wall of the through hole, the first redistribution layer is electrically connected to the second metal layer so that the first passive device is electrically connected to the second passive device, and the second passive device includes at least a portion of the first redistribution layer; and / or

[0043] When the first passive component and the second passive component are formed in the cap substrate, the semiconductor device further includes a second conductive plug located in the cap substrate, and the second passive component is electrically connected to the first passive component through the second conductive plug.

[0044] The semiconductor device and manufacturing method of the embodiment of the present application form at least one passive device in a cap substrate, and then bond the device substrate containing a thin film bulk acoustic wave device to the cap substrate, and directly perform impedance matching at the end of the thin film bulk acoustic wave device, thereby improving the performance of the thin film bulk acoustic wave device (such as a thin film bulk acoustic wave filter). At the same time, the semiconductor device after bonding is smaller in size, more integrated, simple in process, and lower in cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The following drawings of the present application are used as part of the present application for understanding the present application. The drawings show embodiments of the present application and their descriptions, which are used to explain the principle of the present application.

[0046] In the attached figure:

[0047] Figure 1A flowchart showing a method for manufacturing a semiconductor device according to a first specific embodiment of the present application is shown;

[0048] Figure 2 A flow chart showing a method for manufacturing a semiconductor device according to a second specific embodiment of the present application is shown;

[0049] Figure 3 A flowchart showing a method for manufacturing a semiconductor device according to a third specific embodiment of the present application is shown;

[0050] Figures 4A-4J A schematic cross-sectional view of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to a specific embodiment of the present application is shown; DETAILED DESCRIPTION

[0051] Next, the present application will be described more fully in conjunction with the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided to make the disclosure thorough and complete and to fully convey the scope of the present application to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals throughout represent like elements.

[0052] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part.

[0053] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the drawings is flipped, then the elements or features described as "under" or "beneath" or "beneath" the other elements will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both the upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0054] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "said / the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0055] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic illustrations of ideal embodiments (and intermediate structures) of the present application. As such, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances are contemplated. Accordingly, embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the region of the device and are not intended to limit the scope of the present application.

[0056] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application relates. It will also be understood that terms such as those defined in commonly used dictionaries should be understood to have a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense unless expressly defined as such herein.

[0057] In order to fully understand the present application, detailed steps and structures will be presented in the following description to illustrate the technical solution proposed by the present application. The preferred embodiments of the present application are described in detail below. However, in addition to these detailed descriptions, the present application may also have other implementation methods.

[0058] As a new type of micro-electro-mechanical system (MEMS) device, the film bulk acoustic wave resonator (FBAR) boasts advantages such as small size, light weight, low insertion loss, wide bandwidth, good out-of-band rejection, high rectangular coefficient, and high quality factor. It is well suited for the upgrading of wireless communication systems. Because FBARs are compatible with semiconductor processes, FBAR technology has become a research hotspot in the communications field. FBAR chips are generally used in conjunction with passive components (inductors and capacitors) to improve out-of-band rejection.

[0059] In related technologies, filters and passive components (capacitors and inductors) are typically fixed to a package substrate and electrically connected via wiring. Alternatively, the passive components are fabricated as separate components and then connected to the filter. The former results in larger chip sizes and lower integration, while the latter is complex, difficult, and expensive to manufacture.

[0060] Therefore, in view of the existence of the above technical problems, the present application proposes a method for manufacturing a semiconductor device, such as Figure 2 As shown, it mainly includes the following steps:

[0061] Step S110: providing a device substrate, on which a thin film bulk acoustic wave device and a first metal layer are formed;

[0062] Step S120: providing a cap substrate, wherein the cap substrate has a first surface and a second surface opposite to each other;

[0063] Step S130: forming an inner groove on one side of the first surface of the cap substrate;

[0064] Step S140: forming a first passive component in the groove;

[0065] Step S150: forming a second metal layer covering at least the end surface of the sidewall of the inner groove;

[0066] Step S160: bonding the device substrate and the cap substrate via the first metal layer and the second metal layer.

[0067] In an embodiment of the present application, at least one passive device is formed in a cap substrate, and then a device substrate containing a thin film bulk acoustic wave device is bonded to the cap substrate, and impedance matching is performed directly at the end of the thin film bulk acoustic wave device, thereby improving the performance of the thin film bulk acoustic wave device (such as a thin film bulk acoustic wave filter). At the same time, the semiconductor device after bonding has a smaller size, a higher degree of integration, a simpler process, and a lower cost.

[0068] Example 1

[0069] Below, reference Figures 1 to 3 、 Figures 4A to 4J The manufacturing method of the semiconductor device of the present application is described in detail, wherein: Figure 1 A flowchart showing a method for manufacturing a semiconductor device according to a first specific embodiment of the present application is shown; Figure 2 A flow chart showing a method for manufacturing a semiconductor device according to a second specific embodiment of the present application is shown; Figure 3 A flowchart showing a method for manufacturing a semiconductor device according to a third specific embodiment of the present application is shown; Figures 4A-4J A cross-sectional schematic diagram of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to a specific embodiment of the present application is shown.

[0070] The semiconductor device may be any suitable type of device known to those skilled in the art. In this embodiment, the technical solution of the present application is explained and illustrated mainly by taking the case where the semiconductor device is a thin film bulk acoustic resonator as an example.

[0071] Illustratively, the method for manufacturing a semiconductor device of the present application includes the following steps:

[0072] First, if Figure 1 As shown, step S110 is performed to provide a device substrate, on which a thin film bulk acoustic wave device and a first metal layer are formed.

[0073] For example, Figure 4AAs shown, a device substrate 200 is provided, a first cavity 2001 with an opening is formed on one side of the device substrate 200, a bottom electrode 201 is formed on the device substrate 200, and the bottom electrode 201 covers the opening of the first cavity 2001; a first conductive structure 206 and a second conductive structure 207 are respectively formed on both sides of the bottom electrode 201 on the substrate 200; and a conductive layer covering the bottom electrode 201, the first conductive structure 206 and the second conductive structure 207 is formed on the device substrate 200. A piezoelectric layer 202 is formed, and a top electrode 203 is formed on the piezoelectric layer 202. The first cavity 2001, the bottom electrode 201, the piezoelectric layer 202, and the top electrode 203 constitute a thin film bulk acoustic wave device 204. Then, a first metal layer 205 is formed on the piezoelectric layer 202. The first metal layer 205 penetrates the piezoelectric layer and is electrically connected to the bottom electrode 201 via a first conductive structure 206. The first metal layer 205 is electrically connected to the top electrode 203 via a second conductive structure 207. Exemplarily, an isolation layer is further formed between the device substrate and the first and second conductive structures, and between the bottom electrode and the opening of the first cavity. The isolation layer is used to increase the stability of the device structure and increase the isolation between the device and the device substrate, thereby reducing the resistivity requirements of the device substrate and preventing leakage between the electrodes of the device. The isolation layer can also serve as a transition layer between the device and the device substrate, improving the consistency of device structure growth and the adhesion between the device substrate and the device film layer, thereby improving device performance and reliability.

[0074] Illustratively, the device substrate 200 can be any suitable semiconductor substrate, such as a silicon substrate, and can also be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, including multilayer structures composed of these semiconductor materials, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), or can also be double-sided polished silicon wafers (Double Side Polished Wafers, DSP), or can also be ceramic substrates such as alumina, quartz or glass substrates, etc.

[0075] The material of the piezoelectric layer 202 can be a piezoelectric material having a wurtzite crystal structure, such as ZnO, AlN, GaN, lead zirconate titanate, or lead titanate. In this embodiment, AlN is preferably used as the piezoelectric layer.

[0076] The bottom electrode 201 and the top electrode 203 may be made of a conductive material or a semiconductor material. The conductive material may be a metal material having conductive properties. The metal material may be a metal such as aluminum (Al), copper (Cu), gold (Au), platinum (Pt), or an alloy thereof. The semiconductor material may be Si, Ge, SiGe, SiC, SiGeC, or the like.

[0077] Then, execute step 120, such as Figure 4B As shown, a capping substrate 300 is provided, wherein the capping substrate has an opposite first surface 301 and a second surface 302. For example, the capping substrate may be made of the same material as or different from the device substrate, which is not limited in the present application.

[0078] Then execute step 130, as Figure 4C As shown, an inner groove is formed on one side of the first surface 301 of the cap substrate 300 .

[0079] Specifically, a patterned mask layer (not shown) is formed on one side of the first surface 301 of the cap substrate 300 to define the size and position of the inner groove. Optionally, the patterned mask layer comprises a photoresist material, and the mask layer is patterned using a photolithography process to form a patterned mask layer. A portion of the cap substrate 300 is then etched using the patterned mask layer as a mask to form the inner groove.

[0080] An inner groove may be formed on one side of the first surface of the cap substrate 300 by, for example, dry etching or wet etching, wherein the inner groove corresponds to the capping thin film bulk acoustic wave device 204 .

[0081] Then, illustratively, continue as Figure 4C As shown, a second insulating layer 303 is formed on the cap substrate 300 .

[0082] Then as Figure 1 and Figure 2 As shown, step S140 is performed to form a first passive component in the inner groove.

[0083] For example, Figure 4DAs shown, the first passive device is a capacitor. First, a first passive device material layer is formed on the inner groove, which includes a stacked lower electrode material layer, a capacitor dielectric material layer, and an upper electrode material layer. For example, the lower electrode material layer and the upper electrode material layer include but are not limited to aluminum, and the capacitor dielectric material layer includes but is not limited to silicon nitride. Then, conventional photolithography and etching techniques in the field are used to perform photolithography and etching on the lower electrode material layer, the capacitor dielectric material layer, and the upper electrode material layer to form a patterned first passive device. The patterned first passive device 307 includes a lower electrode 304, a capacitor dielectric layer 305, and an upper electrode 306. The capacitor dielectric layer 305 is located between the lower electrode 304 and the upper electrode 306. The lower electrode 304 contacts the bottom surface of the inner groove, and the upper electrode 306 faces away from the lower electrode 304. Then as Figure 4E As shown, a first insulating layer 308 is formed on the first passive device 307 , and the first insulating layer 308 includes a first opening and a second opening. The first opening exposes a portion of the lower electrode 304 , and the second opening exposes a portion of the upper electrode 306 . The first insulating layer 308 and the second insulating layer 303 surround the first passive device 307 .

[0084] Then execute Figure 1 and Figure 2 In step S150 , a second metal layer is formed to at least cover the end surface of the sidewall of the inner groove.

[0085] Illustratively, the first metal layer and the second metal layer include but are not limited to at least one of materials such as Au or Sn, and specific appropriate materials can be selected according to actual needs.

[0086] For example, Figure 4E As shown, before forming the second metal layer 309, a portion of the second insulating layer 303 is removed to expose the end surface of the side wall of the inner groove and a portion of the first surface 301, and then the second metal layer 309 is formed. The second metal layer covers the end surface of the side wall of the inner groove, a portion of the first surface 301 and a portion of the second insulating layer 303, and fills the first opening and the second opening so that the upper electrode 306 and the lower electrode 304 of the first passive device are led out through the second metal layer 309.

[0087] Then execute Figure 1 and Figure 2 Step S160 shown in FIG. Figure 4EAs shown, the device substrate 200 and the cap substrate 300 are bonded via a first metal layer 205 and a second metal layer 309. The second metal layer 309 on the top surface of the inner groove sidewall (i.e., the end surface of the inner groove sidewall facing the device substrate 200) is bonded to the first metal layer 205. After bonding, a second cavity is formed between the device substrate 200 and the cap substrate 300. The bottom electrode 201 of the FBAW device 204 is electrically connected to the top electrode 306 of the first passive device 307 via the first conductive structure 206, and the top electrode 203 of the FBAW device 204 is electrically connected to the bottom electrode 304 of the first passive device 307 via the second conductive structure 207. It is worth mentioning that the above connection method is only an example. The bottom electrode 201, the top electrode 203 of the thin film bulk acoustic wave device 204, the upper electrode 306 and the lower electrode 304 of the first passive device 307 can also be led out in other ways. For example, the bottom electrode and the top electrode of the thin film bulk acoustic wave device and the upper electrode and the lower electrode of the first passive device can be electrically led out respectively through multiple conductive through holes, and multiple conductive through holes can be set in the cap substrate 300.

[0088] The description of the key steps of integrating the thin film bulk acoustic wave device with the first passive device (such as a capacitor) has been completed. In other embodiments, a second passive device (such as an inductor) may be formed on the cap substrate.

[0089] For example, the following is then performed: Figure 1 In step S170 , a second passive component is formed on the second surface of the cap substrate.

[0090] Specifically, first Figure 4F As shown, the cap substrate 300 is thinned on the second surface 302 of the cap substrate 300, and then at least one through hole 310 is formed in the thinned cap substrate 300, as shown in FIG. Figure 4G As shown, the through hole 310 exposes a portion of the second metal layer 309, that is, the through hole extends from the second surface to the first surface and passes through the side wall of the inner groove. Figure 4H As shown, a first redistribution layer 311 is formed on the bottom and sidewall of the through hole 310 and a portion of the second surface 302, and then as shown in FIG. Figure 4I As shown, a first dielectric layer 312 is formed on the second surface 302 , the first dielectric layer 312 covers the first redistribution layer 311 , and a first contact hole 313 is formed in the first dielectric layer 312 , the first contact hole 313 exposes a portion of the first redistribution layer 311 .

[0091] Then as Figure 4J As shown, a conductive material is formed to fill the first contact hole 313 to form a first conductive plug 315 and also to cover a portion of the surface of the first dielectric layer 312 to form a second redistribution layer 318;

[0092] A second dielectric layer 316 is formed on the first dielectric layer 312. The second dielectric layer 316 covers the second redistribution layer 318, and a second contact hole 317 is formed in the second dielectric layer 316. The second contact hole 317 exposes a portion of the second redistribution layer 318. The first redistribution layer 311 and the second redistribution layer 318 constitute a second passive component (such as an inductor). The second passive component is electrically connected to the second metal layer 309 on the top surface of the sidewall of the inner groove at the bottom of the through hole 310 through the first redistribution layer 311. The second metal layer 309 is then electrically connected to the upper electrode 306 and the lower electrode 304 of the first passive component, thereby achieving electrical connection between the first passive component and the second passive component. In some embodiments, the operation of forming the second redistribution layer and the second dielectric layer can be repeated to form a multilayer inductor coil.

[0093] Exemplarily, a metal bump is formed in the second contact hole for electrical extraction.

[0094] For example, the material of the first dielectric layer and the second dielectric layer may include but is not limited to PI (polyimide).

[0095] In an exemplary embodiment, a second conductive plug (not shown) is also formed in the cap substrate, and the second conductive plug is used to electrically connect the second passive device and the first passive device. For example, the second conductive plug passes through the cap substrate and corresponds to the first passive device, the top surface of the second conductive plug is electrically connected to the first redistribution layer of the second passive device, the bottom surface of the second conductive plug is electrically connected to the second metal layer, and the second metal layer is electrically connected to the first passive device, thereby realizing the electrical connection between the first passive device and the second passive device. Alternatively, the upper electrode and the lower electrode of the first passive device can be directly electrically connected to the corresponding second passive device through the conductive plug provided in the cap substrate.

[0096] In some embodiments, only the second passive device may be formed in the cap substrate, and the key steps are as follows: Figure 3 As shown, Figure 3 The process steps shown are similar to Figure 1 and Figure 2 Similarly, the same steps are not described in detail here, and reference can be made to the above detailed description.

[0097] like Figure 3 In the process steps shown, step S330 is performed to form an inner groove on the first surface of the cap substrate, and then step S340 is performed to form a second metal layer covering at least the end surface of the sidewall of the inner groove. At this time, there is no first passive device in the inner groove, only the second metal layer, and then Figure 1 and Figure 2The process is the same as shown, and step S350 is performed to bond the device substrate and the cap substrate. After bonding, step 360 is performed to form a second passive device on the second surface of the cap substrate. The steps of forming the second passive device can also be referred to the detailed description above.

[0098] It is worth mentioning that a plurality of first passive components and a plurality of second passive components may be formed on the cap substrate according to actual needs.

[0099] This completes the description of the key steps of the semiconductor device manufacturing method of the present application. The complete semiconductor device manufacturing method may also include other steps, which will not be described one by one here. It is worth mentioning that the order of the above steps can be adjusted without conflict.

[0100] In summary, in the embodiments of the present application, at least one passive device is formed in the cap substrate, and then the device substrate containing the thin film bulk acoustic wave device is bonded to the cap substrate, and impedance matching is performed directly at the end of the thin film bulk acoustic wave device, thereby improving the performance of the thin film bulk acoustic wave device (such as a thin film bulk acoustic wave filter). At the same time, the semiconductor device after bonding is smaller in size, more integrated, simple in process, and lower in cost.

[0101] Example 2

[0102] The present application also provides a semiconductor device, which can be manufactured by the method for manufacturing the semiconductor device in the aforementioned embodiment 1. Some details of this embodiment can be referred to the relevant description of the method above and will not be repeated here.

[0103] Specifically, if Figure 4J As shown, the semiconductor device includes: a device substrate 200 and a cap substrate 300. A FBAW device 204 and a first metal layer 205 located outside the FBAW device are disposed on the device substrate 200. The cap substrate 300 has opposing first and second surfaces 301 and 302, with an inner groove formed on one side of the first surface. A first passive component 307 and / or a second passive component are disposed on the first surface, and a second metal layer 309 covers at least the end surfaces of the sidewalls of the inner groove. The first passive component 307 is disposed within the inner groove, and the second passive component is disposed on the second surface. When the first passive component is disposed within the inner groove, the second passive component is electrically connected to the first passive component 307. The side of the cap substrate 300 where the inner groove is formed faces the side of the device substrate 200 where the FBAW device 204 is disposed, and the cap substrate 300 is bonded to the second metal layer 309 via the first metal layer 205. After bonding, a second cavity is formed between the device substrate 200 and the cap substrate 300.

[0104] For example, Figure 4JAs shown, the first passive device includes a stacked lower electrode 304, a capacitor dielectric layer 305 and an upper electrode 306. The lower electrode 304 and the upper electrode 306 are electrically connected to different second metal layers 309 respectively. There is an electrical isolation region between the second metal layers 309 connecting the lower electrode 304 and the upper electrode 306 to prevent the upper electrode 306 and the lower electrode 304 from being connected.

[0105] For example, Figure 4A As shown, a first cavity 2001 with an opening is formed on one side of a device substrate 200. The thin film bulk acoustic wave device includes: a bottom electrode 201, a piezoelectric layer 202, a top electrode 203, a first conductive structure 206, and a second conductive structure 207. The bottom electrode 201 covers the opening of the first cavity 2001. The first conductive structure 206 and the second conductive structure 207 are located on either side of the bottom electrode 201 on the device substrate 200. The piezoelectric layer 202 covers the bottom electrode 201, the first conductive structure 206, and the second conductive structure 207. The first metal layer 205 penetrates the piezoelectric layer 202 and is electrically connected to the bottom electrode 201 through the first conductive structure 206. The first metal layer 205 is electrically connected to the top electrode 203 through the second conductive structure 207. The first metal layer 205 electrically connected to the first conductive structure 206 and the first metal layer 205 electrically connected to the second conductive structure 207 are electrically isolated from each other.

[0106] Exemplarily, the second passive device includes: at least two redistribution layers, wherein upper and lower adjacent redistribution layers are electrically connected via conductive plugs; a dielectric layer covering the second surface of the cap substrate, wherein the at least two redistribution layers and the conductive plugs are disposed in the dielectric layer. Figure 4J As shown, the second passive device includes: a first redistribution layer 311, a first dielectric layer 312, a second redistribution layer 318 and a second dielectric layer 316, wherein the first redistribution layer 311 is at least partially located on the second surface 302, the first dielectric layer 312 covers the first redistribution layer 311, a first conductive plug 315 is formed in the first dielectric layer 312, the first redistribution layer 311 and the second redistribution layer 318 are electrically connected through the first conductive plug 315, the second dielectric layer 316 covers the first dielectric layer 312 and the second redistribution layer 318, a second contact hole 317 is formed in the second dielectric layer 316, the second contact hole 317 exposes a portion of the second redistribution layer 318, which is used for subsequent electrical connection or lead-out of the second redistribution layer 318.

[0107] For example, Figure 4JAs shown, when the first passive device 307 and the second passive device are formed in the cap substrate 300, the semiconductor device further includes a through hole 310 located in the cap substrate 300. A first redistribution layer 311 is formed on the bottom and inner wall of the through hole 310. The first redistribution layer 311 is electrically connected to the second metal layer 309 to electrically connect the first passive device 307 to the second passive device. The second passive device includes at least a portion of the first redistribution layer 311. Exemplarily, when the first passive device and the second passive device are formed in the cap substrate, the semiconductor device further includes a second conductive plug located in the cap substrate. The second passive device is electrically connected to the first passive device via the second conductive plug.

[0108] This concludes the introduction to the structure of the semiconductor device of the present invention. A complete device may also include other components, which will not be detailed here. Since the semiconductor device of the present application is manufactured using the aforementioned manufacturing method, it has the same advantages as the aforementioned method.

[0109] Although a number of embodiments are described herein, it should be understood that a variety of other modifications and embodiments may be devised by those skilled in the art, all of which fall within the spirit and scope of the concepts disclosed herein. More particularly, within the scope of the present disclosure, the accompanying drawings, and the appended claims, various modifications and changes may be made to the arrangements and / or components of the subject matter in combination. In addition to modifications and changes to the components and / or arrangements, the use of alternatives will also be readily apparent to those skilled in the art.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The manufacturing method comprises: Providing a device substrate, on which a thin film bulk acoustic wave device and a first metal layer are formed; providing a capping substrate having opposing first and second surfaces; forming an inner groove on one side of the first surface of the cap substrate; forming a second metal layer covering at least the end surface of the side wall of the inner groove; Bonding the device substrate and the cap substrate through the first metal layer and the second metal layer; Wherein, before forming the second metal layer, the method further includes: forming a first passive device in the inner groove; and / or, After the bonding, a second passive component is formed on the second surface of the cap substrate, and when the first passive component is formed in the inner groove, the second passive component is electrically connected to the first passive component.

2. The manufacturing method according to claim 1, characterized in that The first passive component is a capacitor, and the first passive component includes a lower electrode, a capacitor dielectric layer and an upper electrode, wherein the capacitor dielectric layer is located between the lower electrode and the upper electrode, the lower electrode contacts the bottom surface of the inner groove, and the upper electrode is away from the lower electrode. After forming the first passive component in the inner groove and before forming the second metal layer, the method includes: forming a first insulating layer on the first passive device; forming a first opening and a second opening in the first insulating layer, wherein the first opening exposes a portion of the lower electrode, and the second opening exposes a portion of the upper electrode; The second metal layer also covers the first passive component and fills the first opening and the second opening.

3. The manufacturing method according to claim 1, characterized in that: The forming of a second passive device on the second surface of the cap substrate comprises: forming a first redistribution layer on the second surface; Forming a first dielectric layer to cover the first redistribution layer and the second surface, and forming a first contact hole in the first dielectric layer, wherein the first contact hole exposes a portion of the first redistribution layer; Forming a conductive material to fill the first contact hole to form a first conductive plug and also cover a portion of the surface of the first dielectric layer to form a second redistribution layer; A second dielectric layer is formed to cover the second redistribution layer and the first dielectric layer, and a second contact hole is formed in the second dielectric layer, wherein the second contact hole exposes a portion of the second redistribution layer, and the first redistribution layer and the second redistribution layer constitute a second passive device.

4. The manufacturing method according to claim 3, characterized in that: When the first passive component is formed in the inner groove, a second conductive plug is also formed in the cap substrate, and the second conductive plug is used to electrically connect the second passive component and the first passive component.

5. The manufacturing method according to claim 3, characterized in that: When the first passive device is formed in the inner groove, the method further includes: forming a through hole in the cap substrate before forming the first redistribution layer, the through hole penetrating the cap substrate and exposing a portion of the second metal layer, wherein when the first redistribution layer is formed on the second surface, the first redistribution layer also covers the side walls and bottom of the through hole, so that the second passive device is electrically connected to the first passive device through the second metal layer.

6. A semiconductor device, characterized in that: The semiconductor device comprises: A device substrate, on which a thin film bulk acoustic wave device and a first metal layer located outside the thin film bulk acoustic wave device are arranged; A cap substrate having a first surface and a second surface opposite to each other, and an inner groove is formed on one side of the first surface; A second metal layer, covering at least the end surface of the side wall of the inner groove; A first passive component is located in the inner groove; and / or a second passive component, located on the second surface, wherein when the first passive component is formed in the inner groove, the second passive component is electrically connected to the first passive component; The side of the cap substrate on which the inner groove is formed is opposite to the side of the device substrate on which the thin film bulk acoustic wave device is formed, and is bonded to the second metal layer through the first metal layer.

7. The semiconductor device according to claim 6, wherein: The first passive device includes a lower electrode, a capacitor dielectric layer and an upper electrode which are stacked, and the lower electrode and the upper electrode are electrically connected to different second metal layers respectively.

8. The semiconductor device according to claim 6, wherein: A first cavity having an opening is formed on one side of the device substrate; The thin film bulk acoustic wave device comprises: A bottom electrode, covering the opening of the first cavity; A first conductive structure and a second conductive structure are respectively located on two sides of the bottom electrode; a piezoelectric layer, located on the device substrate and covering the bottom electrode, the first conductive structure and the second conductive structure, wherein the first metal layer penetrates the piezoelectric layer and is electrically connected to the bottom electrode through the first conductive structure; A top electrode is located on the piezoelectric layer, and the first metal layer is electrically connected to the top electrode through the second conductive structure.

9. The semiconductor device according to claim 6, wherein: The second passive component comprises: At least two redistribution layers, wherein the upper and lower adjacent redistribution layers are electrically connected via a conductive plug; A dielectric layer covers the second surface of the cap substrate, and the at least two redistribution layers and the conductive plug are arranged in the dielectric layer.

10. The semiconductor device according to claim 9, wherein: When the cap substrate is formed with the first passive device and the second passive device, the semiconductor device further comprises a through hole in the cap substrate, a first redistribution layer is formed on the bottom and inner wall of the through hole, the first redistribution layer is electrically connected to the second metal layer so that the first passive device is electrically connected to the second passive device, and the second passive device comprises at least a portion of the first redistribution layer; and / or When the first passive device is formed in the cap substrate, the semiconductor device further includes a second conductive plug located in the cap substrate, and the second passive device is electrically connected to the first passive device through the second conductive plug.

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