Method capable of adaptively setting detection threshold based on periodic pulse signal
Through the adaptive detection threshold setting method based on periodic pulse signals, the detection threshold is dynamically adjusted using the sampling data of FPGA and ADC chips, which solves the problem of complex interference signal misjudgment and threshold setting in the prior art, and realizes the synchronization and efficiency of signal distinction and output.
Patent Information
- Application Number
- CN202411768861.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-04
- Publication Date
- 2025-03-28
AI Technical Summary
When existing signal detection technology appears at the same time as useful signals and interfering signals, it is difficult to effectively distinguish them, resulting in misjudging the interference signals as valid signals. The adaptive threshold setting method is complex and takes up a lot of resources, resulting in the output delay or the pulse width protection indication shortened.
Through a method based on periodic pulse signals, the ADC chip is sampled using FPGA to obtain signal noise value and power value, and a fixed threshold is calculated, and the maximum value of signals larger than the fixed threshold is selected through the adaptive signal threshold setting program, and the detection threshold is dynamically adjusted to ensure that only the valid signal output is output.
The correct distinction between useful signals and interfering signals is achieved, which avoids the interfering signals being misjudged as valid signals, and ensures the synchronization of detection signal output and wide-maintaining pulse output, reducing system complexity and resource utilization.
Smart Images
Figure CN119727670A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of signal detection and processing, and in particular to a method for adaptively setting a detection threshold based on a periodic pulse signal. Background Art
[0002] In a certain communication system, the signal detection threshold is adjusted in real time by detecting the size of the periodic pulse signal, so as to ensure that only valid signals and width maintenance indicators are output when one or more periodic interference pulse signals exist at the same time.
[0003] During the development and implementation process, a certain working mode of the system requires that a useful signal and one or more interference signals appear in the same or similar periodic pulse signal state at the same time. If the detection values of both exceed the fixed detection threshold value, the system will mistakenly detect the interference signal with the same pulse period but slightly less power than the useful signal, and output an erroneous signal and width maintenance indication.
[0004] The existing detection technology is to detect signals according to a set fixed detection threshold value; the other is to set the detection threshold value by accumulating and averaging the sampled signals to obtain an average detection signal value.
[0005] In actual use, the fixed detection threshold responds quickly. As long as the signal exceeds the set threshold value, it can be judged as valid. However, it has no inhibitory effect on interference signals that are smaller than normal signals and larger than the fixed threshold. If a fixed effective signal threshold and a fixed interference signal threshold are set, it is only applicable to effective signals and interference signals with fixed power. Once the signal power changes, the set threshold becomes ineffective.
[0006] Although the accumulation and averaging of sampled signals can realize the adaptive setting of detection thresholds, it takes some time to collect, store and calculate real-time signals. This will cause the output pulse signal width indication to become shorter or delayed, which is not allowed by system indicators. In addition, the accumulation and averaging procedures have many factors to be considered in their design, with a large amount of data, high resource usage and relatively complex design. Summary of the invention
[0007] In order to solve the above technical problems, the present invention proposes a method for adaptively setting a detection threshold based on a periodic pulse signal.
[0008] A method for adaptively setting a detection threshold based on a periodic pulse signal comprises the following steps: S1: The RF periodic pulse signal is input into the detector. The detector converts the RF periodic pulse signal into a level signal and inputs it into the detection ADC chip. The FPGA samples the ADC chip to obtain the detection signal noise value and the detection signal power value, and analyzes the signal noise value and signal power value to determine whether the detection hardware system is normal. S2: Calculate the detection signal fixed threshold through the sampled detection signal noise value and detection signal power value. If the sampled value is less than the detection signal fixed threshold value, it is regarded as a valid signal, and the valid signal is input into the adaptive signal threshold setting program. S3: The adaptive signal threshold setting program registers the sampling signals that are greater than the fixed threshold, and selects the maximum value of the sampling signal within the time allowed by the system. If the maximum value obtained plus the fixed weighted value is greater than the actual sampling signal, it is set to the adaptive threshold. If the signal is less than the adaptive threshold value, it is a valid signal, and a frequency conversion signal, a width maintenance indication and a switch instruction are output. The adaptive signal threshold setting program updates the threshold value in the register to the fixed threshold of the detection noise, and then repeats the cycle to achieve adaptive setting of the signal threshold.
[0009] Furthermore, a method for adaptively setting a detection threshold based on a periodic pulse signal, wherein step S1 includes the following sub-steps: S11: Input the non-periodic pulse signal into the RF channel, and use the FPGA to detect the ADC chip to sample the base noise of the communication system to obtain the base noise value when there is no signal; S12: Inputting the radio frequency periodic pulse signal with the minimum power accepted by the communication system into the radio frequency channel, and the FPGA detection ADC chip samples the signal noise of the communication system to obtain the noise value and the minimum signal power value when there is a signal; S13: Determine whether the detection hardware system is normal: If the difference between the base noise value when there is no signal and the noise value when there is a signal is less than the set difference, and the difference between the minimum signal power value and the base noise value is less than the set threshold, the detection hardware system works normally; If the difference between the base noise value when there is no signal and the noise value when there is a signal is greater than or equal to the set difference, or the difference between the minimum signal power value and the base noise value is greater than or equal to the set threshold, the detection hardware system is not working properly and the following steps are not performed.
[0010] Furthermore, a method for adaptively setting a detection threshold based on a periodic pulse signal, wherein step S2 includes the following sub-steps: Set the detection signal fixed threshold = small signal power value + fluctuation range to determine whether it is a valid signal: If the sampled signal is less than the set detection signal fixed threshold, it is a valid signal and enters the adaptive signal threshold setting program for processing; If the sampling signal is greater than or equal to the set detection signal fixed threshold, it is an invalid signal and will not enter the adaptive signal threshold setting procedure; The fluctuation range is set to 1 dB.
[0011] Further, a method for adaptively setting a detection threshold based on a periodic pulse signal, wherein S3 includes the following sub-steps: S31: FPGA sets the adaptive signal threshold setting program, and initializes the basic threshold register, temporary signal register, counter and state machine when powered on; S32: Entering the threshold, the adaptive signal threshold setting program determines that the state machine enters the 0 state, 1 state, 2 state, and 3 state cycle; S33: When calculating the maximum value in the temporary register, the effective signal threshold and the noise threshold range are judged and set at the same time.
[0012] Further, a method for adaptively setting a detection threshold based on a periodic pulse signal, wherein S32 includes the following sub-steps: S321: 0 state: Set the temporary signal register value to the fixed threshold value of the detection signal to determine whether to enter 2 state: If the detection AD data collected by the ADC chip of the FPGA is less than the temporary signal register value, the adaptive signal threshold setting program determines that the sampled detection signal is valid and enters state 1; If the detection AD data collected by the ADC chip of the FPGA is greater than or equal to the temporary signal register value, the adaptive signal threshold setting program determines that the sampled detection signal is invalid, and detects whether the detection signal meets the conditions for entering the 1 state in the 0 state; S322: 1 state: set the threshold detection time, start the counting process, and compare the AD data with the temporary signal register value: If the detected AD data is less than the temporary signal register value during the counter counting period, the detected AD data replaces the temporary signal register value; If the detected AD data is greater than or equal to the temporary signal register value during the counter counting period, the temporary signal register value remains unchanged, and the maximum value comparison continues until the counting ends, entering state 2; The threshold detection time meets the system indicator to allow RTK to pull up the post-processing and the processing time when the signal power changes; S323: State 2: Calculate the maximum value in the temporary register and set it in the detection threshold register, and enter state 3. The formula is: Detection threshold = temporary register rate value + fluctuation range S324: State 3: After waiting for one FPGA working clock, it returns to state 0 and restarts detection, and the state machine works in a loop.
[0013] Further, a method for adaptively setting a detection threshold based on a periodic pulse signal, said S33 comprises the following sub-steps: S331: assign the maximum value +1dBm in the temporary register to the noise threshold of the adaptive dynamic threshold register; S332: Determine whether the detection signal is noise: If the detection signal is less than the noise threshold, the detection signal + 3dBm is assigned to the noise threshold of the adaptive dynamic threshold register; If the detection signal value is greater than or equal to the noise threshold, it is a noise signal, and the output signal, width maintenance indication, and switch operation are stopped; S333: Before waiting for the next detection signal to be detected, the noise threshold remains unchanged: If the detection signal becomes larger and exceeds the noise threshold, the valid signal, the interference signal and the width indication are output at the same time, allowing the communication system to process the program time. When the new sound threshold is updated, only the valid signal is output, which has no impact on the communication system. If the detection signal becomes smaller, both the effective signal and the interference signal have not reached the noise threshold, and there is no output within the program processing time allowed by the communication system. When the new sound threshold is updated, only the effective signal is output, which has no impact on the communication system.
[0014] Furthermore, a method for adaptively setting a detection threshold based on a periodic pulse signal also includes the following steps for a glitch signal of a sampling clock period: S41: Assume that the value sampled by the first clock is A, the value sampled by the second clock is B, and the value sampled by the third clock is C. The adaptive signal threshold setting program sets the judgment conditions: AB>9 and CB>9 and (AC<4 or CA<4), then the maximum value sampled by the second clock is invalid, which solves the occasional glitches from unknown sources inside the ADC chip.
[0015] The beneficial effects of the present invention are as follows: through a method for adaptively setting a detection threshold based on a periodic pulse signal, a detection threshold corresponding to the sampled signal is set in real time according to the size of the sampled signal, the detection signal value is calculated and compared with the value thereof, and the detection threshold is correctly set when the useful signal and the interference signal are in the same or similar periodic pulse signal state at the same time. The detection threshold changes with the signal size, ensuring that the interference signal will not be misjudged as a valid signal, and at the same time ensuring the synchronization of the detection signal output and the width-maintaining pulse output to the greatest extent. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 It is the schematic diagram of digital control circuit.
[0017] Figure 2 This is an example diagram of FPGA sampling base noise signal data.
[0018] Figure 3 This is an example diagram of FPGA sampling periodic pulse signal data.
[0019] Figure 4 It is the FPGA program processing flow chart.
[0020] Figure 5 This is the timing diagram of dynamic threshold setting. DETAILED DESCRIPTION
[0021] The present invention is further described below, but the protection scope of the present invention is not limited to the following description.
[0022] As attached Figures 1 to 4 As shown, a method for adaptively setting a detection threshold based on a periodic pulse signal comprises the following steps: S1: inputting a radio frequency periodic pulse signal into a detector, the detector converting the radio frequency periodic pulse signal into a level signal and inputting it into a detection ADC chip, FPGA sampling the ADC chip to obtain a detection signal noise value and a detection signal power value, analyzing the signal noise value and the signal power value, and judging whether the detection hardware system is normal; S2: Calculate the detection signal fixed threshold through the sampled detection signal noise value and detection signal power value. If the sampled value is less than the detection signal fixed threshold value, it is regarded as a valid signal, and the valid signal is input into the adaptive signal threshold setting program. S3: The adaptive signal threshold setting program registers the sampling signals that are greater than the fixed threshold, and selects the maximum value of the sampling signal within the time allowed by the system. If the maximum value obtained plus the fixed weighted value is greater than the actual sampling signal, it is set to the adaptive threshold. If the signal is less than the adaptive threshold value, it is a valid signal, and a frequency conversion signal, a width maintenance indication and a switch instruction are output. The adaptive signal threshold setting program updates the threshold value in the register to the fixed threshold of the detection noise, and then repeats the cycle to achieve adaptive setting of the signal threshold.
[0023] According to the actual situation of the system, the ADC sampling chip used in the present invention is AD9058 with an 8-bit data width, and the sampling value trend is a negative slope, that is, the smaller the sampling value, the larger the signal. Any operation is performed when the receiving timing RTK is high. The following embodiments are all illustrated with actual system test data.
[0024] Specific embodiment 1 As shown in the attached Figure 2~3 As shown, a method for adaptively setting a detection threshold based on a periodic pulse signal, the step S1 includes the following sub-steps: S11: Input the non-periodic pulse signal into the RF channel, and the FPGA detects the ADC chip to sample the base noise of the communication system to obtain the base noise value 193 when there is no signal; S12: Input the radio frequency periodic pulse signal with the minimum power accepted by the communication system into the radio frequency channel, and the FPGA detects the ADC chip to sample the signal noise of the communication system, and obtain the noise value of 192 when there is a signal and the minimum signal power value of -60dBm is about 186; S13: Determine whether the detection hardware system is normal: The difference between the base noise value when there is no signal and the noise value when there is a signal is less than the set difference of 3dB, and the difference between the minimum signal power value and the base noise value is less than the set threshold, and the detection hardware system works normally.
[0025] As attached Figure 4 As shown, a method for adaptively setting a detection threshold based on a periodic pulse signal, the step S2 includes the following sub-steps: Set the detection signal fixed threshold = small signal power value + fluctuation range, and get the detection signal fixed threshold 186+3=186 to determine whether it is a valid signal: If the sampled signal is less than the set detection signal fixed threshold, it is a valid signal and enters the adaptive signal threshold setting program for processing; If the sampling signal is greater than or equal to the set detection signal fixed threshold, it is an invalid signal and will not enter the adaptive signal threshold setting procedure; The fluctuation range is set to 1 dB.
[0026] Further, a method for adaptively setting a detection threshold based on a periodic pulse signal, wherein S3 includes the following sub-steps: S31: FPGA sets the adaptive signal threshold setting program, and initializes the basic threshold register, temporary signal register, counter and state machine when powered on; S32: Entering the threshold, the adaptive signal threshold setting program determines that the state machine enters the 0 state, 1 state, 2 state, and 3 state cycle; S33: When calculating the maximum value in the temporary register, the effective signal threshold and the noise threshold range are judged and set at the same time.
[0027] Further, a method for adaptively setting a detection threshold based on a periodic pulse signal, wherein S32 includes the following sub-steps: S321: 0 state: Set the temporary signal register value to the detection signal fixed threshold value 186, and determine whether to enter 2 state: If the detection AD data collected by the ADC chip of the FPGA is less than 186, the adaptive signal threshold setting program determines that the sampled detection signal is valid and enters state 1; If the detection AD data collected by the ADC chip of the FPGA is greater than or equal to the temporary signal register value, the adaptive signal threshold setting program determines that the sampled detection signal is invalid, and detects whether the detection signal meets the conditions for entering the 1 state in the 0 state; S322: 1 state: set the threshold detection time, start the counting process, and compare the AD data with the temporary signal register value: If the detected AD data is less than the temporary signal register value during the counter counting period, the detected AD data replaces the temporary signal register value; If the detected AD data is greater than or equal to the temporary signal register value during the counter counting period, the temporary signal register value remains unchanged, and the maximum value comparison continues until the counting ends, entering state 2; The threshold detection time meets the system indicator to allow RTK to pull up the post-processing and the processing time when the signal power changes; S323: State 2: Calculate the maximum value in the temporary register and set it in the detection threshold register, and enter state 3. The formula is: Detection threshold = temporary register rate value + fluctuation range S324: State 3: After waiting for one FPGA working clock, it returns to state 0 and restarts detection, and the state machine works in a loop.
[0028] Further, a method for adaptively setting a detection threshold based on a periodic pulse signal, said S33 comprises the following sub-steps: S331: assign the maximum value +1dBm in the temporary register to the noise threshold of the adaptive dynamic threshold register. At this time, the value in the temporary register is about 109, and the adaptive dynamic threshold TAG_max_up is set to 109+3=112; S332: Determine whether the detection signal is noise: If the detection signal is less than 112, the detection signal 109+9 (3dBm) is assigned to the noise threshold of the adaptive dynamic threshold register. That is, when the detection signal value is greater than 118, it is considered to be a noise signal, and the output signal, width indication and switch operation are stopped; If the size of the useful signal is 109, the size of the interference signal is 122, and the adaptive dynamic threshold is set to 112 according to the program design, the size of the interference signal is 122 and does not exceed the adaptive dynamic threshold, so no processing is done on the interference signal, and the output is still the signal of the effective signal, the width indication and the switch operation, and the dynamic adaptive threshold is set successfully; As attached Figure 5As shown, S333: before waiting for the next detection signal to be detected, the noise threshold remains unchanged. Assuming that the detection signal becomes larger at this time, the effective signal sampling value is 90, the interference signal sampling value is 110, and the dynamic adaptive threshold value is maintained at 112: If the detection signal becomes larger and exceeds the noise threshold, the valid signal, the interference signal and the width indication are output at the same time, allowing the communication system to process the program time. When the new sound threshold is updated, only the valid signal is output, which has no impact on the communication system. If the detection signal becomes smaller, both the effective signal and the interference signal have not reached the noise threshold, and there is no output within the program processing time allowed by the communication system. When the new sound threshold is updated, only the effective signal is output, which has no impact on the communication system.
[0029] Furthermore, a method for adaptively setting a detection threshold based on a periodic pulse signal also includes the following steps for a glitch signal of a sampling clock period: Although the signal fluctuates, due to system indicator requirements, the effective signal entering the ADC chip is very stable, and the value fluctuations of several adjacent clocks sampled by the FPGA will not change much. However, when the ADC chip runs at full clock rate, a glitch signal of a sampling clock cycle will occasionally appear. The current solution system does not use the full rate; therefore, in the maximum value detection process, if the value A sampled by the first clock is 110, the value B sampled by the second clock is 95, and the value C sampled by the third clock is 109, the judgment conditions in the program: AB>9, CB>9 and AC<4 or CA<4 are met at the same time, then the maximum value at moment B is judged to be invalid. This method is to solve the occasional glitches from unknown sources inside the ADC chip.
[0030] Specific embodiment 2 A method for adaptively setting a detection threshold based on a periodic pulse signal, judging that the logic is not 1. The detection noise value of the ADC chip sampled by FPGA is 200. The minimum signal that the detector can detect within the dynamic range of the system design indicators is sent to the ADC. At this time, the ADC data sampled by FPGA is 185. The trend of the ADC chip used in the system is a negative slope. Then the detection threshold value is set to 186, that is, the signal less than 186 is regarded as a valid signal, and the width preservation indication is output. The signal greater than 191 is regarded as noise, and the width preservation indication is stopped.
[0031] 2. When selecting the large signal threshold, set the large signal basic threshold parameters according to the system usage. For example, if the system sets the signal above -25dBm as a large signal, and the ADC value sampled by the FPGA is 125 at -25dBm, then set the basic detection threshold to 130. When the ADC value sampled by the FPGA is less than 130, the signal is considered valid, and a value greater than 135 is considered noise.
[0032] 3. FPGA adaptive judgment threshold comparison program design process, taking the large signal threshold as an example: a. Initialize the basic threshold register and the temporary signal register, set the basic threshold register value to 130, and set the temporary signal register value to 130; b. Enter the threshold judgment state machine setting: State 0: Set the value of the temporary signal register to 130; when the real-time ADC value sampled by the FPGA is less than 130, the signal is considered valid and enters state 1. Otherwise, the signal is always detected in state 0. State 1: Set the threshold detection time. Start the counting process and compare the ADC real-time value with the temporary signal register value. During the counter counting period, if the ADC real-time value is less than the temporary register value, the ADC real-time value will replace the temporary register value. This cycle will be repeated until the counting ends. After the counting ends, enter state 2; State 2: Set the maximum value obtained by comparison to the detection threshold and enter state 3; State 3: After waiting for one system clock, it returns to state 0 and restarts detecting the size of the system periodic signal, performing cyclic detection.
[0033] c. Determination of effective signal threshold range Although the signal fluctuates, the effective signal entering the ADC is very stable through the processing of the system hardware, and the fluctuation of the values sampled by adjacent clocks will not change much. However, when the ADC runs at full clock rate, a glitch signal of a system sampling clock cycle will occasionally appear. Therefore, in the maximum value detection process, if the value A sampled by the first clock is 110, the value B sampled by the second clock is 95, and the value C sampled by the third clock is 109, the judgment conditions in the program: AB>10 and CB>10 are met at the same time, then the maximum value at moment B is judged to be invalid; if A is 140, B is 145, and C is 147, A, B, and C are simultaneously greater than the basic threshold register value of 130, and the signal amplitude is judged to be less than the minimum detection threshold, and the output width is stopped; if A is 120, B is 122, and C is 140, it is necessary to meet the conditions that A, B, and C are simultaneously greater than the basic threshold register value of 130. At this time, it is judged that signal C is not a valid signal below the threshold, and the output width indication processing is not stopped.
[0034] When the program determines that the maximum signal is a valid signal, the dynamic threshold TAG_max_up of the signal is set to 5~10 greater than the maximum value. The specific value can be set according to the actual measurement of the system. For example, the signal value collected is 109, and the dynamic threshold TAG_max_up is set to 109+5, that is, values less than 114 are regarded as valid signals, and the width-keeping indication is output. At the same time, TAG_max_down is set to 114+5. When the signal value collected is greater than 119, it is considered to be an invalid signal and the width-keeping indication is stopped.
[0035] This scheme uses a method for adaptively setting the detection threshold based on a periodic pulse signal. The detection threshold corresponding to the sampling signal is set in real time according to the size of the sampling signal. The detection signal value is calculated and compared with the value thereof. The detection threshold is correctly set when the useful signal and the interference signal are in the same or similar periodic pulse signal state at the same time. The detection threshold changes with the signal size to ensure that the interference signal will not be misjudged as a valid signal. At the same time, the synchronization of the detection signal output and the width-maintaining pulse output is guaranteed to the greatest extent.
[0036] The above shows and describes the basic principles and main features of the present invention and the advantages of the present invention. It should be understood by those skilled in the art that the present invention is not limited to the above embodiments. The above embodiments and descriptions are only for explaining the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, which fall within the scope of the present invention to be protected. The scope of protection of the present invention is defined by the attached claims and their equivalents.
Claims
1. A method for adaptively setting a detection threshold based on a periodic pulse signal, characterized in that: The following steps are involved: S1: The RF periodic pulse signal is input into the detector. The detector converts the RF periodic pulse signal into a level signal and inputs it into the detection ADC chip. The FPGA samples the ADC chip to obtain the detection signal noise value and the detection signal power value, and analyzes the signal noise value and signal power value to determine whether the detection hardware system is normal. S2: Calculate the detection signal fixed threshold through the sampled detection signal noise value and detection signal power value. If the sampled value is less than the detection signal fixed threshold value, it is regarded as a valid signal, and the valid signal is input into the adaptive signal threshold setting program. S3: The adaptive signal threshold setting program registers the sampling signals that are greater than the fixed threshold, and selects the maximum value of the sampling signal within the time allowed by the system. If the maximum value obtained plus the fixed weighted value is greater than the actual sampling signal, it is set to the adaptive threshold. If the signal is less than the adaptive threshold value, it is a valid signal, and the frequency conversion signal, width maintenance indication and switch instruction are output. The adaptive signal threshold setting program updates the threshold value in the register to the fixed threshold of the detection noise, and then repeats the cycle to achieve adaptive setting of the signal threshold.
2. The method for adaptively setting a detection threshold based on a periodic pulse signal according to claim 1, characterized in that: The step S1 comprises the following sub-steps: S11: Input the non-periodic pulse signal into the RF channel, and use the FPGA to detect the ADC chip to sample the base noise of the communication system to obtain the base noise value when there is no signal; S12: Inputting the radio frequency periodic pulse signal with the minimum power accepted by the communication system into the radio frequency channel, and the FPGA detection ADC chip samples the signal noise of the communication system to obtain the noise value and the minimum signal power value when there is a signal; S13: Determine whether the detection hardware system is normal: If the difference between the base noise value when there is no signal and the noise value when there is a signal is less than the set difference, and the difference between the minimum signal power value and the base noise value is less than the set threshold, the detection hardware system works normally; If the difference between the base noise value when there is no signal and the noise value when there is a signal is greater than or equal to the set difference, or the difference between the minimum signal power value and the base noise value is greater than or equal to the set threshold, the detection hardware system is not working properly and the following steps are not performed.
3. The method for adaptively setting a detection threshold based on a periodic pulse signal according to claim 1, characterized in that: The step S2 comprises the following sub-steps: Set the detection signal fixed threshold = small signal power value + fluctuation range to determine whether it is a valid signal: If the sampled signal is less than the set detection signal fixed threshold, it is a valid signal and enters the adaptive signal threshold setting program for processing; If the sampling signal is greater than or equal to the set detection signal fixed threshold, it is an invalid signal and will not enter the adaptive signal threshold setting procedure; The fluctuation range is set to 1 dB.
4. The method for adaptively setting a detection threshold based on a periodic pulse signal according to claim 1, characterized in that: The S3 comprises the following sub-steps: S31: FPGA sets the adaptive signal threshold setting program, and initializes the basic threshold register, temporary signal register, counter and state machine when powered on; S32: Entering the threshold, the adaptive signal threshold setting program determines that the state machine enters the 0 state, 1 state, 2 state, and 3 state cycle; S33: When calculating the maximum value in the temporary register, the effective signal threshold and the noise threshold range are judged and set at the same time.
5. The method for adaptively setting a detection threshold based on a periodic pulse signal according to claim 1, characterized in that: The S32 includes the following sub-steps: S321: 0 state: Set the temporary signal register value to the fixed threshold value of the detection signal to determine whether to enter 2 state: If the detection AD data collected by the ADC chip of the FPGA is less than the temporary signal register value, the adaptive signal threshold setting program determines that the sampled detection signal is valid and enters state 1; If the detection AD data collected by the ADC chip of the FPGA is greater than or equal to the temporary signal register value, the adaptive signal threshold setting program determines that the sampled detection signal is invalid, and detects whether the detection signal meets the conditions for entering the 1 state in the 0 state; S322: 1 state: set the threshold detection time, start the counting process, and compare the AD data with the temporary signal register value: If the detected AD data is less than the temporary signal register value during the counter counting period, the detected AD data replaces the temporary signal register value; If the detected AD data is greater than or equal to the temporary signal register value during the counter counting period, the temporary signal register value remains unchanged, and the maximum value comparison continues until the counting ends, entering state 2; The threshold detection time meets the system indicator to allow RTK to pull up the post-processing and the processing time when the signal power changes; S323: State 2: Calculate the maximum value in the temporary register and set it in the detection threshold register, and enter state 3. The formula is: Detection threshold = temporary register rate value + fluctuation range S324: State 3: After waiting for one FPGA working clock, it returns to state 0 and restarts detection, and the state machine works in a loop.
6. The method for adaptively setting a detection threshold based on a periodic pulse signal according to claim 1, characterized in that: The S33 comprises the following sub-steps: S331: assign the maximum value +1dBm in the temporary register to the noise threshold of the adaptive dynamic threshold register; S332: Determine whether the detection signal is noise: If the detection signal is less than the noise threshold, the detection signal + 3dBm is assigned to the noise threshold of the adaptive dynamic threshold register; If the detection signal value is greater than or equal to the noise threshold, it is a noise signal, and the output signal, width maintenance indication, and switch operation are stopped; S333: Before waiting for the next detection signal to be detected, the noise threshold remains unchanged: If the detection signal becomes larger and exceeds the noise threshold, the valid signal, the interference signal and the width indication are output at the same time, allowing the communication system to process the program time. When the new sound threshold is updated, only the valid signal is output, which has no impact on the communication system. If the detection signal becomes smaller, both the effective signal and the interference signal have not reached the noise threshold, and there is no output within the program processing time allowed by the communication system. When the new sound threshold is updated, only the effective signal is output, which has no impact on the communication system.
7. The method for adaptively setting a detection threshold based on a periodic pulse signal according to claim 1, characterized in that: Also included are the steps for glitch signals for the sampling clock period: S41: Assume that the value sampled by the first clock is A, the value sampled by the second clock is B, and the value sampled by the third clock is C. The adaptive signal threshold setting program sets the judgment conditions: AB>9 and CB>9 and (AC<4 or CA<4), then the maximum value sampled by the second clock is invalid, which solves the occasional glitches from unknown sources inside the ADC chip.