Pipelined successive approximation analog-to-digital converter and second order gain error shaping method

Abstract

The application discloses a pipeline successive approximation analog-to-digital converter and a second-order gain error shaping method. The analog-to-digital converter comprises a first-stage successive approximation analog-to-digital converter, an inter-stage amplifier, a second-stage successive approximation analog-to-digital converter and a gain error shaping circuit. The method comprises the following steps: performing digital domain calculation on the output code value of the second stage in the last two periods to obtain a feedback code value; sampling and quantizing a first input signal to output a first digital code value; subtracting the feedback code value from the residual voltage of the first stage and amplifying the result through the inter-stage amplifier; performing backfilling on the second stage in a novel way to obtain a second digital code value; and integrating the first digital code value and the second digital code value to obtain an output code value. The application can suppress in-band leakage noise in normal working timing, and the novel backfilling method of the second stage avoids backfilling error generated in the backfilling process. The application can be widely applied in the technical field of mixed signal circuits.

Description

Technical Field

[0001] This application relates to the field of mixed-signal circuit technology, and in particular to a pipelined successive approximation analog-to-digital converter and a second-order gain error shaping method. Background Technology

[0002] Analog-to-digital converters (ADCs) serve as a bridge between analog and digital signals, playing a crucial role in converting various physical information from nature into digital information that is easy to store and process. Pipelined SAR ADCs combine the advantages of both pipelined ADCs and SAR ADCs. However, due to the introduction of interstage amplifiers, a large part of the accuracy requirements of pipelined SAR ADCs are transferred to the interstage amplifiers. But with advanced technology, it is difficult to design interstage amplifiers with high gain to meet the accuracy requirements of the ADC, because the interstage amplifiers need to meet the accuracy requirements of the entire ADC; otherwise, the ADC's SNR will drop significantly.

[0003] Related techniques include calibrating gain error in the digital domain through calibration methods. However, the background calibration techniques used in this method suffer from slow convergence speed, making it impossible to provide a long convergence time for calibration results in some application scenarios. Furthermore, the calibration results of this method are correlated with the input signal, introducing additional nonlinearity. Another related technique involves eliminating gain error through the design of the interstage amplifier by increasing the equivalent loop gain of the interstage amplifier. However, this method increases the output load of the interstage amplifier by introducing new capacitors, requiring higher dynamic settling performance from the interstage amplifier. Additionally, the introduction of an extra stage reduces the amplification time for the interstage amplifier, limiting the speed of the ADC.

[0004] In summary, the technical problems existing in the relevant technologies need to be improved. Summary of the Invention

[0005] The main objective of this application is to propose a pipelined successive approximation analog-to-digital converter and a second-order gain error shaping method, which is mainly applied to high-precision analog-to-digital converters. It can solve the problem of difficult capacitor value manufacturing process under high precision without introducing additional timing processes, and provides a novel code value compensation scheme, thereby suppressing leakage noise caused by amplifier gain error in the signal band during normal operation.

[0006] To achieve the above objectives, one aspect of this application proposes a high-precision pipelined successive approximation analog-to-digital converter (ADC). The ADC includes a first-stage successive approximation ADC, an interstage amplifier, a second-stage successive approximation ADC, and a gain error shaping circuit. The first-stage successive approximation ADC, the interstage amplifier, and the second-stage successive approximation ADC are sequentially connected. The gain error shaping circuit is connected to both the first-stage and second-stage successive approximation ADCs via a feedback loop.

[0007] The first-stage successive approximation analog-to-digital converter is used to sample the input signal and perform quantization processing to obtain the first-stage digital code value;

[0008] The amplifier is used to acquire the difference between the margin signal of the first-stage analog-to-digital converter and the feedback signal and amplify it to obtain the amplified second-stage input signal.

[0009] The second-stage successive approximation analog-to-digital converter is used to sample and quantize the output signal of the amplifier to obtain the second-stage digital code value;

[0010] The gain error shaping circuit is used to perform noise high-pass shaping on the amplifier's gain error based on the first margin signal and the second digital code value, so that the in-band noise of the output code value is high-pass shaped.

[0011] In some embodiments, the transfer function of the analog-to-digital converter is specifically as follows:

[0012]

[0013] In the above formula, D OUT V represents the output code value of the analog-to-digital converter. in Δ represents the input signal, Q1 represents the gain error of the analog-to-digital converter, Q2 represents the margin voltage of the first-stage successive approximation analog-to-digital converter, G represents the amplification factor of the analog-to-digital converter, and Z represents the Laplace variable.

[0014] In some embodiments, the analog-to-digital converter further includes a register, a frequency divider, and an adder array, wherein:

[0015] The register is used to store the feedback code value of the previous cycle;

[0016] The frequency divider is used to divide the feedback code value of the previous cycle to obtain a first feedback code value and a second feedback code value.

[0017] The adder array is used to calculate the feedback code value for the current period by combining the first feedback code value and the second feedback code value.

[0018] To achieve the above objectives, another aspect of this application proposes a second-order gain error shaping method for a pipelined successive approximation analog-to-digital converter, the method comprising the following steps:

[0019] The output code values ​​of the second-stage successive approximation analog-to-digital converter in the previous two cycles are obtained and digital domain calculations are performed to obtain the feedback code value. The digital domain calculation represents the sum of the interstage gain and the residual error signal of the first-stage successive approximation analog-to-digital converter after reducing the interstage gain by one-tenth. The interstage gain represents the amplification factor of the interstage amplifier.

[0020] The first input signal is sampled and quantized by the first-stage successive approximation analog-to-digital converter, and the first digital code value is output.

[0021] Obtain the upper-stage board margin voltage of the first-stage successive approximation analog-to-digital converter and subtract it from the feedback code value to obtain the interstage amplifier input signal;

[0022] The interstage amplifier input signal is amplified by an interstage amplifier to obtain an amplified interstage amplifier input signal.

[0023] Based on the output code value of the second-stage successive approximation analog-to-digital converter in the previous cycle, the second-stage successive approximation analog-to-digital converter is back-compensated, and the amplified interstage amplifier input signal is sampled to obtain the second digital code value.

[0024] The first digital code value and the second digital code value are integrated to obtain the output code value of the analog-to-digital converter.

[0025] In some embodiments, after the sampling operation of the first-stage successive approximation analog-to-digital converter (ADC) is completed, the sampling operation of the second-stage successive approximation ADC is performed simultaneously with the amplification operation of the interstage amplifier. After the sampling operation of the second-stage successive approximation ADC is completed, the conversion operation of the second-stage successive approximation ADC is performed simultaneously with the sampling operation of the first-stage successive approximation ADC in the next cycle, forming a pipeline cycle.

[0026] In some embodiments, the number of bits in the feedback code value is determined by the number of bits in the second-stage successive approximation analog-to-digital converter.

[0027] In some embodiments, based on the CDAC capacitor arrays in the first-stage successive approximation analog-to-digital converter and the second-stage successive approximation analog-to-digital converter, a GES CDAC capacitor array is introduced, and the upper-level board of the CDAC capacitor array is connected to the upper-level board of the GES CDAC capacitor array to form a parallel structure. The total capacitance value of the GES CDAC capacitor array is one-tenth of the interstage gain of the total capacitance value of the CDAC capacitor array.

[0028] In some embodiments, the total capacitance value of the GES CDAC capacitor array and the total capacitance value of the CDAC capacitor array are controlled by a reference voltage scaling method. The reference voltage includes a first reference voltage and a second reference voltage. The sampling and quantization of the first-stage successive approximation analog-to-digital converter uses the first reference voltage, and the sampling and quantization of the second-stage successive approximation analog-to-digital converter uses the second reference voltage.

[0029] In some embodiments, the relationship between the first-level reference voltage and the second-level reference voltage is expressed as follows:

[0030] V ref1 =4V ref2

[0031] In the above formula, V ref1 This represents the first-level reference voltage, V. ref2 This indicates the second-level reference voltage.

[0032] In some embodiments, the method further includes performing noise high-pass shaping based on the output code value of the analog-to-digital converter to obtain a noise-shaped output code value.

[0033] The embodiments of this application include at least the following beneficial effects: This application provides a high-precision pipelined successive approximation analog-to-digital converter and a second-order gain error shaping method. This scheme obtains the feedback code value by acquiring the output code value of the second-stage successive approximation analog-to-digital converter in the previous two cycles and performing digital domain calculation; it samples and quantizes the first input signal through the first-stage successive approximation analog-to-digital converter and outputs the first digital code value; it obtains the upper-stage board margin voltage of the first-stage successive approximation analog-to-digital converter and subtracts it from the feedback code value to obtain the interstage amplifier input signal. This eliminates the need for additional timing processes, improving the adaptability of the analog-to-digital converter. Furthermore, the interstage amplifier output signal is further processed by the interstage amplifier. The input signal is amplified to obtain the amplified input signal of the interstage amplifier. Then, based on the output code value of the second-stage successive approximation analog-to-digital converter in the previous cycle, the second-stage successive approximation analog-to-digital converter is back-compensated, and the amplified input signal of the interstage amplifier is sampled to obtain the second digital code value. The processed feedback code value with the same polarity is added to the output of the interstage amplifier to eliminate the code value fed back at the input of the interstage amplifier. Finally, the first digital code value and the second digital code value are integrated to obtain the output code value of the analog-to-digital converter. By introducing gain error shaping of the feedback loop in the normal operating timing, the leakage noise caused by the gain error of the interstage amplifier in the signal band is suppressed. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of a pipelined successive approximation analog-to-digital converter provided in an embodiment of this application;

[0035] Figure 2 This is a schematic diagram of the steps of a second-order gain error shaping method for a pipelined successive approximation analog-to-digital converter provided in an embodiment of this application;

[0036] Figure 3 This is a schematic diagram of the signal flow during the feedback loop signal sampling stage provided in an embodiment of this application;

[0037] Figure 4 This is a schematic diagram of the signal flow in the first-stage SAR conversion phase of the feedback loop signal provided in the embodiments of this application;

[0038] Figure 5 This is a schematic diagram of the signal flow of the first-stage feedback phase of the feedback loop signal provided in the embodiments of this application;

[0039] Figure 6 This is a schematic diagram of the signal flow during the feedback loop signal amplification stage provided in an embodiment of this application;

[0040] Figure 7 This is a schematic diagram illustrating the acquisition of the second-order feedback code value provided in an embodiment of this application;

[0041] Figure 8 This is a schematic diagram of the spectrum curve without GES under a 10% gain error provided in the embodiments of this application;

[0042] Figure 9 This is a schematic diagram of the spectrum curves of a second-order GES with a gain error of 10% provided in the embodiments of this application. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit it. In the following description, when referring to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this application; they are merely examples of systems and methods consistent with some aspects of the embodiments of this application as detailed in the appended claims.

[0044] It is understood that the terms “first,” “second,” etc., used in this application may be used herein to describe various concepts, but unless otherwise stated, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the words “if,” “when,” or “in response to a determination” as used herein may be interpreted as “when…” or “when…” or “in response to a determination.”

[0045] As used in this application, the terms "at least one", "multiple", "each", "any", etc., "at least one" includes one, two or more, "multiple" includes two or more, "each" refers to each of the corresponding multiples, and "any" refers to any one of the multiples.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0047] Before providing a detailed description of the embodiments of this application, some of the nouns and terms involved in the embodiments of this application will be explained first. The nouns and terms involved in the embodiments of this application are subject to the following interpretations.

[0048] 1) Analog-to-Digital Converters (ADCs) act as a bridge between analog and digital signals, playing a crucial role in converting various physical information from nature into easily stored and processed digital information. High-speed, high-precision ADCs are widely used in consumer electronics, medical devices, communication equipment, and testing instruments. Currently, research in the ultra-high precision field (SNDR > 90dB) aims to overcome the limitations of traditional ADC architectures in terms of accuracy and speed. Novel hybrid architectures have been extensively studied due to their superior performance. In particular, research on pipelined successive approximation ADCs is increasing, demonstrating the unique advantages of this structure.

[0049] 2) Pipelined SAR ADCs combine pipelined ADCs and SAR ADCs. Since each stage of a SAR ADC typically has a high bit depth, a two-stage structure is generally adopted, consisting of a first-stage SAR ADC, an analog-to-digital converter (ADC), and a second-stage SAR ADC. The SAR ADC's sampling switch, DAC, and ADC together form a gain-multiplying DAC (MDAC). In a pipelined SAR ADC, there is no need for a front-end sample-and-hold circuit; the DAC in the first-stage subpipeline directly performs the sampling and subtraction of the input signal.

[0050] It's also worth noting that pipelined successive approximation ADCs fully combine the advantages of both architectures. Traditional pipelined ADCs typically require a front-end sample-and-hold circuit. In pipelined SAR ADCs, because the SAR ADC replaces the traditional sub-ADC and sub-DAC, the sample-and-hold circuit is integrated into the DAC, eliminating the need for an additional circuit. Furthermore, using a SAR ADC instead of the Flash structure in a pipelined ADC allows for very high precision per bit, significantly reducing area and power consumption. Compared to traditional N-bit SAR ADCs, the two-stage design greatly reduces the precision requirements of the comparator. The addition of an analog-to-digital converter attenuates noise in the second stage, simplifying subsequent design. Moreover, dividing the N bits into N1+N2 significantly reduces the total capacitance area.

[0051] Because of the introduction of analog-to-digital converters, a large part of the accuracy requirements of pipelined successive approximation ADCs are transferred to the analog-to-digital converters. However, with advanced technology, it is difficult to design interstage amplifiers with high gain to meet the accuracy requirements of the ADC, because the analog-to-digital converters need to meet the accuracy requirements of the entire ADC; otherwise, the ADC's SNR will drop significantly.

[0052] Some shortcomings exist in related technologies, such as calibrating gain errors in the digital domain through calibration methods. One approach incorporates a position weight calibration system into the ADC, including a first-stage quantization unit, an interstage amplifier, a second-stage quantization unit, a background gain calibration control logic circuit, a front-end position weight calibration control logic circuit, and a digital reconstruction module. By injecting a pseudo-random PN signal into the second DAC module to track the gain changes of the interstage amplifier in real time, background calibration of the interstage amplifier is performed. The actual gain of the interstage amplifier obtained from background calibration is combined with the proportional relationship between the position weights of the second DAC module obtained from front-end calibration to obtain the real-time position weights. These are then combined with the first-stage and second-stage digital codes to reconstruct the signal. However, the background calibration technique used in this method suffers from slow convergence speed, which cannot provide a long convergence time to wait for calibration results in some application scenarios. Furthermore, the calibration results of this method are correlated with the input signal, introducing additional nonlinearity.

[0053] Some shortcomings remain in related technologies, such as eliminating gain errors through increasing the equivalent loop gain of the interstage amplifier from the design perspective. One approach involves introducing a technique called correlated level shifting. This involves adding a level shift stage after sampling and amplification in a traditional MDAC. By using a CLS capacitor to shift the amplitude of the interstage amplifier's output voltage, the input of the interstage amplifier is brought closer to the virtual point, thus achieving an equivalent loop gain that is squared. On an interstage amplifier with a 30dB loop gain, an equivalent 60dB loop gain can be obtained, achieving true track-to-track amplification. However, this technique increases the output load of the interstage amplifier due to the introduction of new capacitors, requiring higher dynamic settling performance. Furthermore, the additional stage reduces the amplification time for the interstage amplifier, limiting the ADC's speed.

[0054] In summary, the related technologies have the disadvantages of long convergence time for digital calibration and the introduction of additional nonlinearity related to the input signal. Furthermore, the related level shifting technology, due to the introduction of more load capacitance and the addition of new timing, places higher demands on the dynamic settling performance of the interstage amplifier, thus limiting the speed of the ADC.

[0055] In view of this, this application provides a high-precision pipelined successive approximation analog-to-digital converter. By calculating the feedback code value in the digital domain from the output code value of the second stage in the previous two cycles, scaling the interstage gain by one-half, and then superimposing it with opposite polarity onto the margin voltage of the upper plate after the first stage successive approximation ADC conversion, which is the input terminal of the interstage amplifier. At the same time, the unscaled code value is compensated with the same polarity during sampling in the second stage successive approximation ADC. This results in high-pass shaping of the leakage noise caused by gain error in the final output transfer function, reducing the noise within the signal bandwidth and greatly improving the accuracy reduction of the entire ADC caused by the gain error of the analog-to-digital converter.

[0056] Reference Figure 1 , Figure 1 A flowchart of a high-precision pipelined successive approximation analog-to-digital converter provided in this embodiment of the invention is shown below. Figure 1 The analog-to-digital converter (ADC) includes a first-stage successive approximation ADC (SAR ADC1), an interstage amplifier (EA), a second-stage successive approximation ADC (SAR ADC2), and a gain error shaping circuit. The first-stage successive approximation ADC, the interstage amplifier, and the second-stage successive approximation ADC are connected sequentially. The gain error shaping circuit is connected to both the first-stage and second-stage successive approximation ADCs via a feedback loop.

[0057] The first-stage successive approximation analog-to-digital converter is used to sample the input signal and perform quantization processing to obtain the first-stage digital code value;

[0058] The amplifier is used to obtain the difference between the margin signal and the feedback signal of the first-stage analog-to-digital converter and amplify it to obtain the amplified input signal of the second stage.

[0059] The second-stage successive approximation analog-to-digital converter is used to sample and quantize the output signal of the amplifier to obtain the second-stage digital code value;

[0060] The gain error shaping circuit is used to perform noise high-pass shaping on the amplifier's gain error based on the first margin signal and the second digital code value, so that the in-band noise of the output code value is high-pass shaped.

[0061] Furthermore, it should be noted that the analog-to-digital converter in this embodiment of the invention also includes a register, a frequency divider, and an adder array. The register is used to store the feedback code value of the previous cycle; the frequency divider is used to divide the feedback code value of the previous cycle to obtain a first feedback code value and a second feedback code value; and the adder array is used to calculate the first feedback code value and the second feedback code value to obtain the feedback code value of the current cycle.

[0062] Furthermore, it should be noted that in the embodiments of the present invention, as... Figure 1 As shown, according to Mason's formula, the input-output transfer function of the signal flow graph can be listed. If the feedback loop of the gain error shaping technique is not introduced, the transfer function of the system is expressed as follows:

[0063] D OUT =V in +ΔQ1-Q2 / G

[0064] In the above formula, D OUT V represents the output code value of the ADC. in Δ represents the input signal, Δ represents the gain error of the interstage amplifier, Q1 represents the margin voltage of the first-stage SAR ADC1, Q2 represents the margin voltage of the second-stage SAR ADC2, and G represents the amplification factor of the analog-to-digital converter.

[0065] As can be seen, due to the gain error Δ of the interstage amplifier, a first-stage quantization noise leakage of ΔQ1 occurs in the final transfer function. This leakage noise overwhelms the ADC's quantization noise in the frequency spectrum. The larger the value of Δ, the greater the leakage noise and the greater the resulting decrease in accuracy.

[0066] After introducing a feedback loop for gain error shaping, the transfer function of the system is expressed as follows:

[0067]

[0068] In the above formula, D OUT V represents the output code value of the analog-to-digital converter. in Δ represents the input signal, Q1 represents the gain error of the analog-to-digital converter, Q2 represents the margin voltage of the first-stage successive approximation analog-to-digital converter, G represents the amplification factor of the analog-to-digital converter, and Z represents the Laplace variable.

[0069] As can be seen in this transfer function, the leakage noise ΔQ1 that causes the decrease in accuracy is multiplied by a second-order high-pass shaping function. In the spectrum, this can achieve the effect of high-pass shaping of the leakage noise within the signal bandwidth, thereby increasing the effective number of bits of the ADC.

[0070] Please see Figure 2 This application also provides a second-order gain error shaping method for a high-precision pipelined successive approximation analog-to-digital converter, which can realize the above-mentioned pipelined successive approximation analog-to-digital converter. The system includes:

[0071] S100. Obtain the output code value of the second-stage successive approximation analog-to-digital converter in the previous two cycles and perform digital domain calculation to obtain the feedback code value. The digital domain calculation represents the sum of the interstage gain and the residual error signal of the first-stage successive approximation analog-to-digital converter after reducing the interstage gain by one-tenth. The interstage gain represents the amplification factor of the interstage amplifier.

[0072] S200: The first input signal is sampled and quantized by the first-stage successive approximation analog-to-digital converter, and the first digital code value is output.

[0073] It should be noted that in some embodiments, the feedback code value is calculated and determined by the output result of the second-stage successive approximation analog-to-digital converter (ADC). Specifically, this includes setting the amplification factor of the ADC; dividing the output result of the second-stage successive approximation ADC in the previous cycle by the amplification factor to obtain a scaled output result of the second-stage successive approximation ADC in the previous cycle; and calculating the feedback code value by combining the scaled output result of the second-stage successive approximation ADC in the previous cycle with the output result of the second-stage successive approximation ADC in the current cycle.

[0074] Specifically, the embodiments of the present invention employ a second-order gain error shaping method, thus requiring code value information for two cycles. The specific implementation is as follows: Figure 7 As shown, the output signal of the second stage is divided by two using a frequency divider. The divided signals are then stored in the register arrays corresponding to the code values ​​from the previous two cycles. When the enable signal for the first stage conversion is active, an adder array calculates the previously stored code values ​​from the previous two cycles to obtain a 7-bit digital code, which serves as the feedback code value for the current cycle. This process does not introduce additional timing procedures and does not affect the overall workflow of the Pipelined SAR ADC, demonstrating significant advantages and adaptability.

[0075] S300: Obtain the upper-stage board margin voltage of the first-stage successive approximation analog-to-digital converter and subtract it from the feedback code value to obtain the interstage amplifier input signal;

[0076] S400: The interstage amplifier input signal is amplified by the interstage amplifier to obtain the amplified interstage amplifier input signal;

[0077] S500: Based on the output code value of the second-stage successive approximation analog-to-digital converter in the previous cycle, the second-stage successive approximation analog-to-digital converter is back-compensated, and the amplified interstage amplifier input signal is sampled to obtain the second digital code value;

[0078] S600. Add the first digital code value and the second digital code value to obtain the output code value of the analog-to-digital converter.

[0079] In summary, the implementation principle of this invention is to use the first-stage SAR ADC1 to receive the input signal V. in (i.e., the first input signal), and simultaneously outputs the D1 digital code value. At this time, the margin signal of the upper stage of SAR ADC1 is Q1. The signal obtained by subtracting the feedback code value from Q1 is used as the input signal of the interstage amplifier (i.e., the second input signal) for amplification. While amplification is in progress, SAR ADC2 samples the output of the interstage amplifier. By adding the feedback code value to the lower stage of SAR ADC2 while SAR ADC2 is sampling, the feedback amount added to the input of the interstage amplifier is canceled out. Finally, SAR ADC2 outputs the D2 digital code value, which is added to D1 to obtain the total ADC code value. Compared with the ordinary Pipelined SAR ADC architecture, this architecture introduces two feedback loops on the basis of the overall Pipelined SAR ADC architecture. The first feedback loop scales the processed feedback code value by 1 / G and adds it with the opposite polarity to the margin of the first-stage SAR ADC before giving it to the input of the interstage amplifier. The second feedback loop directly adds the processed feedback code value with the same polarity to the output of the interstage amplifier, eliminating the code value fed back at the input of the interstage amplifier. This does not affect the overall operation of the ADC. Specifically, the output code value of the second stage in the previous cycle is scaled by half the interstage gain and then superimposed with the opposite polarity onto the margin voltage of the upper plate after the first stage successively approximates the ADC conversion, which is the input of the interstage amplifier. At the same time, the unscaled code value is compensated with the same polarity during the second stage successively approximates the ADC sampling. This results in high-pass shaping of the leakage noise caused by the gain error in the final output transfer function, reducing the noise within the signal bandwidth and greatly improving the accuracy reduction of the entire ADC caused by the gain error of the analog-to-digital converter.

[0080] Specifically, the number of bits in the feedback code value is determined based on the number of bits in the second-stage successive approximation analog-to-digital converter, thereby reducing the compensation error caused by the number of bits in the feedback during the second-stage compensation process.

[0081] Furthermore, it should be noted that the 18-bit high-precision Pipelined SAR ADC used in this embodiment of the invention has a gain of 512 times, which is a very large gain. Therefore, when scaling the main CDAC array, considering the feasibility of the manufacturing process, it is difficult to achieve a unit capacitor value that meets the requirements for the number of feedback code bits. Considering that the amplified signal does not exceed the quantization range of the second-stage ADC, the reference voltage of the second-stage ADC is scaled to one-quarter of that of the first stage. Similarly, the scaling of the reference voltage can be added to the first-stage GES CDAC array, thus allowing for the design of a minimum unit capacitor value that is feasible in the manufacturing process. Regarding the selection of the number of feedback bits, since the code value after second-order gain error shaping will have a gain of twice, and two reference voltages V differing by a factor of four are provided... ref1 =4V ref2 Therefore, the high N2-3 bits of the second-level code value are selected as the feedback code value. After calculation, an N2-2 bit second-order feedback code value is obtained. This N2-2 bit feedback code value is fed back to all the low bits of the second-level ADC except for the MSB bit. At the same time, the low MSB-1 bits are used with V during code value backfilling. ref1 As its reference voltage, the high MSB bit still uses V. ref2 Using this as a reference voltage, an equivalent double gain is achieved. This process can completely compensate for the feedback signal subtracted from the amplifier input, avoiding the generation of compensation error. That is, the second-order gain error shaping in this embodiment of the invention can be summarized as follows:

[0082] 1) Signal sampling stage, such as Figure 3 As shown, at this time, the first-stage SAR ADC is in the sampling phase, the interstage amplifier is in the reset state, and the second-stage SAR ADC converts the value sampled in the previous cycle, with the reference voltage being V. ref2 .

[0083] 2) First-stage SAR ADC conversion phase, such as Figure 4 As shown, according to the successive approximation logic, the lower plate of the main CDAC array switches the potential, the GES CDAC array is in a reset state, the interstage amplifier is in a reset state, and the second-stage SAR ADC continues to convert the output of the interstage amplifier in the previous cycle.

[0084] 3) First-level SAR feedback stage, such as Figure 5 As shown, the signal triggered by the first-stage SAR conversion adds the feedback code value stored in the register to the lower plate of the GES CDAC, using a reference voltage of V. ref2 This process involves subtracting the residual difference from the top plate of the first-stage CDAC. The interstage amplifier is in the reset phase, at which point the second-stage conversion ends, and the feedback code value for that cycle is stored in the register.

[0085] 4) Scale-up stage, such as Figure 6 As shown, the first-stage SAR ADC remains unchanged, the interstage amplifier starts working, and the upper plate of the second-stage CDAC samples the output signal of the interstage amplifier. Simultaneously, the MSB of the second-stage CDAC is in the hold-reset phase, and a feedback code value of opposite polarity is added to the lower MSB-1 base plate. The reference voltage is V. ref1 This cancels out the amplified feedback signal from the interstage amplifier input. Finally, the second-stage SAR ADC converts the canceled signal, and the first-stage SAR ADC re-enters the sampling stage. The two ADCs complete the sampling and conversion in a pipeline manner.

[0086] Furthermore, it should be noted that, such as Figure 8 and Figure 9 As shown, for an 18-bit Pipelined SAR ADC, the output code value after FFT is plotted when a 10% gain error is introduced by the analog-to-digital converter. It can be seen that without GES (Gas-Effective Synergistic) technology, a 10% gain error in the Pipelined SAR ADC leads to significant noise in the output spectrum, severely impacting the effective bit depth of the ADC. With second-order GES, it is evident that the noise in the low-frequency spectrum is significantly suppressed, which can generally be addressed with a small oversampling. The plotted spectrum, with an oversampling factor of five, shows that compared to without GES, the effective bit depth of the output increases from 15.49 bits to 17.66 bits after adding second-order GES, powerfully demonstrating the effectiveness of this technology in mitigating the accuracy degradation caused by interstage gain errors in the interstage amplifier.

[0087] It is understood that the content of the above method embodiments is applicable to this system embodiment. The specific functions implemented in this system embodiment are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those achieved in the above method embodiments.

[0088] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A pipelined successive approximation analog-to-digital converter, characterized in that, The analog-to-digital converter (ADC) includes a first-stage successive approximation ADC, an interstage amplifier, a second-stage successive approximation ADC, and a gain error shaping circuit. The first-stage successive approximation ADC, the interstage amplifier, and the second-stage successive approximation ADC are connected sequentially. The gain error shaping circuit is connected to both the first-stage and second-stage successive approximation ADCs via a feedback loop. The first-stage successive approximation analog-to-digital converter is used to sample the first input signal and perform quantization processing to obtain the first-stage digital code value; The interstage amplifier is used to obtain the difference between the margin voltage of the first-stage successive approximation analog-to-digital converter and the feedback code value of the current period, and amplify it to obtain the amplified interstage amplifier input signal; wherein, the feedback code value of the current period is determined by the output code value of the second-stage successive approximation analog-to-digital converter in the previous two periods and the current period. The second-stage successive approximation analog-to-digital converter is used to sample and quantize the amplified interstage amplifier input signal output by the interstage amplifier to obtain the second-stage digital code value. The gain error shaping circuit is used to determine the output code value of the analog-to-digital converter based on the margin voltage of the first-stage successive approximation analog-to-digital converter and the digital code value of the second stage, and to perform noise high-pass shaping on the gain error of the interstage amplifier based on the output code value of the analog-to-digital converter to obtain the noise-shaped output code value. The feedback loop includes a first feedback loop and a second feedback loop. The gain error shaping circuit is connected to the upper-level board of the first-stage successive approximation analog-to-digital converter (ADC) through the first feedback loop, and the gain error shaping circuit is connected to the lower-level board of the second-stage successive approximation ADC through the second feedback loop. The first feedback loop is used to superimpose the feedback code value of the current period onto the margin voltage of the upper-level board of the first-stage successive approximation ADC. The second feedback loop is used to superimpose the feedback code value of the current period onto the lower-level board of the second-stage successive approximation ADC to achieve code value compensation for the second-stage successive approximation ADC.

2. The pipelined successive approximation analog-to-digital converter according to claim 1, characterized in that, The transfer function of the analog-to-digital converter is as follows: In the above formula, This represents the output code value of the analog-to-digital converter. Indicates the input signal. This indicates the gain error of the analog-to-digital converter. This represents the margin voltage of the first-stage successive approximation analog-to-digital converter. This represents the margin voltage of the second-stage successive approximation analog-to-digital converter. Indicates the amplification factor of the analog-to-digital converter. This represents a Laplace variable.

3. A pipelined successive approximation analog-to-digital converter according to claim 1, characterized in that, The analog-to-digital converter also includes a register, a frequency divider, and an adder array, wherein: The register is used to store the feedback code values ​​of the previous two cycles and the current cycle; The frequency divider is used to divide the feedback code values ​​of the previous two cycles and the current cycle to obtain a first feedback code value and a second feedback code value. The adder array is used to calculate the feedback code value for the current period by combining the first feedback code value and the second feedback code value.

4. A second-order gain error shaping method for a pipelined successive approximation analog-to-digital converter, applied to a pipelined successive approximation analog-to-digital converter as described in any one of claims 1-3, characterized in that, The method includes the following steps: The output code values ​​of the second-stage successive approximation analog-to-digital converter in the previous two cycles and the current cycle are obtained and digital domain calculations are performed to obtain the feedback code value of the current cycle. The first input signal is sampled and quantized by the first-stage successive approximation analog-to-digital converter, and the first-stage digital code value is output. Obtain the margin voltage of the first-stage successive approximation analog-to-digital converter and subtract it from the feedback code value of the current period to obtain the interstage amplifier input signal; The interstage amplifier input signal is amplified by an interstage amplifier to obtain an amplified interstage amplifier input signal. Based on the output code value of the second-stage successive approximation analog-to-digital converter in the previous two cycles and the current cycle, the second-stage successive approximation analog-to-digital converter is back-compensated, and the amplified input signal of the interstage amplifier is sampled to obtain the second-stage digital code value; The first-level digital code value and the second-level digital code value are integrated to obtain the output code value of the analog-to-digital converter.

5. The method according to claim 4, characterized in that, After the sampling operation of the first-stage successive approximation analog-to-digital converter (ADC) is completed, the sampling operation of the second-stage successive approximation ADC and the amplification operation of the interstage amplifier are performed simultaneously. After the sampling operation of the second-stage successive approximation ADC is completed, the conversion operation of the second-stage successive approximation ADC and the sampling operation of the first-stage successive approximation ADC in the next cycle are performed simultaneously, forming a pipeline cycle.

6. The method according to claim 4, characterized in that, The number of bits in the feedback code value is determined by the number of bits in the second-stage successive approximation analog-to-digital converter.

7. The method according to claim 4, characterized in that, Based on the CDAC capacitor arrays in the first-stage successive approximation analog-to-digital converter and the second-stage successive approximation analog-to-digital converter, a GES CDAC capacitor array is introduced. The upper-level board of the CDAC capacitor array is connected to the upper-level board of the GES CDAC capacitor array to form a parallel structure. The total capacitance value of the GES CDAC capacitor array is one-tenth of the interstage gain of the total capacitance value of the CDAC capacitor array.

8. The method according to claim 7, characterized in that, The total capacitance value of the GESCDAC capacitor array and the total capacitance value of the CDAC capacitor array are controlled by a reference voltage scaling method. The reference voltage includes a first reference voltage and a second reference voltage. The sampling and quantization of the first-stage successive approximation analog-to-digital converter uses the first reference voltage, and the sampling and quantization of the second-stage successive approximation analog-to-digital converter uses the second reference voltage.

9. The method according to claim 8, characterized in that, The relationship between the first reference voltage and the second reference voltage is expressed as follows: In the above formula, Indicates the first reference voltage. This indicates the second reference voltage.

10. The method according to claim 4, characterized in that, It also includes performing noise high-pass shaping based on the output code value of the analog-to-digital converter to obtain the noise-shaped input signal.

Images