A capacitive mismatch foreground calibration method suitable for SAR ADC

Abstract

The application relates to a capacitor mismatch foreground calibration method suitable for a SARADC, wherein the capacitor mismatch foreground calibration method comprises the following steps: S1, inputting an analog input signal, a random dithering signal and a dynamic element into a capacitor type digital-to-analog converter; S2, comparing the output of the capacitor type digital-to-analog converter with a reference point through a comparator, and storing the obtained output digital code; S3, calculating the evaluation value of the corresponding output digital code; S4, obtaining the error between the actual output value and the evaluation value of the reference output value; S5, using an LMS algorithm to iteratively adjust the capacitor weight and the random signal according to the error size; and S6, continuously adjusting the capacitor weight and the random signal so that the error is within the allowable range, and more accurate output is obtained. The application does not need to increase an additional analog circuit for capacitor mismatch calibration, and obviously improves the effective bit number and the spur-free dynamic range and other parameters of the ADC.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of digital-analog hybrid integrated circuit design, and particularly relates to a capacitor mismatch foreground digital calibration method suitable for a SAR ADC (successive approximation analog-to-digital converter). BACKGROUND

[0002] As a bridge between analog signals and digital signals, an analog-to-digital converter is widely used in fields such as communication radars, medical images and audio processing. Among them, a successive approximation analog-to-digital converter (SAR ADC) is an ADC structure based on a binary search algorithm, which is composed of an input sampling switch, a DAC array, a comparator and a SAR digital control logic module, and has a simple structure and superior energy efficiency, and thus becomes a mainstream architecture in fields such as medium speed, medium accuracy and low power consumption. However, due to the chip production and manufacturing process, the DAC capacitor often has a mismatch problem, which seriously affects the performance of the SAR ADC.

[0003] At present, the calibration technology for capacitor mismatch is mainly digital calibration technology, in which the calibration technology that an additional periodic calibration phase is performed before the SAR ADC normally works is called foreground calibration. The least mean square (LMS) algorithm is a common algorithm applied to capacitor mismatch digital calibration. The LMS circuit is equivalent to an adaptive filter circuit, which constantly updates the weight coefficient of the filter to make the difference between the target signal and the filter output signal infinitely small and tend to zero. The LMS algorithm is also called a stochastic gradient algorithm. Since the samples are different, the direction of weight adjustment each time also has randomness, but overall, it is adjusted in the optimal direction. Using the LMS algorithm for mismatch calibration can effectively eliminate error terms and achieve fast convergence.

[0004] However, although the foreground digital calibration has a relatively small hardware overhead, the calibration process mostly excessively relies on the input signal, has a slow convergence speed, has a great influence on the conversion process of the SAR ADC, and is not conducive to deep calibration. Therefore, a capacitor mismatch calibration method without additional circuit and with fast calibration convergence speed is needed, which can not only achieve calibration but also achieve fast convergence effect, and effectively improve the effective number of bits and the spurious-free dynamic range of the SAR ADC. SUMMARY

[0005] In view of the deficiencies of the existing calibration technology for capacitor array mismatch, the application provides a capacitor mismatch foreground digital calibration method for a SAR ADC.

[0006] To achieve the above purpose, the technical scheme adopted by the application is as follows:

[0007] A capacitor mismatch foreground calibration method suitable for a SAR ADC, comprising the following steps:

[0008] S1. Analog input signal, random jitter signal and dynamic element matching are input to capacitive digital-to-analog converter (CDAC);

[0009] S2. The output of CDAC is compared with the reference point by a comparator, and the output digital code is stored.

[0010] S3. Calculate the evaluation value of the corresponding output digital code;

[0011] S4. Calculate the error between the actual output value and the estimated reference output value;

[0012] S5. Use the LMS algorithm to iterate the capacitor weights and random signal according to the error magnitude;

[0013] S6. Continuously change the capacitor weights and random signals to keep the error within the allowable range and obtain a more accurate output.

[0014] In one embodiment, S1 specifically involves setting the analog input signal to zero and simultaneously applying it to the capacitor array of the CDAC along with the random jitter signal and the dynamic element. This random signal is denoted as r(n). The capacitor array includes a first capacitor array and a second capacitor array. The first capacitor array consists of high M-bit quantization capacitors (MSB) and the second capacitor array consists of low (NM)-bit quantization capacitors (LSB), where M is a positive integer not greater than N.

[0015] In one embodiment, S2 specifically involves switching the pre-charge phase and charge redistribution phase sequentially from the high bit to the low bit, comparing the output point of the CDAC with the reference point using a comparator, switching the capacitor array according to the comparator output, performing successive approximation comparisons, and storing the resulting digital output code.

[0016] In one embodiment, the switching process of the capacitor array in S2 includes:

[0017] The base plate of the capacitor array is connected to the input signal being sampled, and the top plate of the capacitor array is grounded. When the sampling phase ends, the first comparison phase begins. Starting from the most significant bit of the MSB capacitor, calibration is performed from the most significant bit to the least significant bit. The base plate of the most significant bit capacitor connected to the inverting input of the comparator is switched to the power supply voltage VREF, and the base plate of the remaining capacitors is switched to ground GND.

[0018] After the above switching operation is completed, the comparator starts to work. If the comparison result is negative, the voltage corresponding to the highest-order capacitor switches to GND, and the voltage corresponding to the second-highest-order capacitor switches to VREF. If the comparison result is positive, the voltage corresponding to the highest-order capacitor remains unchanged, and the voltage corresponding to the second-highest-order capacitor switches to VREF.

[0019] Repeat the above comparison and switching operations until the last comparison result is output, and the entire successive approximation process is completed.

[0020] In one embodiment, the formula for calculating S3 is:

[0021]

[0022] in, For the actual output, W i (n) represents the weight of the i-th capacitor, D i (n) represents the output numeric code of the i-th bit.

[0023] In one embodiment, the formula for calculating S4 is:

[0024]

[0025] Where Error(n) is the error. V is an estimate of the theoretical output value. OUT This is the output value.

[0026] In one embodiment, in S5, the iterative formulas for the capacitor weights and the random signal are as follows:

[0027]

[0028] r(n+1)=r(n)-μ r Error(n);

[0029] In the formula, μ W and μ r These are the weight convergence factor and the random signal convergence factor in the LMS algorithm, respectively.

[0030] In one embodiment, W is calculated using the iterative formula. i By updating r to the next sampling conversion cycle, the preset values ​​of capacitor weights and the size of the injected random signal can be continuously changed, ultimately keeping the error within the allowable range.

[0031] In one embodiment, μ W The value of μ is 1 / 256. r The value range is 0.005 to 0.01.

[0032] The beneficial effects of this invention are as follows: The SAR ADC pre-conversion digital calibration method transforms the non-ideal characteristic of comparator mismatch into the desired output value in the LMS algorithm. Simultaneously, it combines jitter and dynamic component matching algorithms to increase the randomness of capacitor selection, thereby converging and optimizing capacitor weights globally. The calibration algorithm is completed before normal ADC conversion, requiring no additional analog circuitry, and the calibration parameters converge quickly, achieving good calibration results with low hardware overhead. After calibration, the overall effective bit depth and spurious-free dynamic range are significantly improved. Attached Figure Description

[0033] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the embodiments of the invention to explain the invention and do not constitute a limitation thereof.

[0034] Figure 1 This is a schematic flowchart of a capacitance mismatch front-end calibration method for SAR ADCs according to an embodiment of the present invention.

[0035] Figure 2 This is a schematic diagram illustrating the working principle of the capacitance mismatch front-end calibration method for SAR ADC according to an embodiment of the present invention.

[0036] Figure 3 This is a schematic diagram of the dynamic performance of the SAR ADC before calibration.

[0037] Figure 4 This is a schematic diagram of the dynamic performance of the SAR ADC after calibration. Detailed Implementation

[0038] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the following embodiments and features described therein can be combined with each other.

[0039] like Figure 2As shown, the SAR ADC includes a sample-and-hold circuit, an N-bit quantization capacitor array, SAR logic, a comparator, and a serial-to-parallel converter (SR). The sample-and-hold circuit has two modes: tracking and holding. In tracking mode, it samples the rapidly changing analog input signal, while in holding mode, it maintains the acquired signal unchanged during quantization. The N-bit quantization capacitor array consists of capacitors arranged in ascending order of their weight values, representing the 0th to N-1th quantization capacitors. It is further divided into a first capacitor array and a second capacitor array. The first capacitor array consists of the high M-bit quantization capacitors (MSB), and the second capacitor array consists of the low (NM)-bit quantization capacitors (LSB), where M is a positive integer not greater than N. The upper plates of the N-bit quantization capacitor array are connected in parallel to serve as the output of the capacitor array, which is then connected to the inverting input of the comparator. The number of bits in the capacitors in the first and second capacitor arrays increases sequentially, moving away from the comparator. In the first capacitor array, the lower plates of multiple capacitors are connected in parallel and then connected to the input signal, SAR logic, ground voltage GND, or the corresponding reference voltage VREF (typically the power supply voltage). In the second capacitor array, the lower plates of multiple capacitors are connected in parallel and then connected to the SAR logic, ground voltage GND, or the corresponding reference voltage VREF. The SAR logic is used to control capacitor switching during the conversion process. The comparator is used to compare the quantized value of the input signal with the reference output value. The positive input terminal of the comparator is grounded to GND. The input terminal of the SR circuit is connected to the output terminal of the comparator, and the output terminal of the SR circuit is connected to the output terminal of the ADC circuit.

[0040] In a SAR ADC, the ADC operates in two modes: calibration mode and normal operation mode. Calibration mode is used for digital front-end calibration to obtain the optimal weights for the N-bit capacitors; normal conversion mode is used for normal sampling and quantization output. Unlike normal conversion mode, calibration mode injects a disturbance by changing the connection of a capacitor switch at a specific bit in the capacitor array before sampling. The quantized value of the disturbance is then iterated through the LMS calibration module to preserve the optimal weights for calibration output in normal conversion mode. The working process in calibration mode is described in detail below.

[0041] like Figure 1 and 2 As shown, a capacitance mismatch front-end calibration method suitable for SAR ADCs includes the following steps:

[0042] S1, Analog input signal, random jitter signal and dynamic element matched input to capacitive digital-to-analog converter (CDAC).

[0043] Specifically, the analog input signal is set to zero, the ADC samples the input signal, and the input signal is applied to the capacitive digital-to-analog converter (CDAC). At this time, the digital random dither signal and the dynamic element matching (DEM) technique are applied to the CDAC array simultaneously, denoted as random signal r(n), and superimposed with the analog input signal to obtain a composite signal.

[0044] S2. The output of CDAC is compared with the reference point by a comparator, and the output digital code is stored.

[0045] Specifically, from the high bit to the low bit, the pre-charge phase and charge redistribution phase are switched sequentially. The output point of the CDAC is compared with the reference point by the comparator. The control module switches the capacitor array according to the output of the comparator, performs successive approximation comparisons, and stores the obtained digital output code.

[0046] For the switching process of the capacitor array: the base plate of the capacitor array is connected to the input signal being sampled, and the top plate of the capacitor array is grounded. After the sampling phase ends, the first comparison phase begins. Starting from the highest bit of the quantization capacitor (MSB) in the high M-bit phase, calibration proceeds from the highest bit to the lowest bit. The base plate of the highest bit capacitor connected to the inverting input of the comparator is switched to VREF (typically the power supply voltage), and the base plates of the remaining capacitors are switched to GND. After the above switching operation is completed, the comparator starts working. If the comparison result is negative, the voltage corresponding to the highest bit capacitor switches to GND, and the voltage corresponding to the second highest bit capacitor switches to VREF; if the comparison result is positive, the voltage corresponding to the highest bit capacitor remains unchanged, and the voltage corresponding to the second highest bit capacitor switches to VREF. This comparison and switching operation is repeated until the last bit of the comparison result is output, completing the entire successive approximation process.

[0047] S3. Calculate the evaluation value of the corresponding output digital code and eliminate the influence of randomly injected signals to obtain the output.

[0048]

[0049] In the formula, W i Let D be the weight of the i-th capacitor. i Output the numeric code for the i-th bit;

[0050] When the effect of capacitor mismatch is ignored, the obtained output value should be an output with comparator offset and non-ideal characteristics, denoted as X. REF_OS This is the theoretical output value; however, the theoretical output value cannot be obtained through direct calculation or simulation. Therefore, let the estimated value of the quantized theoretical output value be... get:

[0051]

[0052] In the formula, V OUT This is the output value.

[0053] The calibration module specifically uses the LMS adaptive method, which includes three modules: error calculation, weight iterative calculation, and perturbation iterative calculation.

[0054] S4. Calculate the error between the actual output value and the estimated reference output value.

[0055] Specifically, the quantization result of the injected perturbation is input into the error calculation module. The error calculation module calculates the difference between the actual output and the reference output value to obtain the error Error(n):

[0056]

[0057] Right now,

[0058] Ideally, the size of Error should be zero, but non-ideal factors such as capacitor mismatch cause the actual result to be non-zero, so further processing of Error is required.

[0059] S5. Use the LMS algorithm to iterate over the capacitor weights and random signal based on the error magnitude.

[0060] Specifically, the Error is placed into the weight iteration module and perturbation iteration module of the LMS feedback loop. Non-zero Error values ​​drive the feedback loop to implement an adaptive LMS loop, continuously iterating based on each error to obtain new weights and perturbation values, providing new parameters for the next error calculation. The weight iteration formula and perturbation iteration formula are as follows:

[0061]

[0062] r(n+1)=r(n)-μ r Error(n);

[0063] Where, μ W and μ r These are the weight convergence factor and the random signal convergence factor in the LMS algorithm, respectively.

[0064] S6. Continuously change the capacitor weights and random signals to keep the error within the allowable range and obtain a more accurate output.

[0065] Specifically, W calculated using the iterative formula iBy updating r to the next sampling conversion cycle, the preset values ​​of capacitor weights and the magnitude of the injected random signal can be continuously changed; ultimately keeping Error within the allowable error range (e.g., Error ≤ VREF*(1 / 2)). N This means completing the pre-processing calibration for capacitor mismatch, resulting in a more accurate output.

[0066] After a certain number of iterations, if the error (Error) is within the allowable range or after a certain number of iterations, the current weight is used as the calibrated weight of the SAR ADC. When the SAR ADC performs a normal conversion, the quantized value obtained from the conversion is added to the compensation calibration value, thus completing the capacitor mismatch pre-conversion calibration and ultimately obtaining a more accurate output after calibration.

[0067] The value of the convergence factor μ affects the convergence speed of the LMS algorithm and the accuracy and steady-state error of the calibrated system. A larger value of μ speeds up the convergence time of the calibration algorithm, but negatively impacts both the system's accuracy and steady-state error. Conversely, a smaller value of μ improves the system's accuracy and steady-state error, but significantly increases the convergence time. Therefore, it is necessary to find a suitable convergence factor μ to strike a balance between the convergence speed of the LMS algorithm and the system's accuracy and steady-state error.

[0068] Simulations were performed using the convergence factor μ as a variable, and the average values ​​of ENOB and SFDR after multiple calibrations (e.g., 100, 200, or 500 times) were used as a reference. Analysis of the simulation results shows that when the convergence factor μ is large, the LMS algorithm fails to converge. Even when convergence is achieved, the steady-state error caused by the weights oscillating around their stable values ​​severely impacts the system's calibration performance. However, when the convergence factor μ meets the accuracy requirements, the SAR ADC after mismatch calibration can achieve the desired performance. Further reducing the convergence factor μ significantly increases the SAR ADC's convergence step size while the performance improvement after calibration is limited. Based on the analysis of the simulation results, when μ... W The value of μ is 1 / 256. r When the value range is 0.005 to 0.01, the accuracy and convergence speed of this calibration method can be reasonably balanced.

[0069] Figure 3 and 4 The dynamic performance of the SAR ADC before and after calibration is shown. Signal-to-noise ratio (SNDR) and spurious-free dynamic range (SFDR) are important indicators for evaluating the dynamic performance of an ADC. Effective number of bits (ENOB) refers to the actual resolution achievable by the ADC after considering various noises and harmonics. Capacitor mismatch introduces nonlinear errors during the actual conversion process of a SAR ADC, directly affecting the SFDR (Signal Response Rate) and SNDR (Signal Response Rate), thereby reducing the ADC's ENOB (Engineering Error Bypass). Figure 3 and Figure 4 As can be seen, the ENOB, SNDR, and SFDR after calibration are significantly improved, and the capacitance mismatch calibration effect of the SAR ADC is significantly improved.

[0070] This invention proposes a capacitance mismatch calibration method for SAR ADCs. Combining DEM and pseudo-random jitter signals, it directly utilizes a CDAC array for calibration, eliminating the need for additional capacitors and analog circuitry, thus significantly reducing circuit area and power consumption. The method evaluates the theoretical input voltage using the actual output digital code and applies the LMS algorithm to iteratively update the capacitor weights and random signals to minimize errors, thereby obtaining the actual weight of each capacitor and effectively correcting capacitance mismatch. This invention achieves good calibration results with low hardware overhead, improving dynamic parameters such as the circuit's signal-to-noise ratio and spurious-free dynamic range.

[0071] The foregoing has shown and described the basic principles, main features, and application effects of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. A capacitance mismatch pre-contact calibration method suitable for SAR ADCs, characterized in that, Includes the following steps: S1. The analog input signal, random jitter signal, and dynamic element matching are jointly input to the capacitor-type digital-to-analog converter (CDAC). Specifically, the analog input signal is set to zero, and the random jitter signal and dynamic element matching are simultaneously applied to the capacitor array of the CDAC, denoted as random signal r(n). The capacitor array includes a first capacitor array and a second capacitor array. The first capacitor array is a high M-bit quantization capacitor MSB, and the second capacitor array is a low (NM)-bit quantization capacitor LSB, where M is a positive integer not greater than N. S2. The output of CDAC is compared with the reference point by a comparator, and the output digital code is stored. S3. Calculate the evaluation value of the corresponding output digital code. The calculation formula is as follows: in, For the actual output, W i (n) represents the weight of the i-th capacitor, D i (n) represents the output numeric code of the i-th bit; S4. Calculate the error between the actual output value and the estimated reference output value. The calculation formula is as follows: Where Error(n) is the error. V is an estimate of the theoretical output value. OUT This is the output value; S5. Using the LMS algorithm, iterate over the capacitor weights and random signal based on the error magnitude. The iteration formulas for the capacitor weights and random signal are as follows: r(n+1)=r(n)-μ r Error(n); In the formula, μ W and μ r These are the weight convergence factor and the random signal convergence factor in the LMS algorithm, respectively. S6. Continuously change the capacitor weights and random signals to keep the error within the allowable range and obtain a more accurate output.

2. The method according to claim 1, characterized in that, Specifically, S2 involves switching between the pre-charge phase and the charge redistribution phase sequentially from the high bit to the low bit. The output point of the CDAC is compared with the reference point by the comparator. The capacitor array is switched according to the output of the comparator to perform successive approximation comparisons, and the resulting digital output code is stored.

3. The method according to claim 2, characterized in that, In S2, the switching process of the capacitor array includes: The base plate of the capacitor array is connected to the input signal being sampled, and the top plate of the capacitor array is grounded. When the sampling phase ends, the first comparison phase begins. Starting from the most significant bit of the MSB capacitor, calibration is performed from the most significant bit to the least significant bit. The base plate of the most significant bit capacitor connected to the inverting input of the comparator is switched to the power supply voltage VREF, and the base plate of the remaining capacitors is switched to ground GND. After the above switching operation is completed, the comparator starts to work. If the comparison result is negative, the voltage corresponding to the highest-order capacitor switches to GND, and the voltage corresponding to the second-highest-order capacitor switches to VREF. If the comparison result is positive, the voltage corresponding to the highest-order capacitor remains unchanged, and the voltage corresponding to the second-highest-order capacitor switches to VREF. Repeat the above comparison and switching operations until the last comparison result is output, and the entire successive approximation process is completed.

4. The method according to claim 3, characterized in that, S6 specifically refers to: calculating W using the iterative formula. i By updating r(n) and r(n) to the next sampling conversion cycle, the preset values ​​of capacitor weights and the size of the injected random signal can be continuously changed, ultimately keeping Error(n) within the allowable error range.

5. The method according to claim 3, characterized in that, μ W The value of μ is 1 / 256. r The value range is 0.005 to 0.01.

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