FPGA Bitstream Fast Compression Method and System

Abstract

The present invention relates to the technical field of FPGA bitstream compression, and a method and system for fast compression of FPGA bitstreams, including: traversing line numbers in a target multi-layer index structure, identifying a data block group, a feature value group, and the number of data blocks corresponding to the line numbers, determining whether the number of data blocks is a preset number, if it is the preset number, then determining whether there is a subsequent single data block group set, if there is, then merging the data block group with the subsequent single data block group set to obtain a merged data block group, if not, then using the data block group as the original data block group, if it is not the preset number, then determining whether there are the same feature values in the feature value group, if there are, then compressing the data block group to obtain a compressed data block group, if not, then using the data block group as the original data block group, and performing bitstream recombination on the merged data block group set, the compressed data block group set, and the original data block group set. The present invention can solve the problems of poor overall compression effect of FPGA bitstream data and relatively large consumption of computing resources.

Description

Technical Field

[0001] The present invention relates to the technical field of FPGA bitstream compression, and particularly to a method and system for fast compression of FPGA bitstreams. Background Art

[0002] FPGA (Field Programmable Gate Array) has been widely used in the design of electronic systems. When an FPGA works, it needs to rely on bitstream data written externally for configuration. By downloading the bitstream data into the corresponding FPGA chip, specific functions can be achieved. As the amount of information in the bitstream data written to the FPGA increases, the time consumed to transfer the bitstream data from the external to the FPGA chip becomes longer, thereby resulting in an extended configuration time of the FPGA.

[0003] To shorten the configuration time of the FPGA, usually the configuration bitstream is compressed to shorten the bitstream length and reduce the configuration time. However, the existing compression method for the configuration bitstream reduces the compression granularity to bytes, that is, when compressing the bitstream data, it is necessary to traverse the bitstream byte by byte. This compression method can provide a good compression effect for complex bitstream data. However, due to the boundary diminishing reason, the overall compression effect is not improved significantly and too much computing resources are occupied. Summary of the Invention

[0004] The present invention provides a method and system for fast compression of FPGA bitstreams, and its main purpose is to solve the problems of poor overall compression effect and large consumption of computing resources of FPGA bitstream data.

[0005] To achieve the above object, a method for fast compression of FPGA bitstreams provided by the present invention includes:

[0006] Parse the pre-constructed original bitstream to obtain the data to be compressed, and divide the data to be compressed according to the preset number of bits per unit, to obtain a set of data blocks, where the number of bits per unit refers to the number of bits written to the storage RAM at one time;

[0007] Extract data blocks from the set of data blocks in sequence, identify the frame type, region type and line number of the data blocks, and calculate the hash value of the data blocks by using the pre-constructed cryptographic hash algorithm;

[0008] Fill the frame type, region type, line number, hash value and data block of the data block into the pre-constructed initial multi-layer index structure to obtain a target multi-layer index structure;

[0009] Traverse the line numbers in the target multi-layer index structure, and identify the data block group, eigenvalue group and number of data blocks corresponding to the line numbers;

[0010] Determine whether the number of the data blocks is a preset number;

[0011] If the number of the data blocks is the preset number, determine whether there is a subsequent single data block group set for the data block group, where the subsequent single data block group set refers to a set of data block groups with the number of data blocks being the preset number after the data block group;

[0012] If there is a subsequent single data block group set for the data block group, merge the data block group and the subsequent single data block group set to obtain a merged data block group;

[0013] If there is no subsequent single data block group set for the data block group, use the data block group as the original data block group;

[0014] If the number of the data blocks is not the preset number, determine whether there are identical eigenvalue in the eigenvalue group;

[0015] If there are identical eigenvalue in the eigenvalue group, compress the data block group to obtain a compressed data block group;

[0016] If there are no identical eigenvalue in the eigenvalue group, use the data block group as the original data block group;

[0017] Collect the merged data block group, the compressed data block group and the original data block group to obtain a merged data block group set, a compressed data block group set and an original data block group set, and perform bitstream recombination on the merged data block group set, the compressed data block group set and the original data block group set by using the target multi-layer index structure to complete fast compression of the FPGA bitstream.

[0018] Optionally, parsing the pre-constructed original bitstream to obtain the data to be compressed includes:

[0019] Identify a specification field in the original bitstream, and extract a preamble bitstream from the original bitstream according to the specification field;

[0020] Parse the preamble bitstream to obtain preamble information, where the preamble information includes: whether the original bitstream has been compressed, the data specification of the original bitstream, and the bitstream length;

[0021] Extract the data to be compressed from the original bitstream according to the bitstream length in the preamble information.

[0022] Optionally, calculating the hash value of the data block by using a pre-constructed cryptographic hash algorithm includes:

[0023] Use the pre-constructed cryptographic hash algorithm to splice the data block into a binary string with a first preset number of bits;

[0024] Pad the binary string of the first preset number of digits to obtain a padded string, where the length of the padded string is the smallest integer multiple of the second preset number of digits;

[0025] Calculate the hash value of the padded string according to the cryptographic hash algorithm to obtain the hash value of the data block.

[0026] Optionally, before filling the frame type, region type, line number, hash value, and data block of the data block into the pre-constructed initial multi-level index structure to obtain the target multi-level index structure, the method further includes:

[0027] Identify the frame type sequence, region type sequence, and line number sequence of the data block set;

[0028] Construct a frame type hierarchy, a region type hierarchy, and a line number hierarchy according to the frame type sequence, region type sequence, and line number sequence respectively;

[0029] Perform associated indexing on the frame type hierarchy, region type hierarchy, and line number hierarchy to obtain an index hierarchy;

[0030] Construct a data block eigenvalue hierarchy and a data block data hierarchy;

[0031] Construct the initial multi-level index structure according to the index hierarchy, data block eigenvalue hierarchy, and data block data hierarchy.

[0032] Optionally, the filling the frame type, region type, line number, hash value, and data block of the data block into the pre-constructed initial multi-level index structure to obtain the target multi-level index structure includes:

[0033] Identify the frame type hierarchy position of the frame type in the frame type hierarchy, identify the region type hierarchy position of the region type in the region type hierarchy, and identify the line number hierarchy position of the line number in the line number hierarchy;

[0034] Determine the index path of the hash value according to the frame type hierarchy position, region type hierarchy position, and line number hierarchy position;

[0035] Identify the eigenvalue hierarchy position and data hierarchy position of the hash value in the data block eigenvalue hierarchy and data block data hierarchy respectively according to the index path;

[0036] Fill the hash value into the eigenvalue hierarchy position and fill the data block into the data hierarchy position until all data blocks in the data block set are filled to obtain the target multi-level index structure.

[0037] Optionally, traversing the line numbers in the target multi-level index structure and identifying the data block group, eigenvalue group, and number of data blocks corresponding to the line numbers includes:

[0038] Successively extract the frame types to be traversed in the frame type sequence, and identify the sequence of area types to be traversed included in the frame types to be traversed;

[0039] Successively extract the area types to be traversed in the sequence of area types to be traversed, and identify the sequence of line numbers to be traversed included in the area types to be traversed;

[0040] Successively extract the line numbers to be traversed in the sequence of line numbers to be traversed, and identify the eigenvalue group, data block group, and number of data blocks corresponding to the line numbers to be traversed.

[0041] Optionally, determining whether there is a subsequent single data block group set for the data block group includes:

[0042] Identify the subsequent line numbers of the line numbers, and obtain the data block group corresponding to the subsequent line numbers;

[0043] Identify the number of data blocks in the data block group corresponding to the subsequent line numbers;

[0044] Determine whether the number of data blocks in the data block group corresponding to the subsequent line numbers is 1;

[0045] If the number of data blocks in the data block group corresponding to the subsequent line numbers is not 1, then there is no subsequent single data block group set for the data block group;

[0046] If the number of data blocks in the data block group corresponding to the subsequent line numbers is 1, then there is a subsequent single data block group set for the data block group.

[0047] Optionally, compressing the data block group to obtain a compressed data block group includes:

[0048] In multiple specific data blocks with the same eigenvalue, obtain the position information of the remaining specific data blocks after the first specific data block;

[0049] Combine the content of the specific data block and the position information of the remaining specific data blocks to obtain a compressed data block group. Optionally, using the target multi-level index structure to perform bitstream recombination on the merged data block group set, compressed data block group set, and original data block group set includes:

[0050] According to the target multi-level index structure, identify the bitstream order of the merged data block group, compressed data block group, and original data block group in the merged data block group set, compressed data block group set, and original data block group set;

[0051] Combine the merged data block group set, the compressed data block group set, and the original data block group set according to the bitstream order to obtain a data block group sequence;

[0052] Obtain the bitstream specification information of the data block group sequence;

[0053] Identify the head position and the tail position of the data block group sequence, and supplement the bitstream specification information to the head position and the tail position of the data block group sequence to obtain an initial reorganized bitstream;

[0054] Calculate the cyclic redundancy check information of the data block group sequence, identify the tail position of the initial reorganized bitstream, and supplement the cyclic redundancy check information to the tail position of the initial reorganized bitstream to complete the bitstream reorganization.

[0055] To achieve the above object, the present invention also provides an FPGA bitstream fast compression system, including:

[0056] A position information and hash value calculation module, which is used to parse a pre-constructed original bitstream to obtain data to be compressed, divide the data to be compressed according to a preset number of bits per unit, where the number of bits per unit refers to the number of bits written to the storage RAM at one time, extract data blocks from the data block set in sequence, identify the frame type, region type, and line number of the data block, and calculate the hash value of the data block using a pre-constructed cryptographic hash algorithm;

[0057] A target multi-layer index structure construction module, which is used to fill the frame type, region type, line number, hash value, and data block of the data block into a pre-constructed initial multi-layer index structure to obtain a target multi-layer index structure;

[0058] A data block group compression module, which is used to traverse the line numbers in the target multi-layer index structure, identify the data block group, eigenvalue group, and the number of data blocks corresponding to the line numbers; determine whether the number of data blocks is a preset number; if the number of data blocks is a preset number, then determine whether the data block group has a subsequent single data block group set, where the subsequent single data block group set refers to a set of data block groups with a preset number of data blocks following the data block group; if the data block group has a subsequent single data block group set, then merge the data block group with the subsequent single data block group set to obtain a merged data block group; if the data block group does not have a subsequent single data block group set, then use the data block group as an original data block group; if the number of data blocks is not a preset number, then determine whether there are the same eigenvalues in the eigenvalue group; if there are the same eigenvalues in the eigenvalue group, then compress the data block group to obtain a compressed data block group; if there are no the same eigenvalues in the eigenvalue group, then use the data block group as an original data block group;

[0059] A bitstream recombination module is configured to collect the merged data block groups, compressed data block groups, and original data block groups to obtain a merged data block group set, a compressed data block group set, and an original data block group set, and perform bitstream recombination on the merged data block group set, the compressed data block group set, and the original data block group set by using the target multi-layer index structure.

[0060] To solve the above problems, the present invention further provides an electronic device, which includes:

[0061] A memory that stores at least one instruction; and a processor that executes the instruction stored in the memory to implement the FPGA bitstream fast compression method described above.

[0062] To solve the above problems, the present invention further provides a computer-readable storage medium, in which at least one instruction is stored, and the at least one instruction is executed by a processor in an electronic device to implement the FPGA bitstream fast compression method described above.

[0063] To solve the problems described in the background art, the present invention first needs to parse the original code stream to obtain the data to be compressed, and then divide the data to be compressed according to the number of unit bits to obtain a set of data blocks. At this time, the frame type, region type, and line number of each data block can be identified, and the hash value of the data block can be calculated using a pre-constructed cryptographic hash algorithm. After obtaining the position information and hash value of the data block, it is necessary to traverse each data block in the set of data blocks. Therefore, the frame type, region type, line number, hash value, and data block of the data block can be filled into the initial multi-layer index structure to obtain the target multi-layer index structure, so as to facilitate traversing the data block. At this time, the line number can be traversed in the target multi-layer index structure, and the data block group, eigenvalue group, and number of data blocks corresponding to the line number can be identified. When compressing the data block group, there are three types of data block groups, and different data block group types correspond to different compression methods. First, it is judged whether the number of data blocks is a preset number. If the number of data blocks is a preset number, it is judged whether there is a subsequent single data block group set for the data block group. If there is a subsequent single data block group set for the data block group, the data block group and the subsequent single data block group set are merged to obtain a merged data block group. If the number of data blocks is not a preset number, it is judged whether there are the same eigenvalues in the eigenvalue group. If there are the same eigenvalues in the eigenvalue group, the data block group is compressed to obtain a compressed data block group. If there are no the same eigenvalues in the eigenvalue group, the data block group is used as the original data block group. Finally, the merged data block group, compressed data block group, and original data block group are collected to obtain a merged data block group set, a compressed data block group set, and an original data block group set, and then the target multi-layer index structure is used to perform bitstream recombination on the merged data block group set, compressed data block group set, and original data block group set, so as to complete the fast compression of the FPGA bitstream. Therefore, the present invention can solve the problems of poor overall compression effect and more computing resources occupied by the FPGA bitstream data. Description of the Drawings

[0064] Figure 1 It is a schematic flowchart of a method for fast compression of an FPGA bitstream provided by an embodiment of the present invention;

[0065] Figure 2 It is a target multi-layer index structure provided by an embodiment of the present invention;

[0066] Figure 3 It is a schematic diagram of data block group compression provided by an embodiment of the present invention;

[0067] Figure 4 It is a functional module diagram of a fast compression system for an FPGA bitstream provided by an embodiment of the present invention;

[0068] Figure 5A schematic diagram of the structure of an electronic device for implementing the FPGA code stream fast compression method provided by an embodiment of the present invention.

[0069] Description of reference numerals:

[0070] 1. Electronic device; 10. Processor; 11. Memory; 12. Bus; 100. FPGA code stream fast compression system; 101. Position information and hash value calculation module; 102. Target multi-layer index structure construction module; 103. Data block group compression module; 104. Code stream reorganization module.

[0071] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0072] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0073] The embodiment of the present application provides a method for fast compression of FPGA code streams. The execution subject of the method for fast compression of FPGA code streams includes but is not limited to at least one of the electronic devices such as a server and a terminal that can be configured to execute the method provided in the embodiment of the present application. In other words, the method for fast compression of FPGA code streams can be executed by software or hardware installed in a terminal device or a server device, and the software can be a blockchain platform. The server includes but is not limited to: a single server, a server cluster, a cloud server or a cloud server cluster, etc.

[0074] Reference Figure 1 FIG. 1 is a flow chart of a method for rapidly compressing an FPGA bitstream provided by an embodiment of the present invention. In this embodiment, the method for rapidly compressing an FPGA bitstream includes:

[0075] S1. Parse the pre-constructed original code stream to obtain data to be compressed, and divide the data to be compressed according to a preset number of unit bits to obtain a data block set.

[0076] Furthermore, the unit bit quantity refers to the number of bits written to the storage RAM at one time.

[0077] It is understandable that the original code stream refers to the code stream data of the FPGA, which is designed by the user, and is generated according to the FPGA code stream configuration library after processes such as synthesis, layout, and routing. FPGA chips need to rely on externally written code stream data for configuration. By downloading the original code stream to the corresponding FPGA chip, specific functions can be achieved. FPGA (Field Programmable Gate Array) is widely used in electronic system design.

[0078] It is understandable that the data to be compressed refers to the data in the original code stream that needs to be compressed. The data block set refers to the set of data blocks waiting to be compressed obtained after dividing the data to be compressed according to the number of bits per unit. Different from other methods that compress the original code stream with bytes as the basic compression unit, in the embodiments of the present invention, the number of bits of the data block used as the basic compression unit is the same as the number of bits written by the storage RAM at one time, which will greatly simplify the decompression process and improve the efficiency of the entire process.

[0079] In the embodiments of the present invention, parsing the pre-constructed original code stream to obtain the data to be compressed includes:

[0080] Identifying a specification field in the original code stream, and extracting a preamble code stream from the original code stream according to the specification field;

[0081] Parsing the preamble code stream to obtain preamble information, where the preamble information includes: whether the original code stream has been compressed, the data specification of the original code stream, and the code stream length;

[0082] Extracting the data to be compressed from the original code stream according to the code stream length in the preamble information.

[0083] It is understandable that the specification field refers to the field in the original code stream that records the data specification of the code stream. The preamble code stream refers to the code stream that records the preamble information of the original code stream.

[0084] Further, after the extraction of the preamble information is completed, it is also necessary to extract and store a postamble code stream from the original code stream by using the specification field for combining with the compressed data to form a complete code stream.

[0085] S2. Sequentially extract data blocks from the data block set, identify the frame type, region type, and row number of the data block, and calculate the hash value of the data block by using a pre-constructed cryptographic hash algorithm.

[0086] It is understandable that the frame type (frame_type) refers to the data frame type of the data block, for example: synchronization frame, data packet frame, and control frame. The region type (region_type) refers to the logical or physical region in the FPGA where the data block is stored. The row number (row_num) refers to the position serial number used to identify the data block in a specific region, reflecting the relative sequential position of the data block in the logical or physical region. The cryptographic hash algorithm refers to the irreversible cryptographic hash algorithm SHA-256.

[0087] In the embodiments of the present invention, calculating the hash value of the data block by using a pre-constructed cryptographic hash algorithm includes:

[0088] Concatenate the data blocks into a binary string of a first preset number of bits using a pre - constructed cryptographic hash algorithm;

[0089] Pad the binary string of the first preset number of bits to obtain a padded string, where the length of the padded string is the smallest integer multiple of a second preset number of bits;

[0090] Calculate the hash value of the padded string according to the cryptographic hash algorithm to obtain the hash value of the data block.

[0091] It can be understood that by using the irreversible cryptographic hash algorithm SHA - 256, the internal data of each data block is concatenated into a binary string of a first preset number of bits, padded to the length of the smallest integer multiple of a second preset number of bits, and then the hash value of the padded string is calculated according to the SHA - 256 compression function. The hash value is used as the characteristic value of the data block. The number of bits of the characteristic value is much smaller than the number of bits of the data block, and the characteristic value (hash value) corresponds one - to - one with the data block. Therefore, the characteristic value can reflect the similarities and differences between different data blocks. By comparing the characteristic values, the calculation amount can be greatly reduced, and the comparison efficiency of the similarities and differences between different data blocks can be improved.

[0092] Preferably, the first preset number of bits is 3232 bits, and the second preset number of bits is 512 bits. The cryptographic hash algorithm is the SHA - 256 algorithm.

[0093] S3. Fill the frame type, region type, line number, hash value and data block of the data block into a pre - constructed initial multi - level index structure to obtain a target multi - level index structure.

[0094] It can be understood that the initial multi - level index structure refers to a multi - level index structure constructed according to the frame type, region type, line number, data block characteristic value and data block data included in the data block set. The target multi - level index structure refers to a multi - level index structure obtained after storing the hash values and data blocks of all data blocks in the data block set according to the frame type, region type and line number.

[0095] In the embodiment of the present invention, before filling the frame type, region type, line number, hash value and data block of the data block into a pre - constructed initial multi - level index structure to obtain a target multi - level index structure, the method further includes:

[0096] Identify the frame type sequence, region type sequence and line number sequence of the data block set;

[0097] Construct a frame type hierarchy, a region type hierarchy and a line number hierarchy according to the frame type sequence, region type sequence and line number sequence respectively;

[0098] Perform an associated index on the frame type level, region type level, and line number level to obtain an index level;

[0099] Construct a data block eigenvalue level and a data block data level;

[0100] Construct the initial multi-layer index structure according to the index level, data block eigenvalue level, and data block data level.

[0101] It can be understood that the frame type sequence, region type sequence, and line number sequence respectively refer to the sequence composed of the frame types corresponding to each data block in the data block set, the sequence composed of the region types, and the sequence composed of the line numbers. The frame type level refers to the level with the frame type as the index item, the region type level refers to the level with the region type as the index item, and the line number level refers to the level with the line number as the index item. The associated index refers to the inclusive pointing association of the frame types, region types, and line numbers in the frame type level, region type level, and line number level. For example: when the frame type type0 includes the region types Top and bottom, the region type Top includes the line numbers row1, row2, row3, the region type bottom includes the line numbers row1, row2, row3, row4, row5, then the associated index can be that the frame type type0 points to the region type Top, and the region type Top points to the line numbers row1, row2, row3 respectively; the frame type type0 points to the region type bottom, and the region type bottom points to the line numbers row1, row2, row3, row4, row5 respectively. Refer to Figure 2 As shown, according to the actual storage location distribution rule of the original code stream in the storage RAM, the position information of each data block can be calculated and recorded as the index values of the first three layers. The first layer is the frame type, the second layer is the region type, and the third layer is the line number.

[0102] Furthermore, the index level refers to the three-layer index structure obtained after the frame type level, region type level, and line number level complete the inclusive pointing association. The data block eigenvalue level refers to the level with the data block eigenvalue as the index item, and the data block data level refers to the level with the data block data as the index item.

[0103] It can be explained that in the embodiment of the present invention, an initial multi-layer index structure of multi-dimensional data is constructed to index data blocks. The multi-layer index of data blocks is stored in dictionary form. Among them, the first three layers of indexes are the position information corresponding to the data blocks in the FPGA memory, the fourth layer of index is the data block eigenvalue, and the fifth layer of index is the data block data.

[0104] In the embodiment of the present invention, filling the frame type, region type, line number, hash value, and data block of the data block into a pre-constructed initial multi-level index structure to obtain a target multi-level index structure includes:

[0105] Identifying the frame type level position of the frame type in the frame type level, identifying the region type level position of the region type in the region type level, and identifying the line number level position of the line number in the line number level;

[0106] Determining the index path of the hash value according to the frame type level position, region type level position, and line number level position;

[0107] Identifying the eigenvalue level position and data level position of the hash value in the data block eigenvalue level and data block data level respectively according to the index path;

[0108] Filling the hash value into the eigenvalue level position and filling the data block into the data level position until all data blocks in the data block set are filled, to obtain a target multi-level index structure.

[0109] It can be understood that the frame type level position refers to the position of the frame type in the frame type level, the region type level position refers to the position of the region type in the region type level, and the line number level position refers to the position of the line number in the line number level. The index path refers to the index route formed by connecting the frame type level position, region type level position, and line number level position for determining the hash value and data block data. For example, when the frame type of the data block is type0, the region type is Top, and the line number is row1, then the index path is type0Toprow1 hash value (data block eigenvalue) data block data, which can be referred to Figure 2 as shown. The eigenvalue level position refers to the position of the data block eigenvalue in the data block eigenvalue level, and the data level position refers to the position of the data block data in the data block data level.

[0110] S4. Traversing the line numbers in the target multi-level index structure to identify the data block group, eigenvalue group, and number of data blocks corresponding to the line numbers.

[0111] It can be understood that the data block group refers to all data block combinations included under the line number, the eigenvalue group refers to the eigenvalue combination corresponding to the data block group, and the number of data blocks refers to the number of data blocks in the data block group.

[0112] In the embodiment of the present invention, traversing the line numbers in the target multi-level index structure to identify the data block group, eigenvalue group, and number of data blocks corresponding to the line numbers includes:

[0113] Successively extract the frame types to be traversed in the frame type sequence, and identify the sequence of area types to be traversed included in the frame types to be traversed;

[0114] Successively extract the area types to be traversed in the sequence of area types to be traversed, and identify the sequence of line numbers to be traversed included in the area types to be traversed;

[0115] Successively extract the line numbers to be traversed in the sequence of line numbers to be traversed, and identify the eigenvalue group, data block group and the number of data blocks corresponding to the line numbers to be traversed.

[0116] It can be understood that the line numbers in the multi-layer index structure can be traversed in the order from top to bottom. For example, first fix frame type 1, area type 1, and line number 1, and then traverse each data block eigenvalue included under frame type 1, area type 1, and line number 1. After that, change to another line number 2 under area type 1 for traversal until all line numbers under area type 1 are traversed. Then, change to area type 2 and fix line number 1 under area type 2, and traverse each data block eigenvalue of line number 1 under area type 2 until all data block eigenvalues included in all area types under all frame types 1 are traversed. Then, change to frame type 2 and continue traversing until all data block eigenvalues included in all frame type sequences are traversed.

[0117] S5. Judge whether the number of data blocks is a preset number.

[0118] Preferably, the preset number is 1.

[0119] If the number of data blocks is the preset number, then execute S6. Judge whether there is a subsequent single data block group set for the data block group.

[0120] Specifically, the subsequent single data block group set refers to the set of data block groups whose subsequent number of data blocks is the preset number for the data block group.

[0121] For example, when the frame type of the data block is type0, the area type is Top, and the line number is row1, and there is only 1 data block eigenvalue a under the index path corresponding to type0, Top, and row1, it means that the number of data blocks is the preset number. When there is only 1 data block eigenvalue b under the index path corresponding to type0, Top, and row2; only 1 data block eigenvalue c under the index path corresponding to type0, Top, and row3; only 1 data block eigenvalue d under the index path corresponding to type0, Top, and row4; and there are 2 data block eigenvalues e and f under the index path corresponding to type0, Top, and row5, the subsequent single data block group set is the set composed of the data blocks corresponding to b, c, and d.

[0122] In an embodiment of the present invention, determining whether there is a subsequent single data block group set for the data block group includes:

[0123] Identifying the subsequent line number of the line number, and obtaining the data block group corresponding to the subsequent line number;

[0124] Identifying the number of data blocks in the data block group corresponding to the subsequent line number;

[0125] Determining whether the number of data blocks in the data block group corresponding to the subsequent line number is 1;

[0126] If the number of data blocks in the data block group corresponding to the subsequent line number is not 1, then there is no subsequent single data block group set for the data block group;

[0127] If the number of data blocks in the data block group corresponding to the subsequent line number is 1, then there is a subsequent single data block group set for the data block group.

[0128] It can be understood that the subsequent line number refers to the next adjacent line number of the line number. For example, when the index path of the line number is type0, Top, row1, the index path of the subsequent line number can be type0, Top, row2.

[0129] If there is a subsequent single data block group set for the data block group, then execute S7, merge the data block group and the subsequent single data block group set to obtain a merged data block group.

[0130] In an embodiment of the present invention, the merged data block group refers to a combination formed by the data block group and its subsequent single data block group set.

[0131] If there is no subsequent single data block group set for the data block group, then execute S8, and use the data block group as the original data block group.

[0132] It can be explained that when the number of data blocks is a preset number and there is no subsequent single data block group set for the data block group, the data block group is not compressed.

[0133] If the number of data blocks is not the preset number, then execute S9, and determine whether there are the same eigenvalue in the eigenvalue group.

[0134] If there are the same eigenvalue in the eigenvalue group, then execute S10, and compress the data block group to obtain a compressed data block group.

[0135] It can be understood that the compressed data block group refers to the data block group obtained after compressing the data blocks corresponding to the same eigenvalue.

[0136] In an embodiment of the present invention, compressing the data block group to obtain a compressed data block group includes:

[0137] Among multiple specific data blocks with the same eigenvalue, obtain the position information of the remaining specific data blocks after the first specific data block;

[0138] Combine the content of the specific data block and the position information of the remaining specific data blocks to obtain a compressed data block group.

[0139] Further, when the number of data blocks with the same eigenvalue in the data block group is greater than 1, the first data block data and the position information of each data block can be selected in the data block group, and then these two items are recombined to obtain a new data block group, and the new data block group replaces the old data block group, so as to obtain a compressed bitstream. Keep the first data block data (uncompressed) in the order of the data blocks in the data block group, and the remaining duplicate data blocks are used as the compressed data blocks, which are replaced by the characters reflecting their position information. Please refer to Figure 3 as shown.

[0140] For example, when the data block group is ABAAB, the 1st, 3rd, and 4th data blocks have the same eigenvalue and can be grouped into the 1st compression group. The 2nd and 5th data blocks have the same eigenvalue and can be grouped into the 2nd compression group. After compressing the 1st compression group, the obtained bitstream is A+addr3,4, and after compressing the 2nd compression group, the obtained bitstream is B+addr5, thus achieving the purpose of replacing duplicate data blocks with short position information and completing the compression of the data block group.

[0141] If there are no identical eigenvalues in the eigenvalue group, execute S11: Use the data block group as the original data block group.

[0142] It can be understood that when there are no identical eigenvalues in the eigenvalue group and the number of data blocks is not the preset number, the data block group is not compressed.

[0143] S12: Aggregate the merged data block group, the compressed data block group, and the original data block group to obtain a merged data block group set, a compressed data block group set, and an original data block group set. Use the target multi-level index structure to perform bitstream recombination on the merged data block group set, the compressed data block group set, and the original data block group set to complete the fast compression of the FPGA bitstream.

[0144] In the embodiment of the present invention, the performing bitstream recombination on the merged data block group set, the compressed data block group set, and the original data block group set by using the target multi-level index structure includes:

[0145] Identify the bitstream order of the merged data block group, the compressed data block group, and the original data block group in the merged data block group set, the compressed data block group set, and the original data block group set according to the target multi-level index structure;

[0146] Combine the merged data block group set, the compressed data block group set, and the original data block group set according to the bitstream order to obtain a data block group sequence;

[0147] Obtain the bitstream specification information of the data block group sequence;

[0148] Identify the head position and the tail position of the data block group sequence, and supplement the bitstream specification information to the head position and the tail position of the data block group sequence to obtain an initial recombined bitstream;

[0149] Calculate the cyclic redundancy check information of the data block group sequence, identify the tail position of the initial recombined bitstream, and supplement the cyclic redundancy check information to the tail position of the initial recombined bitstream to complete the bitstream recombination.

[0150] It can be understood that the bitstream order refers to the order of the merged data block group, the compressed data block group, and the original data block group in the target multi-level index structure from top to bottom for each data block group. For example: when the row numbers of the merged data block group corresponding to the frame type type0 and the area type Top are row3, row4, row5, the row numbers of the compressed data block group 1 and the compressed data block group 2 are row1, row2, and the row number of the original data block group is row6, then the bitstream order is successively the compressed data block group 1, the compressed data block group 2, the merged data block group, and the original data block group, and the data block group sequence is the compressed data block group 1, the compressed data block group 2, the merged data block group, and the original data block group. The head position refers to the head position of the new bitstream composed of the data block group sequence, and the tail position refers to the tail position of the new bitstream composed of the data block group sequence. The cyclic redundancy check information can be calculated according to the information of the newly generated initial recombined bitstream. When all data frame configurations are completed, supplement the bitstream specification information at the head and tail of the new bitstream and supplement the cyclic redundancy check information after the bitstream specification information at the tail to complete the compression of the entire original bitstream.

[0151] To solve the problems described in the background art, the present invention first needs to parse the original code stream to obtain the data to be compressed, and then divide the data to be compressed according to the number of unit bits to obtain a set of data blocks. At this time, the frame type, region type, and line number of each data block can be identified, and the hash value of the data block can be calculated using a pre-constructed cryptographic hash algorithm. After obtaining the position information and hash value of the data block, it is necessary to traverse each data block in the set of data blocks. Therefore, the frame type, region type, line number, hash value, and data block of the data block can be filled into the initial multi-level index structure to obtain the target multi-level index structure, thereby facilitating the traversal of the data blocks. At this time, the line number can be traversed in the target multi-level index structure, and the data block group, eigenvalue group, and number of data blocks corresponding to the line number can be identified. When compressing the data block group, there are three types of data block groups, and different data block group types correspond to different compression methods. First, it is determined whether the number of data blocks is a preset number. If the number of data blocks is the preset number, it is determined whether there is a subsequent single data block group set for the data block group. If there is a subsequent single data block group set for the data block group, the data block group and the subsequent single data block group set are merged to obtain a merged data block group. If the number of data blocks is not the preset number, it is determined whether there are the same eigenvalues in the eigenvalue group. If there are the same eigenvalues in the eigenvalue group, the data block group is compressed to obtain a compressed data block group. If there are no the same eigenvalues in the eigenvalue group, the data block group is used as the original data block group. Finally, the merged data block group, compressed data block group, and original data block group are aggregated to obtain a merged data block group set, a compressed data block group set, and an original data block group set, and then the target multi-level index structure is used to perform bitstream recombination on the merged data block group set, compressed data block group set, and original data block group set, thereby completing the fast compression of the FPGA bitstream. Therefore, the present invention can solve the problems of poor overall compression effect of FPGA bitstream data and more computing resources occupied.

[0152] As Figure 4 shown, it is a functional module diagram of an FPGA bitstream fast compression system provided by an embodiment of the present invention.

[0153] The FPGA bitstream fast compression system 100 of the present invention can be installed in an electronic device. According to the implemented functions, the FPGA bitstream fast compression system 100 can include a position information and hash value calculation module 101, a target multi-level index structure construction module 102, a data block group compression module 103, and a bitstream recombination module 104. The modules of the present invention can also be referred to as units, which refer to a series of computer program segments that can be executed by a processor of an electronic device and can complete fixed functions, and are stored in the memory of the electronic device.

[0154] The position information and hash value calculation module 101 is configured to parse a pre-built original code stream to obtain data to be compressed, divide the data to be compressed according to a preset number of bits per unit, where the number of bits per unit refers to the number of bits written by the storage RAM at one time, to obtain a data block set. Sequentially extract data blocks from the data block set, identify the frame type, region type, and line number of the data blocks, and calculate the hash value of the data blocks using a pre-built cryptographic hash algorithm;

[0155] The target multi-layer index structure construction module 102 is configured to fill the frame type, region type, line number, hash value, and data blocks of the data blocks into a pre-built initial multi-layer index structure to obtain a target multi-layer index structure;

[0156] The data block group compression module 103 is configured to traverse the line numbers in the target multi-layer index structure, identify the data block group, eigenvalue group, and number of data blocks corresponding to the line numbers; determine whether the number of data blocks is a preset number; if the number of data blocks is the preset number, determine whether the data block group has a subsequent single data block group set, where the subsequent single data block group set refers to a set of data block groups whose subsequent number of data blocks is the preset number; if the data block group has a subsequent single data block group set, merge the data block group with the subsequent single data block group set to obtain a merged data block group; if the data block group does not have a subsequent single data block group set, use the data block group as the original data block group; if the number of data blocks is not the preset number, determine whether there are the same eigenvalues in the eigenvalue group; if there are the same eigenvalues in the eigenvalue group, compress the data block group to obtain a compressed data block group; if there are no the same eigenvalues in the eigenvalue group, use the data block group as the original data block group;

[0157] The code stream recombination module 104 is configured to collect the merged data block groups, compressed data block groups, and original data block groups to obtain a merged data block group set, a compressed data block group set, and an original data block group set, and perform code stream recombination on the merged data block group set, the compressed data block group set, and the original data block group set using the target multi-layer index structure.

[0158] Specifically, each module in the FPGA code stream fast compression system 100 in the embodiments of the present invention uses the same technical means as those in the above Figure 1 and can produce the same technical effects, which will not be elaborated here.

[0159] As Figure 5 shown, it is a schematic structural diagram of an electronic device for implementing the FPGA code stream fast compression method provided by an embodiment of the present invention.

[0160] The electronic device 1 may include a processor 10, a memory 11, and a bus 12, and may further include a computer program stored in the memory 11 and executable on the processor 10, such as an FPGA bitstream fast compression method program.

[0161] Among them, the memory 11 includes at least one type of readable storage medium, and the readable storage medium includes flash memory, mobile hard disk, multimedia card, card-type memory (such as SD or DX memory, etc.), magnetic memory, magnetic disk, optical disk, etc. In some embodiments, the memory 11 may be an internal storage unit of the electronic device 1, such as the mobile hard disk of the electronic device 1. In some other embodiments, the memory 11 may also be an external storage device of the electronic device 1, such as a plug-in mobile hard disk, a Smart Media Card (SMC), a Secure Digital (SD) card, a Flash Card, etc. equipped on the electronic device 1. Further, the memory 11 also includes the internal storage unit of the electronic device 1 and also includes an external storage device. The memory 11 can be used not only to store application software installed on the electronic device 1 and various types of data, such as the code of the FPGA bitstream fast compression method program, etc., but also to temporarily store data that has been output or will be output.

[0162] In some embodiments, the processor 10 may be composed of integrated circuits. For example, it may be composed of a single packaged integrated circuit, or may be composed of multiple integrated circuits with the same or different functions, including a combination of one or more Central Processing Units (CPUs), microprocessors, digital processing chips, graphics processors, and various control chips, etc. The processor 10 is the control core (Control Unit) of the electronic device, connecting various components of the entire electronic device through various interfaces and lines, and by running or executing programs or modules stored in the memory 11 (such as the FPGA bitstream fast compression method program, etc.), and calling data stored in the memory 11, to perform various functions of the electronic device 1 and process data.

[0163] The bus 12 may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The bus 12 can be divided into an address bus, a data bus, a control bus, etc. The bus 12 is set to achieve connection and communication between the memory 11 and at least one processor 10, etc.

[0164] Figure 5 Only an electronic device with components is shown. Those skilled in the art can understand that Figure 5 the shown structure does not constitute a limitation on the electronic device 1, and it may include fewer or more components than shown, or combine certain components, or have different component arrangements.

[0165] For example, although not shown, the electronic device 1 may further include a power source (such as a battery) for powering each component. Preferably, the power source can be logically connected to the at least one processor 10 through a power management device, so as to implement functions such as charge management, discharge management, and power consumption management through the power management device. The power source may also include any components such as one or more DC or AC power sources, a recharge device, a power failure detection circuit, a power converter or inverter, and a power status indicator. The electronic device 1 may also include various sensors, a Bluetooth module, a Wi-Fi module, etc., which will not be elaborated here.

[0166] Furthermore, the electronic device 1 may further include a network interface. Optionally, the network interface may include a wired interface and / or a wireless interface (such as a WI-FI interface, a Bluetooth interface, etc.), which is usually used to establish a communication connection between the electronic device 1 and other electronic devices.

[0167] Optionally, the electronic device 1 may further include a user interface. The user interface may be a display (Display), an input unit (such as a keyboard (Keyboard)). Optionally, the user interface may also be a standard wired interface or a wireless interface. Optionally, in some embodiments, the display may be an LED display, a liquid crystal display, a touch liquid crystal display, and an OLED (Organic Light-Emitting Diode) toucher, etc. Among them, the display may also be appropriately referred to as a display screen or a display unit, which is used to display the information processed in the electronic device 1 and to display a visual user interface.

[0168] The FPGA bitstream fast compression method program stored in the memory 11 of the electronic device 1 is a combination of multiple instructions. When running in the processor 10, it can implement:

[0169] Parse the pre-built original bitstream to obtain the data to be compressed, and segment the data to be compressed according to a preset number of bits per unit to obtain a set of data blocks, where the number of bits per unit refers to the number of bits written to the RAM at one time;

[0170] Successively extract data blocks from the set of data blocks, identify the frame type, region type, and line number of the data blocks, and calculate the hash value of the data blocks using the pre-built cryptographic hash algorithm;

[0171] Fill the frame type, region type, line number, hash value, and data block of the data block into a pre-constructed initial multi-layer index structure to obtain a target multi-layer index structure;

[0172] Traverse the line numbers in the target multi-layer index structure to identify the data block group, eigenvalue group, and the number of data blocks corresponding to the line numbers;

[0173] Judge whether the number of data blocks is a preset number;

[0174] If the number of data blocks is the preset number, then judge whether there is a subsequent single data block group set for the data block group, where the subsequent single data block group set refers to the set of data block groups with the number of data blocks being the preset number after the data block group;

[0175] If there is a subsequent single data block group set for the data block group, then merge the data block group and the subsequent single data block group set to obtain a merged data block group;

[0176] If there is no subsequent single data block group set for the data block group, then use the data block group as the original data block group;

[0177] If the number of data blocks is not the preset number, then judge whether there are the same eigenvalues in the eigenvalue group;

[0178] If there are the same eigenvalues in the eigenvalue group, then compress the data block group to obtain a compressed data block group;

[0179] If there are no same eigenvalues in the eigenvalue group, then use the data block group as the original data block group;

[0180] Collect the merged data block group, compressed data block group, and original data block group to obtain a merged data block group set, a compressed data block group set, and an original data block group set, and use the target multi-layer index structure to perform bitstream recombination on the merged data block group set, compressed data block group set, and original data block group set to complete the fast compression of the FPGA bitstream.

[0181] Specifically, the specific implementation method of the processor 10 for the above instructions can refer to Figures 1 to 5 the description of the relevant steps in the corresponding embodiment, which will not be elaborated here.

[0182] Further, if the modules / units integrated in the electronic device 1 are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. The computer-readable storage medium can be volatile or non-volatile. For example, the computer-readable medium can include: any entity or device capable of carrying the computer program code, a recording medium, a USB flash drive, a mobile hard disk, a magnetic disk, an optical disc, a computer memory, a read-only memory (ROM, Read-Only Memory).

[0183] The present invention also provides a computer-readable storage medium, where the readable storage medium stores a computer program, and when the computer program is executed by a processor of an electronic device, it can implement:

[0184] Parse a pre-constructed raw code stream to obtain data to be compressed, and segment the data to be compressed according to a preset number of bits per unit, to obtain a set of data blocks, where the number of bits per unit refers to the number of bits written by the storage RAM at one time;

[0185] Successively extract data blocks from the set of data blocks, identify the frame type, region type and line number of the data blocks, and calculate the hash value of the data blocks using a pre-constructed cryptographic hash algorithm;

[0186] Fill the frame type, region type, line number, hash value and data block of the data block into a pre-constructed initial multi-layer index structure to obtain a target multi-layer index structure;

[0187] Traverse the line numbers in the target multi-layer index structure to identify the data block group, eigenvalue group and number of data blocks corresponding to the line numbers;

[0188] Judge whether the number of data blocks is a preset number;

[0189] If the number of data blocks is a preset number, then judge whether there is a subsequent single data block group set for the data block group, where the subsequent single data block group set refers to a set of data block groups whose number of data blocks after the data block group is a preset number;

[0190] If there is a subsequent single data block group set for the data block group, then merge the data block group and the subsequent single data block group set to obtain a merged data block group;

[0191] If there is no subsequent single data block group set for the data block group, then use the data block group as the original data block group;

[0192] If the number of data blocks is not a preset number, then judge whether there are the same eigenvalues in the eigenvalue group;

[0193] If there are identical eigenvalues within the eigenvalue group, compress the data block group to obtain a compressed data block group;

[0194] If there are no identical eigenvalues within the eigenvalue group, use the data block group as the original data block group;

[0195] Collect the merged data block group, the compressed data block group, and the original data block group to obtain a merged data block group set, a compressed data block group set, and an original data block group set, and perform bitstream recombination on the merged data block group set, the compressed data block group set, and the original data block group set by using the target multi-level index structure to complete fast compression of the FPGA bitstream.

[0196] In several embodiments provided by the present invention, it should be understood that the disclosed devices, systems, and methods can be implemented in other ways. For example, the system embodiments described above are merely illustrative, and there may be other partitioning methods in actual implementation.

[0197] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0198] In addition, in each embodiment of the present invention, the functional modules can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above integrated units can be implemented in the form of hardware or in the form of a combination of hardware and software functional modules.

[0199] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above exemplary embodiments, and without departing from the spirit or basic characteristics of the present invention, the present invention can be implemented in other specific forms.

[0200] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A method for fast compression of FPGA code stream, characterized in that: The method comprises: Parsing the pre-constructed original code stream to obtain data to be compressed, dividing the data to be compressed according to a preset unit bit number to obtain a data block set, wherein the unit bit number refers to the number of bits written to the storage RAM at one time; Extracting data blocks in the data block set in sequence, identifying the frame type, region type and row number of the data block, and calculating the hash value of the data block using a pre-built cryptographic hash algorithm; Filling the frame type, region type, row number, hash value and data block of the data block into a pre-built initial multi-layer index structure to obtain a target multi-layer index structure; Traversing the row numbers in the target multi-layer index structure, identifying the data block group, feature value group and number of data blocks corresponding to the row numbers; Determining whether the number of data blocks is a preset number; If the number of data blocks is a preset number, determining whether the data block group has a subsequent single data block group set, the subsequent single data block group set refers to a set of data block groups whose number of data blocks subsequent to the data block group is a preset number; If the data block group has a subsequent single data block group set, merging the data block group and the subsequent single data block group set to obtain a merged data block group; If there is no subsequent single data block group set for the data block group, the data block group is used as the original data block group; If the number of data blocks is not the preset number, determining whether there are identical eigenvalues ​​in the eigenvalue group; If the same eigenvalue exists in the eigenvalue group, compressing the data block group to obtain a compressed data block group; If the same eigenvalue does not exist in the eigenvalue group, the data block group is used as the original data block group; The merged data block groups, compressed data block groups and original data block groups are collected to obtain merged data block group sets, compressed data block group sets and original data block group sets, and the merged data block group sets, compressed data block group sets and original data block group sets are reorganized into code streams using the target multi-layer index structure to complete the FPGA code stream fast compression.

2. The FPGA code stream fast compression method according to claim 1, characterized in that: The parsing of the pre-constructed original code stream to obtain the data to be compressed includes: Identifying a specification field in the original bitstream, and extracting a preamble bitstream from the original bitstream according to the specification field; Parsing the pre-stream to obtain pre-information, wherein the pre-information includes: whether the original stream has been compressed, the data specification of the original stream, and the stream length; The data to be compressed is extracted from the original code stream according to the code stream length in the preamble information.

3. The FPGA code stream fast compression method according to claim 1, characterized in that: The calculating the hash value of the data block by using a pre-built cryptographic hash algorithm comprises: Using a pre-built cryptographic hash algorithm, the data blocks are concatenated into a binary string of a first preset number of bits; Filling the binary string of the first preset number of digits to obtain a filled string, wherein the length of the filled string is a minimum integer multiple of the second preset number of digits; The hash value of the padding string is calculated according to an encrypted hash algorithm to obtain the hash value of the data block.

4. The FPGA code stream fast compression method according to claim 1, characterized in that: Before filling the frame type, region type, row number, hash value and data block of the data block into the pre-built initial multi-layer index structure to obtain the target multi-layer index structure, the method further includes: Identifying a frame type sequence, a region type sequence, and a row number sequence of the data block set; Constructing a frame type hierarchy, a region type hierarchy and a row number hierarchy respectively according to the frame type sequence, the region type sequence and the row number sequence; Associatively indexing the frame type level, the region type level, and the line number level to obtain an index level; Constructing a data block feature value hierarchy and a data block data hierarchy; The initial multi-layer index structure is constructed according to the index level, the data block feature value level and the data block data level.

5. The FPGA code stream fast compression method as claimed in claim 4, characterized in that: The step of filling the frame type, region type, row number, hash value and data block of the data block into a pre-built initial multi-layer index structure to obtain a target multi-layer index structure includes: identifying a frame type level position of the frame type in the frame type level, identifying a region type level position of the region type in the region type level, and identifying a line number level position of the line number in the line number level; Determine an index path of the hash value according to the frame type level position, the region type level position and the line number level position; Identify the feature value level position and the data level position of the hash value at the data block feature value level and the data block data level respectively according to the index path; The hash value is filled into the characteristic value level position, and the data block is filled into the data level position until all the data blocks in the data block set are filled in, thereby obtaining a target multi-layer index structure.

6. The FPGA code stream fast compression method as claimed in claim 5, characterized in that: The traversing the row numbers in the target multi-layer index structure to identify the data block group, the feature value group and the number of data blocks corresponding to the row numbers includes: Extracting the frame types to be traversed in sequence from the frame type sequence, and identifying the region type sequence to be traversed contained in the frame types to be traversed; Extracting the area types to be traversed in sequence from the area type sequence to be traversed, and identifying the row number sequence to be traversed contained in the area type to be traversed; The row numbers to be traversed are sequentially extracted from the sequence of row numbers to be traversed, and the characteristic value groups, data block groups and the number of data blocks corresponding to the row numbers to be traversed are identified.

7. The FPGA code stream fast compression method according to claim 1, characterized in that: The determining whether the data block group has a subsequent single data block group set includes: Identify a subsequent row number of the row number, and obtain a data block group corresponding to the subsequent row number; Identify the number of data blocks in the data block group corresponding to the subsequent row number; Determine whether the number of data blocks in the data block group corresponding to the subsequent row number is 1; If the number of data blocks in the data block group corresponding to the subsequent row number is not 1, then there is no subsequent single data block group set in the data block group; If the number of data blocks in the data block group corresponding to the subsequent row number is 1, then the data block group has a subsequent single data block group set.

8. The FPGA code stream fast compression method according to claim 1, characterized in that: The step of compressing the data block group to obtain a compressed data block group includes: Among multiple specific data blocks having the same characteristic value, obtaining position information of remaining specific data blocks after the first specific data block; A compressed data block group is obtained according to the content of the specific data block and the position information of the remaining specific data blocks.

9. The FPGA code stream fast compression method according to claim 8, characterized in that: The step of using the target multi-layer index structure to reorganize the merged data block set, the compressed data block set and the original data block set into a code stream comprises: Identify the code stream sequence of the merged data block group, the compressed data block group and the original data block group in the merged data block group set, the compressed data block group set and the original data block group set according to the target multi-layer index structure; Combining the merged data block set, the compressed data block set and the original data block set according to the code stream sequence to obtain a data block group sequence; Obtaining code stream specification information of the data block group sequence; Identify the head bit position and the tail bit position of the data block group sequence, and add the code stream specification information to the head bit position and the tail bit position of the data block group sequence to obtain an initial recombined code stream; Calculate the cyclic redundancy check information of the data block group sequence, identify the tail position of the initial reorganized code stream, add the cyclic redundancy check information to the tail position of the initial reorganized code stream, and complete the code stream reorganization.

10. An FPGA code stream fast compression system, characterized in that: The system comprises: A position information and hash value calculation module is used to parse the pre-constructed original code stream to obtain data to be compressed, divide the data to be compressed according to a preset unit bit number to obtain a data block set, wherein the unit bit number refers to the number of bits written to the storage RAM at one time, extract data blocks in the data block set in sequence, identify the frame type, region type and row number of the data block, and calculate the hash value of the data block using a pre-constructed encrypted hash algorithm; A target multi-layer index structure construction module is used to fill the frame type, region type, row number, hash value and data block of the data block into the pre-constructed initial multi-layer index structure to obtain a target multi-layer index structure; a data block group compression module, for traversing the row number in the target multi-layer index structure, identifying the data block group, the characteristic value group and the number of data blocks corresponding to the row number; judging whether the number of data blocks is a preset number; if the number of data blocks is a preset number, judging whether the data block group has a subsequent single data block group set, the subsequent single data block group set refers to a set of data block groups whose subsequent number of data blocks of the data block group is a preset number; if the data block group has a subsequent single data block group set, merging the data block group with the subsequent single data block group set to obtain a merged data block group; if the data block group does not have a subsequent single data block group set, taking the data block group as the original data block group; if the number of data blocks is not a preset number, judging whether the same characteristic value exists in the characteristic value group; if the same characteristic value exists in the characteristic value group, compressing the data block group to obtain a compressed data block group; if the same characteristic value does not exist in the characteristic value group, taking the data block group as the original data block group; The code stream reorganization module is used to collect the merged data block groups, the compressed data block groups and the original data block groups to obtain the merged data block group sets, the compressed data block group sets and the original data block group sets, and use the target multi-layer index structure to perform code stream reorganization on the merged data block group sets, the compressed data block group sets and the original data block group sets.

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